MC74VHCT374A

Octal D-Type Flip-Flop

with 3-State Output
The MC74VHCT374A is an advanced high speed CMOS octal
flip−flop with 3−state output fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power http://onsemi.com
dissipation.
This 8−bit D−type flip−flop is controlled by a clock input and an
output enable input. When the output enable input is high, the eight MARKING
outputs are in a high impedance state. DIAGRAMS
The internal circuit is composed of three stages, including a buffer 20
output which provides high noise immunity and stable output.
The VHCT inputs are compatible with TTL levels. This device can VHCT374A
be used as a level converter for interfacing 3.3 V to 5.0 V, because it SOIC−20WB AWLYYWWG
1
has full 5.0 V CMOS level output swings. SUFFIX DW
CASE 751D 1
The VHCT374A input and output (when disabled) structures
provide protection when voltages between 0 V and 5.5 V are applied,
regardless of the supply voltage. These input and output structures 20
help prevent device destruction caused by supply VHCT
voltage−input/output voltage mismatch, battery backup, hot insertion, 374A
etc. 1 ALYWG
TSSOP−20
G
SUFFIX DT
Features CASE 948E 1
• High Speed: fmax = 140 MHz (Typ) at VCC = 5.0 V
A = Assembly Location
• Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C WL, L = Wafer Lot
• TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V YY, Y = Year
WW, W = Work Week
• Power Down Protection Provided on Inputs and Outputs G or G = Pb−Free Package
• Balanced Propagation Delays (Note: Microdot may be in either location)
• Designed for 4.5 V to 5.5 V Operating Range
• Low Noise: VOLP = 1.6 V (Max) FUNCTION TABLE
• Pin and Function Compatible with Other Standard Logic Families
INPUTS OUTPUT
• Latchup Performance Exceeds 300 mA
OE CP D Q
• ESD Performance:
Human Body Model > 2000 V; L H H
L L L
Machine Model > 200 V
L L, H, X No Change
• Chip Complexity: 276 FETs or 69 Equivalent Gates H X X Z
• These Devices are Pb−Free and are RoHS Compliant

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

October, 2014 − Rev. 6 MC74VHCT374A/D
 MC74VHCT374A

OE 1 20 VCC
3 2
D0 Q0
4 5 Q0 2 19 Q7
D1 Q1
7 6 D0 3 18 D7
D2 Q2
8 9
DATA D3 Q3 D1 4 17 D6
13 12 NONINVERTING
INPUTS D4 Q4
14 15 OUTPUTS Q1 5 16 Q6
D5 Q5
17 16 Q2 6 15 Q5
D6 Q6
18 19
D7 Q7 D2 7 14 D5
11
CP D3 8 13 D4

1 Q3 9 12 Q4
OE
GND 10 11 CP

Figure 1. Logic Diagram Figure 2. Pin Assignment

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Value Unit This device contains protection

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC DC Supply Voltage – 0.5 to + 7.0 V circuitry to guard against damage
due to high static voltages or electric

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin DC Input Voltage – 0.5 to + 7.0 V fields. However, precautions must

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
be taken to avoid applications of any
Vout DC Output Voltage Outputs in 3−State – 0.5 to + 7.0 V
voltage higher than maximum rated
High or Low State – 0.5 to VCC + 0.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
voltages to this high−impedance cir-
IIK Input Diode Current − 20 mA cuit. For proper operation, Vin and

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
IOK Output Diode Current (VOUT < GND; VOUT > VCC) ± 20 mA
Vout should be constrained to the

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
range GND v (Vin or Vout) v VCC.
Iout DC Output Current, per Pin ± 25 mA Unused inputs must always be

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ICC DC Supply Current, VCC and GND Pins ± 75 mA
tied to an appropriate logic voltage

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
level (e.g., either GND or V CC ).
PD Power Dissipation in Still Air, SOIC Package† 500 mW Unused outputs must be left open.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TSSOP Package† 450

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Tstg Storage Temperature – 65 to + 150
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any
of these limits are exceeded, device functionality should not be assumed, damage may occur
_C

and reliability may be affected.

†Derating − SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC DC Supply Voltage 4.5 5.5 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin DC Input Voltage 0 5.5 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vout DC Output Voltage Outputs in 3−State 0 5.5 V
High or Low State 0 VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA Operating Temperature − 40 + 85 _C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf Input Rise and Fall Time VCC =5.0V ±0.5V 0 20
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ns/V

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 MC74VHCT374A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
VCC TA = 25°C TA = − 40 to 85°C

ÎÎ
Symbol Parameter Test Conditions V Min Typ Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIH Minimum High−Level Input Voltage 4.5 to 5.5 2.0 2.0 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIL Maximum Low−Level Input Voltage 4.5 to 5.5 0.8 0.8 V
VOH Minimum High−Level Output IOH = − 50mA 4.5 4.4 4.5 4.4 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Voltage Vin = VIH or VIL
IOH = − 8mA 4.5 3.94 3.80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VOL Maximum Low−Level Output IOL = 50mA 4.5 0.0 0.1 0.1 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Voltage Vin = VIH or VIL
IOL = 8mA 4.5 0.36 0.44

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Current Vin = 5.5 V or GND 0 to 5.5 ± 0.1 ± 1.0 mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
IOZ Maximum 3−State Leakage Current Vin = VIL or VIH 5.5 ± 0.25 ± 2.5 mA
Vout = VCC or GND

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ICC
ICCT ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎ
Maximum Quiescent Supply Current

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Quiescent Supply Current
Vin = VCC or GND
Per Input: VIN = 3.4V
5.5
5.5
4.0
1.35
40.0
1.50
mA
mA

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎÎ
Other Input: VCC or GND

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
IOPD Output Leakage Current VOUT = 5.5V 0 0.5 5.0 mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ TA = 25°C TA = − 40 to 85°C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions Min Typ Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
fmax Maximum Clock Frequency VCC = 5.0 ± 0.5V CL = 15pF 90 140 80 MHz
(50% Duty Cycle) CL = 50pF 85 130 95

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, VCC = 5.0 ± 0.5V CL = 15pF 4.1 9.4 1.0 10.5 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL CP to Q CL = 50pF 5.6 10.4 1.0 11.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZL, Output Enable Time, VCC = 5.0 ± 0.5V CL = 15pF 6.5 10.2 1.0 11.5 ns
tPZH OE to Q RL = 1kW CL = 50pF 7.3 11.2 1.0 12.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLZ, Output Disable Time VCC = 5.0 ± 0.5V CL = 50pF 7.0 11.2 1.0 12.0 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHZ OE to Q RL = 1kW

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tOSLH, Output to Output Skew VCC = 5.0 ± 0.5V CL = 50pF 1.0 1.0 ns
tOSHL (Note 1)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin Maximum Input Capacitance 4 10 10 pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cout
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
Maximum 3−State Output Capacitance
(Output in High−Impedance State)
9 pF

Typical @ 25°C, VCC = 5.0V

CPD Power Dissipation Capacitance (Note 2) 25 pF
1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 8 (per flip−flop). CPD is used to determine the
no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.

NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)

TA = 25°C
Symbol Parameter Typ Max Unit
VOLP Quiet Output Maximum Dynamic VOL 1.2 1.6 V
VOLV Quiet Output Minimum Dynamic VOL −1.2 −1.6 V
VIHD Minimum High Level Dynamic Input Voltage 2.0 V
VILD Maximum Low Level Dynamic Input Voltage 0.8 V

TIMING REQUIREMENTS (Input tr = tf = 3.0ns)

TA = 25°C TA = − 40 to 85°C
Symbol Parameter Test Conditions Typ Limit Limit Unit
tw Minimum Pulse Width, CP VCC = 5.0 ± 0.5 V 6.5 8.5 ns
tsu Minimum Setup Time, D to CP VCC = 5.0 ± 0.5 V 2.5 2.5 ns
th Minimum Hold Time, D to CP VCC = 5.0 ± 0.5 V 2.5 2.5 ns

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 MC74VHCT374A

ORDERING INFORMATION
Device Package Shipping†
MC74VHCT374ADWRG SOIC−20WB 1000 / Tape & Reel
(Pb−Free)

MC74VHCT374ADTRG TSSOP−20 2500 / Tape & Reel

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

3V

CP 1.5V
GND
tW
1/fmax
tPLH tPHL
VOH
Q 1.5V
VOL

Figure 3. Switching Waveform

3V
OE 1.5V
GND
tPZL tPLZ
HIGH
IMPEDANCE
Q 1.5V
VOL +0.3V
tPZH tPHZ
VOH -0.3V
Q
1.5V
HIGH
IMPEDANCE
Figure 4. Switching Waveform

VALID
3V
D 1.5V
GND
tsu th
3V
CP 1.5V
GND
Figure 5. Switching Waveform

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 MC74VHCT374A

TEST POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 6. Test Circuit

TEST POINT
CONNECT TO VCC WHEN
OUTPUT 1 kW
TESTING tPLZ AND tPZL.
DEVICE CONNECT TO GND WHEN
UNDER TESTING tPHZ AND tPZH.
TEST CL*

*Includes all probe and jig capacitance

Figure 7. Test Circuit

D0 D1 D2 D3 D4 D5 D6 D7
3 4 7 8 13 14 17 18
D Q D Q D Q D Q D Q D Q D Q D Q

C C C C C C C C

11
CP

1
OE
2 5 6 9 12 15 16 19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Figure 8. Expanded Logic Diagram

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 MC74VHCT374A

PACKAGE DIMENSIONS

TSSOP−20
CASE 948E−02
ISSUE C
NOTES:
20X K REF K 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

ÍÍÍÍ
0.15 (0.006) T U S 0.10 (0.004) M T U S V S K1 2. CONTROLLING DIMENSION:
MILLIMETER.

ÍÍÍÍ
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
J J1

ÍÍÍÍ
20 11 BURRS. MOLD FLASH OR GATE BURRS
2X L/2 SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
B SECTION N−N INTERLEAD FLASH OR PROTRUSION
L −U− SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
PIN 1 5. DIMENSION K DOES NOT INCLUDE
IDENT DAMBAR PROTRUSION. ALLOWABLE
N 0.25 (0.010)
DAMBAR PROTRUSION SHALL BE 0.08
1 10 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M 6. TERMINAL NUMBERS ARE SHOWN FOR
0.15 (0.006) T U S REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
A N MILLIMETERS INCHES
−V− DIM MIN MAX MIN MAX
F A 6.40 6.60 0.252 0.260
B 4.30 4.50 0.169 0.177
DETAIL E C --- 1.20 --- 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
−W− H 0.27 0.37 0.011 0.015
C
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
D G K 0.19 0.30 0.007 0.012
H K1 0.19 0.25 0.007 0.010
DETAIL E L 6.40 BSC 0.252 BSC
0.100 (0.004) M 0_ 8_ 0_ 8_
−T− SEATING
PLANE
SOLDERING FOOTPRINT
7.06

0.65
PITCH

16X 16X
0.36
1.26 DIMENSIONS: MILLIMETERS

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 MC74VHCT374A

PACKAGE DIMENSIONS

SOIC−20 WB
DW SUFFIX
CASE 751D−05
ISSUE G

NOTES:
D 1. DIMENSIONS ARE IN MILLIMETERS.
A q 2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
20 11 PROTRUSION.
M

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

B

5. DIMENSION B DOES NOT INCLUDE DAMBAR

X 45 _
H

PROTRUSION. ALLOWABLE PROTRUSION

M

E SHALL BE 0.13 TOTAL IN EXCESS OF B

10X

0.25

DIMENSION AT MAXIMUM MATERIAL

h
CONDITION.

1 10 MILLIMETERS
DIM MIN MAX
A 2.35 2.65
A1 0.10 0.25
20X B B B 0.35 0.49
C 0.23 0.32
0.25 M T A S B S D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
A L 0.50 0.90
q 0_ 7_

L
SEATING
PLANE
18X e A1 T C

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