ch340g Part 3
ch340g Part 3
ch340g Part 3
Table of Contents
CH340G USB to UART Interface Datasheet
Disclaimer from DreamCity Innovations 1
1. Overview 1
2. Features 1
Table of Contents 2
3. Specifications 3
3.1. Absolute Maximum Ratings 3
3.2. DC characteristics 3
3.3. AC characteristics 3
4. Pinout 4
5. Application Notes 4
5.1. Example: USB RS232 adapter 5
5.2. Example: Optically isolated USB to UART adapter 6
4. Pinout
Pin # Name Direction Comment
1 GND Power Ground reference of the chip. Connect to the ground pin of USB bus.
Internal 3.3V reference for USB physical layer. Decouple with a 4.7-20nF
4 V3 Power
capacitor when in 5V operation, or tie to VCC when in 3.3V operation.
Input of the crystal oscillator. Connect to the crystal resonator and load
7 XI Input
capacitors.
Output of the crystal oscillator. Connect to the crystal resonator and load
8 XO Output
capacitors.
15 R232 Input Auxiliary RS232 enable. Active high, internal pull down.
5. Application Notes
CH340 chip have built in USB bus pull-up resistors and on-chip signal termination, UD+ and
UD- pins should be connected to the USB bus lines directly.
CH340 have built in power on reset circuitry.
During operation CH340 requires a 12MHz clock signal present at XI pin. Generally this clock
signal is provided by connecting a 12MHz crystal resonator and load capacitors between XI
and XO pins, and the built-in crystal resonator will provide the required clock signal. When
using an external oscillator feed the clock signal into XI pin, and leave XO pin unconnected.
CH340 supports 5V and 3.3V operation. When using 5V operation, supply 5V to VCC pin, and
decouple the internal 3.3V reference with a capacitor of 4.7-20nF from V3 pin to ground.
When using 3.3V operation, tie V3 pin to VCC pin and supply 3.3V power.
CH340 supports USB device suspension to reduce energy consumption. When NOS# signal
is active this feature is disabled. (Note: CH340G does not have this pin.)
Supported hardware flow control signals: CTS#, DSR#, RI#, DCD#, DTR# and RTS#. All flow
control pins are software controlled.
Auxiliary pins: IR#, R232, CKO and ACT#. (Note: only R232 is present on CH340G) When
R232 signal is asserted the RXD signal is inverted. R232 is latched during Power-On Reset.
+3V3
+5V
+5V
MF-SMDF050
C2
IC2
10n 16
VCC TXD
2 TXD
U$1
GND
1 3 RXD
X1 GND RXD
4
V3
1 C1 RTS#
14 RTS
USB
2 D- 13 DTR
DTR#
3 D+ 10µ 7
XI DCD#
12 DCD
4 Q1 8 11 RI
XO RI#
12M 10 DSR
DSR#
C3 C4 CTS#
9 CTS
D+ 5
D+
PN61729-S 22p 22p D- 6
D- R232
15
GND
VDD
GND
+5V
R5
OK1
10k R1
CTS 4 1
VDD
IC1G$1
510
3 2 4 2
R2 GNDIO
PC817 74LVC1G06DBV
OK2 JP1
VCC
VCC
10k
5
R6 1 4 C5
GND
510 CTS IC1G$2 IC3G$2
TXD 2 3
VCC
10µ
GND
GND
R7 TXO
3
PC817 VDD
RXI
OK3
10k R3 DTR
RXD 4 1
IC3G$1
510
3 2 4 2 GNDIO
R4
PC817 74LVC1G06DBV
OK4
R8 10k
1 4
510
DNP
C6
DTR 2 3
PC817
GNDIO
GND
This adapter provides optically isolated inputs and outputs with 4 PC817 optoisolators.
Respect the isolation border when laying out the board, and if possible, cut slots under the
optoisolators. The two 74LVC1G06 is optional, but helpful when the input pins cannot source
too many current.