CS121: Fundamentals of Computer Sciences

CPU Organization & Design

Instruction Set Completeness
Common Bus System
Control Unit
Instruction Cycle

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THE VON NEUMANN ARCHITECTURE

General-purpose (von Neumann) Architecture

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REGISTERS IN THE BASIC COMPUTER
11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
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BASIC COMPUTER INSTRUCTION FORMAT

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation

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BASIC COMPUTER INSTRUCTION SET
Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off

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 INSTRUCTION SET COMPLETENESS
The set of instructions are said to be complete if all of the
following categories are covered.

- Arithmetic, logic, and shift instructions

- ADD, CMA, INC, CIR, CIL, AND, CLA

- Data transfers between main memory and processor registers

- LDA, STA

- Program Control Instructions

- Program sequencing, control, status condition
- BUN, BSA, ISZ

- Input/ Output Instructions

- INP, OUT

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COMMON BUS SYSTEM OF BASIC COMPUTER

• The registers and memory of the Basic Computer are connected

using a common bus

• This gives a savings in circuitry over dedicated connections

between registers

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COMMON BUS SYSTEM
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read

AR 1

LD INR CLR

PC 2

LD INR CLR

DR 3

LD INR CLR

E
ALU AC 4

LD INR CLR

INPR
IR 5

LD
TR 6

LD INR CLR

OUTR Clock
LD
16-bit common bus

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 INSTRUCTION CYCLE
• A program residing in the memory of the computer consists of a
sequence of instructions.
• The program is executed by going through a cycle for each
instruction.
– For every operation, there is a sequence of microoperations needed to implement that
operation.
• Each instruction consists of the following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. If the instruction has an indirect address, read the effective
address from memory
4. Execute the instruction

• After an instruction is executed, the cycle starts again at Step 1,

for the next instruction
• The process continues until the last instruction is executed.

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Recall: HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERS

Example: Implementation of controlled transfer P: R2  R1

Block diagram Control P Load

R2 Clock
Circuit
n
R1

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 FETCH and DECODE
• Fetch and Decode T0: AR  PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2

T0 S1 Bus

S0

Memory 7
unit
Address
Read

AR 1

LD

PC 2

INR

IR 5

LD
Clock
Common bus

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 DECODING AN INSTRUCTION
• An instruction read from memory is placed in the Instruction Register (1R).

Instruction register (IR)

15 14 13 12 11 - 0

3x8
decoder
7654321 0

I D7 … D1 D0

• The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder.

• The eight outputs of the decoder are designated by the symbols D0 through D7.
▪ The subscripted decimal number is equivalent to the binary value of the
corresponding operation code.

• Bit 15 of the instruction is transferred to a flip-flop designated by the symbol I.

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CONTROL UNIT OF BASIC COMPUTER

Instruction register (IR)

15 14 13 12 11 - 0

3x8
decoder
7 6 5 4 3 2 10
D0
I Combinational
D7 Control Control
signals
logic

T15

T0

15 14 ....21 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

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 FETCH and DECODE
• Fetch and Decode T0: AR  PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2

T0 S1 Bus

S0

Memory 7
unit
Address
Read

AR 1

LD

PC 2

INR

IR 5

LD
Clock
Common bus

CSE504 Advanced Computer Architecture 14

 MEMORY REFERENCE INSTRUCTIONS

- The execution of memory reference instruction starts with T4

AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC

ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E

LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0

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DETERMINE THE TYPE OF INSTRUCTION
Start
SC  

T0
AR  PC

T1
IR  M[AR], PC  PC + 1

T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7 I T3: AR  M[AR]

D'7 I' T3: Nothing
D7 I' T3: Execute a register-reference instr.
D7 I T3: Execute an input-output instr.
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FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS
Start
SC  

T0
AR  PC

T1
IR  M[AR], PC  PC + 1

T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7 I T3: AR  M[AR]

D'7 I' T3: Nothing

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