MCA05/MSCIT-05/PGDCA-05/BCA-11

▪ 5-1 Instruction Codes

▪ The user of a computer can control the process by means of a program
▪ A program is a sequence of instructions that specify the operations, operand, the
sequence(control)
▪ A instruction is a binary code that specifies a sequence of microoperations
▪ Instruction codes together with data are stored in memory(=Stored Program
Concept)
▪ The computer reads each instruction from memory and places it in a control
register. The control then interprets the binary code of the instruction and
proceeds to execute it by issuing a sequence of microoperations.
▪ Instruction Code :
▪ A group of bits that instruct the computer to perform a specific operation
▪ It is usually divided into parts(refer to Fig. 5-1 instruction format)
▪ Operation Code :
▪ The most basic part of an instruction code
▪ A group of bits that define such operations as add, subtract, multiply, shift, and
complement(bit 12-15 : 24 = 16 distinct operations)
15 12 11 0

Op. Code Address

▪ Stored Program Organization :
▪ The simplest way to organize a computer
▪ One processor register : AC(Accumulator)
▪ The operation is performed with the memory operand and the content of AC
▪ Instruction code format with two parts : Op. Code + Address
▪ Op. Code : specify 16 possible operations(4 bit)
▪ Address : specify the address of an operand(12 bit)
▪ If an operation in an instruction code does not need an operand from memory, the
rest of the bits in the instruction(address field) can be used for other purpose
▪ .Memory : 12 bit = 4096 word(Instruction and Data are stored)
▪ Store each instruction code(program) and operand (data) in 16-bit memory word
▪ Addressing Mode
▪ Immediate operand address :
▪ the second part of an instruction code(address field) specifies an operand
▪ Direct operand address :
▪ the second part of an instruction code specifies the address of an operand
▪ Indirect operand address :
▪ the bits in the second part of the instruction designate an address of a memory word
in which the address of the operand is found
▪ One bit of the instruction code is used to distinguish between a direct and an indirect
address : I=0 : Direct, 15 14 12 11 0

I=1 : Indirect I Opcode Address

 ▪ Effective Address
▪ The operand address in computation-type instruction or the target address in a branch-
type instruction

▪ 5-2 Computer Registers

▪ List of Registers for the Basic Computer : Tab. 5-1
▪ Basic computer registers and memory : Fig. 5-3
▪ Data Register(DR) : hold the operand(Data) read from memory
▪ Accumulator Register(AC) : general purpose processing register
▪ Instruction Register(IR) : hold the instruction read from memory
▪ Temporary Register(TR) : hold a temporary data during processing
▪ Address Register(AR) : hold a memory address, 12 bit width
▪ Program Counter(PC) :
▪ hold the address of the next instruction to be read from memory after the current
instruction is executed
▪ Instruction words are read and executed in sequence unless a branch instruction is
encountered
▪ A branch instruction calls for a transfer to a nonconsecutive instruction in the
program
▪ The address part of a branch instruction is transferred to PC to become the address of
the next instruction
▪ To read instruction, memory read cycle is initiated, and PC is incremented by
one(next instruction fetch)
 ▪ Input Register(INPR) : receive an 8-bit character from an input device
▪ Output Register(OUTR) : hold an 8-bit character for an output device
▪ Common Bus System
▪ The basic computer has eight registers, a memory unit, and a control unit
▪ Paths must be provided to transfer information from one register to another
and between memory and registers
▪ A more efficient scheme for transferring information in a system with many
registers is to use a common bus.
▪ The connection of the registers and memory of the basic computer to a
common bus system :
▪ The outputs of seven registers and memory are connected to the common
bus
▪ The specific output is selected by mux(S0, S1, S2) :

▪ Control Input : LD, INC, CLR, Write, Read

▪ Address Register
▪ Accumulator(AC) : 3 Path
s2
▪ 1) Register Microoperation : clear s1
s0
Bus

AC, shfift AC,… Memory unit

4096×16 Address
7

▪ 2) Data Register : add DR to AC, and

Write Read
DR to AC(AC End carry bit AR
1
set/reset), memory READ(DR) LD INR CLR

▪ 3) INPR PC 2

▪ Note) Two microoperations can be LD INR CLR

executed at the same time DR

3
LD INR CLR
DR  AC : s2 s1s0 = 100(4), DR(load )
AC  DR : DR → Adder & Logic → AC (load ) Adder
and
E
AC 4
logic
LD INR CLR

INPR

IR 5

LD

TR
6
LD INR CLR

OUTR

Clock
LD

16-bit common bus

 Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx And memory word to AC
▪ 5-3 Computer Instruction ADD
LDA
1xxx 9xxx
2xxx Axxx
Add memory word to AC
Load memory word to AC
▪ 3 Instruction Code Formats : STA 3xxx Bxxx Store content of AC in memory
▪ Memory-reference instruction BUN
BSA
4xxx Cxxx
5xxx Dxxx
Branch unconditionally
Branch and Save return address
▪ Opcode = 000  110 ISZ 6xxx Exxx Increment and skip if zero
CLA 7800 Clear AC
▪ I=0 : 0xxx ~ 6xxx, I=1: 8xxx ~Exxx CLE 7400 Clear E
CMS 7200 Complement AC
I=0 : Direct, 15 14 12 11 0
CME 7100 Complement E
I=1 : Indirect I Opcode Address CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instruction if AC positive
▪ Register-reference instruction SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
▪ 7xxx (7800 ~ 7001) : CLA, CMA, …. SZE 7002 Skip next instruction if E is 0
HLT 7001 Halt computer
15 14 12 11 0 INP F800 Input character to AC
OUT F400 Output character from AC
0 1 1 1 Register Operation SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt On
IOF F040 Interrupt Off
▪ Input-Output instruction
▪ Fxxx(F800 ~ F040) : INP, OUT, ION, SKI, ….
15 14 12 11 0

1 1 1 1 I/O Operation
 ▪ Instruction Set Completeness
▪ Arithmetic, Logical, and shift : CMA, INC, ..
▪ Moving information to and from memory and AC : STA, LDA
▪ Program control : BUN, BSA, ISZ
▪ Input/Output : INP, OUT

▪ 5-4 Timing and Control

▪ Clock pulses
▪ A master clock generator controls the timing for all registers in the basic computer
▪ The clock pulses are applied to all F/Fs and registers in system
▪ The clock pulses do not change the state of a register unless the register is enabled by a control
signal
▪ The control signals are generated in the control unit :
▪ The control signals provide control inputs for the multiplexers in the common bus, control
inputs in processor registers, and microoperations for the accumulator
▪ Two major types of control organization
▪ Hardwired Control :
▪ The control logic is implemented with gates, F/Fs, decoders, and other digital circuits
▪ + Fast operation, - Wiring change(if the design has to be modified)
▪ Microprogrammed Control :
▪ The control information is stored in a control memory, and the control memory is
programmed to initiate the required sequence of microoperations
▪ + Any required change can be done by updating the microprogram in control
memory, - Slow operation
Instruction register (IR)
15 14 13 12 11 - 0
◆ Control Unit :
Control Unit = Control Logic Gate +
3×8
3 X 8 Decoder + Instruction Register decoder
Other inputs

7 6 5 4 3 2 1 0
+ Timing Signal
I D0
Timing Signal = 4 X 16 Decoder + .
.
D7 . Control
Control
4-bit Sequence Counter logic
outputs

gates
Exam) Control timing : T15
.

» Sequence Counter is cleared when T0

.
.

.
.
.
D3T4 =1 : D3T4 : SC  0 15 14 10

.
.
.
4×16
Memory R/W cycle time > Clock decoder

cycle time
Increment(INR)
» wait cycle. 4-bit
sequence
Clear(CLR)
counter
(SC)
Clock
 ▪ Exam) Register transfer statement :
▪ A transfer of the content of PC into AR if timing signal T0 is active
▪ 1) During T0 active, the content of PC is placed onto the bus
▪ 2) LD(load) input of AR is enabled, the actual transfer occurs at the next positive transition of
the clock(T0 rising edge clock)
▪ 3) SC(sequence counter) is incremented :

▪ 5-5 Instruction Cycle

▪ Instruction Cycle
▪ 1) Instruction Fetch from Memory
▪ 2) Instruction Decode
▪ 3) Read Effective Address(if indirect addressing mode)
▪ 4) Instruction Execution
▪ 5) Go to step 1) : Next Instruction[PC + 1]
▪ Instruction Fetch : T0, T1
T0 : AR  PC
T1 : IR  M [ AR ], PC  PC + 1
▪ T0 = 1
▪ 1) Place the content of PC onto the bus by making the bus selection inputs S2S1S0=010
▪ 2) Transfer the content of the bus to AR by enabling the LD input of AR
 ▪ T1 = 1 T1 : IR  M [ AR ], PC  PC + 1
▪ 1) Enable the read input memory
▪ 2) Place the content of memory onto the bus by making S2S1S0= 111
▪ 3) Transfer the content of the bus to IR by enable the LD input of IR
▪ 4) Increment PC by enabling the INR input of PC

◆ Instruction Decode : T2
T2 : D0 ,...., D7  Decode IR(12 − 14), AR  IR(0 − 11), I  IR(15)
Op.code Address Di/Indirect

◆ Instruction Execution : T3, T4, T5, T6

IR(12 − 14)
D7=1 Register(I=0) D7I’T3(Execute) Read effective
= 111
I/O (I=1) D7IT3 (Execute) Address
D7=0 : Memory Ref. Indirect(I=1) D7’IT3( AR  M [AR ] )
Direct (I=0) nothing in T3
Register Memory Ref Operand effective address
Memory Ref.
◆ Flowchart for instruction cycle(Initial
Configuration) :
T1=1
T0=1 s2 0 1
1 1
s1
Bus 0 1
s0

Memory
Memory unit
unit 7
Address

Read

AR 1
LD

PC 2
INR

IR 5

LD

Clock

Common bus
 ▪ Register Ref. Instruction
▪ r = D7I’T3 : Address
▪ IR(i) = Bi IR(0 -11)
B0 - B11 : 12 Register Ref. Instruction (Tab.
5-3)

▪ 5-6 Memory Ref. Instruction

D7 : Register or I/O = 1 IR(12,13,14)
3 X 8 D - D : 7 Memory Ref. = 111
6 0
Decoder
Instruction(Tab. 5-4)
▪ AND to AC

D0T4 : DR  M [ AR ]
▪ ADDDto : AC  AC  DR , SC  0
0T5AC

D1T4 : DR  M [ AR ]
▪ LDAD:1Tmemory read
5 : AC  AC + DR , E  Cout , SC  0

D2T4 : DR  M [ AR ]
D2T5 : AC  DR , SC  0
 Start
SC 0

T0
AR PC

T1
IR M[AR], PC PC+1

T2
Decode operation code in IR(12-14)
AR IR(0-11), I I(15)

(Register or I/O) = 1 0 = (Memory-reference

I

(I/O) = 1 0 = (register) (indirect) = 1 0 = (direct)

I I

T3 T3 T3 T3

Execute Execute
AR M[AR] Nothing
input-output register-reference
instruction instruction
SC 0 SC 0

Execute
memory-reference
instruction
SC 0
 Fig. 5-10 Example of BSA

PC = 10 0 BSA 135
PC = 21 next instruction

▪ STA : memory write

D3T4 : M [ AR ]  AC , SC  0 135 21(return address)
▪ BUN : branch unconditionally PC = 136
D4T4 : PC  AR , SC  0 Subroutine

▪ BSA : branch and save return address 1 BUN 135

D5T4 : M [ AR ]  PC , AR  AR + 1
D5T5 : PC  AR , SC  0 D5T4 : M [135]  21( PC ), 136( AR )  135 + 1
▪ Return Address : save return address ( 135 21 )
▪ Subroutine Call : Fig. 5-10 D5T5 : 136( PC )  136( AR ), SC  0
▪ DISZ
T :: DR
increment
 M [ ARand
] skip if zero
6 4

D6T5 : DR  DR + 1
D6T6 : M [ AR ]  DR , if ( DR = 0) then ( PC  PC + 1), SC  0
▪ Control Flowchart :
▪ Flowchart for the 7 memory reference instruction
▪ The longest instruction : ISZ(T6)
▪ 3 bit Sequence Counter)
 ▪ 5-7 Input-Output and Interrupt
▪ Input-Output Configuration :
▪ Input Register(INPR), Output Register(OUTR)
▪ These two registers communicate with a communication interface serially and with the AC in
parallel
1 : Ready ▪ Each quantity of information has eight bits of an alphanumeric code
0 : Not ready▪ Input Flag(FGI), Output Flag(FGO)
▪ FGI : set when INPR is ready, clear when INPR is empty
▪ FGO : set when operation is completed, clear when output device is in the process of
printing
▪ Input-Output Instruction : Tab. 5-5
▪ p = D7IT3
Address
▪ IR(i) = Bi IR(6 -11)
B6 - B11 : 6 I/O Instruction
▪ Program Interrupt
▪ I/O Transfer Modes
▪ 1) Programmed I/O, 2) Interrupt-initiated I/O, 3) DMA, 4) IOP
▪ 2) Interrupt-initiated I/O
▪ Maskable Interrupt Int. mask
▪ Interrupt Cycle : Instruction cycle =0
R
=1 Interrupt cycle

▪ During the execute phase, IEN is checked by the control Fetch and decode
Store return address
instruction
in location 0

▪ IEN = 0 : the programmer does not want to use the interrupt, M[0] PC

=0
Execute IEN

so control continues with the next instruction cycle instruction

=1
Branch to location 1
PC 1

▪ IEN = 1 : the control circuit checks the flag bit, If either flag
=1
FGI

=0

set to 1, R F/F is set to 1 =1

FGO
IEN
R
0
0

▪ At the end of the execute phase, control checks the value of R =0

▪ R = 0 : instruction cycle
R 1

▪ R = 1 : Instruction cycle
▪ Demonstration of the interrupt cycle :
▪ The memory location at address 0 as the place for storing the return address
▪ Interrupt Branch to memory location 1 0 256(return address)
▪ Interrupt cycle T0T1 T2 ( IEN )( FGI + FGO ) : R  1
' ' ' PC = 1 0 BUN 1120

▪ The condition for R = 1 Main Program

Interrupt 255
Here 256
▪ Modified Fetch Phase
▪ Modified Fetch and Decode Phase 1120 Interrupt
RT0 : AR  0, TR  PC Service Routine
RT1 : M [ AR ]  TR, PC  0 1 BUN 0

RT2 : PC  PC + 1, IEN  0, R  0, SC  0
▪ Mano, M. Morris (October 1992). Computer System Architecture
(3rd ed.). Prentice-Hall. ISBN 0-13-175563-3
▪ Lecture notes of Dept. of Info. & Comm., Korea Univ. of Tech. &
Edu., Korea