Name: Aishwarya Tapadiya

Reg. No: 17BEC0194

Slot: C2 + TC2
Course: Computer Organisation and Architecture

Digital Assignment - 2
Analysis and Design of Low Power Scan D Flip Flop Based on Positive Edge
Trigger
Question 1:
Explain how the selected paper related to COA syllabus/curriculum.
A flip flop is an electronic circuit with two stable states that can be used to store
binary data. The stored data can be changed by applying varying inputs.
Flip-flops and latches are fundamental building blocks of digital electronics
systems used in computers, communications, and many other types of systems.
Flip-flops and latches are used as data storage elements.
It is the basic storage element in sequential logic.
D Flip Flop:

Scan D Flip Flop:

D flip flop is a better alternative that is very popular with digital electronics.
They are commonly used for counters and shift-registers and input
synchronisation.

Clock D Q Q’

↓»0 0 0 1

↑»1 0 0 1

↓»0 1 0 1

↑»1 1 1 0

In a D flip flop, the output can be only changed at the clock edge, and if the
input changes at other times, the output will be unaffected.

The change of state of the output is dependent on the rising edge of the clock.
The output (Q) is same as the input and can only change at the rising edge of the
clock.
Question 2.
Draw the Existing architectures discussed in the paper using Microsoft VISIO
and Adobe Photoshop software in Encapsulated PostScript (EPS) file format.
Scan-D Flip Flop:

Clocked Scan:

LSSD:
MUX-DFF:

Master-Slave Positive Edge Trigger Circuit:

Question 3.
Draw the Tabulated results and graphs using Microsoft office suite in
Encapsulated PostScript (EPS) file format.
The performance of the proposed Positive edge trigger SCAN D-FF is evaluated
by comparing the average power, delay and timing constraints for normal flip
flop and proposed scan D-FF.

Table 1: power dissipation(pJ)

ARC DFF SDFF
Ck->q(R) 0.00298 0.00263
Ck->q(F) 0.00041 0.00007
RD->q 0.0545 0.00654
SD->q 0.00267 0.00525

Table 2: propagation delay(ns)

ARC DFF SDFF
Ck->q(R) 0.25266 0.25080
Ck->q(F) 0.28197 0.277736
RD->q 0.09053 0.09064
SD->q 0.34350 0.36387

Table 3: Timing Constraints (ms)

Description DFF SDFF
Setup D r CK r 0.09182 0.16220
Setup D f CK r 0.08109 0.22855
Hold D r CK r -0.02437 -0.07521
Hold D f CK r 0.06059 -0.00783
Question 4. Draw the Proposed architectures discussed in the paper using
Microsoft VISIO software in Encapsulated PostScript (EPS) file format.
MUX DFF:
Ao
A1 D00 Q
S0 D01 4-to-1 DFF
MUX
D10
B0 D11
B1 S1 S0 CLK CLR
S1

Question 5. Draw the transistor level internal diagrams using Multisim or

CAD tools in Encapsulated PostScript (EPS) file format.
MultiSim Simulation:
Question 6. Compare the proposed architecture with existing architecture in
your reference books.
The proposed architecture is MUX-DFF while the architectures listed in other
reference books are LSSD and Clocked-Scan Architecture. Below listed is the
methodology and the explanation of these architecture.

DFT Advisor, the Mentor Graphics internal scan synthesis tool, supports the
insertion of mux-DFF (mux-scan), clocked-scan, and LSSD architectures.
Additionally, DFT Advisor supports all standard scan types or combinations
therefore, in designs containing pre-existing scan circuitry. You can use the
type of scan architecture you want inserted in your design. Each scan style
provides different benefits. Mux-DFF or clocked-scan are generally the best
choice for designs with edge-triggered flip-flops. Additionally, clocked-scan
ensures data hold for non-scan cells during scan loading. LSSD is most
effective on latch-based designs. The following subsections detail the mux-
DFF, clocked-scan, and LSSD architectures.

Clocked-Scan:

The clocked-scan architecture is very similar to the mux-DFF architecture,

but uses a dedicated test clock to shift in scan data instead of a multiplexer.

operation, the system clock (sys_clk) clocks system data (data) into the circuit
and through to the output (Q). In scan mode, the scan clock (sc_clk) clocks
scan input data (sc_in) into the circuit and through to the output (sc_out).

LSSD (Level Sensitive Scan Design):

LSSD, or Level-Sensitive Scan Design, uses three independent clocks to capture
data into the two polarity hold latches contained within the cell.

In normal mode, the master latch captures system data (data) using the
system clock (sys_clk) and sends it to the normal system output (Q). In test
mode, the two clocks (Aclk and Bclk) trigger the shifting of test data through
both master and slave latches to the scan output (sc_out). There are several
varieties of the LSSD architecture, including single latch, double latch, and
clocked LSSD.
MUX-DFF:

A mux-DFF cell contains a single D flip-flop with a multiplexed input line that
allows selection of either normal system data or scan data. In normal
operation (sc_en = 0), system data passes through the multiplexer to the D
input of the flip-flop, and then to the output Q. In scan mode (sc_en = 1), scan
input data (sc_in) passes to the flip-flop, and then to the scan output
(sc_out).

Question 7. List the advantage of the proposed design over existing design.

Adding more features into a single chip also increases the complexity which
demands highly testable circuitries.

Therefore, inserting scan chain throughout the entire chip is a technique

which cannot be ignored anymore.

During the test mode a known set of test vectors are loaded into the scan
chain to test the combinational logic between pipeline stages.

If there was no scan chain in the circuit the entire chip would have had to run
for multiple cycles to send the test results to the chip boundary.

Stitching flops makes it possible to serialize the test results and send them
through the scan chain.

The timing of a design significantly depends on the speed of these flip-flops

and also has a major contribution in the total power consumption of the
design.

An important FLIP FLOP function for ASIC testing is called SCAN capability.
The idea is to be able to drive the FLIP FLOPs.

D input with an alternate source of the data during drive testing. When all
the flip flops put into the testing mode, a test pattern can be scanned in to
the ASIC using the flip flops alternative data inputs. After the test pattern is
loaded, the flip-flops are put back into normal mode, and all of the flip flops
are clocked normally.
After one or more clock ticks, the flip-flops are back into test mode and the
test result are “scanned out”.

In scan architectures the scan MUX-DFF is easy to test the circuit compare to the
other two architectures. This is due to the reason that the scan MUX-DFF
contains only one clock, but Clocked-scan contains two clocks.
The LSSD is level sensitive, if any change in the transition the circuit output will
change. The circuit complexity also less compare to the Clocked-scan and LSSD.
So, Scan MUX-DFF is better than the other architectures and the designs.

Question 8. List the merits and demerits of the proposed and existing
techniques/hardware.
Merits of MUX-DFF are

1) It reduces number of wires.

2) It reduces circuit complexity and cost.
3) We can implement many combination circuits using MUX.
4) It does not need Kmaps and simplification.

Demerits of MUX-DFF are

1) Added delays in switching port.

2) Limitations on which ports can be used simultaneously.
3) Added firmware complexity to handle switching ports.
4) Added delays in I/O signals propagating through the multiplexer.
5) Extra I/O ports required to control the multiplexer.
6)Time-Skew problems can lead to short circuits.
7)Slower Speed

Merits of LSSD:
1) Correct operation independent of AC charactristics is guaranteed.
2) FSM is reduced to combinational lofic as far as testing is concerned.
3) Hazards and races are eliminated, which simplifies test generation and
fault simulation.
Demerits of LSSD:
1) If the path is a critical timing path, performance of the whole system is
affected.
2) When Compared to some other DFT techniques, scan chain takes very
long.
3) Shifting test vectors and result vectors out takes a large fraction of the
test time, so the system cannot be tested at full operational speed.
4) Complex Design.
5) Asynchronous designs are not allowed in this approach.
6) Not good for memory intensive designs.

Question 9. List the application of proposed design.

A Multiplexer is used in various applications wherein multiple data can be

transmitted using a single line.

Communication System – A Multiplexer is used in communication systems,

which has a transmission system and also a communication network. A
Multiplexer is used to increase the efficiency of the communication system by
allowing the transmission of data, such as audio & video data from different
channels via cables and single lines.

Telephone Network – A multiplexer is used in telephone networks to integrate

the multiple audio signals on a single line of transmission.

Transmission from the Computer System of a Satellite:

A Multiplexer is used to transmit the data signals from the computer system of
a satellite to the ground system by using a GSM communication.
Question 10. Draw the flowchart or algorithm or transistor level circuit
proposed in the design in Encapsulated PostScript (EPS) file format.