Asynchronous Circuit ATPG
Ganesh C. Patil
Tuesday, November 7, 2023
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Combinational Loop
Combinational Circuit
Combinational Loop/Asynchronous loop/ loop/
Synchronous latch
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Asynchronous Circuit
Asynchronous Circuit
Synchronous Circuit
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Asynchronous Circuit
An asynchronous circuit contains unclocked memory
often realized by combinational feedback.
Almost impossible to build, let alone test, a large
asynchronous circuit.
Many large synchronous systems contain small
portions of localized asynchronous circuitry.
Sequential circuit ATPG should be able to generate
tests for circuits with limited asynchronous parts,
even if it does not detect faults in those parts.
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Asynchronous Model
CK Synchronous PIs
Combinational
Feedback Paths:
Feedback set
Feedback-free
Combinational
PPI Logic PPO
CK Synchronous POs
System Clocked
Clock, CK Flip-flops
Fast model Feedback
Modeling circuit is
Clock, FMCK delays
Shown in orange.
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Time-Frame Expansion
Vector k
PI
Feedback Feedback
C C C C
set set
CK FMCK FMCK FMCK PPO
PPI
PO Asynchronous feedback
stabilization
Time-frame Time-frame
-k+1 Time-frame k -k-1
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Simulation based Methods
Difficulties with time-frame method:
Long initialization sequence
Impossible to guarantee initialization with three-
valued logic
Circuit modeling limitations
Timing problems – tests can cause races/hazards
High complexity
Inadequacy for asynchronous circuits
Advantages of simulation-based methods
Advanced fault simulation technology
Accurate simulation model exists for verification
Variety of tests – functional, heuristic, random
Used since early 1960s
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Contest
A Concurrent test generator for sequential
circuit testing (Contest).
Search for tests is guided by cost-functions.
Three-phase test generation:
Initialization – no faults targeted; cost-function computed
by true-value simulator.
Concurrent phase – all faults targeted; cost function
computed by a concurrent fault simulator.
Single fault phase – faults targeted one at a time; cost
function computed by true-value simulation and dynamic
testability analysis.
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Genetic Algorithms (GAs)
Theory of evolution by natural selection (Darwin, 1809-82.)
C. R. Darwin, On the Origin of Species by Means of Natural
Selection, London: John Murray, 1859.
J. H. Holland, Adaptation in Natural and Artificial Systems, Ann
Arbor: University of Michigan Press, 1975.
D. E. Goldberg, Genetic Algorithms in Search, Optimization, and
Machine Learning, Reading, Massachusetts: Addison-Wesley, 1989.
P. Mazumder and E. M. Rudnick, Genetic Algorithms for VLSI Design,
Layout and Test Automation, Upper Saddle River, New Jersey:
Prentice Hall PTR, 1999.
Basic Idea: Population improves with each generation.
Population
Fitness criteria
Regeneration rules
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Difficulties in Seq. ATPG
Poor initializability.
Poor controllability/observability of state
variables.
Gate count, number of flip-flops, and
sequential depth do not explain the problem.
Cycles are mainly responsible for complexity.
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Finite State Machines
A fault in a machine M0 transforms into another machine Mi
with n or fewer states
A test sequence is a sequence of inputs that distinguishes M0
from each of Mi defined by a fault
A synchronizing sequence for a sequential machine M is an
input sequence whose application is guaranteed to leave M in
a certain final state irrespective of initial state of M
A homing sequence for M is an input sequence whose
application makes it possible to determine the final state of M
by observing the corresponding output sequence that M
produces
A distinguishing sequence is an input sequence whose
application makes it possible to determine the initial state of M
by observing the corresponding output sequence M produces
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Scan Design
Circuit is designed using pre-specified design rules.
Test structure (hardware) is added to the verified
design:
Add a test control (TC) primary input.
Replace flip-flops by scan flip-flops (SFF) and connect to form
one or more shift registers in the test mode.
Make input/output of each scan shift register
controllable/observable from PI/PO.
Use combinational ATPG to obtain tests for all
testable faults in the combinational logic.
Add shift register tests and convert ATPG tests into
scan sequences for use in manufacturing test.
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Scan Design Rules
Use only clocked D-type of flip-flops for all
state variables.
At least one PI pin must be available for test;
more pins, if available, can be used.
All clocks must be controlled from PIs.
Clocks must not feed data inputs of flip-flops.
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Correcting a Rule Violation
All clocks must be controlled from PIs.
Comb.
logic D1 Q
FF Comb.
D2 logic
CK
Comb.
logic
Q
D1
D2 FF Comb.
CK logic
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Adding Scan Structure
PI PO
Combinational SFF SCANOUT
logic SFF
SFF
TC or TCK Not shown: CK or
SCANIN MCK/SCK feed all
SFFs.
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Design for Testability (DFT)
Ganesh C. Patil
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Design for Testability (DFT)
Design for testability (DFT) refers to those
design techniques that make test generation
and test application cost-effective.
DFT methods for digital circuits:
Ad-hoc methods
Structured methods:
Scan
Partial Scan
Built-in self-test (BIST)
Boundary scan
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Design for Testability Basics
Ad hoc DFT
Effects are local and not systematic
Not methodical
Difficult to predict
A structured DFT
Easily incorporated and budgeted
Yield the desired results
Easy to automate
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Ad-Hoc DFT Methods
Good design practices learnt through experience are used
as guidelines:
Avoid asynchronous (unclocked) feedback.
Make flip-flops initializable.
Avoid redundant gates. Avoid large fanin gates.
Provide test control for difficult-to-control signals.
Avoid gated clocks.
Consider ATE requirements (tristates, etc.)
Design reviews conducted by experts or design auditing
tools.
Disadvantages of ad-hoc DFT methods:
Experts and tools not always available.
Test generation is often manual with no guarantee of high fault
coverage.
Design iterations may be necessary.
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Structured Approach
Scan design
Convert the sequential design into a scan design
Three modes of operation
– Normal mode
All test signals are turned off
The scan design operates in the original functional
configuration
– Shift mode
– Capture mode
In both shift and capture modes, a test mode signal TM is
often used to turn on all test-related fixes
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Structured Approach - Scan Design
Assume that a stuck-at fault f in the
combinational logic requires the primary
input X3, flip-flop FF2, and flip-flop FF3,
to be set to 0, 1, and 0.
The main difficulty in testing a sequential
circuit stems from the fact that it is difficult
to control and observe the internal state
of the circuit.
Difficulty in testing a sequential circuit
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Structured Approach - Scan Design
How to detect stuck-at fault f :
Converting selected (1) switching to shift mode and shifting in the
storage elements in the desired test stimulus, 1 and 0, to FF2 and FF3,
design into scan cells. respectively
Stitching them together to (2) driving a 0 onto primary input X3
form scan chains. (3) switching to capture mode and applying one
clock pulse to capture the fault effect into FF1
(4) switching back to shift mode and shifting out the
test response stored in FF1, FF2, and FF3 for
comparison with the expected response.
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Scan Cell Design
A scan cell has two inputs: data input and
scan input
In normal/capture mode, data input is selected to
update the output
In shift mode, scan input is selected to update the
output
Three widely used scan cell designs
Muxed-D Scan Cell
Clocked-Scan Cell
LSSD Scan Cell
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Muxed-D Scan Cell
This scan cell is composed of a D
flip-flop and a multiplexer.
The multiplexer uses an additional
scan enable input SE to select
between the data input DI and the
scan input SI.
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Muxed-D Scan Cell In normal/capture mode, SE
is set to 0. The value present
at the data input DI is
captured into the internal D
flip-flop when a rising clock
edge is applied.
In shift mode, SE is set to 1.
The scan input SI is used to
shift in new data to the D flip-
flop, while the content of the
D flipflop is being shifted out.
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Muxed-D Scan Cell
This scan cell is composed
of a multiplexer, a D latch,
and a D flip-flop.
In this case, shift operation is
conducted in an edge-
triggered manner, while
normal operation and
capture operation is
conducted in a level-
sensitive manner.
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Clocked-Scan Cell
In the clocked-scan cell, input
selection is conducted using
two independent clocks, DCK
and SCK.
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Clocked-Scan Cell
In normal/capture mode, the
data clock DCK is used to
capture the contents present at
the data input DI into the
clocked-scan cell.
In shift mode, the shift clock
SCK is used to shift in new
data from the scan input SI into
the clocked - scan cell, while
the content of the clocked-scan
cell is being shifted out.
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LSSD Scan Cell An LSSD scan cell is used for
level-sensitive latch base
designs.
This scan cell contains two
latches, a master 2-port D
latch L1 and a slave D latch
L2. Clocks C, A and B are
used to select between the
data input D and the scan
input I to drive +L1 and +L2.
In an LSSD design, either +L1
or +L2 can be used to drive
the combinational logic of the
design.
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LSSD Scan Cell In order to guarantee race-
free operation, clocks A, B,
and C are applied in a non-
overlapping manner.
The master latch L1 uses the
system clock C to latch
system data from the data
input D and to output this
data onto +L1. Clock B is
used after clock A to latch the
system data from latch L1
and to output this data onto
+L2.
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Comparing three scan cell designs
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Scan Architectures
Full-Scan Design
All or almost all storage element are converted into
scan cells and combinational ATPG is used for test
generation
Partial-Scan Design
A subset of storage elements are converted into
scan cells and sequential ATPG is typically used for
test generation
Random-Access Scan Design
A random addressing mechanism, instead of serial
scan chains, is used to provide direct access to
read or write any scan cell
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Full-Scan Design
All storage elements are replaced with scan cells
All inputs can be controlled
All outputs can be observed
Advantage:
Converts sequential ATPG into combinational ATPG
Almost full-scan design
A small percentage of storage elements are not
replaced with scan cells
– For performance reasons
Storage elements that lie on critical paths
– For functional reasons
Storage elements driven by a small clock domain that are
deemed too insignificant to be worth the additional scan
insertion effort
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Muxed-D Full-Scan Design
The three D flipflops, FF1,
FF2 and FF3, are
replaced with three
muxed-D scan cells,
SFF1, SFF2 and SFF3,
respectively.
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Muxed-D Full-Scan Design
To form a scan chain, the
scan input SI of SFF2
and SFF3 are connected
to the output Q of the
previous scan cell, SFF1
and SFF2, respectively.
In addition, the scan
input SI of the first scan
cell SFF1 is connected to
the primary input SI, and
the output Q of the last
scan cell SFF3 is
connected to the primary
output SO.
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Muxed-D Full-Scan Design
Primary inputs (PIs)
– the external inputs to the circuit
– can be set to any required logic values
– set directly in parallel from the external inputs
Pseudo primary inputs (PPIs)
– the scan cell outputs
– can be set to any required logic values
– are set serially through scan chain inputs
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Muxed-D Full-Scan Design
Primary outputs (POs)
– the external outputs of the circuit
– can be observed
– are observed directly in parallel from the
external outputs
Pseudo primary outputs (PPOs)
– the scan cell inputs
– can be observed
– are observed serially through scan chain
outputs
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Muxed-D Full-Scan Design
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Clocked Full-Scan Design
In a muxed-D fullscan circuit,
a scan enable signal SE is
used.
In a clocked fullscan design,
two operations are
distinguished by properly
applying the two independent
clocks SCK and DCK during
shift mode and capture
mode.
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Scan Overheads
IO pins: One pin necessary.
Area overhead:
Gate overhead = [4 nsff/(ng+10nsff)] x 100%,
where ng = comb. gates; nff = flip-flops;
Example – ng = 100k gates, nsff = 2k flip-flops,
overhead = 6.7%.
More accurate estimate must consider scan wiring
and layout area.
Performance overhead:
Multiplexer delay added in combinational path;
approx. two gate-delays.
Flip-flop output loading due to one additional fanout;
approx. 5-6%.
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Hierarchical Scan
Scan flip-flops are chained within
subnetworks before chaining subnetworks.
Advantages:
Automatic scan insertion in netlist
Circuit hierarchy preserved – helps in debugging and
design changes
Disadvantage: Non-optimum chip layout.
Scanin Scanout
SFF1 SFF4
SFF1 SFF3
Scanin
Scanout
SFF2 SFF3 SFF4 SFF2
Hierarchical netlist Flat layout
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Optimum Scan Layout
X’
X
IO SFF
pad cell
SCANIN
Flip-
flop
cell
Y Y’
TC SCAN
OUT
Routing
channels
Interconnects Active areas: XY and X’Y’
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Timing and Power
Small delays in scan path and clock skew
can cause race condition.
Large delays in scan path require slower
scan clock.
Dynamic multiplexers: Skew between TC and
TC signals can cause momentary shorting of
D and SD inputs.
Random signal activity in combinational
circuit during scan can cause excessive
power dissipation.
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Thank you !!!
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