Overview Variables
◆ Logistics ◆ wire
■ HW5 due today ■ Connects components together
■ HW6 due next Friday
◆ reg
■ Saves a value
◆ Last lecture µ Part of a behavioral description
■ Finish basic latches and Flip-flops ■ Does NOT necessarily become a register when you synthesize
■ Registers µ May become a wire
µ Shift registers
µ Counters ◆ The rule
■ Basic state machine design ■ Declare a variable as reg if it is a target of an assignment
statement inside an always block
◆ Today µ Continuous assign doesn’t count
■ Sequential Verilog
CSE370, Lecture 16 1 CSE370, Lecture 16 2
Sequential Verilog always block
◆ Sequential circuits: Registers & combinational logic ◆ A construct that describes a circuit’s behavior
■ Use positive edge-triggered registers ■ Can contain multiple statements
■ Avoid latches and negative edge-triggered registers ■ Can contain if, for, while, case
■ Triggers at the specified conditions
◆ Register is triggered by “posedge clk” ■ begin/end groups statements within always block
module register(Q, D, clock); Example: A D flip-flop module register(Q, D, clock);
input D, clock; input D, clock;
output Q; output Q;
reg Q; reg Q;
A real register. Holds Q
between clock edges
always @(posedge clock) begin always @(posedge clock) begin
Q <= D; Q <= D;
end end
endmodule endmodule
CSE370, Lecture 16 3 CSE370, Lecture 16 4
Incomplete sensitivity list or incomplete
always example
assignment
◆ What if you omit an input trigger (e.g. in2)
module and_gate(out, in1, in2); Not a real register!! ■ Compiler will insert a latch to hold the state
input in1, in2; Holds assignment in ■ Becomes a sequential circuit — NOT what you want
always block
output out;
module and_gate (out, in1, in2);
reg out; input in1, in2; Real state!! Holds out
The compiler will not synthesize output out; because in2 isn’t specified
always @(in1 or in2) begin this code to a register, because reg out; in always sensitivity list
out = in1 & in2; out changes whenever in1 or in2
change. Can instead simply write always @(in1) begin
end out = in1 & in2;
endmodule wire out, in1, in2;
end
and (out, in1, in2); endmodule 2 rules:
1) Include all inputs in the trigger list
2) Use complete assignments
specifies when block is executed
⇒ Every path must lead to an assignment for out
i.e. triggered by changes in in1 or in2
⇒ Otherwise out needs a state element
CSE370, Lecture 16 5 CSE370, Lecture 16 6
Incomplete sensitivity lists Assignments
◆ • always @(a or b) // it’s or, not || ◆ Be careful with always assignments
■ Which of these statements generate state?
f = a & b;
always @(c or x) begin always @(c or x) begin
◆ • always @(a) if (c) begin value = x;
value = x; if (c) begin
f = a & b; end value = 0;
y = value; end
◆ • always end y = value;
end
always @(c or x) begin
f = a & b; if (c) always @(a or b)
value = 0; f = a & b & c;
◆ • Just use always@(*) for combinational logic else if (x) end
value = 1;
2 rules:
end
1) Include all inputs in the sensitivity list
2) Use complete assignments
⇒ Every path must lead to an assignment for out
CSE370, Lecture 16 7 CSE370, Lecture 16 ⇒ Otherwise out needs a state element 8
Another way: Use functions if
◆ Functions for combinational logic ◆ Same as C if statement
■ Functions can’t have state
// Simple 4-1 mux
module mux4 (sel, A, B, C, D, Y);
module and_gate (out, in1, in2); input [1:0] sel; // 2-bit control signal
input in1, in2; input A, B, C, D;
output out; output Y;
reg Y; // target of assignment
assign out = myfunction(in1, in2);
function myfunction; always @(sel or A or B or C or D)
input in1, in2; Benefits: if (sel == 2’b00) Y = A;
begin Functions force a result else if (sel == 2’b01) Y = B;
myfunction = in1 & in2;
⇒ Compiler will fail if function else if (sel == 2’b10) Y = C;
end
does not generate a result else if (sel == 2’b11) Y = D;
endfunction endmodule
endmodule ⇒ If you build a function wrong
the circuit will not synthesize.
If you build an always block ⇒ Single if statements synthesize to multiplexers
wrong you get a register ⇒ Nested if /else statements usually synthesize to logic
CSE370, Lecture 16 9 CSE370, Lecture 16 10
if (another way) case
// Simple 4-1 mux
// Simple 4-1 mux
module mux4 (sel, A, B, C, D, Y);
module mux4 (sel, A, B, C, D, Y);
input [1:0] sel; // 2-bit control signal input [1:0] sel; // 2-bit control signal
input A, B, C, D; input A, B, C, D;
output Y; output Y;
reg Y; // target of assignment reg Y; // target of assignment
always @(sel or A or B or C or D) always @(sel or A or B or C or D)
if (sel[0] == 0) case (sel)
if (sel[1] == 0) Y = A; 2’b00: Y = A;
else Y = B; 2’b01: Y = B;
else 2’b10: Y = C;
if (sel[1] == 0) Y = C; 2’b11: Y = D;
else Y = D; endcase case executes sequentially
endmodule endmodule ⇒ First match executes
⇒ Don’t need to break out of case
case statements synthesize to muxes
CSE370, Lecture 16 11 CSE370, Lecture 16 12
case (another way) default case
// Simple 4-1 mux // Simple binary encoder (input is 1-hot)
module mux4 (sel, A, B, C, D, Y); module encode (A, Y);
input [1:0] sel; // 2-bit control signal input [7:0] A; // 8-bit input vector
input A, B, C, D; output [2:0] Y; // 3-bit encoded output
output Y; reg [2:0] Y; // target of assignment
assign out = mymux(sel, A, B, C, D); always @(A)
function mymux; case (A)
input [1:0] sel, A, B, C, D; 8’b00000001: Y = 0; If you omit the default, the compiler will
begin 8’b00000010: Y = 1; create a latch for Y
case (sel) 8’b00000100: Y = 2; ⇒ Either list all 256 cases
2’b00: mymux = A; 8’b00001000: Y = 3; ⇒ Or use a function (compiler will
2’b01: mymux = B; 8’b00010000: Y = 4; warn you of missing cases)
2’b10: mymux = C; 8’b00100000: Y = 5;
2’b11: mymux = D; 8’b01000000: Y = 6;
endcase 8’b10000000: Y = 7;
end default: Y = 3’bx; // Don’t care about other cases
Note: You can define a function in a file endcase
endfunction
endmodule Then include it into your Verilog module endmodule
CSE370, Lecture 16 13 CSE370, Lecture 16 14
case executes sequentially for
// Priority encoder // simple encoder
module encode (A, Y); module encode (A, Y);
input [7:0] A; // 8-bit input vector input [7:0] A; // 8-bit input vector
output [2:0] Y; // 3-bit encoded output output [2:0] Y; // 3-bit encoded output
reg [2:0] Y; // target of assignment reg [2:0] Y; // target of assignment
integer i; // Temporary variables for program
always @(A) reg [7:0] test;
case (1’b1)
A[0]: Y = 0; always @(A) begin
A[1]: Y = 1; test = 8b’00000001;
A[2]: Y = 2;
Case statements execute sequentially
Y = 3’bx;
A[3]: Y = 3; ⇒ Take the first alternative that matches for (i = 0; i < 8; i = i + 1) begin
A[4]: Y = 4; if (A == test) Y = i;
A[5]: Y = 5; test = test << 1; // Shift left, pad with 0s
A[6]: Y = 6; end
A[7]: Y = 7; end for statements synthesize as
default: Y = 3’bx; // Don’t care when input is all 0’s endmodule
endcase
cascaded combinational logic
endmodule ⇒ Verilog unrolls the loop
CSE370, Lecture 16 15 CSE370, Lecture 16 16
Verilog while/repeat/forever Blocking and non-blocking assignments
◆ while (expression) statement ◆ Blocking assignments (Q = A)
■ execute statement while expression is true ■ Variable is assigned immediately
■ New value is used by subsequent statements
◆ repeat (expression) statement ◆ Non-blocking assignments (Q <= A)
■ execute statement a fixed number of times ■ Variable is assigned after all scheduled statements are executed
■ Value to be assigned is computed but saved for later
◆ forever statement
■ execute statement forever ◆ Example: Swap
always @(posedge CLK) always @(posedge CLK)
begin begin
temp = B; A <= B;
B = A; B <= A;
A = temp; end
end
CSE370, Lecture 16 17 CSE370, Lecture 16 18
Blocking and non-blocking assignments Swap
◆ The following code executes incorrectly
■ One block executes first
reg B, C, D; reg B, C, D;
■ Loses previous value of variable
always @(posedge clk) always @(posedge clk)
begin begin always @(posedge CLK) always @(posedge CLK)
B = A; B <= A; begin begin
C = B; C <= B; A = B; B = A;
D = C; D <= C; end end
end end
◆ Non-blocking assignment fixes this
■ Both blocks are scheduled by posedge CLK
always @(posedge CLK) always @(posedge CLK)
begin begin
A <= B; B <= A;
end end
CSE370, Lecture 16 19 CSE370, Lecture 16 20
A simple stateful example Parallel versus serial execution
◆ assign statements are implicitly parallel
module stateful_and (out, in, clk); ■ “=” means continuous assignment B A
input in, clk; ■ Example C
assign E = A & D;
output out;
assign A = B & C; E
reg out;
■ A and E change if B changes D
always @(posedge clk) begin ◆ always blocks execute in parallel
out <= in & out; ■ always @(posedge clock)
end
endmodule ◆ Procedural block internals not necessarily parallel
■ “=” is a blocking assignment (sequential)
■ “<=” is a nonblocking assignment (parallel)
■ Examples of procedures: always, function, etc.
CSE370, Lecture 16 21 CSE370, Lecture 16 22
Synthesis examples
wire [3:0] x, y, a, b, c, d;
assign apr = ^a;
assign y = a & ~b;
assign x = (a == b) ?
a + c : d + a;
Verilog tips and traps
a +
c
x a
+ +
d c x
d
==
==
b
b
CSE370, Lecture 16 23 CSE370, Lecture 16 24
Constants: 32 bits, decimal Truncation
wire [7:0] a = 8’hAB;
• wire [7:0] foo = 127; // synthesis warning!
wire b; // oops! forgot width
• wire [7:0] foo = 8’d127;
wire [7:0] c;
• wire [7:0] foo = 8’b11111111;
assign b = a; // synthesis warning if lucky.
• wire [7:0] foo = 8’hff;
assign c = a;
• wire [7:0] foo = 8’hFF;
• watch out: 1010 looks like 4’b1010!
CSE370, Lecture 16 25 CSE370, Lecture 16 26
TIP: (blocking) = vs. <= (non-
(non-blocking) Verilog Stratified Event Queue [1]
◆ • Simple rule: ◆ Region 1: Active Events
■ • If you want sequential logic, use ■ Most events except those explicitly in other regions
■ Includes $display system tasks
always @(posedge clk) with <= (non-blocking)
◆ Region 2: Inactive Events
■ • If you want combinational logic, use ■ Processed after all active events
■ #0 delay events (bad!)
always @(*) with = (blocking)
◆ Region 3: Non-blocking Assign Update Events
■ Evaluation previously performed
■ Update is after all active and inactive events complete
◆ Region 4: Monitor Events
■ Caused by $monitor and $strobe system tasks
◆ Region 5: Future Events
■ Occurs at some future simulation time
■ Includes future events of other regions
■ Other regions only contain events for CURRENT simulation time
CSE370, Lecture 16 27 CSE370, Lecture 16 28
Verilog Stratified Event Queue [2]
within a block,
blocking
assignments,
are in order
CSE370, Lecture 16 29
