Behavioral Modeling:Procedural blocks
IMPORTANT POINTS:
1. Initial block execute only once.
2. Always block execute continuously.
3. LHS must be reg type.
4. Statement inside initial and always blocks
runs sequentially, so the name procedural
blocks.
5. Use of begin mark the onset of procedural
block and end finishes the sequential
execution.
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Behavioural Modelling: logic gates
Behavioural level
module logic_gates( input wire a, b, output reg y0,y1, y2, y3, y4, y5 );
always @(a,b)
begin
y0 = ~a;
y1 = a & b;
y2 = a | b;
y3 = ~(a & b);
y4 = ~(a | b);
y5 = a ^ b;
y6 = ~(a ^ b);
end
endmodule
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Conditional Statements:
• If-else
• case
Synthesizable: Hardware is created.
Loops
• While
• For
• Forever
• Repeat
Non-Synthesizable: Ignored during Hardware mapping, so do not use loops in Design
File.
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If else conditional statement
Type 1: if block
Type 2: if-else block
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If else conditional statement
Type 3: if else-if…else
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Example MUX: Behaviroal Modelling
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If-else
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case statement
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4x1 Multiplexer using case - statement
module mux_4to1_case ( input [3:0] a, // 4-bit input called a
input [3:0] b, // 4-bit input called b
input [3:0] c, // 4-bit input called c
input [3:0] d, // 4-bit input called d
input [1:0] sel, // input sel used to select between a,b,c,d
output reg [3:0] out); // 4-bit output based on input sel
always @ (a or b or c or d or sel) begin
case (sel)
2'b00 : out = a;
2'b01 : out = b;
2'b10 : out = c;
2'b11 : out = d;
default: out=4’d0;
endcase
end
endmodule
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Half Adder using case - statement
module ha(s,c,a,b);
input a,b;
output reg s,c;
always@(a,b)
begin
case({a,b})
2'b00 :begin s=1'b0; c=1'b0; end
2'b01 :begin s=1'b1; c=1'b0; end
2'b10 :begin s=1'b1; c=1'b0; end
2'b11 :begin s=1'b0; c=1'b1; end
default : begin s=1'b0; c=1'b0; end
endcase
end
endmodule
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Loops
There are four types of looping statements in
Verilog:
• while
• for
• repeat
• Forever
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While Loops
while loop: It executes until the while-expression
becomes false.
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for Loop
for Loop contains three parts:
An initial condition;
A check to see if the terminating condition is true;
A procedural assignment to change value of the control variable
NOTE: for Loops are generally used when there is a fixed beginning
and end to the loop. If the Loop is simply looping on a certain
condition, it is better to use the while loop.
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forever loop
forever loop does not contain any expression and executes forever until the
$finish task is encountered. A forever loop can be exited by the use of the
disable statement.
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Assignment statements
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Blocking and Non-blocking assignment
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