INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic

Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

HEF4030B
gates
Quadruple exclusive-OR gate
Product specification January 1995
File under Integrated Circuits, IC04
Philips Semiconductors Product specification

HEF4030B
Quadruple exclusive-OR gate
gates

DESCRIPTION
The HEF4030B provides the positive quadruple
exclusive-OR function. The outputs are fully buffered for
highest noise immunity and pattern insensitivity of output
impedance.

Fig.2 Pinning diagram.

HEF4030BP(N): 14-lead DIL; plastic

(SOT27-1)
HEF4030BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4030BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.1 Functional diagram.

Fig.2 Logic diagram (one gate).

TRUTH TABLE FAMILY DATA, IDD LIMITS category GATES

I1 I2 O1 See Family Specifications

L L L
H L H
L H H
H H L

Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)

January 1995 2
Philips Semiconductors Product specification

HEF4030B
Quadruple exclusive-OR gate
gates

AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns

VDD TYPICAL EXTRAPOLATION

SYMBOL TYP. MAX.
V FORMULA
Propagation delays
In → On 5 85 175 ns 57 ns + (0,55 ns/pF) CL
HIGH to LOW 10 tPHL 35 75 ns 24 ns + (0,23 ns/pF) CL
15 30 55 ns 22 ns + (0,16 ns/pF) CL
5 75 150 ns 47 ns + (0,55 ns/pF) CL
LOW to HIGH 10 tPLH 30 65 ns 19 ns + (0,23 ns/pF) CL
15 25 50 ns 17 ns + (0,16 ns/pF) CL
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL
HIGH to LOW 10 tTHL 30 60 ns 9 ns + (0,42 ns/pF) CL
15 20 40 ns 6 ns + (0,28 ns/pF) CL
5 60 120 ns 10 ns + (1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns + (0,42 ns/pF) CL
15 20 40 ns 6 ns + (0,28 ns/pF) CL

VDD
TYPICAL FORMULA FOR P (µW)
V
Dynamic power 5 1 100 fi + ∑(fo CL) × VDD2 where
dissipation per 10 4 900 fi + ∑(fo CL) × VDD2 fi = input freq. (MHz)
package (P) 15 14 400 fi + ∑(fo CL) × VDD 2 fo = output freq. (MHz)
CL = load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)

January 1995 3
Philips Semiconductors

Package information Package outlines

SO

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

D E A
X

y HE v M A

14 8

Q
A2
(A 3) A
A1
pin 1 index
θ
Lp

1 7 L

e w M detail X
bp

0 2.5 5 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ

0.25 1.45 0.49 0.25 8.75 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 o
0.10 1.25 0.36 0.19 8.55 3.8 5.8 0.4 0.6 0.3 8
0.010 0.057 0.019 0.0100 0.35 0.16 0.244 0.039 0.028 0.028 0o
inches 0.069 0.01 0.050 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.34 0.15 0.228 0.016 0.024 0.012

Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION

95-01-23
SOT108-1 076E06S MS-012AB
97-05-22

January 1995 3