1

An Improved FPGA Implementation of Direct

Torque Control for Induction Machines
Tole Sutikno, Member, IEEE, Nik Rumzi Nik Idris, Senior Member, IEEE, Auzani Jidin, Member,
IEEE, and Marcian N. Cirstea, Senior Member, IEEE

 computation approach, this is impossible to achieve due to the

Abstract—This paper presents a novel direct torque control delay between the torque sampling instant and the instant the
(DTC) approach for induction machines, based on an improved corresponding switching status is passed to the inverter [2].
torque and stator flux estimator and its implementation using The ripple might exceed beyond the hysteresis bands, and
Field Programmable Gate Arrays (FPGA). The DTC
hence tends to select the reverse voltage vector that causes
performance is significantly improved by the use of FPGA, which
can execute the DTC algorithm at higher sampling frequency. rapid increase/decrease of the torque [3]. This, consequently,
This leads to the reduction of the torque ripple and improved will produce larger torque ripples and slightly degrade the
flux and torque estimations. The main achievements are: i) performance of DTC. Several methods were proposed to
calculating a discrete integration operation of stator flux using minimize the output torque ripple. These include the use of
backward Euler approach, ii) modifying a so called non-restoring space vector modulation (SVM) [4-7], the injection of
method in calculating the complicated square root operation in
dithering signal [8], the use of constant carrier frequency [3]
stator flux estimator, iii) introducing a new flux sector
determination method, iv) increasing the sampling frequency to and recently, the hysteresis based DTC with predictive control
200kHz such that the digital computation will perform similar to [9-12]. All these methods require knowledge and
that of the analog operation, and v) using two’s complement modifications of machine parameters which will complicate
fixed-point format approach to minimize calculation errors and the simple DTC structure and will increase its control
the hardware resource usage in all operations. The design was sensitivity. Moreover, the same effectiveness in minimizing
achieved in VHDL, based on a Matlab/Simulink simulation
the output torque ripple using those methods can be achieved
model. The Hardware-In-the-Loop (HIL) method is used to
verify the functionality of the FPGA estimator. The simulation if a higher switching frequency is applied, with a high speed
results are validated experimentally. Thus, it is demonstrated processor.
that FPGA implementation of DTC drives can achieve excellent Traditionally, the DTC algorithm is executed using a Digital
performance at high sampling frequency. Signal Processor (DSP) [13-15], with code written using C-
programming or a graphical programming approach, a much
Index Terms—Direct Torque Control, Field Programmable simpler method, appropriate for rapid prototyping. It should be
Gate Arrays, Induction Machine, VHDL
noted that the sampling frequency of the processor depends on
the computational burden. For the basic DTC algorithm,
I. INTRODUCTION normally the sampling frequency of the DSP (e.g. DSPACE
1104 or TMS C2000 series) can reach up to 20 kHz. This,
D IRECT Torque Control (DTC) of machine drives has
gained popularity since it can provide fast instantaneous
torque control with simple control structure. The original DTC
however, is still insufficient to operate the discrete hysteresis
controller, similar to that of analog/continuous hysteresis
system, so that the output torque ripple can be restricted within
scheme was proposed by Takahashi in 1986 [1] and uses the band, even when it operates at the worst conditions (i.e. at
hysteresis controllers to control independently both the stator very low speeds that cause extreme torque slope).
flux and the torque. Ideally, the error or ripple of the torque Some works used a combination of DSP and Field
(or flux) is restricted within the hysteresis band, so that the Programmable Gate Arrays (FPGA), reducing DSP’s
output torque (or flux) will satisfy its demand. However, in computational burden by distributing some DTC algorithm
practice, as the hysteresis controller follows a discrete tasks (look-up table, blanking time generator and hysteresis
controllers) to the FPGA. Thus, the sampling period to execute
Manuscript received December 15, 2011. This work was supported in part
by the Universiti Teknologi Malaysia under Grant VOT 78584. the overall DTC algorithms can be minimized to the output
T. Sutikno is with the Electrical Engineering Department, Universitas torque ripple [16-18]. However, the combination of controllers
Ahmad Dahlan, Yogyakarta, Indonesia. He is currently pursuing for his PhD increases the cost and complexity of the interfacing circuit,
at Universiti Teknologi Malaysia. (email: tole@ee.uad.ac.id).
N. R. N. Idris is with the Energy Conversion Department, Universiti and is not a practical solution for commercialization purposes.
Teknologi Malaysia (UTM), Johor, Malaysia (corresponding author, phone: Some attempts [19-20] implemented entire DTC algorithms on
60-755-36139; fax: 60-755-66272; e-mail: nikrumzi@ieee.org). a single FPGA but the HD coding there was generated using
A. Jidin is with the Power Electronics and Drives Department, Universiti
Teknikal Malaysia Melaka, Melaka, Malaysia (e-mail: auzani@ieee.org).
third party packages , i.e. MATLAB/Simulink, with the Xilinx
M. Cirstea is with the Computing and Technology Department, Anglia System Generator Fixed-point toolbox, which is not fully
Ruskin University, Cambridge, UK (e-mail: marcian@ieee.org).
 2

optimized to achieve fast sampling frequency. Work [20] φs : stator flux linkage space vectors in stationary reference frame
reports significant max. sampling frequency improvement to φr : rotor flux linkage space vectors in stationary reference frame
twice of that obtained with a DSP (which is 40 kHz). ωr : rotor electrical speed in rad/s
vs : stator voltage space vector in stationary reference frame
This paper presents an effective way to design, simulate and
implement the flux and torque estimations for hysteresis-based
Te,ref + ΔHBTe
DTC utilizing FPGAs. The main contribution of this paper is
the development of the flux and torque estimators using (a) Te,ref
VHDL code on the FPGA (i.e. from scratch), the code being
Te,ref - ΔHBTe
optimized to achieve a sampling frequency of 200 kHz. With
the highest sampling frequency, it is therefore possible for the Te,ref + ΔHBTe
torque ripple to be restricted within its hysteresis band and (b) Te,ref
hence minimize the ripple by reducing the band size.
Te,ref - ΔHBTe
Moreover, the performance of flux estimation as well as the
inherent current control in DTC system can be improved. Te,ref + ΔHBTe
Taking this into account, the estimations in DTC are the main Te,ref
parts to be implemented using FPGA, as they involve complex (c)
Te,ref - ΔHBTe
calculations (e.g. integrals, square-root, multiplication and
precise current scaling factor). The optimized VHDL code DT

design will be based on the MATLAB simulation model, Fig. 1. The waveforms of output torque sampled at DT in the hysteresis
where the type of data, number of bits (resolution), sampling comparator for (a) low speed, (b) middle speed and (c) high speed
time, scaling factor performed in simulation are similar to that
of FPGA implementation. The estimations of stator flux and
To illustrate this, waveforms of discretized electromagnetic
torque in the DTC of the induction machine will be presented
torque under 3 different steady-state operating conditions are
in Section II. The equations of stator flux and torque in
shown in Fig. 1. These are drawn so that only the effects of
discrete form and sector identification will be given in Section
motor speed and the applied voltage are considered. During
III. Section IV will present the description of the estimations
the positive torque slope, the active voltage vector is applied;
using MATLAB simulation and Modelsim Altera simulation.
otherwise, the zero voltage vector is selected. It can be noticed
Finally, the simulation and experimental results are compared,
that the torque slopes (for positive and negative slopes) vary
to verify code/design effectiveness at the highest sampling
with the operating speed. As a result, the torque switching
frequency.
frequency and hence the VSI switching frequency also vary
with operating conditions. Thus, it is common practice to
II. MAJOR PROBLEM IN HYSTERESIS-BASED DTC
select the device with switching capability based on the worst
Despite its simplicity, the DTC based on hysteresis case of operating conditions.
controller causes some major problems such as variable
inverter switching frequency, high torque ripple and high B. High torque ripple
sampling requirement for digital implementation [3-8]. These In digital implementation, the output torque is calculated,
problems are briefly described as follows. and the appropriate switching states are determined at fixed
sampling time (DT in Fig. 1). This, however, causes a delay
A. Variable inverter switching frequency between the instant the variables are sampled and the instant
In hysteresis-based DTC, the switching frequency of a VSI in which the corresponding switching status is passed to the
is mainly governed by the switching of the torque hysteresis inverter, therefore, the torque ripple cannot be restricted
comparator. The slope of the torque waveform, which directly exactly within the hysteresis band. If the band is set to be too
affects the switching of the hysteresis comparator, vary with small, the overshoot of the torque beyond the hysteresis band
the operating conditions (rotor speed, stator and rotor fluxes, could cause a reverse active voltage vector selection, instead
DC link voltage) [5]. This can be seen from the discrete form of a zero voltage vector selection. The selection of the reverse
of the torque equation given by (1): voltage vector causes the torque to decrease rapidly and as a
result the torque ripple increases [8, 18, 21-24]. This situation
Te,n 1  Te,n  1 1 
Torque slope    Te,n   

is illustrated in Fig. 1(a).
Δt στ
 s στ r 
(1) C. The need for high speed processor
P m vs,n  jωr  s,n   j r,n 
3 L
Reducing torque ripple by lowering the band width of
2 σLs Lr hysteresis comparator would be fruitless when the processor
where: used has a limited sampling frequency. All the constraints
Te : electromagnetic torque P : number of pole pairs which have been mentioned above can be eliminated if a high-
∆t : small value Lm : mutual inductance
σ : total flux leakage factor Ls : stator self-inductance
speed processor is utilized, where the discrete hysteresis
τs : stator time constant Lr : rotor self-inductance controller performs closer to the operation of an analog based
τr : rotor time constant
J : moment of inertia comparator. As shown in Fig. 1(a) and discussed in sub-
 3

section B, the rapid decrease of torque due to the selection of

reverse voltage vector can be avoided if the sampling time
(DT) is sufficiently reduced.

III. PROPOSED DIRECT TORQUE CONTROL

Fig. 2 shows a simple structure of hysteresis-based DTC by
Takahashi [1]. A decoupled control of torque and flux was
established to permit fast instantaneous control. The stator flux
is controlled using a 2-level hysteresis comparator, while the
electromagnetic torque is controlled using a 3-level hysteresis
comparator. The outputs of the comparators, along with sector
flux information, are used to index the look-up Table, to select
the appropriate voltage vectors to control simultaneously both Fig. 2. Control structure of DTC based induction machine
the stator flux and the torque. The most significant element
that can guarantee a satisfactory DTC performance is the IV. DESIGN OF TORQUE AND STATOR FLUX ESTIMATOR
estimation of the stator flux and the torque. A. Proposed Method to Improve Torque and Stator Flux
In order to estimate the stator flux and the electromagnetic Estimator
torque, several parameters need to be determined. The This paper presents an improved FPGA-based torque and
mathematical model to be used is tailored to the needs of stator flux estimator for DTC induction motor drives, which
controlled drives [25]. Firstly, the stator currents from the permits very fast calculations. The improvements are
motor Ia and Ib, are transformed into α-β coordinates [26], performed by: i) calculation of the discrete integration
which are adequately suited to the DTC algorithm, as follows: operation of the stator flux using backward Euler approach; ii)
I  I a (2) reducing the sampling time down to 5µs; to avoid saturation
due to DC offset present in the sensed currents, the LPF Filter
3
I  ( I a  2Ib ) (3) is applied; iii) modifying the non-restoring method to calculate
3 complicated square root operation of the stator flux; iv)
At the same time, by using the switching status (Sa, Sb and introducing a new sector judgment method. In all operations
Sc) produced by the switching table, the stator voltages in the of FPGA implementation, the two’s complement fixed-point
α-β reference frame are determined: format approach is used in order to minimize calculation
errors and the hardware resources usage.
Vdc
V  ( 2 S a  Sb  S c ) (4) 1. Fixed-point Arithmetic
3
A fixed-point variable consists of a binary pattern which is
3 encoded in two’s complement number, and a binary point. It is
V  Vdc ( Sb  S c ) (5)
3 a way to encode negative numbers into ordinary binary. The
Then, using the calculated Iα, Iβ, Vα and Vβ, the estimation of size of the binary pattern and the location of the binary point
the stator flux in α-β coordinates is performed as follows: are specified using three parameters, namely: sign bit, integer
word length (IWL) and fraction word length (FWL). The total
  old  ( V  RS I )Ts (6) number of binary pattern bits is well-known as word length
    old  ( V  RS I  )Ts (7) (WL). The approach can represent numbers in the range [-
2IWL, 2IWL] with a step size of 2-FWL. When using this
Finally, equation (8) calculates the flux magnitude by using a arithmetic, the most important aspect is always to consider the
square root calculation, whereas the electromagnetic torque is binary point location for every variable. VHDL has supported
estimated through equation (9). the fixed-point arithmetic operations, and designers have some
manipulation flexibility to improve performance.
 s  2   2 (8)
2. Backward Euler Approach
3
Te  P( I    I   ) (9) The discrete backward Euler formula is
4
y( n )  y( n  1 )  k .T .u( n ) . It is simpler for FPGA
The original scheme is based on hysteresis controllers, where hardware implementation, comparing to the forward Euler and
the output status from the controllers, together with the sector Trapezoidal method in that they require the register to store
flux information, are used to select the optimized voltage the previous value of u( n  1 ) function. The backward Euler
vectors from the look-up table to satisfy simultaneously both integration method also can to maintain the system stability in
flux and torque references. The flux vector is controlled to the large step size. Therefore, the discrete backward Euler
form a circular flux shape. integration method is chosen to calculate the quadrature flux
(  and   ).
 4

3. LP Filter
Notice that Rs is the estimated stator resistance, while Ts is Through the simplification, it will be possible to get simpler
the implementation sampling time. Works [27-28] suggested logic of the sector analysis for FPGA implementation through
that a filter should be added to the integrator in the practical VHDL gate level coding; each sector is represented on 3-bits.
implementation to avoid integration drift problem due to the
DC offset in the sensed currents. The stator flux equations are: B. The Design Flow
  ( old  ( V  RS I )Ts )( 1  c * Ts ) (10) The validation of the designed torque and flux estimators
   (  old  ( V  RS I  )Ts )( 1  c * Ts ) (11) was performed by using the Hardware-in-the-Loop (HiL)
method. The DTC MATLAB/Simulink model was simulated
4. Non-restoring Square Root Algorithm and then, the same data Ia, Ib, Sa, Sb, and Sc used for the
In DTC drives, the stator flux (  s ) is calculated as square simulation, was copied from the MATLAB workspace to
VHDL codes, along with the inputs for the targeted FPGA.
root of the quadrature flux magnitude. To calculate the stator
The VHDL codes were simulated in ModelSim-Altera before
flux (  s ), the non-restoring square root algorithm, proposed being synthesized and implemented in FPGA.
by [29], is modified as below (D=radicand, q=quotient,
r=remainder, and n=half of the radicand word size): V. MATLAB AND MODELSIM-ALTERA SIMULATIONS
r0  1 ( n 2  2bits ) In order to verify the torque and stator flux estimator
q0  0 (n 2  1bits )
models, a comprehensive DTC simulation was conducted. in
For i=0 to n-1 do: Matlab/Simulink (Fig. 3). The upper model is a standard
If ri  0 then model (which is not ready yet to be implemented in FPGA)
 
ri 1  4ri  D( n  2i )1 D( n  2i ) 2  ( 4qi  1 ) and the lower model is generated as one ready to be
implemented in FPGA. The simulations of the DTC model,
else
 
ri 1  4ri  D( n  2i )1D( n  2i ) 2  ( 4qi  3 )
which perform double-precision calculations, are used as
references to digital computations executed in FPGA
If ri  1 0 implementation.
qi 1  2qi  1 The standard Simulink models are not ready as direct FPGA
else design input, , the designer must prepare them, as the FPGA
qi 1  2qi programming will be conducted in two’s complement. In
principle, the procedure is similar with the one in [19, 32],
The square root result is qn( n 2 -1 downto 0), coded in n
2 bits. which is aimed to use a minimum number of operators that
process a maximum number of operations.
5. New Sector Identification The DTC model was simulated in Matlab/Simulink and
The present work has created a simpler method to analyze then the same data (Ia, Ib, Sa, Sb and Sc) used for the simulation
the sectors of the voltage vector, based on a comparison was copied from the Matlab workspace to VHDL code, as
between   , 3 , 3 and 0, which is modified from [30]. well as the inputs for the targeted FPGA. The VHDL codes
were simulated in ModelSim-Altera before being synthesized
With the comparison, it is simpler to determine the sector of
and implemented in FPGA. However, the stage is optional.
the voltage vector, compared to the conventional methods of
From Matlab simulation, the designers can go the to FPGA
using arc tan of angle, three stages comparison based on
implementation stage, without using ModelSim-Altera
 ,  or determination of angle using CORDIC algorithm
simulation stage. Quartus simulation environment can be used
[31]. The proposed method is single stage, based on the fact to verify the design.
that three comparisons are performed in parallel, without angle
calculation, so that faster computation is achieved and less VI. FPGA IMPLEMENTATION OF THE TORQUE AND FLUX
incorrect voltage vector selections. Table I shows the ESTIMATORS
Karnaugh map of the proposed sector identification.
The algorithm of torque and flux estimation is implemented
TABLE I
KARNAUGH MAP OF THE PROPOSED SIMPLER IDENTIFICATION OF in an architecture consisting of six main blocks, as shown in
THE SECTORS Fig. 4. This architecture has six inputs: two 21-bit currents (Ia
INPUT OUTPUT and Ib), 12-bit high voltage DC-supply (Vdc) and three
 > 0  > 3   >  3 
(sector) switching statuses Sa, Sb and Sc. At the end, it produces three
0 0 0 101 outputs: the estimation values of torque (T e), flux (  s ) and
0 1 0 110 sector. The sampling time chosen is 5 µs, which is limited by
0 0 1 100
the ADC used.
0 1 1 ddd
1 0 0 ddd A. The Architecture of Torque and Flux Estimator
1 1 0 001
1 0 1 011 All the equations modeling the motor’s behavior are
1 1 1 010 implemented in a two-stage-pipelined architecture, as in Fig. 5
 5

Fig. 3. Control structure of DTC based induction machine

VII. FPGA IMPLEMENTATION OF THE TORQUE AND FLUX

ESTIMATORS
The algorithm of torque and flux estimation is implemented
in an architecture consisting of six main blocks, as shown in
Fig. 4. This architecture has six inputs: two 21-bit currents (Ia
and Ib), 12-bit high voltage DC-supply (Vdc) and three
switching statuses Sa, Sb and Sc. At the end, it produces three Fig. 4. Block Diagram of torque and flux estimators.
outputs: the estimation values of torque (Te), flux (  s ) and
sector. The sampling time chosen is 5 µs, which is limited by µs to 10 µs.
the ADC used.
B. The Digital Properties of the Torque and Flux
A. The Architecture of Torque and Flux Estimator Estimators
All the equations modeling the motor’s behavior are To achieve a good implementation, several digital
implemented in a two-stage-pipelined architecture, as properties need to be considered when designing these
presented in Fig. 5. Several mathematical operations are estimators. Adopted binary format, quantization and sampling
performed in parallel. At the first stage, stator currents and time are amongst the key factors.
voltages in αβ-coordinates are calculated in parallel, so that 1. Binary format representation
those results can be used to estimate the stator flux in the same In this implementation, two’s complement fixed-point
stage. The resulted currents and flux are used to determine the representation is used during all the operations, except for the
flux magnitude and the torque estimation in the second stage. square root calculation. In that particular case, unsigned fixed-
A 62-bit non-restoring square root is implemented in order to point representation is applied, since its operand and its results
compute the flux magnitude. are always positive.
Paper [20] has proposed that a three-stage-pipelined
architecture should be implemented in this module, by 2. Quantization
separating the computation of stator currents and voltages The determination of word size (word length) is one of the
from the estimation of the stator flux. However, the former critical parts in FPGA implementation. On one hand, the use
can be considered as an immediate calculation and therefore, of an insufficient number of bits may reduce the precision or
those calculations can be merged into a single stage. As a cause a calculation error, which can unstabilize the whole
consequence, the latency of the estimator is reduced from 15 system. On the other hand, the use of larger words may
increase the hardware implementation area.
 6
[5.12] [7.12] [6.12]
[6.12] iβ [6.29]
[6.20]
[7.12]

[6.12]
[5.12] [6.12] [6.12]
iα [11.12]
[11.12] [1.27] [1.27]

[8.54]
[4.27] [4.27]
[10.12] [8.54]
[4.13]
Vβ
[11.12]
φβ
[11.12] [1.27] [1.27]
[4.27]
[8.54]
[10.12]
Vα
φα

Fig. 5. The architecture of torque and flux estimators.

iα[17..0]
The efficient implementation of the algorithms largely
depends on the designer’s experience [33]. Therefore, the
paper offers a simpler arithmetic concept based on two’s
iβ[17..0]
complement fixed-point format for VHDL programming.

2. Vα and Vβ Calculation
The function of this block is to calculate the stator voltages
in α-β components - refer to equations (4) and (5). The input is
Fig. 6. Block Arithmetic unit of the Iα and Iβ calculations 12-bit high voltage DC-supply and three switching status. The
output voltages are represented in 22-bit two’s-complement
fixed-point format [10.12]. The RTL viewer of the calculation
3. Sampling time
The sampling time Ts is limited to 5 µs by the ADC used. is shown in Fig. 7. The numbers “19’ h24F35” and “19’
√
Therefore, all the operations involved in this model were h15555” are to represent and in equation (4) and (5)
performed within this sampling time.
respectively. In these cases represent 87381 (i.e ) and
√
C. The VHDL Design of the Torque and Stator Flux 151349 (i.e ) respectively in binary 19-bits, each as
Estimators [1.18]. It is important to be known that the results (before
The algorithm of stator flux and torque estimator is truncated) of the Vα and Vβ are allocated each to 34-bit, as
implemented in an architecture consisting of seven blocks: [16.18], but the final values of the Vα and Vβ are only 22-bit.
1. Iα and Iβ Calculation The most significant 9-bit and lest significant 6-bit of each the
The function of this block is to transform the stator currents Vα and Vβ 34-bits are truncated, so only 27th – 6th bits are used
from the motor Ia and Ib into α-β coordinates (Iα and Iβ) refer to to represent the final values of each the Vα and Vβ as 22-bit,
equation (1) and (2). In this design, the values (I a, Ib) and (Iα i.e. [10.12]. The truncations are conducted to minimize
and Iβ) are represented on 17-bits and 18-bits two’s- hardware resources, while still retaining sufficient precision.
complement fixed-point format [5.12 bit] and [6.12 bit] Once again, the tailoring and adaptation made by the designers
respectively to get the precise values. As shown in Fig. 5, to are very important here.
avoid overflow that the result calculation of “Ia+2Ib” and 1
3
3 3.  s Calculation
of the equation (2) are represented each on 19 bits, as [7.12] a.  and   Calculation
1
and [1.18] respectively. The part of 3
3 of the equation (2) is After the calculation of α-β components of current and
voltage, the α-β flux is calculated in this block (refer to
represented as 151349 (i.e 1
3 x 218 ). In Fig. 6, the value of
3 equation (6) and (7)). The other input, Rs, is represented on 10-
1
3 x 218 is represented as “19’ h24F35” (the 19 is number bits (5.5 bit). The output α-β components of the stator flux are
3
represented in 31-bit two’s-complement fixed-point format
of bits, and the h24F35 is value of 151349 in hexadecimal). [4.27]. In this paper, the sampling time (T s) is 5 µs. The value
The output of the signed multiplier is represented on 38-bits, of Ts is represented in [1.27] as “28’ h000029F” (=671), and
as [8.30]. However, the Iβ is only represented on 18-bits as therefore the sampling time of 5 µs will be calculated as
[6.12] to minimize hardware resource, so the 38-bit [8.30] is 4.99934 µs (671/227 ≈ 0,00000499934 s). Consider the
truncated to become 18-bit [6.12]. Based on the evaluation
result, the 18-bit has been considered suitable to represent Iβ ( 1  c * Ts ) filter part of equation (9) and (10), the part is
precisely. Here, the “tailor made” experience of designers is selected: 0.999975. In this case, the value is represented in
very important in order to develop the VHDL code effectively. [1.22] as “23’ h3FFF97“ (=4194199), so 0.999974966 will be
 7

Fig. 10. RTL viewer of the Torque Calculator

(a)
Fig. 7. RTL viewer of the VD and VQ calculations

(b)
Fig. 11. The effect sampling time to torque ripple;
(a) Estimated torque for Ts=50µs, (b) Estimated torque for Ts=5µs.

DTC - FPGA

T* + Torque
Fig. 8. RTL viewer of the magnitude calculator hysteresis Voltage
- comparator vector
Test
Look-up
+ table
φ* Flux hysteresis
comparator
-
φest
sector
Test Stator flux and torque
φest estimators

ia ib ic Vdc
Sa
Te Induction machine
Sb
look-up table-based
φs simulator (FPGA) Sc

Fig. 12. HiL implementation of DTC

Fig. 9. RTL viewer of the sector judgment c. Square Root Calculation

This block is design to calculate stator flux (  s ) using
obtained to represent the 0.999975 filter. The filter is designed
modified non-restoring square root algorithm. The first output
to overcome the problem of integration drift. Therefore, the
of the block is represented in 31 bit fixed-point format, and
low-pass filter is used to replace the pure integrator with
then it is truncated to 17 bit (4.13 bit). The principle of the
appropriate cut-off frequency.
calculation is based on the powerful improved method
b. Magnitude Calculation presented in reference [34], which is created by authors
This block is designed to calculate the magnitude of the originally, and can be used in general applications.
stator flux. The inputs of the block are the α-β components of 4. Determination of Sector
stator flux, and the output is their magnitude, which is The work has created a simpler method to judge the sector
represented in 62 bit fixed-point format (8.54 bit). The RTL voltage vector, based on a comparison refered to in Table II,
viewer for the magnitude calculation is shown in Fig. 8. which is modified from [30]. By using Karnaugh map
 8

simplification, it only involves two comparisons (not three this paper, with other works, are shown in Table II.
comparisons). The RTL viewer of the sector judgment is
TABLE II
shown in Fig. 9. COMPARISON OF THE LES CONSUMPTION
No Reference LEs DTC sampling
5. Torque Calculation consumption period (kHz)
The function of this block is to calculate torque - refer to 1 Ferreira [20] 4,100 40
equation (8). The output is represented on 55 bits [14.41] 2 Llor [36] 3,901 40
3 Utsumi [37]
fixed-point format, and then it is truncated to 26 bits [6.20]. - Type A controller 3,737 20
The RTL magnitude calculation viewer is shown in Fig. 10. - Type B controller 5,622 40
4 Bossoufi [38] 3,166 20
D. Synchronizations 5 Proposed 2,093 200
In the proposed architecture of the torque and flux As an alternative solution to the implementation, a low cost
estimators, synchronizations are conducted in two stages. The FPGA devices, such as from Cyclone family, can be used. For
first stage is used to synchronize the output of α-β stator example Altera DE2 board which offers a rich set of features
currents ( i and i  ) and α-β stator fluxes (   and   ), and the is suitable for sophisticated digital systems implementation.
second stage to synchronize the flux magnitude ( Te ) and the APEX EP20K200EFC484-2X was used for our
implementation due to the availability of this device/board in
electromagnetic torque (  s ). It is very important to consider our laboratory during the development of the system.
that the delay or un-synchrony in estimating the flux and
torque, becomes the root case where the switching frequency
can’t be raised.
The synchronizations are designed in one cycle of the
sampling time (in this case 5 µs), same with the sampling time.
By using the low sampling time (high switching frequency) like
this, the torque ripple can be reduced significantly. In other
words, the undesired overshoot or undershoot in torque can be
minimized by employing a faster sampling time. The 5 µs
sampling time (in the flux and torque estimators) is only
possible to be conducted/achieved by employing FPGA, and it
is not possible to use microprocessors or DSPs in current
condition. The one cycle synchronizations also have a function
as buffer, so that the parameters can be loaded to the buffer in
each clock cycle. The similar data-path and buffering concept
have been introduced in [35], for application to an automatic
speech recognition system based on FPGA.

VIII. RESULTS AND DISCUSSION

A. Effect of the sampling time to torque ripple
In the implementation of the DTC drive based on an FPGA,
there are many digital properties which need considering, such
as binary format representation (data type), quantization,
sampling time and word length (size). In fact, errors or
inaccuracies which are due to these digital problems can affect
seriously the performance of the drive. For example, the effect
of the sampling time on the torque ripple can be reduced from
2N-m to 0.2N-m by changing the sampling time from 50µs to
5µs, as shown in Fig. 11. Such digital properties have been
considered in the research.
B. Performance Analysis through Simulation and
Experimental results
The experiments were conducted on Altera APEX
EP20K200EFC484-2x, and consumes 2093 logic elements for
the implementation. The comparisons of the area (LEs)
consumption between the results of the research presented in
 9

the torque and flux estimator, obviously this contribution has

been eagerly awaited by researchers to support, enable and
take forward their DTC improvements.

IX. CONCLUSIONS
(a) This paper has achieved the reduction of the sampling time
(to increase the sampling frequency) by using FPGAs, so that
the appropriate value of the band width of the hysteresis
comparator can be achieved. The technique will retain the
simple control structures of the DTC drive. The paper
presented an effective way to design, simulate and implement
hysteresis-based DTC utilizing FPGAs. All modules in the
(b) system have been designed in fully generic VHDL code,
Fig. 13. The comparison between MATLAB/Simulink simulation and which is independent of the FPGA target implementation
experimental result for torque estimation. (a) MATLAB/Simulink technology. All calculations in the modules are conducted in
simulation, (b) FPGA based experimental result two's complement fixed-point arithmetic with appropriate
word sizes. The choice of word sizes, the binary format and
the sampling time used are very important in order to achieve
a good implementation of the estimators. To get simpler
implementation and fast computation, several methods were
introduced: i) the backward Euler approach to calculate the
discrete integration operation of stator flux, ii) the modified
non-restoring method to calculate complicated square root
operation of stator flux, iii) a new sector analysis method; the
(a) (b) simulation results of the DTC model in MATLAB/Simulink,
Fig. 14. The comparison between MATLAB/Simulink simulation and the
experimental result for flux locus. (a) MATLAB/Simulink simulation, TABLE III
(b) FPGA based experimental result INDUCTION MACHINE PARAMETERS
Parameters Type or values
Rotor type Squirrel-cage
The tests have taken place only during certain periods of Nominal power 2425 VA
motor’s steady state and the results were observed on the Voltage (line to line) 400 V
oscilloscope. The experiment results are based on hardware- Frequency 50 Hz
Stator resistance, Rs 5.5 ohm
in-the-loop (HiL). In order to evaluate these FPGA-based
Rotor resistance, Rr 4.45 ohm
estimators and controller, the induction machine is simulated Stator self inductance, Ls 0.0149 H
using the FPGA device. The induction motor is modeled based Rotor self inductance, Lr 0.0149 H
on look-up table whereby the motor currents are generated Mutual inductance, Lm 0.299 H
based on the switching status generated by the DTC controller Combined inertia, J 0.00925 kg-m2
Combined viscous friction, B 0.006 N.m.s
and the DC link voltage. The HiL set-up is illustrated in Number of pole pairs, P 2
Fig. 12 and the parameters used for the simulation and HiL are
listed in Table III. Thereafter, the results were compared to the
which performed double-precision calculations, are used as
validated MATLAB/Simulink simulations (carried out in
references to digital computations executed in FPGA
double precision). Fig. 13 and Fig. 14 show some comparison
implementation. The Hardware-in-the-loop (HIL) method is
results between MATLAB/Simulink simulations and the
used to verify the minimal error between MATLAB/Simulink
experimental results. The conclusion is that of a fairly good
simulation and the experimental results. The design, which
match, It is important to know that the experimental outputs
was coded in synthesizable VHDL code for implementation
are displayed through a 12-bit DAC. So, all outputs are
on Altera APEX20K200EFC484-2x device, has produced very
truncated within 12-bits. Therefore, it is fair to accept that the
good estimations, giving minimal errors when being compared
outputs are not perfectly the same as the simulation outputs.
to MATLAB/Simulink double-precision calculations.
However, the results have proved that the proposed FPGA
implementation of the torque and stator flux estimators was
successful. This means that the main problem - "the heart of ACKNOWLEDGMENT
the DTC" of the FPGA implementation - has been resolved. The authors would like to thank the Universiti Teknologi
All units in the system have been designed in fully generic Malaysia (UTM) for providing the funding for this research.
VHDL code, independent of the target implementation
technology, without the need for third party products or
special FPGAs. Given that most of the DTC research solutions
have limitations on the performance of the implementation of
 10

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