DS1302

Trickle Charge Timekeeping Chip

www.dalsemi.com

FEATURES PIN ASSIGNMENT

Real time clock counts seconds, minutes,
V CC2 1 8 V CC1
hours, date of the month, month, day of the
X1 2 7 SCLK
week, and year with leap year compensation
X2 3 6 I/O
valid up to 2100
GND 4 5 RST
31 x 8 RAM for scratchpad data storage
Serial I/O for minimum pin count DS1302
2.05.5 volt full operation 8-Pin DIP (300-Mil)
Uses less than 300 nA at 2.0 volts
Singlebyte or multiplebyte (burst mode) V CC2 1 8 V CC1
data transfer for read or write of clock or X1 2 7 SCLK
RAM data X2 3 6 I/O
8pin DIP or optional 8pin SOICs for GND 4 5 RST
surface mount
DS1302S 8-Pin SOIC (200-Mil)
Simple 3wire interface
DS1302Z 8-Pin SOIC (150-Mil)
TTLcompatible (VCC = 5V)
Optional industrial temperature range 40C
to +85C PIN DESCRIPTION
DS1202 compatible X1, X2 32.768 kHz Crystal Pins
Added features over DS1202 GND Ground
Optional trickle charge capability to VCC1 RST Reset
Dual power supply pins for primary and I/O Data Input/Output
backup power supplies SCLK Serial Clock
Backup power supply pin can be used for VCC1 , VCC2 Power Supply Pins
battery or super cap input
Additional scratchpad memory (7 bytes)
ORDERING INFORMATION
PART # DESCRIPTION
DS1302 Serial Timekeeping Chip;
8pin DIP
DS1302S Serial Timekeeping Chip;
8pin SOIC (200-mil)
DS1302Z Serial Timekeeping Chip;
8pin SOIC (150-mil)

DESCRIPTION
The DS1302 Trickle Charge Timekeeping Chip contains a real time clock/calendar and 31 bytes of static
RAM. It communicates with a microprocessor via a simple serial interface. The real time clock/calendar
provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is
automatically adjusted for months with less than 31 days, including corrections for leap year. The clock
operates in either the 24hour or 12hour format with an AM/PM indicator.

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Interfacing the DS1302 with a microprocessor is simplified by using synchronous serial communication.
Only three wires are required to communicate with the clock/RAM: (1) RST (Reset), (2) I/O (Data line),
and (3) SCLK (Serial clock). Data can be transferred to and from the clock/RAM 1 byte at a time or in a
burst of up to 31 bytes. The DS1302 is designed to operate on very low power and retain data and clock
information on less than 1 microwatt.

The DS1302 is the successor to the DS1202. In addition to the basic timekeeping functions of the
DS1202, the DS1302 has the additional features of dual power pins for primary and backup power
supplies, programmable trickle charger for VCC1 , and seven additional bytes of scratchpad memory.

OPERATION
The main elements of the Serial Timekeeper are shown in Figure 1: shift register, control logic, oscillator,
real time clock, and RAM. To initiate any transfer of data, RST is taken high and 8 bits are loaded into
the shift register providing both address and command information. Data is serially input on the rising
edge of the SCLK. The first 8 bits specify which of 40 bytes will be accessed, whether a read or write
cycle will take place, and whether a byte or burst mode transfer is to occur. After the first eight clock
cycles have loaded the command word into the shift register, additional clocks will output data for a read
or input data for a write. The number of clock pulses equals 8 plus 8 for byte mode or 8 plus up to 248 for
burst mode.

COMMAND BYTE
The command byte is shown in Figure 2. Each data transfer is initiated by a command byte. The MSB
(Bit 7) must be a logic 1. If it is 0, writes to the DS1302 will be disabled. Bit 6 specifies clock/calendar
data if logic 0 or RAM data if logic 1. Bits 1 through 5 specify the designated registers to be input or
output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic
1. The command byte is always input starting with the LSB (bit 0).

DS1302 BLOCK DIAGRAM Figure 1

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 DS1302
ADDRESS/COMMAND BYTE Figure 2

RESET AND CLOCK CONTROL

All data transfers are initiated by driving the RST input high. The RST input serves two functions. First,
RST turns on the control logic which allows access to the shift register for the address/command
sequence. Second, the RST signal provides a method of terminating either single byte or multiple byte
data transfer.

A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, data must be
valid during the rising edge of the clock and data bits are output on the falling edge of clock. If the RST
input is low all data transfer terminates and the I/O pin goes to a high impedance state. Data transfer is
illustrated in Figure 3. At powerup, RST must be a logic 0 until VCC ] 2.0 volts. Also SCLK must be at
a logic 0 when RST is driven to a logic 1 state.

DATA INPUT
Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge
of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data
is input starting with bit 0.

DATA OUTPUT
Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling
edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling
edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes
should they inadvertently occur so long as RST remains high. This operation permits continuous burst
mode read capability. Also, the I/O pin is tristated upon each rising edge of SCLK. Data is output
starting with bit 0.

BURST MODE
Burst mode may be specified for either the clock/calendar or the RAM registers by addressing location 31
decimal (address/command bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0
specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar
Registers or location 31 in the RAM registers. Reads or writes in burst mode start with bit 0 of address 0.

As in the case with the DS1202, when writing to the clock registers in the burst mode, the first eight
registers must be written in order for the data to be transferred. However, when writing to RAM in burst
mode it is not necessary to write all 31 bytes for the data to transfer. Each byte that is written to will be
transferred to RAM regardless of whether all 31 bytes are written or not.

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CLOCK/CALENDAR
The clock/calendar is contained in seven write/read registers as shown in Figure 4. Data contained in the
clock/ calendar registers is in binary coded decimal format (BCD).

CLOCK HALT FLAG

Bit 7 of the seconds register is defined as the clock halt flag. When this bit is set to logic 1, the clock
oscillator is stopped and the DS1302 is placed into a lowpower standby mode with a current drain of less
than 100 nanoamps. When this bit is written to logic 0, the clock will start. The initial power on state is
not defined.

AM-PM/12-24 MODE
Bit 7 of the hours register is defined as the 12 or 24hour mode select bit. When high, the 12hour mode
is selected. In the 12hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24hour mode,
bit 5 is the second 10-hour bit (20 23 hours).

WRITE PROTECT BIT

Bit 7 of the control register is the write-protect bit. The first seven bits (bits 0 6) are forced to 0 and will
always read a 0 when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high,
the write protect bit prevents a write operation to any other register. The initial power on state is not
defined. Therefore the WP bit should be cleared before attempting to write to the device.

TRICKLE CHARGE REGISTER

This register controls the trickle charge characteristics of the DS1302. The simplified schematic of Figure
5 shows the basic components of the trickle charger. The trickle charge select (TCS) bits (bits 4 7)
control the selection of the trickle charger. In order to prevent accidental enabling, only a pattern of 1010
will enable the trickle charger. All other patterns will disable the trickle charger. The DS1302 powers up
with the trickle charger disabled. The diode select (DS) bits (bits 2 3) select whether one diode or two
diodes are connected between VCC2 and VCC1 . If DS is 01, one diode is selected or if DS is 10, two diodes
are selected. If DS is 00 or 11, the trickle charger is disabled independently of TCS. The RS bits (bits 0
1) select the resistor that is connected between VCC2 and VCC1 . The resistor selected by the resistor select
(RS) bits is as follows:

RS Bits Resistor Typical Value

00 None None
01 R1 2K
10 R2 4K
11 R3 8K

If RS is 00, the trickle charger is disabled independently of TCS.

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Diode and resistor selection is determined by the user according to the maximum current desired for
battery or super cap charging. The maximum charging current can be calculated as illustrated in the
following example. Assume that a system power supply of 5V is applied to VCC2 and a super cap is
connected to VCC1 . Also assume that the trickle charger has been enabled with one diode and resistor R1
between VCC2 and VCC1 . The maximum current Imax would therefore be calculated as follows:
Imax = (5.0V diode drop) / R1
~ (5.0V 0.7V) / 2K
~ 2.2 mA
Obviously, as the super cap charges, the voltage drop between VCC2 and VCC1 will decrease and therefore
the charge current will decrease.

CLOCK/CALENDAR BURST MODE

The clock/calendar command byte specifies burst mode operation. In this mode the first eight
clock/calendar registers can be consecutively read or written (see Figure 4) starting with bit 0 of address
0.

If the write protect bit is set high when a write clock/calendar burst mode is specified, no data transfer
will occur to any of the eight clock/calendar registers (this includes the control register). The trickle
charger is not accessible in burst mode.

RAM
The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space.

RAM BURST MODE

The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be
consecutively read or written (see Figure 4) starting with bit 0 of address 0.

REGISTER SUMMARY
A register data format summary is shown in Figure 4.

CRYSTAL SELECTION
A 32.768 kHz crystal can be directly connected to the DS1302 via pins 2 and 3 (X1, X2). The crystal
selected for use should have a specified load capacitance (CL) of 6 pF. For more information on crystal
selection and crystal layout consideration, please consult Application Note 58, Crystal Considerations
with Dallas Real Time Clocks."

POWER CONTROL
VCC1 provides low power operation in single supply and battery operated systems as well as low power
battery backup.

VCC2 provides the primary power in dual supply systems where VCC1 is connected to a backup source to
maintain the time and data in the absence of primary power.

The DS1302 will operate from the larger of VCC1 or VCC2 . When VCC2 is greater than VCC1 + 0.2V, VCC2
will power the DS1302. When VCC2 is less than VCC1 , VCC1 will power the DS1302.
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DATA TRANSFER SUMMARY Figure 3

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REGISTER ADDRESS/DEFINITION Figure 4

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 DS1302
DS1302 PROGRAMMABLE TRICKLE CHARGER Figure 5

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ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground 0.5V to +7.0V
Operating Temperature 0C to 70C
Storage Temperature 55C to +125C
Soldering Temperature 260C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.

The Dallas Semiconductor DS1302 is built to the highest quality standards and manufactured for long-
term reliability. All Dallas Semiconductor devices are made using the same quality materials and
manufacturing methods. However, standard versions of the DS1302 are not exposed to environmental
stresses, such as burnin, that some industrial applications require. Products which have successfully
passed through this series of environmental stresses are marked IND or N, denoting their extended
operating temperature and reliability rating. For specific reliability information on this product, please
contact the factory in Dallas at (972) 3714448.

RECOMMENDED DC OPERATING CONDITIONS (0C to 70C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC1, 2.0 5.5 V 1, 11
Supply Voltage VCC1 , VCC2
VCC2
Logic 1 Input VIH 2.0 VCC+0.3 V 1
VCC=2.0V -0.3 +0.3
Logic 0 Input VIL V 1
VCC=5V 0.3 +0.3

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 DS1302
DC ELECTRICAL CHARACTERISTICS (0C to 70C; VCC = 2.0 to 5.5V*)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage ILI +500 A 6
I/O Leakage ILO +500 A 6
VCC=2.0V 1.6
Logic 1 Output VOH V 2
VCC=5V 2.4
VCC=2.0V 0.4
Logic 0 Output VOL V 3
VCC=5V 0.4
VCC1 =2.0V 0.4
Active Supply Current ICC1A mA 5, 12
VCC1 =5V 1.2
VCC1 =2.0V 0.3
Timekeeping Current ICC1T A 4, 12
VCC1 =5V 1
VCC1 =2.0V 100 10, 12,
Standby Current ICC1S nA
VCC1 =5V 100 14
VCC2 =2.0V 0.425
Active Supply Current ICC2A mA 5, 13
VCC2 =5V 1.28
VCC2 =2.0V 25.3
Timekeeping Current ICC2T A 4, 13
VCC2 =5V 81
VCC2 =2.0V 25
Standby Current ICC2S A 10, 13
VCC2 =5V 80
R1 2 K?
Trickle Charge Resistors R2 4 K?
R3 8 K?
Trickle Charge Diode Voltage Drop VT D 0.7 V
*Unless otherwise noted.

CAPACITANCE (t A = 25C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CI 10 pF
I/O Capacitance CI/O 15 pF
Crystal Capacitance CX 6 pF

AC ELECTRICAL CHARACTERISTICS (0C to 70C; VCC = 2.0 to 5.5V*)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC=2.0V 200
Data to CLK Setup tDC ns 7
VCC=5V 50
VCC=2.0V 280
CLK to Data Hold tCDH ns 7
VCC=5V 70
VCC=2.0V 800
CLK to Data Delay tCDD ns 7, 8, 9
VCC=5V 200
VCC=2.0V 1000
CLK Low Time tCL ns 7
VCC=5V 250
VCC=2.0V 1000
CLK High Time tCH ns 7
VCC=5V 250

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 DS1302
AC ELECTRICAL CHARACTERISTICS (contd) (0C to 70C; VCC = 2.0 to 5.5V*)
VCC=2.0V 0.5
CLK Frequency tCLK MHz 7
VCC=5V DC 2.0
VCC=2.0V 2000
CLK Rise and Fall tR, tF ns
VCC=5V 500
VCC=2.0V 4
RST to CLK Setup tCC s 7
VCC=5V 1
VCC=2.0V 240
CLK to RST Hold tCCH ns 7
VCC=5V 60
VCC=2.0V 4
RST Inactive Time tCWH s 7
VCC=5V 1
VCC=2.0V 280
RST to I/O High Z tCDZ ns 7
VCC=5V 70
VCC=2.0V 280
SCLK to I/O High Z tCCZ ns 7
VCC=5V 70
*Unless otherwise noted.

TIMING DIAGRAM: READ DATA TRANSFER Figure 5

TIMING DIAGRAM: WRITE DATA TRANSFER Figure 6

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NOTES:
1. All voltages are referenced to ground.
2. Logic one voltages are specified at a source current of 1 mA at VCC=5V and 0.4 mA at VCC=2.0V,
VOH=VCC for capacitive loads.
3. Logic zero voltages are specified at a sink current of 4 mA at VCC=5V and 1.5 mA at VCC=2.0V,
VOL=GND for capacitive loads.
4. ICC1T and ICC2T are specified with I/O open, RST set to a logic 0, and clock halt flag=0 (oscillator
enabled).
5. ICC1A and ICC2A are specified with the I/O pin open, RST high, SCLK=2 MHz at VCC=5V; SCLK=500
kHz, VCC=2.0V and clock halt flag=0 (oscillator enabled).
6. RST , SCLK, and I/O all have 40K? pulldown resistors to ground.
7. Measured at VIH=2.0V or VIL=0.8V and 10 ms maximum rise and fall time.
8. Measured at VOH=2.4V or VOL=0.4V.
9. Load capacitance = 50 pF.
10. ICC1S and ICC2S are specified with RST , I/O, and SCLK open. The clock halt flag must be set to logic
one (oscillator disabled).
11. VCC=VCC2 , when VCC2 >VCC1 +0.2V; VCC=VCC1 , when VCC1 >VCC2 .
12. VCC2 =0 volts.
13. VCC1 =0 volts.
14. Typical values are at 25C.

DS1302 SERIAL TIMEKEEPER 8PIN DIP (300-MIL)

PKG 8-PIN
DIM MIN MAX
A IN. 0.360 0.400
MM 9.14 10.16
B IN. 0.240 0.260
MM 6.10 6.60
C IN. 0.120 0.140
MM 3.05 3.56
D IN. 0.300 0.325
MM 7.62 8.26
E IN. 0.015 0.040
MM 0.38 1.02
F IN. 0.120 0.140
MM 3.04 3.56
G IN. 0.090 0.110
MM 2.29 2.79
H IN. 0.320 0.370
MM 8.13 9.40
J IN. 0.008 0.012
MM 0.20 0.30
K IN. 0.015 0.021
MM 0.38 0.53

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 DS1302
DS1302S SERIAL TIMEKEEPER 8PIN SOIC (150-MIL AND 200-MIL)

PKG 8-PIN 8-PIN

(150 MIL) (200 MIL)
DIM MIN MAX MIN MAX
A IN. 0.188 0.196 0.203 0.213
MM 4.78 4.98 5.16 5.41
B IN. 0.150 0.158 0.203 0.213
MM 3.81 4.01 5.16 5.41
C IN. 0.048 0.062 0.070 0.074
MM 1.22 1.57 1.78 1.88
E IN. 0.004 0.010 0.004 0.010
MM 0.10 0.25 0.10 0.25
F IN. 0.053 0.069 0.074 0.084
MM 1.35 1.75 1.88 2.13
G IN. 0.050 BSC
MM 1.27 BSC
H IN. 0.230 0.244 0.302 0.318
MM 5.84 6.20 7.67 8.08
J IN. 0.007 0.011 0.006 0.010
MM 0.18 0.28 0.15 0.25
K IN. 0.012 0.020 0.013 0.020
MM 0.30 0.51 0.33 0.51
L IN. 0.016 0.050 0.019 0.030
MM 0.41 1.27 0.48 0.76
phi 0 8 0 8
56-G2008-001
56-G4010-001

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