DS1307/DS1308

DS1307/DS1308
64 X 8 Serial Real Time Clock

FEATURES PIN ASSIGNMENT

• Real time clock counts seconds, minutes, hours, date X1 1 8 VCC
of the month, month, day of the week, and year with
leap year compensation valid up to 2100 X2 2 7 SQW/OUT

• 56 byte nonvolatile RAM for data storage

VBAT 3 6 SCL
GND 4 5 SDA
• 2–wire serial interface
DS1307 8–PIN DIP (300 MIL)
• Programmable squarewave output signal
• Automatic power fail detect and switch circuitry X1 1 8 VCC
X2 2 7 SQW/OUT
• Consumes less than 500 nA in battery backup mode VBAT 3 6 SCL
with oscillator running
GND 4 5 SDA
• Optional industrial temperature range –40°C to
DS1307Z 8–PIN SOIC (150 MIL)
+85°C (IND) available for DS1307 and DS1308
• DS1307 available in 8–pin DIP or SOIC
A B C D

• DS1308 available in 36–pin SMD BGA (Ball Grid

1 GND

Array) GND 2
VCC
• DS1308 accuracy is better than ±2 minute/month at 3
25°C 4 SQW/
VBAT OUT
5
ORDERING INFORMATION
GND 6 GND
DS1307 Serial Timekeeping Chip;
8–pin DIP 7
SCL SDA
DS1307Z Serial Timekeeping Chip; 8
8–pin SOIC (150 mil)
GND 9 GND
DS1307N 8–pin DIP (IND)
DS1307ZN 8–pin SOIC (IND) DS1308
DS1308 36–pin BGA 36–PIN SMD BGA
(TOP VIEW)
DS1308N 36–pin BGA(IND)
PIN DESCRIPTION DS1307/DS1308
DESCRIPTION VCC – Primary Power Supply
The DS1307 Serial Real Time Clock is a low power, full X1, X2 – 32.768 kHz Crystal Connection
BCD clock/calendar plus 56 bytes of nonvolatile SRAM. VBAT – +3 Volt Battery Input
Address and data are transferred serially via a 2–wire GND – Ground
bi–directional bus. The clock/calendar provides SDA – Serial Data
seconds, minutes, hours, day, date, month, and year SCL – Serial Clock
SQW/OUT – Square wave/Output Driver
information. The end of the month date is automatically
DS1308 PIN IDENTIFIER
adjusted for months with less than 31 days, including
VCC – C2, C3, D2, D3
corrections for leap year. The clock operates in either VBAT – A4, A5, B4, B5
the 24–hour or 12–hour format with AM/PM indicator. SDA – C7, C8, D7, D8
The DS1307 has a built–in power sense circuit which SCL – A7, A8, B7, B8
detects power failures and automatically switches to the SQW/OUT – C4, C5, D4, D5
battery supply. GND – All Remaining Balls

020999 1/14
 DS1307/1308

The DS1308 incorporates the DS1307 chip with a lowed by a register address. Subsequent registers can
32.768 kHz crystal in a surface mountable, 36–pin ball be accessed sequentially until a STOP condition is
grid array package (BGA). The close proximity of the executed. When VCC falls below 1.25 x VBAT the device
embedded crystal to the high impedance crystal input terminates an access in progress and resets the device
pins on the DS1307 minimizes capacitive loading and address counter. Inputs to the device will not be recog-
noise injection problems associated with many other nized at this time to prevent erroneous data from being
oscillator designs. The total area required for installa- written to the device from an out of tolerance system.
tion is less than that of 1 United States dime: thus, mini- When VCC falls below VBAT the device switches into a
mizing PCB space required. low current battery backup mode. Upon power up, the
device switches from battery to VCC when VCC is greater
OPERATION than VBAT+0.2V and recognizes inputs when VCC is
The DS1307/1308 operates as a slave device on the greater than 1.25 x VBAT. The block diagram in Figure 1
serial bus. Access is obtained by implementing a START shows the main elements of the Serial Real Time Clock.
condition and providing a device identification code fol-

DS1307/DS1308 BLOCK DIAGRAM Figure 1

NOTE: THE DS1308 INCLUDES THE CRYSTAL AND

CONNECTIONS TO X1, X2.

X1 X2

OSCILLATOR RTC
AND DIVIDER

SQUARE WAVE
SQW/OUT OUT
RAM
(56 X 8)
CONTROL
LOGIC
VCC
VBAT POWER
CONTROL
GND

SCL

SERIAL BUS ADDRESS

INTERFACE REGISTER
SDA

020999 2/14
 DS1307/DS1308

SIGNAL DESCRIPTIONS
VCC, GND – DC power is provided to the device on NOTE: X1, X2 are not applicable for the DS1308 or
these pins. VCC is the +5 volt input. When 5 volts is DS1308N.
applied within normal limits, the device is fully accessi-
ble and data can be written and read. When a 3 volt bat- X1, X2 – Connections for a standard 32.768 KHz quartz
tery is connected to the device and VCC is below 1.25 x crystal. The internal oscillator circuitry is designed for
VBAT, reads and writes are inhibited. However, the operation with a crystal having a specified load capaci-
Timekeeping function continues unaffected by the lower tance (CL) of 12.5 pF.
input voltage. As VCC falls below VBAT the RAM and
timekeeper are switched over to the external power sup- For more information on crystal selection and crystal
ply (nominal 3.0V DC) at VBAT. layout considerations, please consult Application Note
58, “Crystal Considerations with Dallas Real Time
VBAT – Battery input for any standard 3 volt lithium cell Clocks”. The DS1307 can also be driven by an external
or other energy source. Battery voltage must be held 32.768 kHz oscillator. In this configuration, the X1 pin is
between 2.0 and 3.5 volts for proper operation. The connected to the external oscillator signal and the X2
nominal write protect trip point voltage at which access pin is floated.
to the real time clock and user RAM is denied is set by
the internal circuitry as 1.25 x VBAT nominal. A Lithium Please review Application Note 95, “Interfacing the
battery with 48 mAhr. or greater will back up the DS1307/DS1308 with a 8051–Compatible Microcon-
DS1307/DS1308 for more than 10 years in the absence troller” for additional information.
of power at 25 degrees C.

SCL (Serial Clock Input) – SCL is used to synchronize RTC AND RAM ADDRESS MAP
The address map for the RTC and RAM registers of the
data movement on the serial interface.
DS1307/DS1308 is shown in Figure 2. The real time
SDA (Serial Data Input/Output) – SDA is the input/ clock registers are located in address locations 00h to
output pin for the 2–wire serial interface. The SDA pin is 07h. The RAM registers are located in address loca-
open drain which requires an external pull–up resistor. tions 08h to 3Fh. During a multi–byte access, when the
address pointer reaches 3Fh, the end of RAM space, it
SQW/OUT (Square Wave/ Output Driver) – When wraps around to location 00h, the beginning of the clock
enabled, the SQWE bit set to 1, the SQW/OUT pin out- space.
puts one of four square wave frequencies (1 Hz, 4 KHz,
8 KHz, 32 KHz). The SQW/OUT pin is open drain which
requires an external pull–up resistor.

020999 3/14
 DS1307/1308

DS1307 ADDRESS MAP Figure 2

00H
SECONDS

MINUTES

HOURS

DAY

DATE

MONTH

YEAR

07H CONTROL
08H

RAM
56 X 8

3FH

CLOCK AND CALENDAR Please note that the initial power on state of all reg-
The time and calendar information is obtained by read- isters is not defined. Therefore it is important to
ing the appropriate register bytes. The real time clock enable the oscillator (CH bit=0) during initial
registers are illustrated in Figure 3. The time and calen- configuration.
dar are set or initialized by writing the appropriate regis-
ter bytes. The contents of the time and calendar regis- The DS1307/DS1308 can be run in either 12–hour or
ters are in the Binary–Coded Decimal (BCD) format. Bit 24–hour mode. Bit 6 of the hours register is defined as
7 of Register 0 is the Clock Halt (CH) bit. When this bit is the 12– or 24–hour mode select bit. When high, the
set to a one, the oscillator is disabled. When cleared to a 12–hour mode is selected. In the 12–hour mode, bit 5 is
zero, the oscillator is enabled. the AM/PM bit with logic high being PM. In the 24–hour
mode, bit 5 is the second 10 hour bit (20–23 hours).

DS1307/DS1308 TIMEKEEPER REGISTERS Figure 3

BIT7 BIT0

00H CH 10 SECONDS SECONDS 00–59

X 10 MINUTES MINUTES 00–59

12 10 HR 01–12
X 10 HR HOURS 00–23
24 A/P

X X X X X DAY 1–7
01–28/29
X X 10 DATE DATE 01–30
01–31

X X X 10 MONTH 01–12
MONTH

10 YEAR YEAR 00–99

07H OUT X X SQWE X X RS1 RS0

020999 4/14
 DS1307/DS1308

CONTROL REGISTER SQUAREWAVE OUTPUT FREQUENCY Table 1

The DS1307/DS1308 Control Register is used to con- RS1 RS0 SQW OUTPUT
trol the operation of the SQW/OUT pin. FREQUENCY
0 0 1 Hz
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 1 4.096 kHz
OUT X X SQWE X X RS1 RS0
1 0 8.192 kHz
OUT (Output control): This bit controls the output level 1 1 32.768 kHz
of the SQW/OUT pin when the square wave output is
disabled. If SQWE = 0, the logic level on the SQW/OUT
pin is 1 if OUT = 1 and is 0 if OUT = 0. 2–WIRE SERIAL DATA BUS
The DS1307 supports a bi–directional 2–wire bus and
SQWE (Square Wave Enable): This bit, when set to a data transmission protocol. A device that sends data
logic 1, will enable the oscillator output. The frequency onto the bus is defined as a transmitter and a device
of the square wave output depends upon the value of receiving data as a receiver. The device that controls
the RS0 and RS1 bits. the message is called a master. The devices that are
controlled by the master are referred to as slaves. The
RS (Rate Select): These bits control the frequency of bus must be controlled by a master device which gener-
the square wave output when the square wave output ates the serial clock (SCL), controls the bus access, and
has been enabled. Table 1 lists the square wave fre- generates the START and STOP conditions. The
quencies that can be selected with the RS bits. DS1307/DS1308 operates as a slave on the 2–wire bus.
A typical bus configuration using this 2–wire protocol is
show in Figure 4.

TYPICAL 2–WIRE BUS CONFIGURATION Figure 4

VCC

RP RP

SDA
2–WIRE
SERIAL DATA
BUS
SCL

MICRO– DS1307 OTHER

PROCESSOR REAL TIME PERIPHERAL
CLOCK DEVICE

Figures 5, 6, and 7 detail how data is transferred on the • During data transfer, the data line must remain stable
2–wire bus. whenever the clock line is HIGH. Changes in the data
line while the clock line is high will be interpreted as
control signals.
• Data transfer may be initiated only when the bus is not
busy. Accordingly, the following bus conditions have been
defined:

Bus not busy: Both data and clock lines remain HIGH.

020999 5/14
 DS1307/1308

Start data transfer: A change in the state of the data Within the 2–wire bus specifications a regular mode
line, from HIGH to LOW, while the clock is HIGH, defines (100 kHz clock rate) and a fast mode (400 kHz clock
a START condition. rate) are defined. The DS1307/DS1308 operates in the
regular mode (100 kHz) only.
Stop data transfer: A change in the state of the data
line, from LOW to HIGH, while the clock line is HIGH, Acknowledge: Each receiving device, when
defines the STOP condition. addressed, is obliged to generate an acknowledge after
the reception of each byte. The master device must
Data valid: The state of the data line represents valid generate an extra clock pulse which is associated with
data when, after a START condition, the data line is this acknowledge bit.
stable for the duration of the HIGH period of the clock
signal. The data on the line must be changed during the A device that acknowledges must pull down the SDA
LOW period of the clock signal. There is one clock pulse line during the acknowledge clock pulse in such a way
per bit of data. that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
Each data transfer is initiated with a START condition setup and hold times must be taken into account. A
and terminated with a STOP condition. The number of master must signal an end of data to the slave by not
data bytes transferred between START and STOP generating an acknowledge bit on the last byte that has
conditions is not limited, and is determined by the mas- been clocked out of the slave. In this case, the slave
ter device. The information is transferred byte–wise and must leave the data line HIGH to enable the master to
each receiver acknowledges with a ninth bit. generate the STOP condition

DATA TRANSFER ON 2–WIRE SERIAL BUS Figure 5

SDA
MSB
SLAVE
ADDRESS
*R/W
DIRECTION ACKNOWLEDGEMENT
BIT SIGNAL FROM
RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM
RECEIVER

SCL 1 2 6 7 8 9 1 2 3–8 8 9

ACK ACK
START STOP CONDITION
CONDITION REPEATED IF OR REPEATED
MORE BYTES ARE START CONDITION
TRANSFERRED

Depending upon the state of the R/W bit, two types of 2. Data transfer from a slave transmitter to a mas-
data transfer are possible: ter receiver. The first byte (the slave address) is
transmitted by the master. The slave then returns an
1. Data transfer from a master transmitter to a acknowledge bit. This is followed by the slave trans-
slave receiver. The first byte transmitted by the mitting a number of data bytes. The master returns
master is the slave address. Next follows a number an acknowledge bit after all received bytes other
of data bytes. The slave returns an acknowledge bit than the last byte. At the end of the last received
after each received byte. Data is transferred with the byte, a ’not acknowledge’ is returned.
most significant bit (MSB) first.

020999 6/14
 DS1307/DS1308

The master device generates all of the serial clock address and *direction bit (See Figure 6). The
pulses and the START and STOP conditions. A transfer address byte is the first byte received after the start
is ended with a STOP condition or with a repeated condition is generated by the master. The address
START condition. Since a repeated START condition is byte contains the 7 bit DS1307/DS1308 address,
also the beginning of the next serial transfer, the bus will which is 1101000, followed by the *direction bit
not be released. Data is transferred with the most signifi- (R/W) which, for a write, is a 0. After receiving and
cant bit (MSB) first. decoding the address byte the device outputs an
The DS1307/DS1308 may operate in the following two acknowledge on the SDA line. After the
modes: DS1307/DS1308 acknowledges the slave address
+ write bit, the master transmits a register address
1. Slave receiver mode (DS1307/DS1308 write to the DS1307/DS1308 This will set the register
mode): Serial data and clock are received through pointer on the DS1307/DS1308. The master will
SDA and SCL. After each byte is received an then begin transmitting each byte of data with the
acknowledge bit is transmitted. START and STOP DS1307/DS1308 acknowledging each byte
conditions are recognized as the beginning and end received. The master will generate a stop condition
of a serial transfer. Address recognition is per- to terminate the data write.
formed by hardware after reception of the slave

DATA WRITE – SLAVE RECEIVER MODE Figure 6

<R/W>

<Slave Address> <Word Address (n)> <Data(n)> <Data (n+1)> <Data (n+X)>

S 1101000 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P

S – START
A – ACKNOWLEDGE
DATA TRANSFERRED
P – STOP (X+1 BYTES + ACKNOWLEDGE)
*R/W – READ/WRITE OR DIRECTION BIT. ADDRESS = D0h

020999 7/14
 DS1307/1308

2. Slave transmitter mode (DS1307/DS1308 read DS1307/DS1308 address, which is 1101000, fol-
mode): The first byte is received and handled as in lowed by the *direction bit (R/W) which, for a read,
the slave receiver mode. However, in this mode, the is a 1. After receiving and decoding the address byte
*direction bit will indicate that the transfer direction the device inputs an acknowledge on the SDA line.
is reversed. Serial data is transmitted on SDA by the The DS1307/DS1308 then begins to transmit data
DS1307/DS1308 while the serial clock is input on starting with the register address pointed to by the
SCL. START and STOP conditions are recognized register pointer. If the register pointer is not written
as the beginning and end of a serial transfer (See to before the initiation of a read mode the first
Figure 7). The address byte is the first byte received address that is read is the last one stored in the reg-
after the start condition is generated by the master. ister pointer. The DS1307/DS1308 must receive a
The address byte contains the 7–bit Not Acknowledge to end a read.

DATA READ – SLAVE TRANSMITTER MODE Figure 7

<R/W>

<Slave Address> <Data(n)> <Data(n+1)> <Data (n+2)> <Data (n+X)>

S 1101000 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P

S – START
DATA TRANSFERRED
A – ACKNOWLEDGE (X+1 BYTES + ACKNOWLEDGE); NOTE: LAST DATA BYTE IS
P – STOP FOLLOWED BY A NOT ACKNOWLEDGE ( A ) SIGNAL)
A – NOT ACKNOWLEDGE

*R/W – READ/WRITE OR DIRECTION BIT ADDRESS = D1h

020999 8/14
 DS1307/DS1308

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground –0.5V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature –55°C to +125°C
Soldering Temperature 260°C for 10 seconds (See NOTE 12)

* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.

The Dallas Semiconductor DS1307/DS1308 is built to the highest quality standards and manufactured for long term
reliability. All Dallas Semiconductor devices are made using the same quality materials and manufacturing methods.
However, standard versions of the DS1307/DS1308 are not exposed to environmental stresses, such as burn–in, that
some industrial applications require. Products which have successfully passed through this series of environmental
stresses are marked IND or N, denoting their extended operating temperature and reliability rating. For specific reli-
ability information on this product, please contact the factory at (972) 371–4448.

RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage VCC 4.5 5.0 5.5 V 1
Logic 1 VIH 2.2 VCC+0.3 V 1
Logic 0 VIL –0.3 +0.8 V 1
VBAT Battery Voltage VBAT 2.0 3.5 V 1

DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC=4.5V to 5.5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage ILI 1 µA 10
I/O Leakage ILO 1 µA 11
Logic 0 Output VOL 0.4 V 2
Active Supply Current ICCA 1.5 mA 9
Standby Current ICCS 200 µA 3
Battery Current (OSC ON); IBAT1 300 500 nA 4
SQW/OUT OFF
Battery Current (OSC ON); IBAT2 480 800 nA 4
SQW/OUT ON (32 KHz)

020999 9/14
 DS1307/1308

AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC=4.5V to 5.5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
SCL Clock Frequency fSCL 0 100 kHz
Bus Free Time Between a STOP tBUF 4.7 µs
and START Condition
Hold Time (Repeated) START tHD:STA 4.0 µs 5
Condition
LOW Period of SCL Clock tLOW 4.7 µs
HIGH Period of SCL Clock tHIGH 4.0 µs
Set–up Time for a Repeated tSU:STA 4.7 µs
START Condition
Data Hold Time tHD:DAT 0 µs 6, 7
Data Set–up Time tSU:DAT 250 ns
Rise Time of Both SDA and SCL tR 1000 ns
Signals
Fall Time of Both SDA and SCL tF 300 ns
Signals
Set–up Time for STOP Condition tSU:STO 4.7 µs
Capacitive Load for each Bus CB 400 pF 8
Line
I/O Capacitance CI/O 10 pF
Crystal Specified Load 12.5 pF
Capacitance

NOTES:
1. All voltages are referenced to ground.
2. Logic zero voltages are specified at a sink current of 5 mA at VCC=4.5V, VOL=GND for capacitive loads.
3. ICCS specified with VCC=5.0V and SDA, SCL=5.0V.
4. VCC=0V, VBAT=3V.
5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the
SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
8. CB – total capacitance of one bus line in pF.
9. ICCA – SCL clocking at max frequency = 100 KHz.
10. SCL only.
11. SDA and SQW/OUT
12. The DS1308 is designed to be subjected to no more than two (2) passes through a solder reflow process to limit
premature crystal aging effects and maintain a reasonable accuracy of ±2 minutes/month at 25 degrees C (Worst
case).

020999 10/14
 DS1307/DS1308

TIMING DIAGRAM Figure 8

SDA

tBUF

tLOW
tR tF tHD:STA

SCL

tHD:STA
tSU:STO
tSU:STA
tHD:DAT tHIGH tSU:DAT
STOP START REPEATED
START

DS1307 64 X 8 SERIAL REAL TIME CLOCK 8–PIN DIP MECHANICAL DIMENSIONS

8 5 PKG 8–PIN

DIM MIN MAX

B A IN. 0.360 0.400

MM 9.14 10.16

B IN. 0.240 0.260

MM 6.10 6.60
1 4
A
C IN. 0.120 0.140
MM 3.05 3.56

D IN. 0.300 0.325

MM 7.62 8.26
C
E IN. 0.015 0.040
MM 0.38 1.02
E F
F IN. 0.120 0.140
K MM 3.04 3.56
G
G IN. 0.090 0.110
MM 2.29 2.79

H IN. 0.320 0.370

D MM 8.13 9.40

J IN. 0.008 0.012

MM 0.20 0.30

J K IN. 0.015 0.021

MM 0.38 0.53

020999 11/14
DS1307/1308

DS1307Z 64 X 8 SERIAL REAL TIME CLOCK 8–PIN SOIC (150 MIL) MECHANICAL
DIMENSIONS

PKG 8–PIN
(150 MIL)

DIM MIN MAX

A IN. 0.188 0.196

MM 4.78 4.98

B IN. 0.150 0.158

MM 3.81 4.01

C IN. 0.048 0.062

MM 1.22 1.57

E IN. 0.004 0.010

MM 0.10 0.25

F IN. 0.053 0.069

MM 1.35 1.75

G IN. 0.050 BSC

MM 1.27 BSC

H IN. 0.230 0.244

MM 5.84 6.20

J IN. 0.007 0.011

MM 0.18 0.28

K IN. 0.012 0.020

MM 0.30 0.51

L IN. 0.016 0.050

MM 0.41 1.27

phi 0° 8°

56–G2008–001

020999 12/14
 DS1307/DS1308

DS1308 MECHANICAL DIMENSIONS

PKG 36–PIN
BALL GRID

DIM MIN MAX

A IN. 0.395 0.405

MM

B IN. 0.445 0.455

MM

C IN. 0.022 0.028

MM

D IN. 0.047 0.053

MM

E IN. 0.047 0.053

MM

F IN. 0.347 0.353

MM

G IN. 0.170 0.190

MM

H IN. 0.025 0.030

MM

020999 13/14
DS1307/1308

DS1308 RECOMMENDED LAYOUT LAND PATTERN

020999 14/14