CXA2503AR

Decoder/Driver/Timing Generator for Color LCD Panels

For the availability of this product, please contact the sales office.
Description
The CXA2503AR is an IC designed exclusively to 64 pin LQFP (Plastic)
drive color LCD panels LCX005BK/BKB and
LCX009AK/AKB.
This IC greatly reduces the number of circuits and
parts required to drive LCD panels by incorporating
RGB decoder functions for video signals, driver
functions, and a timing generator for driving panels
onto a single chip.
This chip has a built-in serial interface circuit and
Absolute Maximum Ratings (Ta = 25C)
electronic attenuators which allow various mode
Supply voltage VCC1 GND1, 3 6 V
settings and adjustments to be performed through
VCC2 GND2 14 V
direct control from an external microcomputer, etc.
VDD1 VSS1 4.5 V
VDD2 VSS2 4.5 V
Features
Analog input pin voltage VINA 0.3 to VCC1 V
Color LCD panels LCX005BK/BKB and LCX009AK/
Digital input pin voltage VIND 0.3 to VDD1 + 0.3 V
AKB driver
Operating temperature Topr 15 to +75 C
Supports NTSC and PAL systems
Storage temperature Tstg 40 to +125 C
Supports 16:9 wide display
Allowable power dissipation
Supports composite inputs, Y/C inputs and Y/color
PD (Ta 75C) 350mW Note)
difference inputs
Serial interface circuit
Operating conditions
Electronic attenuators (D/A converter)
Supply voltage VCC1 GND1, 3 4.25 to 5.25 V
BPF, trap and delay line
VCC2 GND2 11.0 to 13.5 V
Sharpness function
VDD1 VSS1 2.7 to 3.6 V
2-point correction circuit
VDD2 VSS2 2.7 to 3.6 V
R, G, B signal delay time adjustment circuit
Polarity inversion circuit (line inverted mode)
Note) With substrate
Supports external RGB input
Size: 114.3 76.1 1.5mm
Supports AC drive for LCD panel during no signal
Material: Glass fabric base epoxy

Applications
LCD viewfinders
Compact liquid crystal projectors
Compact LCD monitors

Structure
Bipolar CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

1
E97910-PS
 CXA2503AR

Block Diagram

SIG.CENTER

G OUT

TEST3
TEST4
R OUT

TEST2
B OUT

GND2

LOAD

DATA

SCLK
FB G

FB B
VCC2

FB R

RGT
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
+12V GND2

SEREAL
buf buf buf BAS I/F

VCC1 49 +4.5V VSS2 32 VSS2

B-Y IN 50 31 VD2

CLAMP PAL ID
R-Y IN 51 DEMOD VGATE WIDE VTST 30 VD1
PAL
EXT COLOR COLOR
SW POL SW
& BALANCE HUE
FRP
C OUT 52 29 EN
INT/EXT
R-BRT
BLK LIM 53 SUB- 28 VCK1
APC VPAL
BRIGHT VWIN
B-BRT
APC 54 LPF PALSW 27 VCK2
VXO HUE PS
BRT
MATRIX BRIGHT
VXO OUT 55 HUE 26 VST
COLOR
CONTRAST
VXO IN 56 CNTRAST S/H 25 TEST1
COLOR CONT -1 D/A
V REG 57 REG. ACC DET RGB GAMMA 24 FLD IN
-2
KILLER
START UP 58 EXT SW 23 FLD OUT
BPF
PIC CONT

C IN 59 ACC AMP HD 22 HD

HAFC
F0 ADJ 60 FILT ADJ
HCNT 21 HCK1
PLL-COUNTER
& DECODER H-PULSE
CLP
GND3 61 BGP 20 HCK2
SBLK
GND3
V-SEP
Y IN 62 CLAMP TRAP DL 1 19 HST
HGATE
PD
H-SKEW DET
PIC 63 18 CLR
SYNC SEP

TEST0 64 +3V 17 VDD2

PLL

H. FILTER
VCO ADJ
GND1 VSS1 +3V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PWRST

RPD
H.FIL OUT

VCO ADJ
SYNC IN

VDD1
EXT B
GND1

CKO
EXT G
TRAP

CKI
EXT R
VD IN

VSS1
S.SEP IN

2
 CXA2503AR

Pin Description

Pin Input pin for

Symbol I/O Description
No. open status
1 PWRST System reset
2 VD IN I External vertical sync input
3 TRAP External trap connection
4 GND1 Analog 4.5V GND
5 SYNC IN I Video input for sync separation
6 H.FIL OUT O Video output for sync input
7 S.SEP IN I Sync separation circuit input
8 EXT R I External digital input R
9 EXT G I External digital input G
10 EXT B I External digital input B
11 VCO ADJ O VCO adjustment voltage output
12 RPD O Phase comparator output
13 VSS1 Digital 3V GND for oscillation cell
14 CKI I Oscillation cell input
15 CKO O Oscillation cell output
16 VDD1 Digital 3V power supply for oscillation cell
17 VDD2 Digital 3V power supply
18 CLR O CLR pulse output
19 HST O H start pulse output
20 HCK2 O H clock pulse 2 output
21 HCK1 O H clock pulse 1 output
22 HD O HD pulse output
23 FLD OUT O Field identification output
24 FLD IN I Field identification input
25 TEST1 Test (Leave this pin open.)
26 VST O V start pulse output
27 VCK2 O V clock pulse 2 output
28 VCK1 O V clock pulse 1 output
29 EN O EN pulse output
30 VD1 O VD1 pulse output
31 VD2 O VD2 pulse output
32 VSS2 Digital 3V GND

3
 CXA2503AR

Pin Input pin for

Symbol I/O Description
No. open status
33 SCLK I Serial interface clock input H
34 DATA I Serial interface data input H
35 LOAD I Serial interface load input H
36 TEST2 Test (Leave this pin open.)
37 TEST3 Test (Leave this pin open.)
38 TEST4 Test (Leave this pin open.)
39 RGT I Switches between Normal scan (H) and Reverse scan (L) H
40 GND2 Analog 12V GND
41 B OUT O B output
42 FB B O B signal DC voltage feedback circuit capacitor connection
43 G OUT O G output
44 FB G O G signal DC voltage feedback circuit capacitor connection
45 R OUT O R output
46 FB R O R signal DC voltage feedback circuit capacitor connection
47 VCC2 Analog 12V power supply
48 SIG.CENTER I RGB output DC voltage adjustment
49 VCC1 Analog 4.5V power supply
50 B-Y IN I B-Y demodulator input (or B-Y color difference signal input)
51 R-Y IN I R-Y demodulator input (or R-Y color difference signal input)
52 C OUT O Chroma signal output
53 BLK LIM I Black peak limiter level adjustment
54 APC O APC detective filter connection
55 VXO OUT O VXO output
56 VXO IN I VXO input
57 V REG O Constant voltage capacitor connection
58 START UP O Startup time constant connection
59 C IN I Chroma signal input
60 F0 ADJ O Internal filter adjusting resistor connection
61 GND3 Analog 4.5V GND
62 Y IN I Y signal input
63 PIC I Y signal frequency response adjustment
64 TEST0 I Test (Leave this pin open.)

(H: Pull up)

4
 CXA2503AR

Analog Block Pin Description

Pin
Symbol Pin voltage Equivalent circuit Description
No.

VDD2

2A TG block system reset pin.

1 The system is reset when this
1 PWRST 1k pin is connected to GND.
Connect a capacitor between
this pin and GND.
GND1

VDD2
50k

50k External vertical sync signal

2 VDIN 2 input.
50k

GND1

VCC1
70A
1k External trap connection.
300 Connect the trap between this
3 TRAP 2.2V 3 pin and GND to remove the
130A chroma component.

GND1

VDD1
1k Sync input.
Normally inputs the Y signal.
5 SYNC IN 1.5V 5 2.1V The standard signal input level
1k
is 0.5Vp-p (100% white level
30A from the sync tip).
GND1

VDD2
20k

Outputs the video signal for

6 H.FIL OUT 2.5V 6 input to the sync separation
circuit.
20k
GND1

5
 CXA2503AR

Pin
Symbol Pin voltage Equivalent circuit Description
No.

VDD2

17k Sync separation circuit input.

7 S.SEP IN 1.0V 7 Input the H FILTER output
signal.
10A 1.8V 2.8V
GND1

External digital signal inputs.

8 EXT-R VCC1 There are two threshold
30A values: Vth1 (= 1.0V) and
Vth2 (= 2.0V). When one of
8
300 the RGB signals exceeds
9 EXT-G 9
Vth1, all of the RGB outputs
10 go to black level; when an
50k 2.7V input exceeds Vth2, only the
10 EXT-B GND1 corresponding output goes to
white level.

VCC2

500 VCO adjustment voltage

11 VCO ADJ 11
output.
70A

GND2

41 B OUT VCC2

41 50
VCC2 43
43 G OUT RGB signal outputs.
2 50
45
40A
GND2
45 R OUT

42 FB B VCC2
Smoothing capacitor
42 connection for the feedback
1k
44
circuit of RGB output DC level
44 FB G 2.5V
control.
46
Use a low-leakage capacitor
because of high impedance.
GND2
46 FB R

6
 CXA2503AR

Pin
Symbol Pin voltage Equivalent circuit Description
No.

VCC2

150k RGB output DC voltage

control.
SIG. 300
48 6.0V 48 When used with a VCC2 of
CENTER
12V or more, apply 6V from
150k an external source.
GND2

Color difference demodulation

VCC1 circuit inputs.
50 B-Y IN Color difference signal is input
when using Y/color difference
50 500 500
input. At this time, the clamp
51
10k
level is approximately 2.8V.
Pin 52 signal is input in other
51 R-Y IN 30A 50A modes. (except D-PAL1) At
GND1 this time, the DC level is
approximately 2.0V.

VCC1

Color adjusted chroma signal

output. The burst level is
52 C OUT 1.3V 52
approximately 140mVp-p (typ.).
350A (420mVp-p during D-PAL.)

GND1

VCC1

50k
Sets the RGB output
53 BLK LIM 53 amplitude (black-black) clip
level.

GND1

VCC1

1k APC detective filter

54 APC 2.7V 54 connection.

GND1

1 D-PAL is a demodulation method that uses an external delay line during demodulation; S-PAL is a demodulation
method that internally processes chroma demodulation.
7
 CXA2503AR

Pin
Symbol Pin voltage Equivalent circuit Description
No.

VCC1

55 VXO OUT 2.9V 55 VXO output.

400A

GND1

VCC1

500
56 VXO IN 3.2V 56 VXO input.
3k

3.2V
GND1

VCC1

Smoothing capacitor
connection for the internally
57 V REG 3.6V 57 60k generated constant voltage
source circuit. Connect a
30k capacitor of 1F or more.
GND1

VCC1
Prevents output of the HST
0.5A and VST pulses for driving
LCD panels for a certain time
1k
58 START UP 58 during power-on. Connect a
capacitor between this pin and
GND. When not using this pin,
connect to VCC1.
GND1

VCC1
Video signal input when using
500 15p
composite signal input.
59 Chroma signal input when
59 C IN
20k
using Y/C signal input.
30A Leave this pin open when
using Y/color difference input.
GND1

8
 CXA2503AR

Pin
Symbol Pin voltage Equivalent circuit Description
No.

VCC1

1k Connect resistance of 82k

60 between this pin and GND1 to
60 F0 ADJ 2.4V
adjust the internal filters using
the outflow current value.
15A

GND1

VCC1
Y signal input.
1k The standard signal input level
62 is 0.5Vp-p (100% white level
62 Y IN 3.1V
from the sync tip).
Input at low impedance (75
70A or less).
GND1

VCC1

20k
30k
Adjusts frequency response of
63 luminance signal.
63 PIC 2.25V 10k Increasing the voltage
2.25V
emphasizes contours.
50A 50A
GND1

9
 CXA2503AR

Setting Conditions for Measuring Electrical Characteristics

When measuring the electrical characteristics, the TG (timing generator) block must be initialized by performing
Settings 1 and 2 below.

Setting 1. System reset

After turning on the power, set SW1 to ON and start up V1 from GND in order to activate the TG
block system reset. (See Fig. 1-1.)

Setting 2. Horizontal AFC adjustment

Input SIG5 (VL = 0mV) to (A) and adjust serial bus register PLL ADJ so that WL and WH of the
TP12 output waveform are the same. (See Fig. 1-2.)

VDD SIG5
WS

V1 (PWRST)
TP12
TR
TR > 10s
WL WH WL = WH

Fig. 1-1. System reset Fig. 1-2. Horizontal AFC adjustment

10
 CXA2503AR

Electrical Characteristics DC Characteristics

Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required.
VCC1 = 4.5V, VCC2 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = VDD2 = 3.0V, VSS1 = VSS2 = 0V, Ta = 25C
SW1, SW53, SW63 = ON
SW8, SW9, SW10, SW59 = A
SW50, SW51 = B
V53 = 0V, V63 = 2.2V
Set the serial bus registers to the "Serial Bus Register Initial Settings".

Item Symbol Conditions Min. Typ. Max. Unit

Power supply characteristics
Input SIG4 to (A) and SIG2 (0dB) to (B).
ICC11 Measure the ICC1 current value. 20 27 34 mA
COMP input mode

Input SIG4 to (A) and SIG2 (0dB) to (B).

Current consumption ICC12 Measure the ICC1 current value. 19 26 33 mA
VCC1 Y/C input mode

Input SIG4 to (A), (D) and (E).

Measure the ICC1 current value.
ICC13 15 21 27 mA
SW50, SW51 = A, SW59 = B
Y/color difference input mode

Current consumption Input SIG4 to (A) and SIG2 (0dB) to (B).

ICC2 3 5 8 mA
VCC2 Measure the ICC2 current value.

Input SIG4 to (A) and SIG2 (0dB) to (B).

IDD1 Measure the IDD current value. 4 6 8 mA
Current consumption LCX009 mode
VDD Input SIG4 to (A) and SIG2 (0dB) to (B).
IDD2 Measure the IDD current value. 3.5 5 6.5 mA
LCX005 mode

11
 CXA2503AR

Item Symbol Conditions Min. Typ. Max. Unit

Digital block I/O characteristics
Input current Normal input VIN = VDD 10
II1 A
FLDIN pin pin VIN = VSS 10
Input pin with pull-up resistor1
Input current II2 145 60 24 A
VIN = VSS

High level input voltage VIH CMOS input cell3 0.7VDD V

Low level input voltage VIL CMOS input cell3 0.3VDD V
High level output voltage
Output pins except CKO VOH1 IOH = 1mA2 2.8 V
and RPD

Low level output voltage

Output pins except CKO VOL1 IOL = 1mA2 0.3 V
and RPD

High level output voltage

VOH2 IOH = 3mA 0.5VDD V
CKO pin

Low level output voltage

VOL2 IOL = 3mA 0.5VDD V
CKO pin

High level output voltage

VOH3 IOH = 0.5mA VDD 1.2 V
RPD pin

Low level output voltage

VOL3 IOL = 0.7mA 1.0 V
RPD pin

Output off leak current High impedance status

IOFF 40 40 A
RPD pin VOUT = VSS or VOUT = VDD

1 Input pins with pull-up resistors: SCLK, DATA, LOAD, RGT

2 Output pins except CKO and RPD: CLR, HST, HCK1, HCK2, HD, VD1, VD2, FLDOUT, VST, VCK1, VCK2, EN
3 CMOS input cells: FLDIN, SCLK, DATA, LOAD, RGT

12
 CXA2503AR

Electrical Characteristics AC Characteristics

Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required.
VCC1 = 4.5V, VCC2 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = VDD2 = 3.0V, VSS1 = VSS2 = 0V, Ta = 25C
SW1, SW53, SW63 = ON
SW8, SW9, SW10 = A
SW50, SW51, SW59 = B
V53 = 0V, V63 = 2.2V
Set the serial bus registers to the "Serial Bus Register Initial Settings".
Unless otherwise specified, measure the non-inverted outputs for TP41, TP43 and TP45.

Item Symbol Conditions Min. Typ. Max. Unit

Y signal system
Input SIG4 to (A) and measure the ratio between the output
Video maximum gain GV 19 22 25 dB
amplitude (white black) and input amplitude at TP43.

Contrast characteristics Input SIG4 to (A) and measure the ratio between the output
GCNTTP 13 17 21 dB
TYP amplitude (white black) and input amplitude at TP43.

Contrast characteristics Input SIG4 to (A) and measure the ratio between the output
GCNTMN 9 5 1 dB
MIN amplitude (white black) and input amplitude at TP43.

Y/C input,
FCYYC Assume the output amplitude at 5.0 MHz
V63 = 1.5V
TP43 when SIG1 (0dB, no burst,
Y signal frequency 100kHz) is input to (A) as 0dB. Composite input
FCYCMN 2.5 MHz
characteristics Vary the frequency of the input (NTSC), V63 = 2.2V
signal to obtain the frequency
Composite input
FCYCMP with an output amplitude of 3dB. 3.0 MHz
(PAL), V63 = 2.2V
Picture adjustment Assume the output amplitude at TP43 when SIG7 (100kHz) is
GSHP1X 8 12 dB
variable amount 1 input to (A) as 0dB. Set SIG7 to 1.8MHz and measure
(composite input, GSHP1X and GSHP1N as the amounts by which the output
GSHP1N amplitude at TP43 changes when V63 = 4V and 0V, respectively. 3 1 dB
LCX005 mode)

Picture adjustment Assume the output amplitude at TP43 when SIG7 (100kHz) is
GSHP2X 6 9 dB
variable amount 2 input to (A) as 0dB. Set SIG7 to 2.0MHz and measure
(composite input, GSHP2X and GSHP2N as the amounts by which the output
GSHP2N amplitude at TP43 changes when V63 = 4V and 0V, respectively. 4 2 dB
LCX009 mode)

Picture adjustment Assume the output amplitude at TP43 when SIG7 (100kHz)
GSHP3X 10 15 dB
variable amount 3 is input to (A) as 0dB. Set SIG7 to 1.8MHz and measure
(Y/C input, GSHP3X and GSHP3N as the amounts by which the output
GSHP3N amplitude at TP43 changes when V63 = 4V and 0V, respectively. 1 2 dB
LCX005 mode)

Picture adjustment Assume the output amplitude at TP43 when SIG7 (100kHz)
GSHP4X 10 14 dB
variable amount 4 is input to (A) as 0dB. Set SIG7 to 2.5MHz and measure
(Y/C input, GSHP4X and GSHP4N as the amounts by which the output
GSHP4N amplitude at TP43 changes when V63 = 4V and 0V, respectively. 2 0 dB
LCX009 mode)
Input SIG2 (0dB) to (A). Using a spectrum analyzer,
measure the input and the 3.58MHz or 4.43MHz
Carrier leak
CRLEKY component of TP43, and obtain 30 mV
(residual carrier)
CRLEKY = 150mV 10CLK/20
using their difference CLK.

TDYYC Y/C input 230 330 430 ns

Input SIG9 (VL = 150mV) to (A).
Measure the delay time from the 2T Composite input
Y signal TDYCMN 430 530 630 ns
pulse peak of the input signal to the (NTSC)
I/O delay time
peak of the non-inverted output at
Composite input
TDYCMP TP43. 430 530 630 ns
(PAL)
13
 CXA2503AR

Item Symbol Conditions Min. Typ. Max. Unit

Chroma signal block
Input SIG5 (VL = 150mV) to (A) and SIG2
NTSC 3 0 3 dB
(0dB/+6dB/20dB, 3.58MHz burst/chroma
ACC amplitude
ACC1 phase = 180, or 4.43MHz burst/chroma
characteristics 1
phase = 135) to (B). Measure the output PAL 3 0 3 dB
amplitude at TP52, assuming the output
corresponding to 0dB, +6dB and 20dB as
V0, V1 and V2, respectively. NTSC 3 0 3 dB
ACC amplitude ACC1 = 20 log (V1/V0)
ACC2
characteristics 2 ACC2 = 20 log (V2/V0)
PAL 3 0 3 dB
SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2

(0dB, 3.58MHz burst/chroma phase = 180,
FAPCN NTSC 500 Hz
or 4.43MHz burst/chroma phase = 135) to
(B). Changing the SIG2 burst frequency,
APC pull-in range measure the frequency fl at which the TP41
output appears (the killer mode is canceled).
NTSC: FAPCN = fl 3579545Hz
FAPCP PAL: FAPCP = fl 4433619Hz PAL 500 Hz
SW59 = A

Color adjustment Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,
characteristics GCOLMX 3.58MHz burst/chroma phase = 180) to (B). Assume 4 6 dB
MAX the chroma output when serial bus register COLOR =
80H, 0FFH and 0H as V0, V1 and V2, respectively.
Color adjustment GCOLMX = 20 log (V1/V0)
characteristics GCOLMN GCOLMN = 20 log (V2/V0) 25 15 dB
MIN SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,

HUE adjustment burst/chroma phase variable) to (B). Assume the
HUEMX 30 40 deg
range MAX phase at which the output amplitude at TP41 reaches
a minimum when serial bus register HUE = 80H,
0FFH and 0H as 0, 1 and 2, respectively.
HUE adjustment HUEMX = 1 0
HUEMN HUEMN = 2 0 30 60 deg
range MIN
SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2

(level variable, 3.58MHz burst/chroma
ACKN NTSC 36 30 dB
phase = 180, or 4.43MHz burst/chroma
Killer operation phase = 135) to (B), and measure the
input level output amplitude at TP41. Gradually reduce
the SIG2 amplitude level and measure the
ACKP PAL 34 28 dB
level at which the killer operation is activated.
SW59 = A

14
 CXA2503AR

Item Symbol Conditions Min. Typ. Max. Unit

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz)

VRBN to B and change the chroma phase. Assume the maximum 0.53 0.63 0.73
Demodulation output
amplitude at TP41 as VB, the maximum amplitude at TP43
amplitude ratio
as VG, and the maximum amplitude at TP45 as VR.
(NTSC)
VGBN VRBN = VR/VB, VGBN = VG/VB 0.25 0.32 0.39
SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz)

RBN to B and change the chroma phase. Assume the phase at 99 109 119 deg
Demodulation output
which the amplitude at TP41, TP43 and TP45 reaches a
phase difference
maximum as B, G and R, respectively.
(NTSC)
GBN RBN = R B, GBN = G B 230 242 254 deg
SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 4.43MHz)

VRBP to B and change the chroma phase. Assume the maximum 0.65 0.75 0.85
Demodulation output amplitude at TP41 as VB, the maximum amplitude at TP43
amplitude ratio (PAL) as VG, and the maximum amplitude at TP45 as VR.
VGBP VRBP = VR/VB, VGBP = VG/VB 0.33 0.40 0.47
SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 4.43MHz)

RBP to B and change the chroma phase. Assume the phase at 80 90 100 deg
Demodulation output
which the amplitude at TP41, TP43 and TP45 reaches a
phase difference
maximum as B, G and R, respectively.
(PAL)
GBP RBP = R B, GBP = G B 232 244 256 deg
SW59 = A

Color difference input Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz,
color adjustment no burst) to (D). Assume the output amplitude at TP41
GEXCMX 4 6 dB
characteristics when serial bus register COLOR = 80H as VC0, when
MAX COLOR = 0H as VC2, and when SIG1 is set to 10dB and
COLOR = 0FFH as VC1.
Color difference input
GEXCMX = 20 log (VC1/VC0) + 10
color adjustment
GEXCMN GEXCMN = 20 log (VC2/VC0) 20 15 dB
characteristics
SW50, SW51 = A
MIN

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz,

no burst) to (D) and (E). Assume the output amplitude at
Color difference
VEXCBL TP41 as VB and the output amplitude at TP45 as VR. 0.8 1.0 1.2
balance
VEXCBL = VR/VB
SW50, SW51 = A

GEXRMX Input SIG5 (VL = 150mV) to (A) and SIG1 (6dB, 100kHz, 2 3 dB
Color difference input no burst) to (D) and (E). Assume the output amplitude at
balance adjustment R TP45 and TP41 when serial bus register HUE = 80H as VR0
and VB0, respectively, when HUE = 0FFH as VR1 and
GEXRMN 3 2 dB
VB1, respectively, and when HUE = 0H as VR2 and VB2,
respectively.
GEXRMX = 20 log (VR1/VR0)
GEXBMX 3 2 dB
GEXRMN = 20 log (VR2/VR0)
Color difference input
GEXBMX = 20 log (VB1/VB0)
balance adjustment B
GEXBMN = 20 log (VB2/VB0)
GEXBMN 2 3 dB
SW50, SW51 = A

15
 CXA2503AR

Item Symbol Conditions Min. Typ. Max. Unit

Input SIG5 (VL = 150mV) to (A) and SIG1
(0dB, 100kHz, no burst) to (D). Assume the NTSC 0.23 0.25 0.28
output amplitude at TP41 as VEXB and the
VEXGB
output amplitude at TP43 as VEXBG.
VEXGB = VEXBG/VEXB PAL 0.17 0.19 0.21
G-Y matrix SW50, SW51 = A
characteristics
Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no
burst) to (E). Assume the output amplitude at TP45 as
VEXGR VEXR and the output amplitude at TP43 as VEXRG. 0.48 0.53 0.58
VEXGR = VEXRG/VEXR
SW50, SW51 = A

RGB signal output block

Input SIG5 (VL = 0mV) to (A). Adjust serial bus register
RGB signal output
VOUT BRIGHT so that the output (black-black) at TP43 is 9Vp-p 5.85 6.00 6.15 V
DC voltage
and measure the DC voltage at TP41, TP43 and TP45.

Input SIG5 (VL = 0mV) to (A). Adjust serial bus register

RGB signal output BRIGHT so that the output (black-black) at TP43 is 9Vp-p,
VOUT 0 100 mV
DC voltage difference measure the DC voltage at TP41, TP43 and TP45, and
obtain the maximum difference between these values.

Input SIG3 to (A). Vary V53 and measure the maximum

VLIMMX value VLIMMX and minimum value VLIMMN of the voltage 9.0 Vp-p
RGB output limiter
range (black black) over which the black limiter operates for
operation voltage
the TP41, TP43 and TP45 outputs. Assume the value when
VLIMMN 5.2 Vp-p
V53 = 0V as VLIMMX, and when V53 = 4.5V as VLIMMN.

Input SIG5 (VL = 0mV) to (A) and measure the output

BRTMX (black black) at TP41, TP43 and TP45 when serial bus 9.0 Vp-p
Amount of change in register BRIGHT = 0H.
brightness
Input SIG5 (VL = 0mV) to (A) and measure the output
BRTMN (black black) at TP41, TP43 and TP45 when serial bus 4.0 Vp-p
register BRIGHT = 0FFH.
Input SIG5 (VL = 0mV) to (A) and measure the difference
Amount of change in between the outputs (black-black) at TP41 and TP45 and
SBBRT 1.5 2.0 V
sub-brightness the output (black black) at TP43 when serial bus registers
R-BRT = B-BRT = 0H and when R-BRT = B-BRT = 0FFH.

Difference in gain Input SIG4 to (A) and obtain the level difference between
between RGB output GRGB the maximum and minimum non-inverted output amplitudes 0.5 0 0.5 dB
signals (white black) at TP41, TP43 and TP45.

Difference in RGB Input SIG4 to (A) and obtain the level difference between
output inverted/ GINV the non-inverted output amplitudes (white black) and the 0.5 0 0.5 dB
non-inverted gain inverted output amplitudes at TP41, TP43 and TP45.

Difference in black level Input SIG4 to (A) and obtain the level difference between
potential between RGB VBL the maximum and minimum black levels of both the inverted 300 mV
output signals and non-inverted outputs at TP41, TP43 and TP45.

16
 CXA2503AR

Item Symbol Conditions Min. Typ. Max. Unit

Input SIG8 to (A). Adjust the non-inverted output black level at
G1 TP43 to 6 4.5V with serial bus register BRIGHT and the non- 23.0 26.0 29.0 dB
inverted output amplitude (white black) at TP43 to 3.5V with
serial bus register CONTRAST. Measure VG1, VG2 and VG3.
gain G2 12.0 15.0 18.0 dB
G1 = 20 log (VG1/0.0357)
G2 = 20 log (VG2/0.0357)
G3 G3 = 20 log (VG3/0.0357)
18.0 22.0 26.0 dB
(See Fig. 5 for definitions of VG1, VG2 and VG3.)

Input SIG8 to (A) and adjust serial bus register BRIGHT so

V1MN that the output at TP43 is 9Vp-p (black black). Read the 0 IRE
1 adjustment variable point where the gain of the non-inverted output at TP43
range changes when serial bus register 1 = 0H and 0FFH from
V1MX the input signal IRE level. 100 IRE
V1MN when 1 = 0H, and V1MX when 1 = 0FFH.

Input SIG8 to (A) and adjust serial bus register BRIGHT so

V2MN that the output at TP43 is 9Vp-p (black black). Read the 100 IRE
2 adjustment variable point where the gain of the non-inverted output at TP43
range changes when serial bus register 2 = 0H and 0FFH from
V2MX the input signal IRE level. 0 IRE
V2MN when 2 = 0H, and V2MX when 2 = 0FFH.

Filter characteristics
Assume the chroma amplitude at TP52 NTSC 1.5MHz 16 10 dB
when SIG5 (VL = 0mV) is input to (A)
and SIG1 (0dB at input center frequency
PAL 2.0MHz 16 10 dB
Amount of BPF (3.58MHz or 4.43MHz)) is input to (B) as
ATBPF
attenuation 0dB. Obtain the amount by which the
NTSC 5.5MHz 7 2 dB
output at TP52 is attenuated when the
frequencies noted on the right are input.
SW59 = A PAL 6.8MHz 8 3 dB

Input SIG2 (0dB, 3.58MHz or 4.43MHz) to (A)

ATRAPN and measure the output at TP43. Assume the NTSC 40 30 dB
Amount of TRAP
amplitude at TP43 during Y/C input mode as 0dB,
attenuation
and obtain the amount of attenuation during
ATRAPP PAL 40 30 dB
COMP input mode.

Assume the amplitude of the 100kHz component of the

output at TP43 when SIG5 (VL = 150mV) is input to (A) and
R-Y, B-Y and LPF SIG2 (0dB, 3.58MHz + 100kHz) is input to (B) as 0dB.
DEMLPF 0.8 1.0 1.3 MHz
characteristics Obtain the frequency which attenuates the beat component
of the output by 3dB when the SIG2 frequency is increased
with respect to 3.58MHz.

Sync separation, TG block

Input SIG5 (VL = 0mV, VS = 143mV, WS variable) to (A)
and confirm that it is synchronized with the HD output at
Input sync signal width
WSSEP TP22. Gradually narrow the WS of SIG5 from 4.7s and 2.0 s
sensitivity
obtain the WS at which synchronization with the HD output
at TP22 is lost.

Input SIG5 (VL = 0mV, WS = 4.7s, VS variable) to (A)

and confirm that it is synchronized with the HD output at
Sync separation input
VSSEP TP22. Gradually reduce the VS of SIG5 from 143mV and 40 60 mV
sensitivity
obtain the VS at which synchronization with the HD output
at TP22 is lost.
17
 CXA2503AR

Item Symbol Conditions Min. Typ. Max. Unit

Input SIG5 (VL = 0mV, WS = 4.7s, VS = 143mV) to (A) and

TDSYL 430 630 830 ns
measure the delay time with the RPD output at TP12. TDSYL is
Sync separation
from the falling edge of the input HSYNC to the falling edge of
output delay time
TDSYH the RPD output at TP12, and TDSYH is from the falling edge of 4.7 5.0 5.3 s
the input HSYNC to the rising edge of the RPD output at TP12.

Input SIG5 (VL = 0mV, WS = 4.7s, VS = 143mV,

HPLLN horizontal frequency variable) to (A) and confirm that NTSC 500 Hz
it is synchronized with the HD output at TP22. Obtain
Horizontal pull-in the frequency fH at which the input and output are
range synchronized by changing the horizontal frequency
of SIG5 from the non-synchronized condition.
HPLLP PAL 500 Hz
HPLLN = fH 15734
HPLLP = fH 15625

tTLH Input SIG5 (VL = 0mV) to (A). 30 ns

Output transition time
Load = 30pF
(2 pins)
tTHL (See Fig. 3.) 30 ns

Input SIG5 (VL = 0mV) to (A).

Cross-point time Measure HCK1/HCK2 and VCK1/VCK2.
T 10 ns
difference Load = 30pF
(See Fig. 4.)

Input SIG5 (VL = 0mV) to (A).

HCK duty DTYHC Measure the HCK1/HCK2 duty. 47 50 53 %
Load = 30pF

External I/O characteristics

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL variable) to (C).
VTEXTB 0.8 1.0 1.2 V
Raise the SIG6 amplitude (VL) from 0V and assume the
External RGB input
voltage where the outputs at TP41, TP43 and TP45 go to black
threshold voltage
VTEXTW level as VTEXTB. Then raise the amplitude further and assume V
1.8 2.0 2.2
the voltage where these outputs go to white level as VTEXTW.

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 3V) to (C).
Propagation delay time TD1EXT 50 100 150 ns
Measure the rise delay time TD1EXT and the fall delay
between external RGB
time TD2EXT of the outputs at TP41, TP43 and TP45.
input and output TD2EXT 50 100 150 ns
(See Fig. 2.)

Output blanking level Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 1.7V) to (C).
during external RGB EXTBK Measure the difference from the black level of the outputs 0 V
input at TP41, TP43 and TP45.

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V) to (C).
Output white level during
EXTWT Measure the difference from the black level of the outputs 3.5 V
external RGB input
at TP41, TP43 and TP45.

18
 CXA2503AR

Item Symbol Conditions Min. Typ. Max. Unit

Serial transfer block
LOAD setup time, activated by the rising edge of SCLK.
ts0 150 ns
(See Fig. 6.)
Data setup time
DATA setup time, activated by the rising edge of SCLK.
ts1 150 ns
(See Fig. 6.)

LOAD hold time, activated by the rising edge of SCLK.

th0 150 ns
(See Fig. 6.)
Data hold time
DATA hold time, activated by the rising edge of SCLK.
th1 150 ns
(See Fig. 6.)
tw1L SCLK pulse width. (See Fig. 6.) 160 ns

Minimum pulse width tw1H SCLK pulse width. (See Fig. 6.) 160 ns
tw2 LOAD pulse width. (See Fig. 6.) 1 s

Other
VPLLMN 5.65 5.8 5.95
Measure the DC voltage of the output at TP11 when serial
AFC adjustment voltage
VPLLTP bus register PLL ADJ = 0H, 80H and 0FFH as VPLLMN, 7.4 7.5 7.6 V
output range
VPLLTP and VPLLMX, respectively.
VPLLMX 9.15 9.3 9.45

19
 Description of Electrical Characteristics Measurement Methods
Serial Bus Register Initial Values
Serial bus

Item Symbol Mode settings DAC settings

Input System Panel S/H H-POSI HD-POSI HUE COLOR BRIGHT CONTRAST R-BRT B-BRT 1 2

Horizontal AFC adjustment COMP NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

ICC11 COMP NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Current consumption VCC1 ICC12 Y/C NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
ICC13 Y/color NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
difference
Current consumption VCC2 ICC2 COMP NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
IDD1 COMP NTSC LCX009 SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Current consumption VDD
IDD2 COMP NTSC LCX005 SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

Power supply characteristics Setting 2

Input current II1 COMP NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Input current II2 COMP NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

20
High level input voltage VIH COMP NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Low level input voltage VIL COMP NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
High level output voltage VOH1 COMP NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Low level output voltage VOL1 COMP NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
High level output voltage VOH2 COMP NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Low level output voltage VOL2 COMP NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
High level output voltage VOH3 COMP NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

Digital block I/O characteristics

Low level output voltage VOL3 COMP NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Output off leak current IOFF COMP NTSC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

(: don't care, ADJ: adjustment, SET: setting)

CXA2503AR
 Serial bus

Item Symbol Mode settings DAC settings

Input System Panel S/H H-POSI HD-POSI HUE COLOR BRIGHT CONTRAST R-BRT B-BRT 1 2
Video maximum gain GV COMP NTSC Through 10H 0H 80H 80H 80H 0FFH 80H 80H 0H 0H
Contrast characteristics
GCNTTP COMP NTSC Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
TYP

Contrast characteristics
GCNTMN COMP NTSC Through 10H 0H 80H 80H 80H 0H 80H 80H 0H 0H
MIN

FCYYC Y/C NTSC LCX009 Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Y signal frequency
FCYCMN COMP NTSC LCX005 Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
response
FCYCMP COMP PAL LCX005 Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Picture quality GSHP1X COMP NTSC LCX005 Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
adjustment variable
amount 1 GSHP1N COMP NTSC LCX005 Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Picture quality GSHP2X COMP NTSC LCX009 Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
adjustment variable
amount 2 GSHP2N COMP NTSC LCX009 Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

Y signal block

21
Picture quality GSHP3X Y/C NTSC LCX005 Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
adjustment variable
amount 3 GSHP3N Y/C NTSC LCX005 Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Picture quality GSHP4X Y/C NTSC LCX009 Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
adjustment variable
amount 4 GSHP4N Y/C NTSC LCX009 Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

Carrier leak CRLEKY COMP Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
TDYYC Y/C Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

Y signal I/O delay time TDYCMN COMP NTSC Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
TDYCMP COMP PAL Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

(: don't care, ADJ: adjustment, SET: setting)

CXA2503AR
 Serial bus

Item Symbol Mode settings DAC settings

Input System Panel S/H H-POSI HD-POSI HUE COLOR BRIGHT CONTRAST R-BRT B-BRT 1 2

ACC amplitude ACC1 COMP NTSC Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
characteristics 1 ACC1 COMP PAL Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

ACC amplitude ACC2 COMP NTSC Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
characteristics 2 ACC2 COMP PAL Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

FAPCN COMP NTSC Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
APC pull-in range
FAPCP COMP PAL Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

Color adjustment
GCOLMX COMP NTSC Through 10H 0H 80H 0FFH 80H 80H 80H 80H 0H 0H
characteristics MAX

Color adjustment
GCOLMN COMP NTSC Through 10H 0H 80H 0H 80H 80H 80H 80H 0H 0H
characteristics MIN

HUE adjustment
HUEMX COMP NTSC Through 10H 0H 0FFH 80H 96H 80H 80H 80H 0H 0H
characteristics MAX

22
HUE adjustment
HUEMN COMP NTSC Through 10H 0H 0H 80H 96H 80H 80H 80H 0H 0H
characteristics MIN

ACKN COMP NTSC Through 10H 0H 80H 80H 96H 80H 80H 80H 0H 0H

Chroma signal block

Killer operation input
level ACKP COMP PAL Through 10H 0H 80H 80H 96H 80H 80H 80H 0H 0H

Demodulation VRBN COMP NTSC Through 10H 0H 80H 80H 96H 80H 80H 80H 0H 0H
output amplitude
ratio NTSC VGBN COMP NTSC Through 10H 0H 80H 80H 96H 80H 80H 80H 0H 0H
Demodulation RBN COMP NTSC Through 10H 0H 80H 80H 96H 80H 80H 80H 0H 0H
output phase
difference NTSC GBN COMP NTSC Through 10H 0H 80H 80H 96H 80H 80H 80H 0H 0H

Demodulation VRBP COMP PAL Through 10H 0H 80H 80H 96H 80H 80H 80H 0H 0H
output amplitude
ratio PAL VGBP COMP PAL Through 10H 0H 80H 80H 96H 80H 80H 80H 0H 0H

Demodulation RBP COMP PAL Through 10H 0H 80H 80H 96H 80H 80H 80H 0H 0H
output phase
difference PAL GBP COMP PAL Through 10H 0H 80H 80H 96H 80H 80H 80H 0H 0H

(: don't care, ADJ: adjustment, SET: setting)

CXA2503AR
 Serial bus

Item Symbol Mode settings DAC settings

Input System Panel S/H H-POSI HD-POSI HUE COLOR BRIGHT CONTRAST R-BRT B-BRT 1 2
Color difference input
color adjustment GEXCMX Y/color Through 10H 0H 80H 0FFH 80H 80H 80H 80H 0H 0H
difference
characteristics MAX

Color difference input

color adjustment GEXCMN Y/color Through 10H 0H 80H 0H 80H 80H 80H 80H 0H 0H
difference
characteristics MIN

Color difference balance VEXCBL Y/color Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
difference
GEXRMX Y/color Through 10H 0H 0FFH 80H 80H 80H 80H 80H 0H 0H
Color difference input difference
balance adjustment R GEXRMN Y/color Through 10H 0H 0H 80H 80H 80H 80H 80H 0H 0H
difference
GEXBMX Y/color Through 10H 0H 0FFH 80H 80H 80H 80H 80H 0H 0H

Chroma signal block

Color difference input difference
balance adjustment B GEXBMN Y/color Through 10H 0H 0H 80H 80H 80H 80H 80H 0H 0H
difference
Y/color NTSC Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
VEXGB difference
G-Y matrix Y/color PAL Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

23
characteristics difference
VEXGR Y/color Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
difference
RGB signal output
VOUT Through 10H 0H 80H 80H ADJ 80H 80H 80H 0H 0H
DC voltage

RGB signal output

VOUT Through 10H 0H 80H 80H ADJ 80H 80H 80H 0H 0H
DC voltage difference

RGB output limiter VLIMMX Through 10H 0H 80H 80H ADJ 80H 80H 80H 0H 0H
operation voltage VLIMMN Through 10H 0H 80H 80H ADJ 80H 80H 80H 0H 0H

Amount of change in BRTMX Through 10H 0H 80H 80H 0H 80H 80H 80H 0H 0H
brightness BRTMN Through 10H 0H 80H 80H 0FFH 80H 80H 80H 0H 0H

RGB signal output block

Amount of change in
SBBRT Through 10H 0H 80H 80H 0B4H 80H SET SET 0H 0H
sub-brightness

Difference in gain between

GRGB Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
RGB output signals

(: don't care, ADJ: adjustment, SET: setting)

CXA2503AR
 Serial bus

Item Symbol Mode settings DAC settings

Input System Panel S/H H-POSI HD-POSI HUE COLOR BRIGHT CONTRAST R-BRT B-BRT 1 2
Difference in RGB
output inverted/ GINV Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
non-inverted gain

Difference in black
level potential between VBL Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
RGB output signals

G1 Through 10H 0H 80H 80H ADJ ADJ 80H 80H 78H 0D7H
gain G2 Through 10H 0H 80H 80H ADJ ADJ 80H 80H 78H 0D7H
G3 Through 10H 0H 80H 80H ADJ ADJ 80H 80H 78H 0D7H

RGB signal output block

1 adjustment variable V1MN Through 10H 0H 80H 80H ADJ 46H 80H 80H 0H 0H
range V1MX Through 10H 0H 80H 80H ADJ 46H 80H 80H 0FFH 0H

2 adjustment variable V2MN Through 10H 0H 80H 80H ADJ 46H 80H 80H 0H 0H
range

24
V2MX Through 10H 0H 80H 80H ADJ 46H 80H 80H 0H 0FFH
Amount of BPF attenuation ATBPF COMP SET Through 10H 0H 80H 80H 96H 80H 80H 80H 0H 0H

Amount of TRAP ATRAPN SET NTSC Through 10H 0H 80H 80H 96H 80H 80H 80H 0H 0H
attenuation ATRAPP SET PAL Through 10H 0H 80H 80H 96H 80H 80H 80H 0H 0H
R-Y, B-Y and LPF
DEMLPF Y/C NTSC Through 10H 0H 80H 80H 96H 80H 80H 80H 0H 0H
characteristics

Filter characteristics
(: don't care, ADJ: adjustment, SET: setting)
CXA2503AR
 Serial bus

Item Symbol Mode settings DAC settings

Input System Panel S/H H-POSI HD-POSI HUE COLOR BRIGHT CONTRAST R-BRT B-BRT 1 2
Input sync signal width
WSSEP Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
sensitivity

Sync separation input

VSSEP Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
sensitivity

Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

Sync separation output TDSYL
delay time TDSYH Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

HPLLN NTSC Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Horizontal pull-in range
HPLLP PAL Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

tTLH SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

Output transition time

Sync separation, TG block

tTHL SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Cross-point time
T SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
difference

25
HCK duty DTYHC SHS1 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H

External RGB input VTEXTB Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
threshold voltage VTEXTW Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Propagation delay time TD1EXT Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
between external RGB
input and output TD2EXT Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
Output blanking level
during external EXTBK Through 10H 0H 80H 80H 80H 80H 80H 80H 0H 0H
RGB input

External I/O characteristics

Output white level during
EXTWT Through 10H 0H 80H 80H 64H 80H 80H 80H 0H 0H
external RGB input

VPPLMN
AFC adjustment
VPPLTP
voltage output range

Other
VPPLMX

(: don't care, ADJ: adjustment, SET: setting)

CXA2503AR
 CXA2503AR

3V
SIG6

0V

TP41, 43, 45
non-inverted output 50%

TD1EXT TD2EXT

Fig. 2. Conditions for measuring the delay between external RGB input and output

90%

50%

10%

tTLH tTHL T T

Fig. 3. Output transition time measurement Fig. 4. Cross-point time difference measurement
conditions conditions

White
VG3
Non-inverted output

VG2 3.5V

VG1
Black
1.5V

Fig. 5. characteristics measurement conditions

26
 CXA2503AR

DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15

ts1 th1

SCLK 50%

tw1H tw1L

LOAD 50%

ts0 th0 tw2

Fig. 6. Serial transfer block measurement conditions

27
 CXA2503AR

Input Waveforms

SG No. Waveform

Sine wave video signal:With/without burst

Amplitude and frequency variable

SIG1 150mV Value noted on left: 0dB

150mV
143mV

Chroma signal: Burst, chroma frequency (3.579545MHz, 4.433619MHz)

Chroma phase and burst frequency variable

SIG2
150mV Value noted on left: 0dB

143mV

Ramp waveform

357mV
SIG3

143mV
1H

5-step staircase waveform

150mV
SIG4
143mV
1H

VL amplitude variable
VS variable: 143mV unless otherwise specified
WS variable:4.7s unless otherwise specified
VL fH variable: 15.734kHz (NTSC) or
SIG5 15.625kHz (PAL)
unless otherwise specified
VS
fH WS

28
 CXA2503AR

SG No. Waveform

30s 5s

VL amplitude variable

SIG6 VL

Horizontal sync signal

75mV

Frequency variable
SIG7 175mV

143mV

10-step staircase waveform

357mV
SIG8

143mV
1H

2T pulse waveform VL amplitude variable

VS variable:143mV unless otherwise specified
WS variable:4.7s unless otherwise specified
VL
fH variable: 15.734kHz (NTSC) or
SIG9 15.625kHz (PAL)
unless otherwise specified
VS
fH WS

29
 CXA2503AR

Electrical Characteristics Measurement Circuit

+12V

ICC2 TP45 TP43 TP41

0.1

47
100p 100p 100p
S39 TP38 TP37 TP36 TP35 TP34 TP33
+4.5V
0.01
0.47 0.47 0.47
ICC1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

B OUT
FB G
VCC2

DATA
TEST3
GND2
G OUT
FB R

SCLK
TEST2
RGT
FB B
R OUT
SIG.CENTER

LOAD
TEST4
47 0.1

49 VCC1 VSS2 32
SW50
(D) A 0.01
50 B-Y IN VD2 31 TP31
B
(E) A 0.01
51 R-Y IN VD1 30 TP30
B
SW51
TP52 52 C OUT EN 29 TP29

53 BLK LIM VCK1 28 TP28

V53 SW53
54 APC VCK2 27 TP27
15k 1
55 VXO OUT VST 26 TP26
0.068
0.22
56 VXO IN TEST1 25 TP25
2

57 V REG FLD IN 24 TP24

1

58 START UP FLD OUT 23 TP23

(B) A
59 C IN HD 22 TP22
SW59 B
82k
60 F0 ADJ HCK1 21 TP21
6
61 GND3 HCK2 20 TP20
1
62 Y IN HST 19 TP19

63 PIC CLR 18 TP18

V63 SW63
H.FIL OUT

VDD2 17
VCO ADJ

64 TEST0
S.SEP IN

S64
SYNC IN
PWRST

EXT G
EXT R

EXT B
GND1
VD IN

TRAP

VDD1
VSS1

CKO
RPD

CKI

3V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TP11 TP12 4 ICC3
SW1 750
S2 B AB A B A
V1 0.033 0.47 1k 220p 68p 47 0.1
4.5V

10k 33k
5 SW8 SW9 SW10 3300p 3
(A)
(C) 3.3

10k 0.01

1 Used crystal: KINSEKI CX-5F 4 L value: 8.2H during LCX005 mode

Frequency deviation: within 30ppm, frequency temperature 3.9H during LCX009 mode
characteristics: within 30ppm, load capacity: 16pF 5 Trap (TDK)
NTSC: 3.579545MHz NTSC: NLT4532-S3R6B
PAL: 4.433619MHz PAL: NLT4532-S4R4
2 NTSC: none, PAL: 18pF 6 Resistance value tolerance: 2%,
3 Varicap diode: 1T369 (SONY) temperature coefficient: 200ppm or less

30
 CXA2503AR

Description of Operation

The CXA2503AR incorporates the three functions of an RGB decoder block, an RGB driver block and a timing
generator (TG) block onto a single chip using BiCMOS technology.

1) RGB decoder block

Input mode switching

The input mode can be switched between composite input, Y/C input and Y/color difference input by the
serial bus settings.
During composite input: The composite signal is input to Pins 5, 59 and 62.
During Y/C input: The Y signal is input to Pins 5 and 62, and the C signal to Pin 59.
During Y/color difference input: The Y signal is input to Pins 5 and 62, the B-Y signal to Pin 50, and the R-Y
signal to Pin 51.

System switching
The input system can be switched between NTSC and PAL (DPAL using external delay line and SPAL) by
the serial bus settings.

Trap, BPF
The center frequency of the built-in trap and BPF can be switched to 3.58MHz during NTSC and 4.43MHz
during PAL.
During composite input, the Y signal enters the trap circuit and the C signal enters the BPF. These signals do
not pass through the trap or BPF during Y/C input and Y/color difference input.

ACC detection, ACC amplifier

The amplitude of the burst signal output from the ACC amplifier is detected and the ACC amplifier is
controlled to maintain the burst signal amplitude at a constant level.

VXO, APC detection

The VXO local oscillation circuit is a crystal oscillation circuit. The phases of the input burst signal and the
VXO oscillator output are compared in the APC detection block, and the detective output is used to form a
PLL loop that controls the VXO oscillation frequency, which means that the need for adjustments is
eliminated.

External inputs
These are digital inputs with two thresholds. When one of the RGB inputs is higher than the lower threshold
Vth1 ( 1.0V), all RGB outputs go to black level. When the higher threshold Vth2 ( 2.0V) is exceeded, the
output for only the signal in question goes to white level, while the other outputs remain at black level.

31
 CXA2503AR

2) RGB driver block

correction
In order to support the characteristics of LCD panels, the I/O characteristics are as shown in Fig. 1. The
characteristics change as shown in Fig. 2 by adjusting the serial bus register 1, and as shown in Fig. 3 by
adjusting 2.

B'
Output Output Output
A' B'
B B
A A
B

Input Input Input

Fig. 1 Fig. 2 Fig. 3

Sample-and-hold circuit
As LCD panels sample RGB signals simultaneously, RGB signals output from the CXA2503AR must be
sampled-and-held in sync with the LCD panel drive pulses.

R S/H1 S/H4 HCK1

S/H2 S/H4 A
G

B
B S/H3 S/H4

C
SH1 SH2 SH3 SH4

RGT = H (normal) RGT = L (inverted)

SHS1 SHS2 SHS3 SHS1 SHS2 SHS3

SH1 B A C SH1 B A C
SH1: R signal SH pulse
SH2 Through Through Through SH2 A C B
SH2: G signal SH pulse
SH3 A C B SH3 Through Through Through SH3: B signal SH pulse
SH4 C B A SH4 C B A SH4: RGB signal SH pulse

The sample-and-hold circuit performs sample and hold by receiving the SH1 to SH4 pulses from the TG
block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must
be compensated by 1.5 dots. This relationship is reversed during right/left inversion. This compensation
timing is also generated by the TG block. The sample-and-hold timing changes according to the phase
relationship with the HCK1 pulse, so the timing should be set to SHS1, 2 or 3 in accordance with the actual
board.
32
 CXA2503AR

RGB output
RGB outputs (Pins 41, 43, and 45) are inverted each horizontal line by the FRP pulse supplied from the TG
block as shown in the figure below. Feedback is applied so that the center voltage (Vsig center) of the output
signal matches the reference voltage (VCC2 + GND2)/2 (or the voltage input to SIG CENTER (Pin 48)). In
addition, the white level output is clipped by the Vsig center 0.7V, and the black level output is clipped by
the limiter operation point that is adjusted at the BLKLIM (Pin 53).

Video IN

FRP

Black level limiter

White level limiter

RGB OUT Vsig center
White level limiter

Black level limiter

3) TG block

PLL and AFC circuits

The TG block contains a PLL circuit phase comparator and frequency division counter, and a PLL circuit can
be comprised by connecting an external VCO circuit.
The PLL error detection signal is generated at the following timing. The phase comparison output of the
entire bottom of HSYNC and the internal frequency division counter becomes RPD. RPD output is converted
to DC error with the lag-lead filter, and then it changes the varicap capacitance to stabilize the oscillation
frequency at 702fH in the LCX005BK/BKB and 1050fH in the LCX009AK/AKB. The PLL of this system is
adjusted by setting the serial bus register PLL ADJ so that RPD changes in the center of the window as
shown in the figure below.

H SYNC
WS

RPD

WL WH WL = WH

H position
The horizontal display position can be set at 2fH intervals in 32 different ways by the serial bus settings.
The picture center is set at the internal default value, but because there is a difference between the RGB
signal and the drive pulse delays on the actual board, the picture center may not match the design center. In
this case, adjust with the serial bus.
33
 CXA2503AR

Right/left inversion
The LCD panel is arranged in a delta pattern, where identical signal lines are offset by 1.5 dots from
adjoining lines. For this reason, a 1.5-bit offset is attached to the horizontal start pulse (HST) between odd
lines and even lines. HCK and S/H are also 1.5-bit offset in a similar manner.
When the panel is driven by left scan (Reverse scan), this offset relationship is inverted for even and odd
lines. Moreover, since the dot arrangement is asymmetrical, the HST position is also changed.
RGT = H: Right scan mode
RGT = L: Left scan mode
Right scan Left scan
(Normal scan) (Reverse scan)

H SCANNER
V SCANNER

Display area

LCD panel

WIDE mode
Setting the WIDE mode by switching the aspect ratio with the serial bus shifts the unit to WIDE mode. In this
mode, the aspect ratio is converted through pulse eliminator processing, allowing 16:9 quasi-WIDE display.
During WIDE mode, vertical pulse eliminator scanning of 1/4 for NTSC or 1/2 and 1/4 for PAL are performed,
and the video signal is compressed to achieve a 16:9 aspect ratio. In addition, in areas outside the display
area, black is displayed by performing high-speed scanning.
The timing during high-speed scanning is a 2H cycle pulse consisting of normal drive (1H) and quadruple-
speed drive (1H) and black signals are written in the 28 and 27 lines, respectively at the top and bottom of
this display area. During this time, FRP is changed to a 4H cycle, HST to a 2H cycle, and EN and CLR are
not output.

See the attached sheets for detailed timing. Vertical high-speed scanning

Black display area 28LINE

(28LINE)

218LINE 163LINE
Display area Display area
(225LINE) (169LINE)

Black display area 27LINE

(28LINE)

4:3 display Vertical pulse eliminator scanning 16:9 display

(during normal-speed scanning)

Numbers in parentheses are for the LCX009AK/AKB.

All other numbers are for the LCX005BK/BKB.
34
 CXA2503AR

During high-speed scanning During normal-speed scanning

VCK1

Quadruple-speed scanning
Normal-speed scanning

HST

2H cycle

FRP
(internal pulse)
4H cycle

SBLK
(internal pulse)

AC driving of LCD panels during no signal

HST, HCK1, HCK2, VST, VCK1, VCK2, HD, VD1, VD2 and FRP are made to run free so that the LCD panel
is AC driven even when there is no composite sync from the SYNC IN pin.
During this time, the HSYNC separation circuit stops and the PLL counter is made to run free. In addition, the
VSYNC separation circuit is also stopped, so the auxiliary V counter is used to create the reference pulse for
generating VD1 and VST.
The cycle of this V counter is designed to be 269H for NTSC and 321H for PAL. However, when there is no
vertical sync signal for 5 frames, the no signal state is assumed and the free running VD1 and VST pulses
are generated from the next field.
In addition, RPD is kept at high impedance when there is no signal in order to prevent the AFC circuit from
causing errors due to phase comparison.

35
 CXA2503AR

Description of Serial Control Operation

1) Control method

Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCLK. This
loading operation starts from the falling edge of LOAD and is completed at the next rising edge. (D13 to D15
are dummy data.)

Digital block control data is established by the vertical sync signal, so if data is transferred multiple times for
the same item, the data immediately before the vertical sync signal is valid.
Analog (electronic attenuator) block control data becomes valid each time the LOAD signal is input.

DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SCLK

LOAD

Serial transfer timing

2) Serial data map

The serial data map is as follows.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VD HD Supported Input
0 0 0 0 S/H phase System
polarity polarity panel switching

External FRP SYNC FRP256 Y/color

0 0 1 0 0 0 1F Mode Aspect difference
VSYNC polarity GEN inversion clamp
0 1 0 HD-POSITION H-POSITION

1 0 0 0 0 HUE

1 0 0 0 1 COLOR

1 0 0 1 0 BRIGHT

1 0 0 1 1 CONTRAST

1 0 1 0 0 R-BRT

1 0 1 0 1 B-BRT

1 0 1 1 0 1

1 0 1 1 1 2

1 1 0 0 0 PLL ADJ

36
 CXA2503AR

3) Serial data mode settings

Input switching
D1 D0
0 X Composite input (default)
1 0 Y/C input
1 1 Y/color difference input
System switching
D3 D2
0 X NTSC (default)
1 0 D-PAL
1 1 S-PAL
Supported panel switching
D4
0 LCX005 (default)
1 LCX009
HD output polarity switching
D5
0 Negative polarity (default)
1 Positive polarity
VD1 output polarity switching
D6
0 Negative polarity (default)
1 Positive polarity
Sample-and-hold timing switching
D8 D7
0 0 SHS1 (default)
0 1 SHS2
1 0 SHS3
1 1 Through (sample-and-hold not performed)
Y/color difference clamp position switching
This switches the position at which the R-Y and B-Y input signals are clamped during Y/color difference input
mode.
D0
0 Pedestal position (default)
1 SYNC position
Aspect switching
D1
0 4:3 (normal) (default)
1 16:9 (pulse eliminator WIDE)
Mode switching
This is the test mode. Set to normal mode.
D2
0 Normal mode (default)
1 Test mode
37
 CXA2503AR

FRP256 field inversion

This further inverts the polarity of the RGB output that is inverted every 1H for 256 fields.
D3
0 OFF (default)
1 ON
Sync generator function
This stops the HST, VST and FRP outputs of the TG block.
D4
0 OFF (default)
1 ON
FRP polarity inversion function
D5
0 ON (1H inversion) (default)
1 OFF (polarity not inverted)
External VSYNC input switching
Internal VSYNC separation is not performed and an externally input VSYNC is used.
D6
0 OFF (default)
1 ON
H position setting
D4 D3 D2 D1 D0
0 0 0 0 0
to to to to to
1 0 0 0 0 (default)
to to to to to
1 1 1 1 1
Variable in 2fH (= 1 bit) increments

CLK (internal)

10001

HST 10000

01111

1 step 1 step
HD phase setting
D9 D8 D7 D6 D5
0 0 0 0 0 (default)
to to to to to
1 1 1 1 1
Variable in 4fH (= 1 bit) increments

HSYNC

HD 00000

11111

31 steps

38
 CXA2503AR

4) Serial data electronic attenuator (D/A converter) settings

HUE
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0 (default)
COLOR
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0 (default)
BRIGHT
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0 (default)
CONTRAST
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0 (default)
R-BRT
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0 (default)
B-BRT
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0 (default)
-1
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 (default)
-2
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 (default)
PLL-ADJ
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 0 0 0 0 (default)

39
 CXA2503AR

LCX005BK/BKB and LCX009AK/AKB Color Coding Diagram

The delta arrangement is used for the color coding in the LCD panels with which this IC is compatible. Note
that the shaded region within the diagram is not displayed.

LCX005BK/BKB pixel arrangement

dummy1 HSW1 HSW2 HSW3 HSW174 HSW175 dummy2 to 5

dummy1 G B R G B R G B R G B R G Photo-shielding
B R G B R
2
area
dummy2 B R G B R G B R G B R G B R G B R G

Vline1 G B R G B R G B R G B R G B R G B R

Vline2 B R G B R G B R G B R G B R G B R G

Vline3 G B R G B R G B R G B R G B R G B R

B R G B R G B R Display
G B area
R G B R G B R G

G B R G B R G B R G B R G B R G B R 218 222

B R G B R G B R G B R G B R G B R G

Vline217 G B R G B R G B R G B R G B R G B R

Vline218 B R G B R G B R G B R G B R G B R G

dummy3 G B R G B R G B R G B R G B R G B R
2
dummy4 B R G B R G B R G B R G B R G B R G

3 521 13

537

Basic specifications

Total horizontal dots: 537H

Horizontal display dots: 521H

Total vertical dots: 222H

Vertical display dots: 218H

Total dots: 119,214H

Display dots: 113,578H

40
 CXA2503AR

LCX009AK/AKB pixel arrangement

dummy1 to 4 HSW1 HSW2 HSW267 HSW268 dummy5 to 8

dummy1 B R G B R G B R G B R G R G B R
B Photo-shielding
area 2
dummy2 R G B R G B R G B R G B R G B R G

Vline1 B R G B R G B R G B R G B R G B R

Vline2 R G B R G B R G B R G B R G B R G

Vline3 B R G B R G B R G B R G B R G B R

R G B R G B R B R area
G Display G B R G B R G

B R G B R G B R G B R G B R G B R 225 228

R G B R G B R G B R G B R G B R G

B R G B R G B R G B R G B R G B R

Vline224 R G B R G B R G B R G B R G B R G

Vline225 B R G B R G B R G B R G B R G B R

dummy3 R G B R G B R G B R G B R G B R G 1

14 800 13

827

Basic specifications

Total horizontal dots: 827H

Horizontal display dots: 800H

Total vertical dots: 228H

Vertical display dots: 225H

Total dots: 188,556H

Display dots: 180,000H

41
 LCX005BK/BKB Horizontal Direction Timing Chart Unless otherwise specified, serial settings are the default values.
NTSC/PAL RGT: H (Normal scan)
702fH

MCK

SYNC 4.7s (52fH)

(BLK) 4.7s (52fH)

HD 2.0s (22fH) 4.5s (50fH)

HST 22.5fH 13fH

HCK1

HCK2
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)

42
SH2
(Internal pulse)
FRP
ODD FIELD EVEN FIELD
(Internal pulse)
VCK1 19.5fH

VCK2

CLR 3.0s (33fH) 0.5s (6fH)

EN
(PAL)
VST/VD1 5fH

ODD LINE

Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX005BK/BKB Horizontal Direction Timing Chart Unless otherwise specified, serial settings are the default values.
NTSC/PAL RGT: H (Normal scan)
702fH

MCK

SYNC 4.7s (52fH)

(BLK) 4.7s (52fH)

HD 2.0s (22fH) 4.5s (50fH)

HST 21.0fH 13fH

HCK1

HCK2
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)

43
SH2
(Internal pulse)
FRP
ODD FIELD EVEN FIELD
(Internal pulse)
VCK1 18.0fH

VCK2

CLR 3.0s (33fH) 0.5s (6fH)

EN
(PAL)
VST/VD1 5fH

EVEN LINE

Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX005BK/BKB Horizontal Direction Timing Chart Unless otherwise specified, serial settings are the default values.
NTSC/PAL RGT: L (Reverse scan)
702fH

MCK

SYNC 4.7s (52fH)

(BLK) 4.7s (52fH)

HD 2.0s (22fH) 4.5s (50fH)

HST 22.0fH 13fH

HCK1

HCK2
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)

44
SH2
(Internal pulse)
FRP
ODD FIELD EVEN FIELD
(Internal pulse)
VCK1 18.0fH

VCK2

CLR 3.0s (34fH) 0.5s (5fH)

EN
(PAL)
VST/VD1 5fH

ODD LINE

Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX005BK/BKB Horizontal Direction Timing Chart Unless otherwise specified, serial settings are the default values.
NTSC/PAL RGT: L (Reverse scan)
702fH

MCK

SYNC 4.7s (52fH)

(BLK) 4.7s (52fH)

HD 2.0s (22fH) 4.5s (50fH)

HST 23.5fH 13fH

HCK1

HCK2
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)

45
SH2
(Internal pulse)
FRP
ODD FIELD EVEN FIELD
(Internal pulse)
VCK1 19.5fH

VCK2

CLR 3.0s (34fH) 0.5s (5fH)

EN
(PAL)
VST/VD1 5fH

EVEN LINE

Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX009AK/AKB Horizontal Direction Timing Chart Unless otherwise specified, serial settings are the default values.
NTSC/PAL RGT: H (Normal scan)
1050fH

MCK

SYNC 4.7s (78fH)

(BLK) 4.7s (78fH)

HD 2.0s (33fH) 4.5s (73fH)

HST 22.5fH 12fH

HCK1

HCK2
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)

46
SH2
(Internal pulse)
FRP
ODD FIELD EVEN FIELD
(Internal pulse)
VCK1 44.5fH

VCK2

CLR 3.0s (50fH) 0.5s (8fH)

EN
(PAL)
VST/VD1 1fH

ODD LINE

Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX009AK/AKB Horizontal Direction Timing Chart Unless otherwise specified, serial settings are the default values.
NTSC/PAL RGT: H (Normal scan)
1050fH

MCK

SYNC 4.7s (78fH)

(BLK) 4.7s (78fH)

HD 2.0s (33fH) 4.5s (73fH)

HST 21.0fH 12fH

HCK1

HCK2
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)

47
SH2
(Internal pulse)
FRP
ODD FIELD EVEN FIELD
(Internal pulse)
VCK1 43.0fH

VCK2

CLR 3.0s (50fH) 0.5s (8fH)

EN
(PAL)
VST/VD1 1fH

EVEN LINE

Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX009AK/AKB Horizontal Direction Timing Chart Unless otherwise specified, serial settings are the default values.
NTSC/PAL RGT: L (Reverse scan)
1050fH

MCK

SYNC 4.7s (78fH)

(BLK) 4.7s (78fH)

HD 2.0s (33fH) 4.5s (73fH)

HST 22.0fH 12fH

HCK1

HCK2
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)

48
SH2
(Internal pulse)
FRP
ODD FIELD EVEN FIELD
(Internal pulse)
VCK1 43.0fH

VCK2

CLR 3.0s (51fH) 0.5s (7fH)

EN
(PAL)
VST/VD1 1fH

ODD LINE

Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX009AK/AKB Horizontal Direction Timing Chart Unless otherwise specified, serial settings are the default values.
NTSC/PAL RGT: L (Reverse scan)
1050fH

MCK

SYNC 4.7s (78fH)

(BLK) 4.7s (78fH)

HD 2.0s (33fH) 4.5s (73fH)

HST 23.5fH 12fH

HCK1

HCK2
SH3
(Internal pulse)
SH1
(Internal pulse)
SH4
(Internal pulse)

49
SH2
(Internal pulse)
FRP
ODD FIELD EVEN FIELD
(Internal pulse)
VCK1 44.5fH

VCK2

CLR 3.0s (51fH) 0.5s (7fH)

EN
(PAL)
VST/VD1 1fH

EVEN LINE

Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX005BK/BKB Vertical Direction Timing Chart
NTSC

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

50
CLR
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 596fH 596fH

ODD FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX005BK/BKB Vertical Direction Timing Chart
NTSC

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

51
CLR
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 246fH 246fH

EVEN FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX005BK/BKB Vertical Direction Timing Chart
PAL

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

52
CLR
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 596fH 596fH

ODD FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX005BK/BKB Vertical Direction Timing Chart
PAL

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

53
CLR
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 246fH 246fH

EVEN FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX009AK/AKB Vertical Direction Timing Chart
NTSC

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

54
CLR
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 714fH 714fH

ODD FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX009AK/AKB Vertical Direction Timing Chart
NTSC

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

55
CLR
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 314fH 314fH

EVEN FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX009AK/AKB Vertical Direction Timing Chart
PAL

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

56
CLR
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 714fH 714fH

ODD FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX009AK/AKB Vertical Direction Timing Chart
PAL

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

57
CLR
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 314fH 314fH

EVEN FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX005BK/BKB Vertical Direction Timing Chart 1/4 pulse elimination
NTSC WIDE

163-line display area

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

CLR

58
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 596fH 596fH

SBLK
(Internal pulse)

ODD FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX005BK/BKB Vertical Direction Timing Chart 1/4 pulse elimination
NTSC WIDE

163-line display area

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

CLR

59
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 246fH 246fH

SBLK
(Internal pulse)

EVEN FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX005BK/BKB Vertical Direction Timing Chart
PAL WIDE

163-line display area

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

CLR

60
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 596fH 596fH

SBLK
(Internal pulse)

ODD FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX005BK/BKB Vertical Direction Timing Chart
PAL WIDE

163-line display area

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

CLR

61
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 246fH 246fH

SBLK
(Internal pulse)

EVEN FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX009AK/AKB Vertical Direction Timing Chart 1/4 pulse elimination
NTSC WIDE

169-line display area

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

CLR

62
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 714fH 714fH

SBLK
(Internal pulse)

ODD FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX009AK/AKB Vertical Direction Timing Chart 1/4 pulse elimination
NTSC WIDE

169-line display area

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

CLR

63
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 314fH 314fH

SBLK
(Internal pulse)

EVEN FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX009AK/AKB Vertical Direction Timing Chart
PAL WIDE

169-line display area

(VD)

SYNC

(BLK)

VST

VCK1

VCK2
FRP
(Internal pulse)
HST

EN

64
CLR
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 714fH 714fH

SBLK
(Internal pulse)

ODD FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 LCX009AK/AKB Vertical Direction Timing Chart
PAL WIDE

169-line display area

(VD)

SYNC

(BLK)

VST

VCK1

VCK2

FRP
(Internal pulse)
HST

EN

65
CLR
FRP
(Internal pulse) (1F inversion)

FLD OUT

VD1

HD

VD2 314fH 314fH

SBLK
(Internal pulse)

EVEN FIELD

Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins.
FRP polarity is not specified for each line and field.
CXA2503AR
 CXA2503AR

Application Circuit (NTSC/PAL, COMP and Y/C input)

+12V
To LCD panel +4.5V
0.1

47 To Serial controller

0.01 0.47 0.47 0.47

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

DATA
TEST3
GND2
G OUT
FB R

SCLK
TEST2
RGT
FB B
R OUT
SIG.CENTER

LOAD
TEST4
B OUT
FB G
VCC2
+4.5V

49 VCC1 VSS2 32
0.1 47
50 B-Y IN VD2 31
0.01
+4.5V 51 R-Y IN VD1 30
0.01
52 C OUT EN 29
47k

53 BLK LIM VCK1 28

0.01

54 APC VCK2 27
15k 1
0.068 55 VXO OUT VST 26
0.22
56 VXO IN TEST1 25
2

+4.5V 57 V REG FLD IN 24

1
To LCD panel
58 START UP FLD OUT 23
Y/C
C IN
59 C IN HD 22
COMP
6 82k
60 F0 ADJ HCK1 21

61 GND3 HCK2 20

+4.5V 62 Y IN HST 19
1
47k 63 PIC CLR 18
H.FIL OUT

VCO ADJ
S.SEP IN

64 TEST0 VDD2 17
SYNC IN

0.01
PWRST

EXT G
EXT R

EXT B
GND1
TRAP
VD IN

VDD1
VSS1

CKO
RPD

CKI

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3V

0.01 4
750
0.47
1k 220p 68p 47 0.1
COMP/Y IN
0.033
10k 33k
3300p 3
5 3.3

10k

1 Used crystal: KINSEKI CX-5F 4 L value: 8.2H during LCX005 mode

Frequency deviation: within 30ppm, frequency temperature 3.9H during LCX009 mode
characteristics: within 30ppm, load capacity: 16pF 5 Trap (TDK), open during Y/C input
NTSC: 3.579545MHz NTSC: NLT4532-S3R6B
PAL: 4.433619MHz PAL: NLT4532-S4R4
2 NTSC: none, PAL: 18pF 6 Resistance value variation: 2%,
3 Varicap diode: 1T369 (SONY) temperature coefficient: 200ppm or less
Connect to +4.5V during Y/C input

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

66
 CXA2503AR

Application Circuit (NTSC/PAL, Y/color difference input)

+12V
To LCD panel +4.5V
0.1

47 To Serial controller

0.01 0.47 0.47 0.47

+4.5V 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

DATA
TEST3
SIG.CENTER

GND2
G OUT
FB R

SCLK
TEST2
RGT
FB B
R OUT

LOAD
TEST4
B OUT
FB G
VCC2

0.1 47
49 VCC1 VSS2 32

B-Y IN 50 B-Y IN VD2 31

0.1
R-Y IN 51 R-Y IN VD1 30
0.1
+4.5V 52 C OUT EN 29

47k 53 BLK LIM VCK1 28

0.01
54 APC VCK2 27

55 VXO OUT VST 26

56 VXO IN TEST1 25

+4.5V 57 V REG FLD IN 24

1
To LCD panel
58 START UP FLD OUT 23

+4.5V 59 C IN HD 22

60 F0 ADJ HCK1 21

61 GND3 HCK2 20

+4.5V 62 Y IN HST 19
1
47k 63 PIC CLR 18
H.FIL OUT

VCO ADJ
S.SEP IN

64 TEST0 VDD2 17
SYNC IN

0.01
PWRST

EXT G
EXT R

EXT B
GND1
TRAP
VD IN

VDD1
VSS1

CKO
RPD

CKI

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3V

0.01 2
750
0.47
Y IN 1k 220p 68p 47 0.1
0.033
10k 33k
3300p 1
3.3

10k

1 Varicap diode: 1T369 (SONY)

2 L value: 8.2H during LCX005 mode
3.9H during LCX009 mode

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

67
 CXA2503AR

Example of Representative Characteristics

HUE adjustment characteristics COLOR adjustment characteristics

50 10
40

30 0
HUE adjustment angle [deg]

20

10
10

Gain [dB]
0
10
20
20
30

40 30

50

60 40
0 30 60 90 0C0 0F0 0 30 60 90 0C0 0F0
DAC value DAC value

BRIGHT adjustment characteristics CONTRAST adjustment characteristics

8 14 10

7 13
5
Non-inverted output black level [V]

6 12
Inverted output black level [V]

5 11 0
Output gain [dB]

4 10
5
3 9

2 8 10

1 7 15
0 6
20
1 5

2 4 25
0 30 60 90 0C0 0F0 0 30 60 90 0C0 0F0
DAC value Non-inverted black DAC value
Inverted black
SUB-BRIGHT adjustment characteristics PLL adjustment voltage
1.0 10
Voltage change with respect to G output [V]

0.5 9
Pin 11 output voltage [V]

0 8

0.5 7

1.0 6

1.5 5
0 30 60 90 0C0 0F0 0 30 60 90 0C0 0F0
DAC value DAC value

68
 CXA2503AR

Color difference balance adjustment Black level limiter adjustment characteristics

5 10

9
3

Limiter level [Vp-p]

8
1
Gain [dB]

1
6

3
5

5 4
0 30 60 90 0C0 0F0 1.0 1.5 2.0 2.5 3.0 3.5 4.0
DAC value B-Y output Pin voltage [V]
R-Y output

69
 CXA2503AR

Sharpness characteristics (COMP, NTSC, 005) Sharpness characteristics (COMP, NTSC, 009)
15 10

10 5
5
0
0
5

Gain [dB]
Gain [dB]

5
10
10
15
15
20
20

25 25

30 30
0 2 4 6 8 10 0 2 4 6 8 10
Frequency [MHz] 0V Frequency [MHz] 0V
2.25V 2.25V
4V 4V
Sharpness characteristics (COMP, PAL, 005) Sharpness characteristics (COMP, PAL, 009)
15 10

10 5
5
0
0
5
Gain [dB]
Gain [dB]

5
10
10
15
15
20
20

25 25

30 30
0 2 4 6 8 10 0 2 4 6 8 10
Frequency [MHz] 0V Frequency [MHz] 0V
2.25V 2.25V
4V 4V

Sharpness characteristics (Y/C, 005) Sharpness characteristics (Y/C, 009)

15 20

15
10

10
5
5
Gain [dB]
Gain [dB]

0
0
5
5
10
10

15 15

20 20
0 2 4 6 8 10 0 2 4 6 8 10
Frequency [MHz] 0V Frequency [MHz] 0V
2.25V 2.25V
4V 4V
70
 CXA2503AR

Notes on Operation

The CXA2503AR contains digital circuits, so the set board pattern must be designed in consideration of
undesired radiation, interference to analog circuits, etc. Care should also be taken for the following items when
designing the pattern.

Make the IC power supply and GND patterns as plain as possible. In particular, GND and VSS should not be
separated and should be connected to the same GND pattern as close to the pins as possible.

Connect the by-pass capacitors between the power supplies and GND as close to the pins as possible.

The trap connected to Pin 3 should be located as close to the pin as possible. Also, take care not to pass
other signal lines close to this pin or the connected trap.

The wiring for the crystal and capacitor connected to Pins 55 and 56 should be as short as possible in order
to prevent floating capacitance. Take care not to pass other signal lines close to these pins in order to
prevent interference such as color unevenness. In addition, the APC pull-in characteristics vary significantly
according to the characteristics of the used crystal and the wiring pattern, so be sure to thoroughly
investigate these items before using the set.

The resistor connected to Pin 60 should be located as close to the pin as possible. Also, take care not to
pass other signal lines close to this pin.

The composite/Y signal and the external R-Y and B-Y signals are clamped at the inputs using the capacitors
connected to the input pins, so these signals should be input at sufficiently low impedance. The C signal is
received by the internal capacitor, so an appropriate DC bias should be applied to this signal from an external
source and this signal should be input at low impedance.

The smoothing capacitor of the DC level control feedback circuit in the output block should have a leak current
with a small absolute value and variance.

This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should be
taken to prevent electrostatic discharge.

71
 CXA2503AR

Package Outline Unit: mm

64PIN LQFP (PLASTIC)

12.0 0.2

10.0 0.2 0.15 0.05

48 33 0.1

49 32

64 17

1 16
+ 0.08 1.7 MAX
1.25 0.5 0.18 0.03
0.1 M

0.1 0.1
(0.5)
0.5 0.2

0 to 10

DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE LQFP-64P-L061 LEAD TREATMENT SOLDER PLATING

EIAJ CODE LQFP064-P-1010-AY LEAD MATERIAL 42 ALLOY

JEDEC CODE PACKAGE WEIGHT 0.3g

72