MAX22530 Isolated ADC

Click here to ask an associate for production status of specific part numbers.
Field-Side Self-Powered, MAX22530–MAX22532

4-Channel, 12-bit, Isolated ADC
• Process Automation
General Description • Motion Control
The MAX22530–MAX22532 are galvanically isolated, 4-
channel, multiplexed, 12-bit, analog-to-digital converters Benefits and Features
(ADC) in the MAXSafe™ family product line. An • Enable Robust Detection of Multichannel
integrated, isolated, DC-DC converter powers all field- Analog/Binary Inputs
side circuitry, and this allows field-side diagnostics even • Withstands 3.5kVRMS Isolation for 60s (VISO) for the
when no input signal is present. SSOP Package
The MAX22530–MAX22532 family continually digitizes • Withstands 5kVRMS Isolation for 60s (VISO) for the
the input voltage on the field-side of an isolation barrier Wide SOIC Package
and transmits the data across the isolation barrier to the • 5.5mm of Creepage and Clearance for 20-pin or 28-
logic-side of the devices where the magnitude of the pin SSOP Package
input voltage is compared to programmable thresholds. • 8mm of Creepage and Clearance for 16-pin Wide
The 12-bit ADC core has a sample rate of 20ksps (typ) SOIC Package
per-channel. ADC data is available through the SPI • Group II CTI Package Material
interface either directly or filtered. Filtering averages the • Reduces BOM and Board Space Through High
most recent 4 readings depending on the setting. Integration
Each input has a comparator with programmable high • Field-Side Self-Powered with Integrated DC-DC
and low thresholds, and an interrupt is asserted when Supply
any input crosses its programmed level based on the • 12-bit, 20ksps Per-Channel ADC
mode setting. The comparator output pin (COUT_) is • Programmable Threshold Comparators for each
high when the input voltage is above the upper threshold Channel
and low when it is below the lower threshold in digital • Isolation for both Data and DC-DC Supply
input mode. Typical response time of the comparator to • Integrated 1.8V Reference
an input change is less than 75µs with filtering disabled. • Increase System “Up Time” and Simplifies System
With filtering enabled, the comparator uses the moving Design & Maintenance
average of the last 4 ADC readings. • Field-Side ADC Functionality Diagnostics
• Field-Side Continuous Power Monitoring
The MAX22530 in a 16-pin wide SOIC package provides • Communication System Self-Diagnostics
8mm of creepage and clearance, and 5kVRMS isolation.
The MAX22531 in a 20-pin SSOP package and the • Flexible Control and Interface
MAX22532 in a 28-pin SSOP package, both provide • Programmable Upper and Lower Input Threshold
5.5mm of creepage and clearance, and 3.5kVRMS Enable Programmable Hysteresis
isolation. All package material has a minimum • Comparator Output (COUT_) Pins for Fastest
comparative tracking index (CTI) of 400, which gives it a Response
group II rating in creepage tables. • SPI Interface with CRC Option
• Precision Internal Reference ±1% (typ)
All devices are rated for operation at ambient • -40°C to +125°C Operating Temperature Range
temperatures between -40°C to +125°C.
Safety Regulatory Approvals
Applications
• UL According to UL1577
• High-Voltage Binary Input • cUL According to CSA Bulletin 5A
• Substation Automation Ordering Information appears at the end of the data
• Distribution Automation sheet.
19-100989; Rev 1; 9/21
© 2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
O n e A n al og W ay, W il mi n gton , MA 0 18 8 7 U.S.A. | T el: 781. 329. 4700 | © 2021 Analog Devic es, I nc. Al l ri ghts res erv ed.
MAX22530–MAX22532 Field-Side Self-Powered,
Four-Channel Isolated ADC

NOTE *:
COUT1 AND COUT2 ARE FOR MAX22531
COUT1, COUT2, COUT3, AND COUT4 ARE FOR MAX22532
REF VDDL = 3.3V
MAX22530/MAX22531/MAX22532
INPUT REFERENCE
VREF = 1.8V
COUT_*
AIN1
AIN2 INT
12-BIT ADC
CS MCU
AIN3
LOGIC AND SPI
AIN4 SCLK
INTERFACE
SDI
AGND LOGIC
CONTROL SDO
VDDPL = 3.3V
VDDF µPOWER ISOLATED
DC-DC
CDDF
GNDF GNDL
TABLE OF CONTENTS
General Description ................................................................................................................................................................. 1
Applications .............................................................................................................................................................................. 1
Benefits and Features .............................................................................................................................................................. 1
Safety Regulatory Approvals ................................................................................................................................................... 1
Four-Channel Isolated ADC ..................................................................................................................................................... 2
Absolute Maximum Ratings ..................................................................................................................................................... 6
Package Information ................................................................................................................................................................ 6
16 W SOIC ........................................................................................................................................................................... 6
20 SSOP .............................................................................................................................................................................. 6
28 SSOP .............................................................................................................................................................................. 6
Electrical Characteristics .......................................................................................................................................................... 7
Timing Diagram ........................................................................................................................................................................ 8
Insulation Characteristics ....................................................................................................................................................... 10
16-pin Wide SOIC .............................................................................................................................................................. 10
20-pin and 28-pin SSOP .................................................................................................................................................... 10
ESD and Transient Immunity Characteristics ....................................................................................................................... 11
Typical Operating Characteristics .......................................................................................................................................... 12
Pin Configurations .................................................................................................................................................................. 13
www.analog.com Analog Devices | 2

Pin Descriptions ..................................................................................................................................................................... 14

Functional Diagrams .............................................................................................................................................................. 16
Detailed Description ............................................................................................................................................................... 17
ADC .................................................................................................................................................................................... 17
Internal Voltage Reference ................................................................................................................................................. 17
Input Comparator with Programmable Thresholds and Two Operational Modes (CO_MODE) ......................................... 17
Digital Input Mode ........................................................................................................................................................... 17
Digital Status Mode ......................................................................................................................................................... 18
Isolated Power and Data Transfer ...................................................................................................................................... 18
Configuration and Monitoring ............................................................................................................................................. 18
SPI Interface ................................................................................................................................................................... 18
Diagnostic and Fault Reporting Features ........................................................................................................................... 20
ADC Functionality Error .................................................................................................................................................. 20
SPI Framing Error ........................................................................................................................................................... 20
Loss of Data Stream ....................................................................................................................................................... 20
CRC Error from Internal Communication ........................................................................................................................ 20
Control Modes .................................................................................................................................................................... 20
Hardware Reset Control ................................................................................................................................................. 20
Software Reset Control ................................................................................................................................................... 20
Clear POR Control .......................................................................................................................................................... 20
DISPWR Control ............................................................................................................................................................. 21
Filter Clearing Control ..................................................................................................................................................... 21
Comparator Limit Control ................................................................................................................................................ 21
CRC Control ................................................................................................................................................................... 21
Interrupts ............................................................................................................................................................................ 21
Digital Isolation ................................................................................................................................................................... 23
Applications Information ......................................................................................................................................................... 24
Power Supply Decoupling .................................................................................................................................................. 24
Layout Considerations ........................................................................................................................................................ 24
Radiated Emissions ............................................................................................................................................................ 24
Register Map .......................................................................................................................................................................... 27
Typical Application Circuits .................................................................................................................................................... 35
High-Voltage DC Monitoring ............................................................................................................................................... 35
Ordering Information .............................................................................................................................................................. 36

LIST OF FIGURES
Figure 1. SPI Write Timing Diagram (with CRC Enabled) ....................................................................................................... 9
Figure 2. SPI Read Timing Diagram (with CRC Enabled) ....................................................................................................... 9
Figure 3. Digital Input Mode ................................................................................................................................................... 17
Figure 4. Digital Status Mode ................................................................................................................................................. 18
Figure 5. Stitching Capacitance Example on a 4- Layer PCB ............................................................................................... 25
Figure 6. Stitching Capacitance on Internal Layers ............................................................................................................... 25
Figure 7. MAX22530 Radiated Emission with 90pF Stitching Capacitance, 3-Meter Antenna Distance, Horizontal Scan ... 25
Figure 8. MAX22530 Radiated Emission with 90pF Stitching Capacitance, 3-Meter Antenna Distance, Vertical Scan ........ 26
Figure 9. MAX22531 Radiated Emission with 100pF Stitching Capacitance, 3-Meter Antenna Distance, Horizontal Scan . 26
Figure 10. MAX22531 Radiated Emission with 100pF Stitching Capacitance, 3-Meter Antenna Distance, Vertical Scan .... 26

Click here to ask an associate for production status of specific part numbers.
Field-Side Self-Powered, MAX22530–MAX22532

LIST OF TABLES
Table 1. SPI Write Command ......................................................................................................................................... 19
Table 2. SPI Read Command ......................................................................................................................................... 19
Table 3. SPI Burst Read Command ................................................................................................................................ 19
Table 4. Safety Regulatory Approvals ............................................................................................................................. 23
19-100246; Rev 1; 7/19
© 2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
O n e A n al o g Way , W il mi ng ton , MA 0 1 8 87 U.S.A. | T el: 781.329. 4700 | © 2021 A nal og Devic es, I nc. Al l ri ghts reserved.
Absolute Maximum Ratings

VDDL to GNDL........................................................... -0.3V to 6V Continuous Power Dissipation (Multilayer Board) (TA =
+70°C, derate 11.9mW/°C above +70°C. 20-pin SSOP) 964mW
VDDPL to GNDL......................................................... -0.3V to 6V
Continuous Power Dissipation (Multilayer Board) (TA =
SDI, CS, INT (To GNDL) ........................................... -0.3V to 6V
+70°C, derate 6.96mW/°C above +70°C. 28-pin SSOP)
SDO, COUT_ (To GNDL) ........................ -0.3V to (VDDL + 0.3V) .................................................................................. 556.72mW
VDDF to GNDF .......................................................... -0.3V to 6V Operating Temperature Range ......................... -40°C to +125°C
REF, AIN_ to AGND .................................................. -0.3V to 2V Maximum Junction Temperature ..................................... +150°C
AGND to GNDF ...................................................... -0.3V to 0.3V Storage Temperature Range ............................. -65°C to +150°C
Continuous Power Dissipation (Multilayer Board) (TA = Lead Temperature (soldering, 10s) ................................. +300°C
+70°C, derate 14.1mW/°C above +70°C. 16-pin Wide SOIC) Soldering Temperature (reflow) ....................................... +260°C
..................................................................................... 1127mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any
other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Package Information
16 W SOIC
Package Code W16MS+14
Outline Number 21-0042
Land Pattern Number 90-0107
Thermal Resistance, Four Layer Board:
Junction-to-Ambient (θJA) 68.8°C/W
Junction-to-Case Thermal Resistance (θJC) 41.6°C/W
20 SSOP
Package Code A20MS+7
Junction-to-Ambient (θJA) 216°C/W
Junction-to-Case Thermal Resistance (θJC) 49°C/W
28 SSOP
Package Code A28MS+5
Junction-to-Ambient (θJA) 143.70°C/W
Junction-to-Case Thermal Resistance (θJC) 47.90°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics
(VDDL - VGNDL = 1.71V to 5.5V, VDDPL - VGNDL = 3.0V to 5.5V, CDDF = 1μF, CREF = 1μF. Limits are 100% tested at TA = +25°C.
Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) (Note
1 Note 2))
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LOGIC-SIDE POWER SUPPLY
Logic Power Supply VDDL 1.71 5.5 V
Logic Supply Current IDDL 1 2.5 mA
Logic-Supply UVLO
VDDL_UVLO 1.5 1.6 1.66 V
Threshold
Logic-Supply UVLO
VDDL_UHYS 50 mV
Hysteresis
Logic Power-Up Time tLPU Valid SPI access 0.6 1 ms
Isolated DC-DC Supply VDDPL 3.0 3.3 5.5 V
Isolated DC-DC Supply
IDDPL VDDPL = 3.3V 7 10 mA
Current
VDDPL_UVLO 2.7 2.8 2.95 V
UVLO Threshold
VDDPL_UHYS 100 mV
UVLO Hysteresis
FIELD-SIDE PARAMETERS
VDDF Supply Voltage VDDF Internally generated 2.7 3.1 5.5 V
Isolated DC-DC Power
tPWRUP CDDF = 1 µF 10 ms
Up Time
ADC AND COMPARATOR
Input-Voltage Range VAIN 0 1.8 V
ADC Resolution 12 Bits
VAIN = 98% VREF, excluding offset error
Gain Error GE -0.2 +0.2 %FS
and reference error
Offset Error OE VAIN = 2% VREF, offset calculated -0.1 +0.1 %FS
Differential Nonlinearity DNL ±1.5 LSB
Integral Nonlinearity INL Included in the gain and offset window ±2.0 LSB
Input-Leakage Current INLKG -600 +600 nA
Throughput per Channel 18 20 22 ksps
AIN# step input to COUT transition (Note
Latency (No filtering) 75 µs
3)
AIN# step input to COUT transition (Note
Latency (4 Readings) 300 µs
3)
CMTI (Note 4) 50 kV/µs
INTERNAL VOLTAGE REFERENCE
Nominal Output Voltage VREF TA = +25°C 1.78 1.80 1.82 V
Output-Voltage TA = -25°C to +85°C -1.5 +1.5
VREF_TOL %
Accuracy TA = -40°C to +125°C -2 +2
Output-Voltage
TCVOUT 50 ppm/°C
Temperature Drift
LOGIC INTERFACE (SCLK, SDI, SDO, CS, COUT, INT)
Input Logic-High 0.7 x
VIH SCLK, SDI, CS V
Voltage VDDL

(VDDL - VGNDL = 1.71V to 5.5V, VDDPL - VGNDL = 3.0V to 5.5V, CDDF = 1μF, CREF = 1μF. Limits are 100% tested at TA = +25°C.
Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.) (Note
1 Note 2))
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
0.3 x
Input Logic-Low Voltage VIL SCLK, SDI, CS V
VDDL
Input Hysteresis VHYST SCLK, SDI, CS 50 mV
Input Leakage Current IIN_LKG SCLK, SDI, CS -1 +1 µA
SCLK, SDI, CS,
Input Capacitance CIN 2 pF
f = 1MHz
Output Logic-High VDDL-
VOH SDO, COUT, sourcing 4mA V
Voltage 0.4
Output Logic-Low
VOL SDO, COUT, INT, sinking 4mA 0.4 V
Voltage
Output High-Impedance
IOLKG INT, SDO -1 +1 µA
Leakage Current
SPI TIMING CHARACTERISTICS
SCLK Clock Frequency fSCLK 10 MHz
SCLK Clock Period tSCLK 100 ns
SCLK Pulse-Width High tSCLKH 40 ns
SCLK Pulse-Width Low tSCLKL 40 ns
CS Fall-to-SCLK Rise
tCS(LEAD) 20 ns
Time
SCLK Fall-to-CS Rise
tCS(LAQ) 80 ns
Time
SDI Hold Time tDINH 20 ns
SDI Setup Time tDINSU 20 ns
SDO Disable Time (CS
Rising to SDO Three- tDOUT(DIS) 40 ns
State)
Output Data
tDO 50 ns
Propagation Delay
Inter-Access Gap tIAG 920 ns
Note 1: All devices are 100% production tested at TA = +25C. Specifications for all temperature limits are guaranteed by design.
Note 2: All currents into the device are positive; all currents out of the device are negative. All voltages are referenced to their
respective ground (GNDL or GNDF), unless otherwise noted.
Note 3: Latency numbers are based on the following condition: a full-scale step is applied at the ADC input and COUTHI_ (register
address 0x9 to 0xC) upper threshold (THU) is set to maximum value (0xFFFh). Latency is the delay from the step at the
ADC input to the digital comparator output.
Note 4: CMTI is the maximum sustainable common-mode voltage slew rate while maintaining the correct output. CMTI applies to
both rising and falling common-mode voltage edges. Tested with the transient generator connected between GNDF and
GNDL (VCM = 1000V).
Timing Diagram

tCSH0 tCSS0 tDS t DH tCL tCH tCP t CSS1 t CSW
CS
SCLK 1 2 3 4 5 6 7 8 9 10 30 31 32
SDI A5 A4 A3 A2 A1 A0 A0 W B D15 C2 C1 C0
NOTE B: BURST BIT
HIGH-Z
SDO
Figure 1. SPI Write Timing Diagram (with CRC Enabled)
tCSH0 tCSS0 tDS tDH tCL tCH tCP tCSS1 tCSW
CS
SCLK 1 2 3 4 5 6 7 8 9 10 N+6 N+7 N+8
SDI A5 A4 A3 A2 A1 A0 R B
tDOT NOTE B: BURST BIT tDOH tDOD
HIGH-Z HIGH-Z
SDO D15 D14 C2 C1 C0
Figure 2. SPI Read Timing Diagram (with CRC Enabled)

Insulation Characteristics
16-pin Wide SOIC
PARAMETER SYMBOL CONDITIONS VALUE UNITS
Method B1 = VIORM x 1.875
Partial Discharge Test Voltage VPR 2250 VP
(t = 1s, partial discharge < 5pC)
Maximum Repetitive-Peak- (Note 5)
VIORM 1200 VP
Isolation Voltage
Maximum Working-Isolation
VIOWM Continuous RMS voltage (Note 5) 848 VRMS
Voltage
Maximum Transient-Isolation (Note 5)
VIOTM 7000 VP
Voltage
Maximum Withstanding- fSW = 60Hz, duration = 60s
VISO (Note 5, Note 6) 5000 VRMS
Isolation Voltage
Maximum Surge-Isolation Basic Insulation, 1.2/50μs pulse per
VIOSM 10000 VP
Voltage IEC61000-4-5
VIO = 500V, TA = 25°C > 1012
Insulation Resistance RIO VIO = 500V, 100°C ≤ TA ≤ 125°C > 1011 Ω
VIO = 500V, TS = 150°C > 109
Barrier Capacitance Field Side-
CIO fSW = 1MHz (Note 7) 2 pF
to-Logic Side
Minimum Creepage Distance CPG 8 mm
Minimum Clearance Distance CLR 8 mm
Internal Clearance Distance through insulation 0.015 mm
Comparative Tracking Index CTI Material Group II (IEC 60112) > 400
Climate Category 40/125/21
Pollution Degree
2
(DIN VDE 0110, Table 1)
20-pin and 28-pin SSOP

PARAMETER SYMBOL CONDITIONS VALUE UNITS
Method B1 = VIORM x 1.875
Partial Discharge Test Voltage VPR 1182 VP
(t = 1s, partial discharge < 5pC)
Maximum Repetitive-Peak-
VIORM (Note 5) 630 VP
Isolation Voltage
Maximum Working-Isolation
VIOWM Continuous RMS voltage (Note 5) 445 VRMS
Voltage
Maximum Transient-Isolation
VIOTM (Note 5) 5300 VP
Voltage
Maximum Withstanding- fSW = 60Hz, duration = 60s
VISO 3750 VRMS
Isolation Voltage (Note 5, Note 6)
Maximum Surge-Isolation Basic Insulation, 1.2/50μs pulse per
VIOSM 10000 VP
Voltage IEC61000-4-5
VIO = 500V, TA = 25°C > 1012
Insulation Resistance RIO VIO = 500V, 100°C ≤ TA ≤ 125°C > 1011 Ω
VIO = 500V, TS = 150°C > 109
Barrier Capacitance Field Side-
CIO fSW = 1MHz (Note 7) 2 pF
to-Logic Side
Minimum Creepage Distance CPG 5.5 mm
Minimum Clearance Distance CLR 5.5 mm

Internal Clearance Distance through insulation 0.015 mm

Comparative Tracking Index CTI Material Group II (IEC 60112) > 400
Climate Category 40/125/21
Pollution Degree
2
(DIN VDE 0110, Table 1)
Note 5: VISO, VIOWM, and VIORM are defined by the IEC 60747-5-5 standard.
Note 6: Product is qualified at VISO for 60s and 100% production tested at 120% of VISO for 1s.
Note 7: Capacitance is measured with all pins on field-side and logic-side tied together.
ESD and Transient Immunity Characteristics

PARAMETER SYMBOL CONDITIONS VALUE (TYP) UNITS
AIN_ to GNDF ≥ 60kΩ input resistor, IEC 61000-4-5 1.2µs/50µs pulse ±7.2
Surge kV
AIN_ to AIN_ ≥ 60kΩ input resistors, IEC 61000-4-5 1.2µs/50µs pulse ±4
Capacitive clamp to input cable pair (AIN_- GNDF) with 60kΩ
EFT AIN_ to GNDF input divider resistor connected AIN_- GNDF, 1nF Y-CAP to ±4 kV
earth, IEC61000-4-4
≥ 60kΩ resistor in series with AIN_ with respect to GNDF, IEC
AIN_ Contact ±8
61000-4-2
ESD ≥ 60kΩ resistor in series with AIN_ with respect to GNDF, IEC kV
AIN_ Air Gap ±15
61000-4-2
Any pin to Any pin Human Body Model ±3

Typical Operating Characteristics

(VDDL - VGNDL = 3.3V, VDDPL - VGNDL = 3.3V, CDDF = 1μF, CREF = 1μF, TA = +25°C, unless otherwise noted.)

(VDDL - VGNDL = 3.3V, VDDPL - VGNDL = 3.3V, CDDF = 1μF, CREF = 1μF, TA = +25°C, unless otherwise noted.)
Pin Configurations
TOP VIEW
REF 1 16 INT
AGND 2 15 CS
MAX22530
AIN1 3 14 SCLK
AIN2 4 13 SDI
AIN3 5 12 SDO
AIN4 6 11 VDDL
VDDF 7 10 VDDPL
GNDF 8 9 GNDL
16 W SOIC
TOP VIEW
+
REF 1 20 INT
AGND 2 19 CS
AIN1 3 18 SCLK
AIN2 4 MAX22531 17 SDI
AGND 5 16 SDO
AIN3 6 15 COUT2
AIN4 7 14 COUT1
AGND 8 13 VDDL
VDDF 9 12 VDDPL
GNDF 10 11 GNDL
20 SSOP

TOP VIEW
+
GNDF 1 28 GNDL
NC 2 27 NC
REF 3 26 INT
AGND 4 25 CS
AIN1 5 24 SCLK
MAX22532
AGND 6 23 SDI
AIN2 7 22 SDO
AGND 8 21 COUT4
AIN3 9 20 COUT3
AGND 10 19 COUT2
AIN4 11 18 COUT1
AGND 12 17 VDDL
VDDF 13 16 VDDPL
GNDF 14 15 GNDL
28 SSOP
Pin Descriptions
PIN REF
NAME FUNCTION
MAX22530 MAX22531 MAX22532 SUPPLY
Output of the DC-DC Converter. Bypass to GNDF with
7 9 13 VDDF 1μF||0.01μF capacitors. The 0.01μF capacitor should be placed
as close as possible to the pin.
GNDF Field-Side Ground for Everything Except the ADC Front-End and
8 10 1, 14 VDDF
Voltage Reference
VDDL Power Input for the Logic-Side. Bypass with 1μF||0.01μF
11 13 17
capacitors to GNDL.
Power Input for the Isolated DC-DC Converter. The DC-DC
10 12 16 VDDPL converter powers the field-side. Bypass with 1μF||0.01μF VDDL
capacitors to GNDL.
9 11 15, 28 GNDL Power and Signal Ground for All Logic-Side Pins
– – 2, 27 N.C. Not Connected
REF External Filter Capacitor. Connect a 1μF||0.01μF capacitor from

1 1 3 VDDF
REF to AGND.
2 2 4 AGND Analog Ground Reference for AIN_ and REF VDDF
AIN1 Analog Input Channel 1 The ADC measures the voltage on this
3 3 5 VDDF
pin with respect to AGND
AIN2 Analog Input Channel 2. The ADC measures the voltage on this
4 4 7 VDDF
pin with respect to AGND.
5 6 9 VDDF
6 7 11 VDDF
- 5, 8 6, 8, 10, 12 AGND Analog Ground Reference for AIN_ and REF VDDF
12 16 22 SDO Serial Data Out for SPI Interface (MISO) VDDL
13 17 23 SDI Serial Data Input for SPI Interface (MOSI) VDDL
14 18 24 SCLK Serial Clock for SPI Interface VDDL
CS Chip Select for SPI Interface. Assert low to enable SPI functions
15 19 25 VDDL
and SDO. SDO and COUT_ are high impedance when CS is high.
COUT1 Digital Comparator Output. COUT1 is high when AIN1 is above
- 14 18 VDDL
the upper threshold (COUTHI1) and low when AIN1 is below the

lower threshold (COUTLO1) in digital input mode. See the Digital

Status Mode section.
Digital Comparator Output. COUT2 is high when AIN2 is above
COUT2 the upper threshold (COUTHI2) and low when AIN2 is below the
- 15 19 VDDL
- - 20 VDDL
- - 21 VDDL
Open-Drain Output that Asserts Low during a number of Different
INT Error Conditions. The cause of the error is latched in the
16 20 26 VDDL
INTERRUPT STATUS register. See the Diagnostic and Fault
Reporting Features section for details on clearing INT.

Functional Diagrams
MAX22530/MAX22531/MAX22532
REF
VDDL
REFERENCE
VREF = 1.8V COUT4*
COUT3*
COUT2*
AIN1 COUT1*
AIN2 INT
12-BIT ADC
AIN3 LOGIC AND SPI CS

INTERFACE
AIN4
SCLK
SDI
LOGIC CONTROL
SDO
AGND
VDDF VDDPL
µPOWER ISOLATED DC-DC
AGND
NOTE *:
COUT1 AND COUT2 ARE FOR MAX22531
GNDF COUT1, COUT2, COUT3, AND COUT4 ARE FOR MAX22532 GNDL

Detailed Description
The MAX22530–MAX22532 family consists up of 12-bit, 4-channel ADCs with either a 3.5kVRMS or 5kVRMS isolated SPI
interface depending upon the package option. Additional features include comparators with programmable upper and lower
threshold levels. The ADC and all field-side circuits are powered by an integrated, isolated, DC-DC converter that allows
field-side functionality to be verified even when there is no input signal or other field-side supply. This makes the MAX22530–
MAX22532 family ideally suited for high-density, multirange, group-isolated, binary-input modules, and provides a complete
solution to any system that requires monitoring inputs without a separate isolated power supply.
ADC
The devices’ ADC employs a 12-bit SAR architecture with a nominal sampling rate of 20ksps per channel and has an input-
voltage range of 0V to +1.8V with respect to AGND. After power-up, the ADC runs continually at the nominal sampling rate.
The 12-bit unfiltered ADC reading and filtered ADC reading are both available through the SPI interface. Filtering averages
the most recent 4 readings. For rapid response without requiring the SPI interface, the MAX22530–MAX22532 family
provides the output of a digital comparator (COUT_) that compares user-programmed thresholds to the ADC reading or the
filtered ADC reading. The comparator has two thresholds, the comparator output is high when the input voltage is above the
upper threshold and low when it is below the lower threshold in default digital-input mode. The response time of the
comparator is less than 75μs (typ) with filtering disabled. With filtering enabled, the comparator uses the moving average of
the last 4 ADC readings for a response time of 300μs (typ). The comparator output pin (COUT_) changes based on the latest
ADC reading, the upper threshold (COTHI_[11:0], register address 0x9, 0xA, 0xB and 0xC) and the lower threshold
(COTLO_[11:0], register address 0x10, 0xD, 0xE and 0xF) according to the CO_MODE_ setting. If enabled, the interrupt
pin INT asserts whenever COUT_ changes.
Internal Voltage Reference
The MAX22530-MAX22532 family features a precision internal voltage reference. The 1.8V internal reference has a
maximum error of ±2% over the entire operating temperature range. The MAX22530-MAX22532 family is not intended to be
used with an external voltage reference.
Input Comparator with Programmable Thresholds and Two Operational Modes (CO_MODE)
The input signal can be recognized in two different ways; one is the digital input mode and the other is the digital status
mode. The mode of operation is set for each input channel in the COUTHI_ registers (address 0x9, 0xA, 0xB and 0xC) with
the CO_MODE bits.
Digital Input Mode
The Digital input mode (see Figure 3) treats the digitized input (from the ADC) as a digital signal of “1” or “0” with hysteresis
where the values for “1” and “0” are set by the upper- and lower-limit thresholds programmed into registers COUTHI_ and
COUTLO_ (see COUT_BLK in register map).
1. Upper limit and lower limit are used as hysteresis (like a Schmitt trigger input).
2. The status of COUT_ changes to “1” only when the ADC (or FADC) value crosses over the upper limit during a low-to-
high transition, and to “0” when it crosses below the lower limit during a high-to-low transition.
3. The status of COUT_ can be “0” or “1” between the lower and upper limits based on the previous status.
ANALOG INPUT/
ADC1 OUTPUT
COTHI1
COTLO1
COUT1
0 1 0 1 0
NOTE: IN PRACTICE, THERE IS A DELAY BETWEEN ANALOG INPUT AND DIGITIZED ADC OUTPUT (CONVERSION TIME).
Figure 3. Digital Input Mode

Digital Status Mode

The Digital status mode (see Figure 4) monitors the input in “Normal” status vs. “OVLO/UVLO” status:
1. The status of COUT_ is “0” when the digitized output of ADC (or FADC) is between the lower limit and the upper limit.
2. The status of COUT_ is “1” when the digitized output of ADC (or FADC) is higher than the upper limit or lower than the
lower limit.
ANALOG INPUT/
ADC1 OUTPUT
COTHI1
COTLO1
COUT1
1 0 1 0 1 0 1 0 1 0 1
NOTE: THERE IS A DELAY BETWEEN ANALOG INPUT AND DIGITIZED ADC OUTPUT (CONVERSION TIME).
Figure 4. Digital Status Mode

Isolated Power and Data Transfer
A simplified view of the isolated power and data transfer sections is shown in the Functional Diagram. The logic-side supply
VDDPL powers an integrated, inductively coupled DC-DC converter that generates a nominal field supply VDDF of 3.1V with
just enough output current to power the field-side of the MAX22530–MAX22532 family. Note that VDDF is not intended to
power an external load.
Serial data is transferred by capacitively-isolated differential transceivers. To verify reliable communication through the
isolation barrier, a cyclic redundancy check (8-bit CRC) is embedded in the transmitted serial data streams. If a CRC fails,
the data is discarded, and no action is taken. If CRC fails, the SPICRC bits in the INTERRUPT STATUS register is set and
INT is asserted if the ENCRC interrupt enable bit is set in the INTERRUPT ENABLE register.
Configuration and Monitoring
An SPI interface is used for transferring configuration, control, and diagnostic data as well as ADC readings between a host
(FPGA or microcontroller) and the MAX22530–MAX22532. The interface consists of four signals: SCLK, CS, SDI and SDO,
and does not support daisy-chain configuration. An optional CRC improves reliability in the data communication to and from
the MAX22530–MAX22532. This feature, disabled by default after reset or power-up, can be enabled or disabled at any time
through the SPI interface. When enabled, it affects both read and write SPI transactions.
SPI Interface
SPI communication includes the following features (see Table 3):
• Serial clock up to 10MHz
• CRC function uses SMBus polynomial: C(x) = (x8 + x2 + x1 + 1) that is added if the ENCRC bit is set in the CONTROL
register.
• Burst Mode for reading multiple registers
The functionality of each SPI pin can be summarized as follows:

• Serial Clock (SCLK): Input for the master serial clock signal. The clock signal determines the speed of the data transfer
(up to 10MHz max). All receiving and transmitting is done synchronous to this clock.
• Chip Select (CS): The CS input enables the SPI interface. A logic-high on CS forces SDO to high-impedance and any
SCLK transitions are ignored. During a CS logic-low state, data is transferred on the edges of SCLK.
• Serial Input (SDI): SDI or MOSI is the serial input port of the SPI shift register and data is clocked LSB first into the shift
register on the rising edge of SCLK. To provide sufficient setup/hold time, the driver should have SDI data transitions at
the falling edge of SCLK. On the rising edge of CS, the input data is latched into the internal registers.

• Serial Output (SDO): SDO or MISO is the serial output port of the SPI shift register, and is in a high-impedance state until
the CS pin goes to a logic-low state and at the end of the BURST data bit. Data is clocked LSB first out of the shift register
on the falling edge of SCLK.
The MAX22530–MAX22532 offers burst and single-register SPI transactions. Single-register SPI transactions can be used
to access any register address and are 3-bytes long without CRC and 4-bytes long with CRC. The CRC byte is calculated
on the previous 3 bytes. The single-register SPI transaction format consists of a 6-bit register address, a read/write bit, a
burst mode bit, 16 bits of payload, and the optional CRC byte, as illustrated in Table 1 for write transaction and in Table 2 for
read transactions. See Figure 1 and Figure 2 for SPI write and read timing diagrams.
-
Table 1. SPI Write Command
HEADER PAYLOAD
A[5:0] W/R = 1 BURST = 0 Data D[15:0] CRC (optional), C[7:0]
Note: The BURST bit in the header is ignored in SPI write transactions
Table 2. SPI Read Command
HEADER PAYLOAD
A[5:0] W/R = 0 BURST = 0 Data D[15:0] CRC (optional), C[7:0]
Burst mode can only be used for reading the filtered or unfiltered ADC data registers and the interrupt status register in one
SPI transaction. Burst SPI transactions are 11-bytes long without CRC and 12-bytes long with CRC. The CRC byte is
calculated on the previous 11 bytes. The burst SPI transaction format consists of the 6-bit register address for ADC1 or
FADC1, a read/write bit, a burst mode bit, the contents of the four filtered or unfiltered ADC registers depending on the 6-bit
address entered, the content of the interrupt status register, and the optional CRC byte, as illustrated in Table 3. The burst
bit is ignored for all other register addresses during read transactions.
The MAX22530–MAX22532 knows that it should receive 24, 32, 88, or 94 bits depending on the combination of CRC
setting and burst mode. If more SPI cycles than expected are received, the transaction is executed. If fewer SPI cycles
than expected are received, the transaction fails.
Table 3. SPI Burst Read Command
HEADER PAYLOAD
W/R = F/ADC_1 F/ADC_2 F/ADC_3 F/ADC_4 INTERRUPT 8-bits CRC (optional),
A[5:0] BURST = 1
0 D[15:0] D[15:0] D[15:0] D[15:0] STATUS[15:0] C[7:0]
• For burst read transactions, if Address A[5:0] is 0x01 (ADC_1), the data read is the unfiltered ADC data. If Address
A[5:0] is 0x05 (FADC_1), the data read is the filtered ADC data.
• The burst bit is ignored for all other register addresses during read transactions.

Diagnostic and Fault Reporting Features

The MAX22530–MAX22532 continuously monitor multiple possible fault conditions, and a hardware alert is provided through
the open drain INT pin, which asserts low when an enabled fault is detected. The possible faults are: ADC functionality error,
SPI framing error, CRC errors from SPI communications, and loss of internal isolated data stream.
The bits in the INTERRUPT ENABLE (0x13) register determine how the INT output responds to the various error conditions
and asserts the INT output if the corresponding bit is enabled in the INTERRUPT ENABLE register.
If the corresponding bit in the INTERRUPT ENABLE register is not set, when an error is flagged, INT is not asserted, but the
bit in the INTERRUPT STATUS register (0x12) is still latched and remains set until the register is read, which automatically
clears all bits in the INTERRUPT STATUS register. Note that if a fault condition still exists when the register is read, the
cleared fault bit is immediately set again.
In a typical application, INT triggers an interrupt routine in the microcontroller or FPGA, which reads the INTERRUPT
STATUS register to determine the cause of the interrupt.
ADC Functionality Error
ADC functionality is checked by looking for changes in the ADC output. To ensure that a change should have occurred, a
special test measurement is made while injecting a small current at the input of the ADC. This special measurement used
for ADC functionality verification is interleaved between normal measurements and does not affect the ADC sampling time.
If the ADC reading does not change, or data is outside of the limits for at least four frames, an ADC functional failure is
declared and bit FADC (bit 11) in the INTERRUPT STATUS (0x12) register is set.
SPI Framing Error
After CS transitions from low to high, if the number of bits clocked in while CS was low is not 24, 32, 88, or 96 bits, an SPI
framing error is declared and bit SPIFRM (bit 9) in the INTERRUPT STATUS (0x12) register is set. The instruction in the SPI
shift register is not decoded and no register value is changed.
Loss of Data Stream
The field-side sends ADC data across the isolation barrier to the logic-side every 50μs except for the startup period. Field-
side loss-of-data (FLD) interrupts are masked for the first 100ms of operation after power-on or reset, and after that if an
internal monitoring signal is not received, an error is flagged. If the periodic field-side data is not received, a loss-of-data-
stream fault is declared and bit FLD (bit 10) in the INTERRUPT STATUS (0x12) register is set. It is possible to recover from
a loss of data stream fault by asserting a hard reset using bit REST (bit 0) in the CONTROL (0x14) register, which causes
field-side power to be rebooted and returns all of the registers to their default state, requiring the MAX22530–MAX22532 to
go through the startup configuration process.
CRC Error from Internal Communication
Internal communication across the isolation barrier includes a CRC code to ensure that corrupt data does not cause system
problems. If the CRC indicates an error, the received data is discarded. If six consecutive CRCs fail, a CRC fault is declared
and bit SPICRC (bit 8) in the INTERRUPT STATUS (0x12) register is set.
Control Modes
The CONTROL (0x14) register includes a number of bits which the host can program and which take immediate effect on
the device.
Hardware Reset Control
If the control bit REST is set to 1, the field-side power supply is shut down and restarted, and the main reset input to the
digital core is asserted, resulting in setting the digital core back to its power-on reset state and all registers are brought back
to their default values, including the control bit, REST.
Software Reset Control
The software reset is initiated by setting bit SRES to 1. Unlike the hardware reset that is effective immediately after assertion,
SRES takes affect after the completion of the frame, during which it is asserted. At that time, the digital core is reset and all
registers are brought back to their default values. The field-side power supply is not affected by SRES.
Clear POR Control
The CLRPOR bit can be set to 1 to clear the ‘Wake Up from Power-On Reset’ POR bit in the PROD_ID (0x00) register. Note
that a hardware reset (REST) causes the POR bit to be reasserted, but a software reset, SRES, has no effect on the status
bit POR.

DISPWR Control
Setting bit DISPWR to 1 disables field-side power (VDDF), effectively stopping ADC conversions. The logic-side or digital
core is not affected.
Filter Clearing Control
The control bits FLT_CLR_1 to FLT_CLR_4 can be set to 1 to clear the ADC moving average filter for that specific channel
at the start of the frame following this assertion. Once the filter reset operation takes place the control bits remain set at 0 for
normal operation.
Comparator Limit Control
The control bit ECOM can be set to 1 to apply the settings of COUTHI1 and COUTLO1 to all four channels regardless of
what values are programmed in the high and low threshold registers for the other three channels. Setting the ECOM bit to 1
does not change what the host reads back from the threshold registers for channels 2 to 4.
CRC Control
If control bit ENCRC is 0, CRC functionality is not enabled, and SPI transactions are 24-bits in length. But if control bit ENCRC
is 1, CRC functionality is enabled making each SPI transaction 32-bits in length. At power-on, or after a hardware or software
reset, the default CRC is disabled. All SPI transactions following the write transaction that sets ENCRC must have the 8-bit
CRC suffix.
Interrupts
In a system, the MAX22530–MAX22531 device operations can be monitored by the host (typically a microcontroller or FPGA)
by either polling the ADC_ registers or by using the end-of-conversion (EOC) interrupt bit in the INTERRUPT ENABLE (0x13)
register to assert the interrupt pin, INT. The ADC core continually digitizes the inputs for the four channels in succession,
and the host can determine the ADC conversion state by polling the ADCs bit in each ADC_ register (bit 15), or by enabling
the EOC to be shown on the INT every 50 µs. If the EOC interrupt is enabled, bit EOC (bit 12) in the INTERRUPT STATUS
(0x12) register is set to 1 and causes the INT pin to be asserted for a duration of 10µs at the end of channel 4 ADC (ADC_4)
conversion. After 10µs the INT pin is deasserted whether the INTERRUPT STATUS register is read or not.
At that time, the unfiltered (ADC_) and filtered (FADC_) data are available to be read through SPI, as well as the comparator
status and comparator-related interrupts.
If the host is polling the SPI interface for ADC status, the burst read command allows it to read all four ADC registers (ADC1
to ADC4, or FADC1 to FADC4. See ADC_STATUS BLK in register map section) in addition to the INTERRUPT STATUS
register. Bit 15 in each ADC_ register is the ADCs bit. If ADCs is 0 the register contents have been updated (new conversion
data) since the last read operation. By performing a data read operation, the ADCs bit is automatically set to 1, indicating the
data has not been refreshed since the last read operation. Upon receiving the INT signal, the host interrupt service routine
can perform a burst read, which automatically clears the bits in the INTERRUPT STATUS register, thereby deasserting the
INT pin.
If the host does not access the ADC_ data registers at least once per frame (whether by polling or responding to INT being
asserted) then data loss occurs, and the register contents are overwritten with new conversion data.
If the ADC_ data register refreshing event occurs while CS is low (i.e., during an SPI transaction), the data refreshing event
is postponed until the deassertion of CS. This scheme eliminates possible data corruption and data loss. However, it
assumes that the rate of the SPI transaction is equal to or greater than the rate of ADC sampling (20ksps), and that the
duration of any SPI transaction is shorter than that of a 4-channel conversion frame. The host can safely read the ADC_ data
registers during the 50µs following the assertion of the end-of-conversion interrupt.
The host can set the limits against which the ADC data is compared. The host can select if a given channel uses the unfiltered
(ADC_) or the filtered ADC (FADC_) data for comparison against the limits using the control bits CO_MODE (bit 15) and
CO_IN_SEL (bit 14) in each COUTHI_ register. The CO_MODE bits determine the comparator mode of operation (Digital
Data Mode if the bit is set to 0 or Digital Status Mode if the bit is set to 1) and CO_IN_SEL selects between unfiltered ADC
data (bit set to 0) of filtered ADC data (bit set to 1). The status of the comparison for each channel can be read from register
COUT STATUS (0x11).
In addition to the diagnostics bits, the comparator outputs can be programmed to assert the INT pin if enabled. If a positive
edge is detected by the comparator, the bit CO_POS_ is set to 1 indicating the ADC_ data is greater than the upper limit
(COUTHI_). Similarly, if a negative edge is detected by the comparator, the bit CO_NEG_ is set to 1 indicating the ADC_
data is lower than the lower limit (COUTLO_).

Changes to comparator control register contents take effect on the next frame. For example, if COUTHI_4[11:0] is changed
during frame N, the new threshold value is used starting frame N+1.
To clear an interrupt and deactivate the INT pin, the host must perform a read operation of the INTERRUPT STATUS register.
All bits in the INTERRUPT STATUS register are “Read Clears All.” Interrupts are cleared whether the CRC is properly
decoded by the host or not. Note that if a fault condition still exists when the register is read, the cleared fault bit is immediately
set again.
If an interrupt is not set at the time that the INTERRUPT STATUS register is read, and if that interrupt gets asserted while
the interrupt register is being read, that interrupt bit is not cleared upon the end of the SPI read transaction.
However, if an interrupt that is set at the time that the interrupt register is read, and if another identical interrupt gets asserted
while the interrupt register is being read, that interrupt bit is cleared upon the end of the SPI transaction. This means that the
host should read the interrupt register upon assertion of INT, or poll the interrupt registers several times per conversion cycles
to avoid missing interrupts.
In a system, the MAX22530–MAX22531 device operations can be monitored by the host (typically a microcontroller or FPGA)
by either polling the ADC_ registers or by using the end-of-conversion (EOC) interrupt bit in the INTERRUPT ENABLE (0x13)
register to assert the interrupt pin, INT. The ADC core continually digitizes the inputs for the four channels in succession,
and the host can determine the ADC conversion state by polling the ADCs bit in each ADC_ register (bit 15), or by enabling
the EOC to be shown on the INT every 50 µs. If the EOC interrupt is enabled, bit EOC (bit 12) in the INTERRUPT STATUS
(0x12) register is set to 1 and causes the INT pin to be asserted for a duration of 10µs at the end of channel 4 ADC (ADC_4)
conversion. After 10µs the INT pin is deasserted whether the INTERRUPT STATUS register is read or not.
At that time, the unfiltered (ADC_) and filtered (FADC_) data are available to be read through SPI, as well as the comparator
status and comparator-related interrupts.
If the host is polling the SPI interface for ADC status, the burst read command allows it to read all four ADC registers (ADC1
to ADC4, or FADC1 to FADC4) in addition to the INTERRUPT STATUS register. Bit 15 in each ADC_ register is the ADCs
bit. If ADCs is 0 the register contents have been updated (new conversion data) since the last read operation. By performing
a data read operation, the ADCs bit is automatically set to 1, indicating the data has not been refreshed since the last read
operation. Upon receiving the INT signal, the host interrupt service routine can perform a burst read, which automatically
clears the bits in the INTERRUPT STATUS register, thereby deasserting the INT pin.
If the host does not access the ADC_ data registers at least once per frame (whether by polling or responding to INT being
asserted) then data loss occurs, and the register contents are overwritten with new conversion data.
If the ADC_ data register refreshing event occurs while CS is low (i.e., during an SPI transaction), the data refreshing event
is postponed until the deassertion of CS. This scheme eliminates possible data corruption and data loss. However, it
assumes that the rate of the SPI transaction is equal to or greater than the rate of ADC sampling (20ksps), and that the
duration of any SPI transaction is shorter than that of a 4-channel conversion frame. The host can safely read the ADC_ data
registers during the 50µs following the assertion of the end-of-conversion interrupt.
The host can set the limits against which the ADC data is compared. The host can select if a given channel uses the unfiltered
(ADC_) or the filtered ADC (FADC_) data for comparison against the limits using the control bits CO_MODE (bit 15) and
CO_IN_SEL (bit 14) in each COUTHI_ register. The CO_MODE bits determine the comparator mode of operation (Digital
Data Mode if the bit is set to 0 or Digital Status Mode if the bit is set to 1) and CO_IN_SEL selects between unfiltered ADC
data (bit set to 0) of filtered ADC data (bit set to 1). The status of the comparison for each channel can be read from register
COUT STATUS.
In addition to the diagnostics bits, the comparator outputs can be programmed to assert the INT pin if enabled. If a positive
edge is detected by the comparator, the bit CO_POS_ is set to 1 indicating the ADC_ data is greater than the upper limit
(COUTHI_). Similarly, if a negative edge is detected by the comparator, the bit CO_NEG_ is set to 1 indicating the ADC_
data is lower than the lower limit (COUTLO_).
Changes to comparator control register contents take effect on the next frame. For example, if COUTHI_4[11:0] is changed
during frame N, the new threshold value is used starting frame N+1.
To clear an interrupt and deactivate the INT pin, the host must perform a read operation of the INTERRUPT STATUS register
(0x12). All bits in the INTERRUPT STATUS register are “Read Clears All.” Interrupts are cleared whether the CRC is properly
decoded by the host or not. Note that if a fault condition still exists when the register is read, the cleared fault bit is immediately
set again.

If an interrupt is not set at the time that the INTERRUPT STATUS register is read, and if that interrupt gets asserted while
the interrupt register is being read, that interrupt bit is not cleared upon the end of the SPI read transaction.
However, if an interrupt that is set at the time that the interrupt register is read, and if another identical interrupt gets asserted
while the interrupt register is being read, that interrupt bit is cleared upon the end of the SPI transaction. This means that the
host should read the interrupt register upon assertion of INT, or poll the interrupt registers several times per conversion cycles
to avoid missing interrupts.
Digital Isolation
The MAX22530-MAX22532 provide basic galvanic isolation for both power and digital signals that are transmitted from the
field side to the logic side.
The MAX22530 device withstands differences in ground potential between the two power domains of up to 5kVRMS (VISO)
for up to 60s, and up to 848VRMS (VIOWM) for extended periods of time. The MAX22530 is available is 16-pin wide body
SOIC package with 8mm of creepage and clearance. The package material has a minimum comparative tracking index (CTI)
of 400V to give a group II rating in creepage tables. See Table 4 for certification information.
The MAX22531 and MAX22532 device withstand differences in ground potential between the two power domains of up to
3.75KVRMS (VISO) for up to 60s, and up to 445VRMS (VIOWM) for extended periods of time. The MAX22531 is available in
20-pin SSOP and MAX22532 is available in 28-pin SSOP with 5.5mm of creepage and clearance. The package material has
a minimum comparative tracking index (CTI) of 400V to give a group II rating in creepage tables. See Table 4 for certification
information.
Table 4. Safety Regulatory Approvals
UL
The MAX22530, MAX22531 are certified under UL1577. For more details, refer to File E351759
The MAX22530 is rated up to 5000VRMS isolation voltage for single protection.
The MAX22531 is rated up to 3750VRMS isolation voltage for single protection.
cUL (Equivalent to CSA notice 5A)
The MAX22530 is certified up to 5000VRMS isolation voltage. For more details, refer to File E351759
The MAX22531 is rated up to 3750VRMS isolation voltage. For more details, refer to File E351759

Applications Information
Power Supply Decoupling
It is recommended to decouple both the VDDL and VDDPL supplies with 1μF capacitors in parallel with 0.01μF capacitors to
GNDL. Place the 0.01μF capacitors as close to VDDL and VDDPL as possible. The VDDF pin is the integrated DC-DC
converter output and it is recommended to decouple it with low-ESR capacitors of 1μF in parallel with 0.01μF to GNDF.
Place the 0.01μF capacitor as close to VDDF as possible.
Layout Considerations
The PCB designer should follow some critical recommendations to get the best performance from the design.
• Keep the input/output traces as short as possible. To keep signal paths low inductance, avoid using vias.
• Have a solid ground plane underneath the signal layer to minimize the noise.
• Keep the area underneath the MAX22530–MAX22532 free from ground and signal planes. Any galvanic or metallic
connection between the field side and logic side defeats the isolation.
• Ensure that the decoupling capacitors between VDDL, VDDPL and GNDL, and between VDDF and GNDF are located
as close as possible to the IC to minimize inductance.
• Route important signal lines close to the ground plane to minimize possible external influences. On the field-side, it is
good practice to separate the ADC input and voltage reference ground AGND from the VDDF reference ground GNDF.
• MAX22531 has two extra AGND pins, and MAX22532 has four extra AGND pins to provide analog ground reference
points for the respective AIN_ channels.
Radiated Emissions
The MAX22530–MAX22532 family features an integrated DC-DC converter to generate a nominal 3.1V supply, powering the
field side of the MAX22530–MAX22532. The DC-DC converter passes power from the logic side across the isolation barrier
through an internal transformer. Due to the isolated nature of the device, the split of the ground planes (GNDL and GNDF)
prevents the return current from flowing back to the logic side; thus, causing high-frequency signals to radiate when crossing
the isolation barrier. A spread-spectrum option is added to the DC-DC converter to reduce the radiated emissions.
The MAX22530–MAX22532 can meet CISPR 22 and FCC radiated emission standards with proper PCB design. A stitching
capacitance of 50pF minimum is recommended to be built into the PCB to pass the CISPR 22 and FCC Class B limits. See
Figure 7 and Figure 8.
To achieve optimal radiated emission performance, the following layout guidelines are recommended:
• Use at least a 4-layer PCB stackup with GNDL and GNDF ground planes on two adjacent internal layers.
• Extend the GNDF and GNDL planes on two adjacent layers so they overlap each other; thus, creating a stitching
capacitance between GNDL and GNDF. See Figure 5 and Figure 6.
Calculate the stitching capacitance value by using the following equation, where A is the overlapping area between the GNDL
and GNDF planes.
C = A × ε0 × εr × d
where,
ε0 = Permittivity of free space (8.854 x 10-12 F/m),
εr = Relative permittivity of the PCB insulation material, and
d = Dielectric thickness between two adjacent layers.
• Adjust the overlapping area (A) or the dielectric thickness (d) to achieve a minimum 50pF stitching capacitance. Make
sure that the creepage and clearance between the GNDF plane and the GNDL plane on the same layer as well as
between two different layers large enough to meet isolation standards for various applications.
• Multiple GNDL and GNDF vias are recommended to be placed next to the GNDF and GNDL pins to provide a good
connection between the stitching capacitor and the device ground pins.
• Apply edge guarding vias to stitch the GNDF and GNDL planes on all layers together to limit the emission from
escaping from the PCB edges.

MAX22530–MAX22532
GNDL GNDF
GNDL GNDF
d
GNDL GNDF
A
GNDL GNDF
L GNDF VIAS
GNDL VIAS
7.36mm W SOIC
5.3mm SSOP
Figure 5. Stitching Capacitance Example on a 4- Layer PCB
GNDL INTERNAL LAYER-2 GNDF
GNDL INTERNAL LAYER-3 GNDF
Figure 6. Stitching Capacitance on Internal Layers
Figure 7. MAX22530 Radiated Emission with 90pF Stitching Capacitance, 3-Meter Antenna Distance, Horizontal Scan

Figure 8. MAX22530 Radiated Emission with 90pF Stitching Capacitance, 3-Meter Antenna Distance, Vertical Scan
Figure 9. MAX22531 Radiated Emission with 100pF Stitching Capacitance, 3-Meter Antenna Distance, Horizontal Scan
Figure 10. MAX22531 Radiated Emission with 100pF Stitching Capacitance, 3-Meter Antenna Distance, Vertical Scan

Register Map
SPI_Register_MAP
ADDRESS NAME MSB LSB
ID_BLK
PROD_ID[15:8] DEVICE_ID[7:0]
0x00
PROD_ID[7:0] POR DEVICE_REV[6:0]
ADC_STATUS BLK
ADC 1[15:8] ADCS – – – ADC[11:8]

0x01
ADC 1[7:0] ADC[7:0]
ADC 2[15:8] ADCS – – – ADC[11:8]

0x02
ADC 2[7:0] ADC[7:0]
ADC 3[15:8] ADCS – – – ADC[11:8]

0x03
ADC 3[7:0] ADC[7:0]
ADC 4[15:8] ADCS – – – ADC[11:8]

0x04
ADC 4[7:0] ADC[7:0]
FADC 1[15:8] – – – – FADC[11:8]

0x05
FADC 1[7:0] FADC[7:0]
FADC 2[15:8] – – – – FADC[11:8]

0x06
FADC 2[7:0] FADC[7:0]
FADC 3[15:8] – – – – FADC[11:8]

0x07
FADC 3[7:0] FADC[7:0]
FADC 4[15:8] – – – – FADC[11:8]

0x08
FADC 4[7:0] FADC[7:0]
COUT_BLK
CO_MOD CO_IN_S
COUTHI 1[15:8] – – COTHI[11:8]
E EL
0x09
COUTHI 1[7:0] COTHI[7:0]
CO_MOD CO_IN_S
0x0A COUTHI 2[15:8] – – COTHI[11:8]
E EL

ADDRESS NAME MSB LSB
CO_MOD CO_IN_S
COUTHI 3[15:8] – – COTHI[11:8]
E EL
0x0B
CO_MOD CO_IN_S
COUTHI 4[15:8] – – COTHI[11:8]
E EL
0x0C
COUTLO 1[15:8] – – – – COTLO[11:8]

0x0D
COUTLO 1[7:0] COTLO[7:0]
COUTLO 2[15:8] – – – – COTLO[11:8]

0x0E
COUTLO 3[15:8] – – – – COTLO[11:8]

0x0F
COUTLO 4[15:8] – – – – COTLO[11:8]

0x10
CONTROL_STATUS
COUT STATUS[15:8] – – – – – – – –
0x11
COUT STATUS[7:0] – – – – CO_4 CO_3 CO_2 CO_1
INTERRUPT
– – – EOC ADCF FLD SPIFRM SPICRC
STATUS[15:8]
0x12
CO_POS_ CO_POS_ CO_POS_ CO_POS_ CO_NEG_ CO_NEG_ CO_NEG_ CO_NEG_
INTERRUPT STATUS[7:0]
4 3 2 1 4 3 2 1
INTERRUPT
– – – EEOC EFADC EFLD ESPIFRM ESPICRC
ENABLE[15:8]
0x13
ECO_PO ECO_PO ECO_PO ECO_PO ECO_NE ECO_NE ECO_NE ECO_NE
INTERRUPT ENABLE[7:0]
S_4 S_3 S_2 S_1 G_4 G_3 G_2 G_1
CONTROL[15:8] ENCRC ECOM – – – – – –
0x14
FLT_CLR FLT_CLR FLT_CLR FLT_CLR
CONTROL[7:0] DISPWR CLRPOR SRES REST
_4 _3 _2 _1
Register Details

PROD_ID (0x0)
Device ID Register
BIT 15 14 13 12 11 10 9 8
Field DEVICE_ID[7:0]
Reset 0x00
Access Type Read Only
BIT 7 6 5 4 3 2 1 0
Field POR DEVICE_REV[6:0]
Reset 0b0 0x01
Access Type Read Only Read Only
BITFIELD BITS DESCRIPTION DECODE
Device ID
DEVICE_ID 15:8 0x0: MAX22530/MAX22531/MAX22532
0x0: Normal Operation

POR 7 Power-On Reset
0x1: Wake up from Power-On Reset
DEVICE_REV 6:0 Revision Control of die 0x0: Initial Die Revision
ADC (0x1, 0x2, 0x3, 0x4)

ADC_ Data Register
BIT 15 14 13 12 11 10 9 8
Field ADCS – – – ADC[11:8]
Reset 0b0 – – – 0x000
Access Type Read Sets All – – – Read Only
BIT 7 6 5 4 3 2 1 0
Field ADC[7:0]
Reset 0x000

0x0: ADC has been updated since last read operation

ADCS 15 ADC Data Read Check function 0x1: ADC has not been updated since last read operation
ADC 11:0 Unfiltered ADC Data
FADC (0x5, 0x6, 0x7, 0x8)

Filtered ADC_ Data Register
BIT 15 14 13 12 11 10 9 8
Field – – – – FADC[11:8]
Reset – – – – 0x000
Access Type – – – – Read Only
BIT 7 6 5 4 3 2 1 0
Field FADC[7:0]
Reset 0x000
BITFIELD BITS DESCRIPTION
FADC 11:0 Filtered ADC Data
COUTHI (0x9, 0xA, 0xB, 0xC)
BIT 15 14 13 12 11 10 9 8
Field CO_MODE CO_IN_SEL – – COTHI[11:8]
Reset 0b0 0b0 – – 0xB32
Access Type Write, Read Write, Read – – Write, Read
BIT 7 6 5 4 3 2 1 0
Field COTHI[7:0]
Reset 0xB32
Access Type Write, Read

0x0: Digital Input Mode

CO_MODE 15 Comparator Output Operation Mode Selection 0x1: Digital Status Mode
0x0: Unfiltered ADC data is used as input to the
CO_IN_SEL 14 Comparator Input Selection comparator
0x1: Filtered ADC data is used as input to the comparator
COTHI 11:0 Comparator Threshold High Value 0xB32h: 70% of range
COUTLO (0x10, 0xD, 0xE, 0xF)
BIT 15 14 13 12 11 10 9 8
Field – – – – COTLO[11:8]
Reset – – – – 0x4CC
Access Type – – – – Write, Read
BIT 7 6 5 4 3 2 1 0
Field COTLO[7:0]
Reset 0x4CC
Access Type Write, Read
COTLO 11:0 Comparator Threshold Low Value 0x4CCh: 30% of range
COUT STATUS (0x11)

Digital Comparator COUT_ Status Register
BIT 15 14 13 12 11 10 9 8
Field – – – – – – – –
Reset – – – – – – – –
Access Type – – – – – – – –
BIT 7 6 5 4 3 2 1 0
Field – – – – CO_4 CO_3 CO_2 CO_1

Reset – – – – 0b0 0b0 0b0 0b0
Access Type – – – – Read Only Read Only Read Only Read Only
0x0: MODE 0: The ADC value is lower than COUTLO

value.
MODE 1: The ADC value is within COUTHI and COUTLO.
CO_4 3 Comparator Output status: when CO_MODE = 0/1 0x1: MODE 0: The ADC value is higher than COUTHI
value.
MODE 1: The ADC value is higher than COUTHI value or
lower than COUTLO value.
value.
value.
value.
value.
value.
value.
INTERRUPT STATUS (0x12)

Interrupt Status Register
BIT 15 14 13 12 11 10 9 8
Field – – – EOC ADCF FLD SPIFRM SPICRC
Reset – – – 0b0 0b0 0b0 0b0 0b0
Read Clears Read Clears Read Clears Read Clears Read Clears
Access Type – – –
All All All All All
BIT 7 6 5 4 3 2 1 0
Field CO_POS_4 CO_POS_3 CO_POS_2 CO_POS_1 CO_NEG_4 CO_NEG_3 CO_NEG_2 CO_NEG_1
Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0
Read Clears Read Clears Read Clears Read Clears Read Clears Read Clears Read Clears Read Clears
Access Type
All All All All All All All All

0x0: No end of conversion event

EOC 12 Enable End of ADC Conversion Interrupt 0x1: End of conversion of one cycle of Channel 1 to 4
event detected
0x0: Correct ADC functionality: ADC Diagnostic values
are in range
ADCF 11 ADC Functionality Interrupt
0x1: Faulty ADC functionality: ADC Diagnostic values are
not in range
0x0: No data loss
FLD 10 Field Data Interrupt
0x1: Loss of data occurred
0x0: No SPI frame error detected
SPIFRM 9 SPI Frame Error Interrupt
0x1: At least one SPI frame error was detected
0x0: No SPI CRC error detected
SPICRC 8 SPI CRC Error Interrupt
0x1: At least one SPI CRC error was detected
0x0: No positive edge was detected by Comparator 4
CO_POS_4 7 Comparator Output 4 low-to-high transition interrupt 0x1: At least one positive edge was detected
by Comparator 4
CO_POS_3 6 Comparator Output 3 low-to-high transition interrupt 0x1: At least one positive edge was detected by
Comparator 3
CO_POS_2 5 Comparator Output 2 low-to-high transition interrupt 0x1: At least one positive edge was detected by
Comparator 2
CO_POS_1 4 Comparator Output 1low-to-high transition interrupt 0x1: At least one positive edge was detected by
Comparator 1
0x0: No negative edge was detected by Comparator 4
CO_NEG_4 3 Comparator Output 4 high-to-low transition interrupt 0x1: At least one negative edge was detected by
Comparator 4
Comparator 3
Comparator 2
Comparator 1
INTERRUPT ENABLE (0x13)

Interrupt Enable Register
BIT 15 14 13 12 11 10 9 8
Field – – – EEOC EFADC EFLD ESPIFRM ESPICRC
Reset – – – 0b0 0b0 0b0 0b0 0b0
Access Type – – – Write, Read Write, Read Write, Read Write, Read Write, Read
BIT 7 6 5 4 3 2 1 0
Field ECO_POS_4 ECO_POS_3 ECO_POS_2 ECO_POS_1 ECO_NEG_4 ECO_NEG_3 ECO_NEG_2 ECO_NEG_1

Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
0x0: EOC Interrupt Disabled

EEOC 12 Enable End of ADC Conversion Interrupt 0x1: FADC Interrupt
0x0: FADC Interrupt Disabled
EFADC 11 Enable ADC Fault Interrupt
0x1: FADC Interrupt Enabled
0x0: EFLD Interrupt Disabled
EFLD 10 Enable Loss Data Fault Interrupt
0x1: EFLD Interrupt Enabled
0x0: SPIFRM Interrupt Disabled
ESPIFRM 9 Enable SPI Frame Fault Interrupt
0x1: SPIFRM Interrupt Enabled
0x0: SPICRC Interrupt Disabled
ESPICRC 8 Enable SPI CRC Fault Interrupt
0x1: SPICRC Interrupt Enabled
0x0: Disable CO_POS4 Interrupt
ECO_POS_4 7 Enable COUT4 Positive Transition Interrupt
0x1: Enable CO_POS4 Interrupt
0x0: Disable CO_NEG4 Interrupt
ECO_NEG_4 3 Enable COUT4 Negative Transition Interrupt
0x1: Enable CO_NEG4 Interrupt
CONTROL (0x14)
Control Register
BIT 15 14 13 12 11 10 9 8
Field ENCRC ECOM – – – – – –
Reset 0b0 0b0 – – – – – –
Access Type Write, Read Write, Read – – – – – –
BIT 7 6 5 4 3 2 1 0
Field FLT_CLR_4 FLT_CLR_3 FLT_CLR_2 FLT_CLR_1 DISPWR CLRPOR SRES REST
Reset 0b0 0b0 0b0 0b0 0b0 0b0 0b0 0b0
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

0x0: CRC not used (24-bit SPI transactions)

ENCRC 15 Enable SPI CRC 0x1: CRC used (32-bit SPI transactions)
Enable Common High and Low Thresholds for all 0x0: Each threshold needs to be individually programmed
ECOM 14 0x1: All comparators use COUTHI1 and COUTLO1 as
Channels threshold values
0x0: Normal operation
FLT_CLR_4 7 Clear ADC4 Moving Average Filter
0x1: Clear ADC4 filter
0x0: Normal Operation, Enable Field Power VDDF
DISPWR 3 Disable Field Power VDDF
0x1: Disable Field Power VDDF
0x0: No action
CLRPOR 2 Clear POR bit
0x1: Clear POR bit in PROD_ID Register
SRES 1 Soft Reset (Reset Logic Core & Registers)
0x1: Soft Reset Enabled (Self-Clearing)
REST 0 Hard Reset (including field supply power off)
0x1: Hard Reset (Self-Clearing)
Typical Application Circuits

High-Voltage DC Monitoring
UP TO 110VDC LINE MONITORING
+ 60kΩ
VDC
1.8V
1kΩ 0.01µF
1µF 0.01µF
+ 60kΩ MAX22530/MAX22531/MAX22532 MICRO-

VDC REFERENCE CONTROLLER
0.01µF VDDL 3.3V
1kΩ VDD
AIN1
AIN2 0.01µF 1µF
12-BIT ADC
+ 60kΩ AIN3
VDC INT
GPI
1kΩ 0.01µF AIN4
LOGIC AND SPI CS CS
INTERFACE SCLK
LOGIC CONTROL SCLK
+ 60kΩ SDI
VDC MOSI
0.01µF SDO MISO
1kΩ
3.1V VDDF
µPOWER VDDPL 3.0V TO 5.5V
ISOLATED DC-DC
AGND
0.01µF 1µF
GNDF GNDL GNDL
1µF 0.01µF
NOTE: INPUT RESISTIVE DIVIDER SETS MAXIMUM DC LINE LEVEL

3-Phase Motor Low Side Monitoring
VCC
Φ1 Φ2 Φ3
PHASE A 3-PHASE
MOTOR
PHASE C
PHASE B
RECTIFIED BUS VOTLAGE Φ1 Φ2 Φ3

(MOTOR SUPPLY)
1kΩ 220kΩ
20mΩ,10A
20mΩ,10A
20mΩ,10A
1.8V
0.01µF
1µF 0.01µF
MAX22530/MAX22531/MAX22532 MICRO-
REFERENCE CONTROLLER
0.01µF VDDL 3.3V
AIN1 VDD
AIN2 0.01µF 1µF

12-BIT ADC
AIN3 INT
GPI
0.01µF AIN4
LOGIC AND SPI CS CS
INTERFACE SCLK
LOGIC CONTROL SCLK
0.01µF
SDI MOSI
SDO MISO
3.1V VDDF 3.0V TO 5.5V

µPOWER VDDPL
AGND ISOLATED DC-DC
0.01µF 1µF
GNDF GNDL GNDL
1µF 0.01µF
Ordering Information
PART NUMBER ISOLATION RATING (VRMS) # OF COUT PINS PIN-PACKAGE
MAX22530AWE+ 5000 0 16-pin WSOIC
MAX22531AAP+ 3500 2 20-pin SSOP
MAX22532AAI+* 3500 4 28-pin SSOP
*Future product–contact Maxim for availability.
+ Denotes lead (Pb)-free/RoHS compliance.

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 3/21 Release for Market Intro —
Updated General Description section, Safety Regulatory Approvals section, Insulation
1 9/21 1, 7, 8, 21, 36
Characteristics table, and Ordering Information table; added Digital Isolation section
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
may result from its use. Specifications subject to change without notice. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the
property of their respective owners.
w w w . a n a l o g . c o m Analog Devices | 37

MAX22530 Isolated ADC

Uploaded by

Document Informationclick to expand document information

Document Informationclick to expand document information

Copyright:

Available Formats

MAX22530 Isolated ADC

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

MAX22530 Isolated ADC

Uploaded by

Copyright:

Available Formats

Click here to ask an associate for production status of specific part numbers.

Field-Side Self-Powered, MAX22530–MAX22532

19-100989; Rev 1; 9/21

Four-Channel Isolated ADC

www.analog.com Analog Devices | 2

Pin Descriptions ..................................................................................................................................................................... 14

www.analog.com Analog Devices | 3

www.analog.com Analog Devices | 4

Field-Side Self-Powered, MAX22530–MAX22532

19-100246; Rev 1; 7/19

Absolute Maximum Ratings

www.analog.com Analog Devices | 6

www.analog.com Analog Devices | 7

www.analog.com Analog Devices | 8

tCSH0 tCSS0 tDS t DH tCL tCH tCP t CSS1 t CSW

Figure 1. SPI Write Timing Diagram (with CRC Enabled)

tCSH0 tCSS0 tDS tDH tCL tCH tCP tCSS1 tCSW

SCLK 1 2 3 4 5 6 7 8 9 10 N+6 N+7 N+8

tDOT NOTE B: BURST BIT tDOH tDOD

Figure 2. SPI Read Timing Diagram (with CRC Enabled)

www.analog.com Analog Devices | 9

20-pin and 28-pin SSOP

www.analog.com Analog Devices | 10

Internal Clearance Distance through insulation 0.015 mm

ESD and Transient Immunity Characteristics

www.analog.com Analog Devices | 11

Typical Operating Characteristics

www.analog.com Analog Devices | 12

www.analog.com Analog Devices | 13

REF External Filter Capacitor. Connect a 1μF||0.01μF capacitor from

www.analog.com Analog Devices | 14

lower threshold (COUTLO1) in digital input mode. See the Digital

www.analog.com Analog Devices | 15

AIN3 LOGIC AND SPI CS

www.analog.com Analog Devices | 16

Figure 3. Digital Input Mode

www.analog.com Analog Devices | 17

Digital Status Mode

Figure 4. Digital Status Mode

The functionality of each SPI pin can be summarized as follows:

www.analog.com Analog Devices | 18

www.analog.com Analog Devices | 19

Diagnostic and Fault Reporting Features

www.analog.com Analog Devices | 20

www.analog.com Analog Devices | 21

www.analog.com Analog Devices | 22

www.analog.com Analog Devices | 23

www.analog.com Analog Devices | 24

Figure 5. Stitching Capacitance Example on a 4- Layer PCB

GNDL INTERNAL LAYER-2 GNDF

GNDL INTERNAL LAYER-3 GNDF

Figure 6. Stitching Capacitance on Internal Layers

www.analog.com Analog Devices | 25

www.analog.com Analog Devices | 26

ADC 1[15:8] ADCS – – – ADC[11:8]

ADC 2[15:8] ADCS – – – ADC[11:8]

ADC 3[15:8] ADCS – – – ADC[11:8]

ADC 4[15:8] ADCS – – – ADC[11:8]