Tps 65192

TPS65192
www.ti.com ....................................................................................................................................................................................................... SLVS962 JULY 2009
9-Channel Level Shifter With Gate Voltage Shaping and Discharge Functions
1FEATURES A tenth level shifter channel specially configured with
9-Channel Level Shifter Supports 6 CLK, a comparator input stage allows designers to
implement panel discharging during power-down.
VST, ODD, and EVEN Signals
Organized as Two Groups of 7 + 2 Channels BLOCK DIAGRAM
Separate Positive Supplies (VGHX) for Each
Group
FLK1
VGHX Levels up to 38V
FLK2
VGL Levels Down to 13V VGH1 FLK3
Panel DISCHARGE Function RE
Suitable for 4-Phase and 6-Phase Applications IN1 OUT1
Gate Voltage Shaping on Channels 1 to 6
IN2 OUT2
Supports Single and Multiple Flicker Clocks
Gate Shaping
Peak Output Currents greater than 500mA IN3 OUT3
28-Pin 55 mm QFN Package IN4 OUT4
IN5 OUT5
APPLICATIONS
LCD Displays Using Gate-in-Panel (GIP) IN6 OUT6
Technology
IN7 OUT7
DESCRIPTION VSENSE -
DISCHARGE
The TPS65192 is a 9 channel level-shifter intended VREF +
for use in LCD display applications such as TVs and

monitors. The device converts the logic-level signals GND VGL
generated by the Timing Controller (T-CON) to the VGH2
high-level signals used by the display panel.
The 9 level shifter channels are organized as two IN8 OUT8
groups. Channels 1 through 7 are powered from VGH1
IN9 OUT9
and VGL, and channels 8 and 9 are powered from
VGH2 and VGL. Each level-shifter channel features low
impedance output stages that achieve fast rise and
fall times even when driving the capacitive loading
typically present in LCD display applications.
Level shifter channels 1 through 6 support gate
voltage shaping, which can be used to improve
picture quality by reducing image sticking. Novel
decoding logic enables a single flicker clock signal to
control gate voltage shaping for all CLK channels
without the need for synchronization. The device also
supports the use of multiple flicker clocks. The rate of
decay is set by an external resistor or resistor
network connected to the RE pin.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS65192
SLVS962 JULY 2009 ....................................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)

TA ORDERING PACKAGE PACKAGE MARKING
40C to 85C TPS65192RHDR 28-Pin QFN TPS65192
(1) The device is supplied taped and reeled, with 3000 devices per reel.
ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1)
VALUE UNIT
(2)
VGH1, VGH2 0.3 to 45 V
Supply voltage
VGL 0.3 to 15 V
IN1 through IN9, VSENSE, FLK1, FLK2, FLK3 0.3 to 7.0 V
Input voltage (2)
RE 0.3 to 45 V
Output current RE 0.1 A
ESD rating HBM 2 kV
MM 200 V
CDM 700 V
Continuous power dissipation See Dissipation Rating Table
Operating ambient temperature range 40 to 85 C
Operating junction temperature range 40 to 150 C
Storage temperature range 65 to 150 C
Lead temperature (soldering, 10 sec) 300 C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND pin.
DISSIPATION RATINGS
JA TA25C TA=70C TA=85C
PACKAGE
POWER RATING POWER RATING POWER RATING
28-Pin QFN (1) 35C/W 3.57W 2.29W 1.86W
(1) This data is based on using a JEDEC High-K board with the exposed die pad connected to a Cu pad
on the board connected to the ground plane by a 2x3 thermal via matrix.
RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT
VGH1, VGH2 Positive supply voltage range 12 30 38 V
VGL Negative supply voltage range 13 7 2 V
TA Operating ambient temperature 40 85 C
TJ Operating junction temperature 40 125 C
2 Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS65192

TPS65192
ELECTRICAL CHARACTERISTICS
VGH1 = VGH2 = 30V; VGL = 7 V; TA = 40C to 85C; typical values are at 25C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
IGH1 VGH1 Supply current IN1 to IN7 = GND; VSENSE = 0V 0.35 3 mA
IGH2 VGH2 Supply current IN8 and IN9 = GND; VSENSE =0V 0.012 1 mA
IGL VGL Supply current IN1 to IN9 = GND; VSENSE = 0V 0.144 4 mA
VUVLO Undervoltage lockout threshold VGH1 rising 10.5 13.5 V
VHYS Undervoltage lockout hysteresis VGH1 falling 450 mV
LEVEL SHIFTERS
Continuous; OUT1 to OUT7 15
mA
Peak; OUT1 to OUT7 300 650
IOUTX Output current
Continuous; OUT8 and OUT9, DISCHARGE 15
mA
Peak; OUT8 an OUT9, DISCHARGE 150 250
IN1 to IN9 = GND 1
IINX Input current A
IN1 to IN9 = 3.3 V 1
VIH High level input voltage IN1 to IN9 2.0 V
VIL Low level input voltage IN1 to IN9 0.5 V
OUT1 to OUT7; ILOAD = 10 mA 0.12 0.4
VDROPH Output voltage drop high V
OUT8 and OUT9, DISCHARGE; ILOAD = 10 mA 0.36 1.0
OUT1 to OUT7; ILOAD = 10 mA 0.07 0.3
VDROPL Output voltage drop low V
OUT8 and OUT9, DISCHARGE; ILOAD = 10 mA 0.17 1.0
OUT1 to OUT7; CLOAD = 4.7 nF (1) 275 520
tR Rise time ns
OUT8 and OUT9; CLOAD = 4.7 nF (1) 761 1000
OUT1 to OUT7; CLOAD = 4.7nF (1) 220 370
tF Fall time (1)
ns
OUT8 and OUT9; CLOAD = 4.7 nF 526 850
tPH Rising edge, CL = 150 pF 60
Propagation delay ns
tPL Falling edge, CL = 150 pF 60
GATE VOLTAGE SHAPING
Propagation delay gate voltage
tPH FLK falling 100 ns
shaping enabled
Time active IN signals must be stable before falling
tSU Set-up time 70 ns
edge of FLK
Resistance between OUT and RE
rDS(on) 70 100
pins
ILEAK Leakage current from RE pin 10 A
DISCHARGE
VSENSE Discharge voltage sense threshold VSENSE falling 1.275 1.5 1.725 V
Discharge voltage sense input
ISENSE VSENSE = 2V 1 A
current
VHYS Discharge voltage sense hysteresis VSENSE rising 40 mV
(1) Rise and fall times are measured between 10% and 90% of the waveforms amplitude.
Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback 3

TPS65192
DEVICE INFORMATION
PIN ASSIGNMENT
DISCHARGE
VSENSE
FLK1
FLK2
FLK3
GND
RE
25
28
26
24
27
23
22
IN9 1 21 OUT9
IN8 2 20 OUT8
IN7 3 19 OUT7
IN6 4
Exposed 18 OUT6
Thermal Die
IN5 5 17 OUT5
IN4 6 16 OUT4
IN3 7 12 15 OUT3
13
14
10
11
8
VGH1
OUT1
IN1
IN2
VGH2
OUT2
VGL
PIN FUNCTIONS
PIN
I/O DESCRIPTION
NAME NO.
IN9 1 I Level shifter channel 9 input. Connect this pin to GND, if not used.
VGH1 10 P Positive supply voltage for level shifter channels 1 through 7 and discharge function. Bypass this pin with
a parallel combination of 10F and 100nF ceramic capacitors.
VGL 11 P Negative supply voltage. Bypass this pin with a parallel combination of 10F and 100nF ceramic
capacitors.
VGH2 12 P Positive supply voltage for level shifter channels 8 and 9. Bypass this pin with a parallel combination of
10F and 100nF ceramic capacitors.
OUT1 13 O Level shifter channel 1 output. Leave this pin floating, if not used.

TPS65192
PIN FUNCTIONS (continued)

PIN
I/O DESCRIPTION
NAME NO.
DISCHARGE 22 O Panel discharge output. Leave this pin floating, if not used.
GND 23 P Ground.
RE 24 O Gate voltage shaping discharge resistor connection. Leave this pin floating, if not used.
FLK3 25 I Gate voltage shaping flicker clock input for channels 3 and 6. Connect this pin to GND if not used.
VSENSE 28 I Panel discharge voltage sense. Connect this pin to GND, if not used.
Exposed Pad P Connect to VGL
Thermal Die
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
Output Rise and Fall Time Channels 1 to 7, CL = 4.7 nF, rising edge Figure 1
Channels 1 to 7, CL = 4.7 nF, falling edge Figure 2
Channels 8 to 9, CL = 4.7 nF, rising edge Figure 3
Channels 8 to 9, CL = 4.7 nF, falling edge Figure 4
Channels 1 to 7, CL = 8 pF, rising edge Figure 5
Channels 1 to 7, CL = 8 pF, falling edge Figure 6
Channels 8 to 9, CL = 8 pF, rising edge Figure 7
Channels 8 to 9, CL = 8 pF, falling edge Figure 8
Propagation Delay IN to OUT, channels 1 to 7, CL = 150 pF, rising edge Figure 9
IN to OUT, channels 1 to 7, CL = 150 pF, falling edge Figure 10
IN to OUT, channels 8 to 9, CL = 150 pF, rising edge Figure 11
IN to OUT, channels 8 to 9, CL = 150 pF, falling edge Figure 12
FLK to OUT, channels 1 to 6, CL = 150 pF, RE = 1 k Figure 13
Output Current Channels 1 to 7, CL = 10 nF Figure 14
Channels 8 to 9, CL = 10 nF Figure 15
Panel Discharge Power-on sequencing Figure 16
Power-off-sequencing Figure 17

TPS65192
OUTPUT RISE TIME OUTPUT FALL TIME

CHANNELS 1-7, COUT = 4.7 nF CHANNELS 1-7, COUT = 4.7 nF
VOUT
10 V/div
VOUT
10 V/div
RISE TIME = 317 ns FALL TIME = 248 ns

MEASURED BETWEEN 10% MEASURED BETWEEN 90%
AND 90% OF VOUT AND 10% OF VOUT
200 ns/div 200 ns/div

Figure 1. Figure 2.
CHANNELS 8-9, COUT = 4.7 nF CHANNELS 8-9, COUT = 4.7 nF
VOUT
10 V/div
VOUT
10 V/div
FALL TIME = 562 ns

RISE TIME = 846 ns MEASURED BETWEEN 90%
MEASURED BETWEEN 10% AND 10% OF VOUT
AND 90% OF VOUT

Figure 3. Figure 4.

TPS65192

CHANNELS 1-7, COUT = 8 pF CHANNELS 1-7, COUT = 8 pF
VOUT
10 V/div
VOUT
10 V/div
RISE TIME = 3 ns
MEASURED BETWEEN 10% FALL TIME = 4 ns
AND 90% OF VOUT MEASURED BETWEEN 90%
AND 10% OF VOUT
5 ns/div 5 ns/div
Figure 5. Figure 6.
CHANNELS 8-9, COUT = 8 pF CHANNELS 8-9, COUT = 8 pF
VOUT
10 V/div
VOUT
10 V/div
RISE TIME = 3 ns FALL TIME = 3 ns

AND 90% OF VOUT AND 10% OF VOUT
5 ns/div 5 ns/div
Figure 7. Figure 8.

TPS65192
OUTPUT FALL TIME PROPAGATION DELAY FALLING

CHANNELS 8-9, COUT = 8 pF IN-OUT, CHANNELS 1-7, COUT = 8 pF
VOUT
10 V/div
VOUT
10 V/div VIN
1 V/div
FALL TIME = 3 ns
MEASURED BETWEEN 90% DELAY = 32 ns
AND 10% OF VOUT MEASURED BETWEEN 50%
OF VIN AND 50% OF VOUT
5 ns/div 10 ns/div
Figure 9. Figure 10.
PROPAGATION DELAY RISING PROPAGATION DELAY FALLING
IN-OUT, CHANNELS 8-9, COUT = 8 pF IN-OUT, CHANNELS 8-9, COUT = 8 pF
VOUT
10 V/div
VIN VIN
1 V/div 1 V/div
VOUT
10 V/div
DEALY = 19 ns DELAY = 28 ns
OF VIN AND 50% OF VOUT OF VIN AND 50% OF VOUT


TPS65192
PROPAGATION DELAY FALLING DISCHARGE DURING POWER-UP

FLK-OUT, CHANNELS 1-6, COUT = 158 pF
VFLK
1 V/div
VOUT
VGH1
10 V/div
10 V/div
VDISCHARGE
DELAY = 55 ns
MEASURED BETWEEN 50% 10 V/div
OF VFLK AND 90% OF VOUT .

RE = 1 k to GND
50 ms/div
100 ns/div
OUTPUT VOLTAGE DROP (HIGH) vs OUTPUT CURRENT

DISCHARGE DURING POWER-DOWN 4.5
4.50
4
4.00
VGH1
3.5
3.50
10 V/div
Output Voltage Drop V
3
3.00 CHANNELS 8-9
2.5
2.50
2
2.00
1.5
1.50
CHANNELS 1-7
VDISCHARGE 1
1.00
10 V/div
0.5
0.50
0
0.00
00 10
10 20
20 30
30 40
40 50 60
50 60 70
70 80
80 90
90 100
100
1 s/div Output Current mA

TPS65192
OUTPUT VOLTAGE DROP (LOW) vs OUTPUT CURRENT

2
2.00
1.75
1.75
1.5
Output Voltage Drop V

1.50
1.25
1.25
CHANNELS 8-9
1
1.00
0.75
0.75
0.5
0.50 CHANNELS 1-7
0.25
0.25
0
0.00
00 10
10 20
20 30
30 40
40 50
50 60
60 70
70 80
80 90
90 100
100
Output Current mA
Figure 17.
DETAILED DESCRIPTION
LEVEL SHIFTERS
The 9 level shifter channels in the TPS65192 are divided into two groups. Channels 1 through 7 are powered
from VGH1 and VGL, channels 8 and 9 are powered from VGH2 and VGL. Channels 1 to 6 support gate shaping and
channels 7 through 9 do not (see the block diagram on page 1).
Figure 18 contains a simplified block diagram of one channel with gate voltage shaping.
VGH1
INx Q1
From Timing Channel
Controller Control OUTx To LCD Panel
FLKx
Q2
Q3
RE
VGL
RE
Figure 18. Level Shifter Channel With Gate Voltage Shaping
On the rising edge of IN, Q1 turns on, Q2 and Q3 turn off, and OUT is driven to VGH1. On the falling edge of FLK,
Q1 turns off, Q3 is turned on, and the panel now discharges through Q3 and RE (see Figure 19). On the falling
edge of IN, Q2 turns on and Q3 turns off, and OUT is driven to VGL. This sequence is repeated in turn for each
channel.

TPS65192
Figure 19. Gate Voltage Shaping Timing Diagram
The alternative configuration shown in Figure 20 can be used to define a minimum gate voltage reached during
gate voltage shaping.
VGH1
INx Q1
From Timing Channel
Controller Control OUTx To LCD Panel
FLKx
Q2
Q3
VGH1
RE1
RE
VGL
RE2
Figure 20. Alternative Gate Voltage Shaping Circuit Configuration
In this circuit, resistors RE1 and RE2 define both the rate of change of gate voltage decay and the minimum gate
voltage VMIN. Using the Thevenin equivalent, the operating parameters of Figure 20 are easily expressed as
follows:
RE2
VMIN = VVG H1
RE1 + R E2
R RE2
RE = E1
RE1 + RE2 (1)
FLICKER CLOCKS
The gate voltage shaping control logic in the TPS65192 allows the device to be used with one, two or three
flicker clock signals, according to the application requirements.
In 6-phase applications where one signal controls gate voltage shaping for six CLK channels, the flicker clock
should be connected to FLK1 and the unused pins FLK2 and FLK3 connected to GND.

TPS65192
In 6-phase applications where three signals control gate voltage shaping for six CLK channels, the flicker clock
for channels 1 and 4 should be connected to FLK1, the flicker clock for channels 2 and 5 connected to FLK2,
and the flicker clock for channels 3 and 6 connected to FLK3.
In 4-phase applications where two signals control gate voltage shaping for four CLK channels, the flicker clock
for phases 1 and 3 should be connected to FLK1, the flicker clock for phases 2 and 4 connected to FLK2, and
the unused pin FLK3 connected to GND. The unused pins IN 3 and IN6 should be connected to VLOGIC.
Alternatively, IN3 can be connected to IN2 and IN6 connected to IN5; this arrangement can simplify PCB layout.
Typical schematics for each of the above cases are included in the Applications section of this data sheet.
Gate voltage shaping is started by the falling edge of the FLK signal(s), which must occur during a valid part of
the clock waveform. For 6-phase systems, this means the last 60 of the clock waveform; for 4-phase systems,
this means the last 90 of the clock waveform (see Figure 21 and Figure 22). Falling edges of the FLK signal(s)
occurring outside the valid part of the clock waveform are ignored. The rising edge of the FLK signal(s) has no
effect, regardless of when it occurs.
Note that gate voltage shaping is disabled when the voltage applied to the VSENSE pin is less than VREF.
IN1
IN2
IN3
IN4
IN5
IN6
Figure 21. FLK Falling Edge Validity, 6-Phase Applications
IN1
IN2
IN3
IN4
IN5
IN6
Figure 22. FLK Falling Edge Validity, 4-Phase Applications

TPS65192
LEVEL SHIFTERS WITHOUT GATE VOLTAGE SHAPING

Channels 7 through 9 do not support gate voltage shaping and are controlled only by the logic level applied to
their INX pin. Figure 23 contains a block diagram of a channel that does not support gate voltage shaping.
VGH1
Q1
From Timing Channel
INx Control OUTx To LCD Panel
Controller
Q2
VGL
Figure 23. Block Diagram of Level Shifter Without Gate Voltage Shaping
PANEL DISCHARGE
The TPS65192 contains a function for discharging the display panel during power-down. The discharge function
comprises a comparator and a level shifter (see Figure 24). During normal operation, the voltage applied to the
VSENSE pin is greater than VREF, the output of the level shifter is low, and the DISCHARGE signal is at VGL.
During power-down, when the voltage applied to the VSENSE pin falls below VREF, the level shifter output goes
high and the DISCHARGE signal tracks VGH1 as it discharges (see Figure 16 and Figure 17). Note that gate
voltage shaping is disabled when the voltage applied to the VSENSE pin is less than VREF.
Figure 24. Panel Discharge Function Block Diagram
Suitable values for resistors R1 and R2 in Figure 24 can be calculated as follows:

V V
R1 = R2 X - 1 = R 2 X - 1
VREF 1.5 V (2)
Where Vx is the voltage used to activate/deactivate the discharge function.
For most applications, a value between 1k and 10k for R2 can be used (R1 depends on the value of R2 and
the value of Vx).

TPS65192
APPLICATION INFORMATION
Power Supply Decoupling

For proper performance, it is recommended that each power supply rail be decoupled with high quality ceramic
decoupling capacitors placed as close to the IC supply pins as possible. The exact values used should be
optimized for each application, but a parallel combination of 10F and 100nF is a good place to start.
PCB LAYOUT
The output stages of the TPS65192 are capable of sinking and sourcing high peak currents greater than
500mA in typical applications and care must be taken during PCB layout to ensure that this performance can
be achieved in practice. In particular, the high rates of change of current occurring at the rising and falling edges
of each output require stray inductance to be minimized. This is most easily achieved by routing the output
signals using short, wide PCB tracks (as far as this is possible) and using a low impedance ground plane on the
other side of the board to conduct return currents. Tracks between the decoupling capacitors and the
corresponding power supply pins should also be kept short and wide as possible.
PCB layout must also be adequate from a thermal as well as electrical point of view. The TPS65192 is supplied
in a 28-pin QFN package designed to eliminate the need for heat sinks to dissipate the power generated in the
IC. The package, shown in Figure 25, is designed so that the lead-frame die pad is exposed on the bottom of the
IC, thereby providing an extremely low thermal resistance path between the die and the exterior of the package
(RJC).
Figure 25. Section View of a QFN Package
Copper areas in and on a PCB act as heat sinks for the QFN device; however, signal routing typically restricts
access to the power pad on the top layer of the PCB. In typical applications, therefore, the main copper area
used to conduct heat away from the IC is on the bottom layer.
TI recommends placing thermal vias in the solder mask defined thermal pad to transfer heat from the top layer of
the PCB to the inner or bottom layer used for heat sinking. The recommended via diameter is 0.3mm or less, and
via spacing 1mm (see Figure 26). For the 5 5 mm QFN package used for the TPS65192, five thermal vias are
typically used.

TPS65192
Figure 26. Recommended Thermal Via Spacing
The thermal vias should make their connection to the bottom (or internal) copper plane with a complete
connection around the entire circumference of the plated through hole, and a ring of exposed copper (0.05mm
wide) around the vias at the bottom of the copper plane. It is not recommended to cover the vias with solder
mask as this can cause excessive voiding, and nor is it recommended to use a thermal relief web or spoke
connection as this impedes the conduction path to the other layers (see Figure 27).
Figure 27. Thermal Via Connection at the Bottom Layer
In any design, the copper areas used as heat sinks should be made as large as possible.
The power pad of the TPS65192 is electrically connected to VGL and therefore must not be connected to
the PCBs ground plane.
For more detailed information concerning the thermal performance of QFN packages and recommendations
about how to mount the ICs on a PCB, refer to the following application reports:
SLOA122 QFN Layout Guidelines

SLUA271A QFN/SON PCB Attachment

TPS65192
APPLICATION CIRCUITS
+27V +27V
10 F 10 F
100 nF 100 nF
VGH1 VGH2
CLK1 IN1 OUT1 CLK1

CLK2 IN2 OUT2 CLK2
CLK3 IN3 OUT3 CLK3
CLK4 IN4 OUT4 CLK4
CLK5 IN5 OUT5 CLK5
From T-CON CLK6 IN6 OUT6 CLK6
To Panel
START IN7 OUT7 START
ODD IN8 OUT8 ODD
EVEN IN9 OUT9 EVEN
FLK FLK1
FLK2
FLK3
100 k
VIN VSENSE DISCHARGE DISCHARGE
RE
20 k
GND VGL
1 k
100 nF
10 F
-7 V
Figure 28. Typical 6-Phase HD TV Application with One Flicker Clock

TPS65192
+27 V +27 V
10 F 10 F
100 nF 100 nF
VGH1 VGH2
CLK1 IN1 OUT1 CLK1

CLK2 IN2 OUT2 CLK2
CLK3 IN3 OUT3 CLK3
CLK4 IN4 OUT4 CLK4
CLK5 IN5 OUT5 CLK5
CLK6 IN6 OUT6 CLK6
From T-CON START IN7 OUT7 START
To Panel
ODD IN8 OUT8 ODD
EVEN IN9 OUT9 EVEN
FLK1 FLK1
FLK2 FLK2
FLK3 FLK3
100 k
RE
20 k
GND VGL
1 k
100 nF
10 F
-7V
Figure 29. Typical 6-Phase F-HD TV Application with Three Flicker Clocks

TPS65192
+27 V +27 V
10 F 10 F
100 nF 100 nF
VGH1 VGH2
CLK1 IN1 OUT1 CLK1

CLK2 IN2 OUT2 CLK2
VLOGIC IN3 OUT3
CLK3 IN4 OUT4 CLK3
CLK4 IN5 OUT5 CLK4
From T-CON IN6 OUT6

START IN7 OUT7 START
To Panel
ODD IN8 OUT8 ODD
EVEN IN9 OUT9 EVEN
FLK1 FLK1
FLK2 FLK2
FLK3
100 k
RE
20 k
GND VGL
1 k
100 nF
10 F
-7 V
Figure 30. Typical 4-Phase Monitor Application with Two Flicker Clocks

PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Top-Side Markings Samples
(1) Drawing Qty (2) (3) (4)
TPS65192RHDR ACTIVE VQFN RHD 28 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
& no Sb/Br) 65192
TPS65192RHDT PREVIEW VQFN RHD 28 TBD Call TI Call TI -40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65192RHDR VQFN RHD 28 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
TPS65192RHDR VQFN RHD 28 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Aug-2014
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65192RHDR VQFN RHD 28 3000 367.0 367.0 35.0
TPS65192RHDR VQFN RHD 28 3000 367.0 367.0 35.0
Pack Materials-Page 2
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www.ti.com ....................................................................................................................................................................................................... SLVS962 JULY 2009

28-Pin 55 mm QFN Package IN4 OUT4

for use in LCD display applications such as TVs and

ORDERING INFORMATION (1)

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

2 Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated

Product Folder Link(s): TPS65192

Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback 3

4 Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated

Product Folder Link(s): TPS65192

PIN FUNCTIONS (continued)

Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback 5

OUTPUT RISE TIME OUTPUT FALL TIME

RISE TIME = 317 ns FALL TIME = 248 ns

200 ns/div 200 ns/div

FALL TIME = 562 ns

500 ns/div 500 ns/div

6 Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated

Product Folder Link(s): TPS65192

OUTPUT RISE TIME OUTPUT FALL TIME

RISE TIME = 3 ns FALL TIME = 3 ns

Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback 7

OUTPUT FALL TIME PROPAGATION DELAY FALLING

10 ns/div 100 ns/div

8 Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated

Product Folder Link(s): TPS65192

PROPAGATION DELAY FALLING DISCHARGE DURING POWER-UP

OF VFLK AND 90% OF VOUT .

OUTPUT VOLTAGE DROP (HIGH) vs OUTPUT CURRENT

Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback 9

OUTPUT VOLTAGE DROP (LOW) vs OUTPUT CURRENT

Output Voltage Drop V

Figure 18. Level Shifter Channel With Gate Voltage Shaping

10 Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated

Product Folder Link(s): TPS65192

Figure 19. Gate Voltage Shaping Timing Diagram

Figure 20. Alternative Gate Voltage Shaping Circuit Configuration

Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback 11

Figure 21. FLK Falling Edge Validity, 6-Phase Applications

Figure 22. FLK Falling Edge Validity, 4-Phase Applications

12 Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated

Product Folder Link(s): TPS65192

LEVEL SHIFTERS WITHOUT GATE VOLTAGE SHAPING

Figure 24. Panel Discharge Function Block Diagram

Suitable values for resistors R1 and R2 in Figure 24 can be calculated as follows:

Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback 13

Power Supply Decoupling

Figure 25. Section View of a QFN Package

14 Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated

Product Folder Link(s): TPS65192

Figure 26. Recommended Thermal Via Spacing

Figure 27. Thermal Via Connection at the Bottom Layer

SLOA122 QFN Layout Guidelines

Copyright 2009, Texas Instruments Incorporated Submit Documentation Feedback 15

CLK1 IN1 OUT1 CLK1

Figure 28. Typical 6-Phase HD TV Application with One Flicker Clock