L-EDIT tutorial
(Layout Editor)
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Introduction
L-Edit is an Integrated Circuit Layout
Tool used to draw the two dimensional
geometry of the masks or layers to
fabricate an integrated circuit.
Different layers are represented by
by different colors and patterns.
Manufacturing constraints can be defined
in L-Edit as design rules.
L-Edit files are saved as file_name.tdb
(Tanner Database).
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L-Edit Modules
L-Edit: The layout editor.
L-Edit/DRC: The Design Rule Checker.
L-Edit /Extract: The layout extractor to
SPICE.
L-Edit /SPR: an automatic standard cell.
placement and routing package.
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L-Edit Window
L-Edit v8.30
File and cell name
Location
Menu Bar
Toolbars
Layer Palette
Drawing
windows
Mouse
Buttons
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L-Edit Toolbars
File>
Print
File>
Open
File>
Copy
Edit>
Edit-in
Place> Edit>
Push Into Find
File>
Undo
File>
File>
File>
File>
File>
New
Save
Cut
Paste
Redo
Draw>
Rotate
Edit>
Duplicate
Draw>
Draw>
Flip>
Slice>
Draw>
Vertical Horizontal Merge
Draw>
view>
Zoom>
Mouse
view>
Edit>
Hierarchy level
View>
Cell
Insides>
Edit-in
Place> Browser
Toggle Pop Out
insides
Draw>
Ungroup
Draw>
Move
By
Help>
LCell>
Edit
Copy
User Guid
Tool>
DRC Box
Edit>
Find
Cell>
Tool>
Open
Cross
Section
Tools>
Edit>
Find Clear Error
Previous Layers
Draw>
Draw>
Draw>
Edit>
Tool>
DRC
Edit>
View>
Tool>
Flip>
Nibble
Horizontal
Slice>
Vertical
Group
Edit
Object
DRC
Setup
Find
Next
Goto
Extract
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L-Edit Toolbars
Selection
tool
Polygon Polygon
(90 deg.) (all-angle)
Rectangular Polygon
Box
(45deg.)
Wire
(35 deg.)
Wire
Wire
Wire Width
Circle
Ruler
Ruler
(90 deg.) (all angle)
Torus
Arc
(90 deg.) (all-angle)
Port
Ruler
(45 deg.)
Layer Palette
Selected
Layer name
Layer Palette
Layer Palette
scrollbar
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Instance
LOGO
Things to know
Lambda Definition ((
L: The channel length of the MOSFET, i.e, half
the size of technology used.
Exp) L=180nm
1Lambda=90nm
Note: You must set the length of the square
to represent One lambda or one Locator Unit.
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Design Parameters Setups
B) Technology
From: Menu> Setup> Design> Technology
Create a name for
your fabrication
process
Relationship between L-Edit
internal units.
one internal unit is1nm
(1/1000lambda)
Technology
unit
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Design Parameters Setups
B) Grid
From: Menu> Setup> Design> Grid
These are just the
dots shown on the
screen.
This is where your
mouse will snap to.
To set
One locator Unit=lambda
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Design Parameters Setups
C) Layers Setup
From: Setup> Layers
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Design Parameters Setups
C) Editing Objects
From: Edit> Edit Object (Ctrl+E)
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Layout Example
Draw the layout of a CMOS inverter given the following:
L= 0.5m, Wn= 1.0m, and Wp= 2.5m.
VDD
Pmos
L=0.5 m
Wp=2.5 m
Vin
Vout
Nmos
L=0.5 m
Wn
p=1.0 m
VSS
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Example
Create new Layout file
File > New.
In the following open window, Browse and choose mamin08.tdb in
Copy TDB setup from file area. It usually locates in setup directory.
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Example
Design Setup
As mentioned before from: From Menu> Setup> Design >
Establishing
l =0.25mm,
therefore
2l =0.5mm.
Click OK: Now the technology is setup!
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Example
Pmos
Choose N-Well in the left palette and draw a box
In the N-Well area, draw P-Select (for D&S) and
N-Select (for Body). Notice that the size and position
should obey Design Rule, which can be found at:
http://www.mosis.com/files/scmos/scmos.pdf.
N-Select
P-Select
2
It is a good idea to run DRC
at each stage of your design
so that you can fix any error
along the way
10
Draw Active.
Draw Poly (Gate).
N-Well
Active
Poly
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Example
Nmos
Do not need to draw P-Well (Why?).
Draw N-Select and P-Select.
Draw Active.
Draw Poly.
P-Select
N-Select
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Example
Draw VDD and GND Lines.
VDD
GND
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Example
Connect Poly of PMOS and NMOS.
Connect source of PMOS to VDD
by Metal1.
Connect source of NMOS to GND
by Metal 1.
Connect Drain of PMOS and NMOS
by Metal 1.
Add an input connect between
Metal1 and Poly.
Label the INPUT, OUTPUT, VDD
and GND.
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Example
L-Edit Design Rule Check
From Tools> DRC (or the DRC box in the toolbar)
Run DRC for the total layout.
Fix the errors listed.
Once there is no DRC error
shown, the layout is ready to
extracted.
be
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Example
L-Edit can be used to generate SPICE-compatible circuit file listings using
the Extract option in the setup window of the menu bar menu bar.
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Example
L-Edit Extractor
General
Enter the name of the
extractor definition file
Enter the name of the
SPICE output file.
name.cir for PSPICE
name.sp for HSPICE
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Example
L-Edit Extractor
Output
Select :
Comments: Write
Nodes Names.
Write Nodes as: Integers
Write Node
parasitic
Capacitance.
Place device labels on
layer: Metal1.
Then Click Run
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Example
L-Edit Extractor
Click: Ignore All
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Example
The generated SPICE file
* NODE NAME ALIASES
*
1 = VIN (-7.5,-6.5)
*
2 = VOUT (27.5,-6)
*
3 = GND (-7.5,-31)
*
4 = VDD (-6,30)
The Nodes corresponding integers
The generated parasitic capacitors
Cpar1 2 0 C=1.72875E-015
Cpar2 3 0 C=1.0445E-015
Cpar3 4 0 C=1.69675E-015
M2 2 1 4 4 PMOS L=5E-007 W=2.5E-006AD=4.375E-012
+ PD=8.5E-006AS=4.375E-012 PS=8.5E-006
M1 2 1 3 3 NMOS L=5E-007 W=1E-006 AD=2.5E-012
+ PD=6.5E-006AS=2.5E-012 PS=6.5E-006
* Total Nodes: 4
* Total Elements: 5
* Extract Elapsed Time: 0 seconds
.END
The generated two MOSFETs
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