PES University

(Established Under Karnataka Act 16 of 2013)

Department of Electronics and Communication Engineering

Digital VLSI Design Lab

EXPERIMENT- 3
Designing the layout for CMOS inverter

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 EXPERIMENT-3
Layout for CMOS Inverter
Design the layout for a CMOS inverter and determine:
Noise Margins NMH and NML,
Rise and fall time and
Power results
For post layout simulation. Also compare schematic and layout simulation results in terms of
above parameters and waveforms.

Theory:
The representation of an integrated circuit in terms of planar geometric shapes that
correspond to the patterns of metal, oxide, or semiconductor layers that make up the
components of the integrated circuit is known as integrated circuit layout. When using a
standard process, where the interaction of the many chemical, thermal, and photographic
variables is known and carefully controlled, the behavior of the final integrated circuit
depends largely on the positions and interconnections of the geometric shapes. Using a
computer-aided layout tool, the layout engineer places and connects all the components that
make up the chip such that they meet certain criteria—typically: performance, size, density,
and manufacturability. The generated layout must pass a series of checks in a process known
as physical verification. The most common checks in this verification process are:
 design rule checking (DRC)
 layout versus schematic (LVS)
 parasitic extraction
When all verification is complete, layout post processing is applied where the data is also
translated into an industry-standard format, typically GDSII, and sent to a semiconductor
foundry. The milestone completion of the layout process of sending this data to the foundry
is now colloquially called "tapeout". The foundry converts the data into mask data and uses
it to generate the photomasks used in a photolithographic process of semiconductor device
fabrication.

Note: Make sure to keep your final CMOS schematic ready with all the required simulation
results, before beginning layout design.

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CMOS Inverter Schematic:

Procedure:
1. Open your final CMOS schematic on S-edit and keep all the simulation results and
netlist ready. DO NOT CLOSE S-EDIT UNTIL THE LAYOUT IS FULLY COMPLETE.
2. Export your final schematic from S-edit.

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 Carefully make the following changes in the window that appears. Specify the path
and make sure your file has the .sp extension. Property name is SDL SPICE. Finally click
on ‘Export’. You will now see a .sp file created in the specified folder.

3. Open another terminal and type in the following: csh -> source mentor.cshrc -> ledit
This opens the L-edit tool.
Next create a new design.

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4. Select OpenAccess and specify Name and Path for your design.
Since this is a schematic driven layout, we require the same libraries used in the
schematic for the layout as well. Therefore, choose OpenAccess referenced libraries
for Technology reference. Click OK.

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5. The libraries used, show up in the window. Select Generic_250nm_Devices and click
on ‘Include’ and then OK.

6. Create a new cell to design your layout. THE CELL NAME SHOULD BE THE SAME
NAME AS THAT OF YOUR FINAL SCHEMATIC from S-EDIT.

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7. Activate SDL Navigator. Make sure the following items are checked.

8. Load your netlist.

Browse and select your .sp file.

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9. Zoom in to see your transistors and ports.

10. As the topmost layer is the metal layer, make all the ports as metal. Select all ports
and do ‘ctrl+E’. Select Metal1:drawing.

The ports turn blue indicating metal layer.

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11. Place the PMOS above NMOS. Select both the transistors using shift key. Select
‘AlignHorizontalCenter’ to align the transistors. This is done to achieve precise
connections.
(if you want to align transistors placed side by side, use ‘AlignVerticalCenter’)

12. Select only the required layers from layer palatte, by choosing the following.

13. Connect the ploy of both the transistors. First select ‘Box’ then select ‘Poly’ from the
palatte.

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 Make sure the width is maintained. In case any changes are to be made, right click on
the poly. Press ‘ctrl’ and right click on the side to be changed. Use the scroll wheel and
drag the poly to make the necessary change.

14. Connect the metal input port and poly using the ‘contact poly via’.
Select ‘Pace Via’ and choose ‘Cnt_Poly’, which is a 4x4 contact cut. Place the via in a
way that it superimposes the poly layer. Next place the input port in the 2x2 white cut.

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15. Draw Vdd (above PMOS) and Gnd (below NMOS) lines. First select ‘box’ and then
select ‘Metal1:drawing’ from the layer palette.

Connect the body and source of the PMOS to the Vdd line and also place the Vdd port
onto this line.

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Next connect the body and source of the NMOS to the Gnd line and also place the Gnd
port onto this line.

Now connect the drain of both the transistors and place the output port onto this
connection.

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 The final layout design will look something like this:

16. Now setup the calibre environment to run the required checks.
Type in the following details:

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 17. The first check is DRC (Design Rule Check).

Note: The parameters in red require inputs/required files. And the ones in green
are already set by default.
Cancel all the ‘Load Runset File’ that appears for each check.

Make sure ‘Export from layout viewer’ is checked. Next click on Rules and select the respective
.cal file. The path is as follows:

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Click on Run DRC. The following window shows up and displays if errors are present.

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Do this to identify the error:

Go to your layout window and correct the highlighted area. Save this and ‘Run DRC’ again.
Select ‘Overwrite’ in the pop-up window.

The following window shows up with nothing listed, to show the design is error free.

18. Next check is LVS (Layout vs Schematic).

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Under netlist, make sure to check ‘Export from schematic viewer’

Next ‘Run LVS’. The following report is generated.

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 19. Next check is PEX (Parasitic Extraction).

Next, under ‘Setup’ choose ‘Set Environment..’

Make the following changes:

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For ‘Runset Value’ add the path as shown:

Now, ‘Run PEX’. A netlist is generated.

Next, ‘Start RVE’. (result viewing environment). R & C details will be displayed.

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You can see a specific parasitic in the layout by doing:

20. Copy all the transistor details from the PEX netlist.

Now open your schematic netlist and paste this information under ***Subcircuits***

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Now to obtain results from the layout, rename the nodes carefully:
Replace the layout node names with the schematic node names.

schematic node names:

layout node names:

Repeat the same for all the transistors.

Now comment the schematic transistor information by using * at the start of each line.

Save this netlist and run simulation again. The results obtained now are because of the layout.

Observe and compare the Transient and DC waveforms obtained from the schematic and
the layout.

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Note down the following Observations made:

Parameters Schematic Layout

Noise Margin High

Noise Margin Low

Input Rise Time

Output Rise Time

Input Fall Time

Output Fall Time

Power results (VV1 & VV2)

Student Name:

Student SRN:
Faculty Signature with date:

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