Guide to cadence IC Design Software

(Virtuoso Schematic/Layout, Analog Environment, and Assura DRC/LVS)

Department of Electrical and Computer Engineering
Fall 2007
(last revised 10/17/07)
Summary

This is a tutorial on how to design, simulate, layout, run DRC & LVS, and generate fabrication files for an
Integrated Circuit (IC) using the cadence Virtuoso design platform.

This tutorial will walk through an example CMOS inverter design from start to finish in order to explain
each of the steps in the design.

Cadence runs in on Linux environment. Linux workstations are available in Cobleigh Hall, Rm 620.

The following lists the steps that will be covered in this tutorial:

Step 1: Launching Cadence

Step 2: Creating a Library
Step 3: Creating a Schematic and Symbol for the Inverter
Step 4: Creating a Simulation Test Bench for the Inverter
Step 5: Running a SPICE simulation (DC and Transient)
Step 6: Creating a Layout
Step 7: Running DRC
Step 8: Running LVS
Step 9: Generating fabrication files to create masks (not available yet)

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Step 1: Launching Cadence

1) Log into the Linux workstations in Cobleigh 620 using the KDE desktop option.

a) If you are enrolled in EE414 (Fall 2007)

- your username is: “first initial” followed by “last name”

- your password is: your banner ID without the “-“

NOTE 1: Don’t change your password, it will only change on the workstation
that you are logged into. You don’t have permission to change
your password on the server. Also don’t change your shell, Cadence
won’t run in any other shell than the default.

NOTE 2: The computers in COBH 620 are dual boot. They automatically
come up in SuSE Linux. If they are booted into windows, you will
need to shutdown and restart to bring up Linux.

When Linux boots, it will automatically mount your home

directory. Your home directory exists on a server called
ece-fileserver. The Linux workstation tries to mount this drive
once every minute. If you boot up and then login before this
drive has been mounted, you will not see any of your files and
not be able to do anything.

The solution is to wait a couple of minutes after booting up and

allow the drive to automatically mount before logging in. This is
only an issue if you have to reboot. If the workstations are already
booted into Linux, then you don’t need to worry about it.

2) Start a terminal window

a) On the taskbar at the bottom of the screen, you’ll see an icon of a monitor with a
little shell next to it. Click on this to bring up a terminal window.

b) The terminal should be brought up in your home directory. Test to make sure
everything is OK by doing a:

>> whoami (it should return your username)

>> pwd (it should return your home directory /home/username)

3) Change into your working directory

a) In the terminal window, change to “work” by typing

>> cd work

NOTE 1: In this directory, you will see a file called “cds.lib”. This
is the file that sets up the Cadence licenses and the toolkit we’ll be using.

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 4) Launch Cadence

a) You will need to be in your “work” directory in order to start Cadence. You can
return to your home directory no matter where you are by typing:

>> cd

Now change to your “work” directory by typing:

>> cd work

b) Start cadence by typing:

>> icfb &

NOTE 1: the “&” means that the program will run in the background. It is
important that when you are done with cadence, you need to close the program
using the “File-Exit”, “Window-Close”, etc… If you click on the “X” button of the
terminal, the program will still be running in the background and your files will be
locked the next type you login.

NOTE 2: If you login and run cadence and your files are locked, you need to find
and delete any *.lck files that exist.

Step 2: Creating a Library

1) Make a directory to store your Cadence Library (only do this once)

a) You will be working with Libraries in cadence. Cadence organizes

all of its files using libraries. To keep things organized, you will create a folder
under work called “Cadence_Libraries”. In this directory, we will create a
library for EE414. You create your libraries in Cadence. We are going to
manually create a Directory using the terminal window called
“Cadence_Libraries”. Then in Cadence, we will create the actual libraries. If you
ever want to create another library for a senior design or research project, you
would do it in this folder:

Make a directory for your library by typing:

>> mkdir Cadence_Libraries

b) Check that the directory was successfully created by typing:

>> ls –al

You should see your recently created library

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2) Create a Library in Cadence

a) We are going to create a Library called “EE414_Library”. This library will

hold all of our projects for the semester. We will do this in the Cadence
Library Manager window. When you launch Cadence, the Library Manager is the
first window that comes up.

First check that the software has come up correctly with the necessary design
kits. You should see the following Libraries in the “Library” section of the
Library Manager.

- ami500hxkx
- ami500hxtx

These are the libraries for the AMI 0.5um CMOS process we will be using. If you
do NOT see these libraries, something is wrong and you need to exit cadence. The
first thing to check is that you launched Cadence in your work directory, which
contained the cds.lib file. The second thing to check is that your home drive was
successfully mounted upon login. If it was mounted correctly, you should
automatically see a work directory in your home directory.

b) Now create a library called “EE414_Library” by using the pull-down menus

in the Library Manager window:

File – New – Library

In the New Library window, enter the following:

Name: EE414_Library
Directory: Browse to your “Cadence_Libraries” directory
Click “OK”

In the Technology File for New Library window that pops up, we want to
attach the AMI 0.5um technology file to our library:

Select “Attached to an existing techfile

Click “OK”

In the Attach Design Library to Technology File window:

Select “ami500hxkx” from the pull-down box.

Click “OK

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Step 3: Creating a Schematic and Symbol for the Inverter

1) Create a cell called INV

a) When we create an item in Cadence, it is called a Cell. A cell can contain various
views such as schematics, symbols, spectre simulation info, Verilog, layout, etc…

We will begin by creating a cell for our inverter called INV that will have a
schematic and a symbol. In order to simulate our INV cell, we’ll create another
cell called test_INV. The test_INV cell will contain a schematic in which we will
instantiate our INV cell.

In the Library Manager window, use the pull-down menus to create a new cell:

File – New – Cell View

In the Create New File window, select:

Library Name: EE414_Library (this is the library the cell will

be part of)
Cell Name: INV (our unique name)
View Name: Schematic (Default)
Tool: Composer-Schematic
Library Path file: verify this is set to: /home/username/work/cds.lib

This will bring up the Virtuoso Schematic Editing window.

2) Enter the schematic for the inverter

a) Enter an NMOS transistor

- on the left hand side of the schematic window, you’ll see some icons. Click on
the “Instance” icon. You can also use the [i] button.

- this brings up the Add Instance window” In this window, select the following:

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 Library: - Browse to the ami500hxtx library
- select the cell called “n”
- select the view called “symbol” (click on it once)

- you will see an NMOS symbol now connected to your mouse in the schematic
window. Click once to drop the symbol in the schematic. Hit the [ESC] button
to exit the “add instance” command mode.

b) Modify the properties for the NMOS transistor

- click on the NMOS symbol

- bring up its properties dialog by either:

- clicking on the Property icon on the left

- hitting the [q] button

- change the Width to 5u (Note the default units are um, so just enter 5)
- Click “OK”

c) Enter a PMOS transistor

- on the left hand side of the schematic window, click on the “Instance” icon.

- in the Add Instance window”, select the following:

Library: - Browse to the ami500hxtx library

- select the cell called “p”
- select the view called “symbol” (click on it once)

- you will see a PMOS symbol now connected to your mouse in the schematic
window. Click once to drop the symbol in the schematic. Hit the [ESC] button
to exit the “add instance” command mode.

d) Modify the properties for the PMOS transistor

- click on the PMOS symbol

- bring up its properties dialog by either:

- clicking on the Property icon on the left (or hit [q])

- change the Width to 10u (Note the default units are um, so just enter 10)
- Click “OK”

e) Add I/O pins

- this circuit will ultimately have a symbol that will be instantiated in a higher
level design. We need to add I/O pins to show the inputs and outputs.

- on the left hand side of the schematic window, click on the “Pin” icon to add an
I/O pin
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 - when you do this, an Add Pin dialog will come up. Fill in the following:

Pin Names: IN
Direction: input

- Now when you drag your mouse into the schematic window, you’ll see a pin
attached to it. While you are dragging the pin around, you can go back into the
Add Pin dialog and rotate the pin to your desired orientation by clicking on
“Rotate”. Click once in the schematic window to add your pin.

- Now that the pin has been placed, you’ll notice that the Add Pin dialog is still
open. You can use this to add the remaining pins. Add the 3 remaining pins to
your inverter as follows (rotate them as you place them to make them fit
properly):

Pin Names: OUT

Direction: output

Pin Names: VDD

Direction: inputOutput

Pin Names: VSS

Direction: inputOutput

- to end the Add Pin command, hit the [ESC] button and the dialog will disappear.

f) Re-Position your instances

- before you wire up your circuit, you want to move around your NMOS, PMOS,
and pins so they are in a good location.

- select an instance by clicking on it once.

- you can move the selected by doing either:

- Edit-Move
- clicking the [m] button

- when in the move command, the instance will be attached to your mouse. To drop
the instance, click once.

- to end the move command, click the [ESC] button.

g) Add wires

- now you will wire up the circuit. On the right hand side of the schematic window
click on the Wire (narrow) icon.

- you are now in add wire mode. If you click once, you will start adding a wire.
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 Cadence will automatically try to create the shortest path between pins. However,
if you want to manually add a corner, you can single-click. You can end the
add wire mode by clicking once on an instance pin or double clicking on the same
location.

- connect up the inverter input, output, VDD, VSS, and body connections. If you
make a mistake, you can get out of the add wire mode by clicking [ESC]. Then
you can highlight a wire and click [Delete] to remove the wire.

h) Check and Save

- in the Schematic window pull-down, do the following:

Design – Check and Save

- if you have any warnings or errors, you will get a pop up window telling you how
many. To see the details of the warnings and errors, look in the Log window.

- leave the schematic window OPEN in order to create a symbol.

3) Create a symbol for the inverter

a) You will now create a symbol view for your INV cell

- in the schematic window, use the pull-downs to perform:

Design – Create Cellview – From Cellview

This will automatically create a symbol for your schematic with ports
associated with the pins that you’ve added.

- In the Cellview From Cellview window ensure the following settings:

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 (NOTE: these should default to the correct settings)

Library Name: EE414_Library

Cell Name: INV
From View Name: schematic
To View Name: symbol
Tool / Data Type: Composer-Symbol

b) Position the pins of your symbol

- in the Symbol Generation Options dialog, you will tell the tool where to locate
your pins. Modify your pins as follows:

Left Pins: In
Right Pins: Out
Top Pins: VDD
Bottom Pins: VSS

Click “OK”

- you should now see a Virtuoso Symbol Editing window pop up that has your
newly generated symbol. You will see your pin names in addition to various
parameters that can be used to pass in information to your lower-level circuit.
For now, leave these as they are. When the parameters are not used, they
will not show up when you instantiate this symbol.

- Using the pull-down menus, perform:

Design – Check and Save

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c) Modify the symbol

- the default shape for the symbol is a rectangle. For this inverter, you should
modify the symbol shape to reflect the traditional “triangle with a bubble” so
that this circuit is easily recognizable.

- You can select and delete the default square shape in the symbol

- You can add a triangle shape using the pull-down menus:

Add – Shape – Polygon

- You can add a circle using the pull-down menus:

Add – Shape – Circle

- You can move shapes, properties, and pins around by first selecting, and
then clicking [m] to get into the move mode. To get out of the move mode,
click the [ESC] button.

- you can also rotate items by selecting them and clicking [r].

- once you have created an accurate symbol for your circuit, perform:

Design – Check and Save

- clean up any warnings or errors that you have.

- close the symbol editor by performing:

Window – Close

- close your schematic window by performing

Window - Close

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Step 4: Creating a Simulation Test Bench for the Inverter

1) Create a cell called test_INV

a) Now we will create a new cell which will consist of a schematic view.
This will contain an instantiation of our INV cell symbol. It will also
contain voltage sources, power supplies, and a load capacitance.

It is ALWAYS a good idea to test each lower-level hierarchical block

separately before incorporating it into a higher level design. As such, your
library will contain many levels of circuit blocks and test benches.

To keep this straight, we will use a prefix of ”test_<cell name>” to easily

identify the cells in our library which are test benches. A test bench
will only contain a schematic view while an actual circuit that will be
fabricated will contain many views such as schematic, symbol, layout,
Verilog, VHDL, aVerilog, etc…

- In Library Manager, use the pull-downs to perform:

File – New – Cell View

- In the Create New File window, fill in the following:

Library Name: EE414_Library

Cell Name: test_INV
View Name: schematic
Tool: Composer-Schematic

Click “OK”

- A new schematic window will pop up.

2) Enter the test bench schematic

a) Instantiate the inverter (INV)

- On the left hand side of the schematic window, click on the

Instance button (NOTE: you can also click the [i] button)

- In the Add Instance dialog, enter the following:

Library: Browse to your EE414_Library

While this browse window is open, select:

Library: EE414_Library
Cell: INV
View: symbol

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 - once you click on the view symbol, the inverter symbol for INV will
be attached to your mouse. You can click once to instantiate it in your
test bench schematic

- click the [ESC] button to exit the instance mode.

b) Enter a Voltage Source for VDD:

- For a test bench, we use ideal components for voltage sources, lumped
capacitors, etc… There is a library called analogLib that exists in
the Library Manager that contains all of these elements.

- Click on the Instance icon on the left hand side of the schematic window:
(or you can click [i]).

- In the Library Browser window, select the analogLib library.

- scroll through the Cells until you find vdc. Select the vdc cell, then select
the symbol view.

- once you click on symbol, the vdc instance will attach to your mouse in
the schematic window. Click once to instantiate vdc. Click [ESC] to end
the add instance mode.

- You can rotate the vdc instance by selecting it and clicking [r].

- You can move the vdc instance by selecting it and clicking [m]

- You can set the properties for vdc by selecting it and hitting [q]:

- Set the DC Voltage to 5

- You can also change the instance name to something
more descriptive if you wish
- Click “OK”

c) Enter a GND node:

- Again, use the instance command to bring up the Library Browser.

- Browse to the analogLib library.

- In the Cell column, scroll down to find gnd.

- Click on the symbol view to instantiate it in your test bench schematic.

- rotate and attach the GND symbol to the VDD supply that you entered
earlier.

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d) Enter the remaining instances of the test bench

- using the same process, enter the following items from analogLib:

- cap (used for a load capacitance, value=150fF)

- vdc (used for Vin in a DC simulation, set to 0v and
name the instance Vin_dc)

- vpulse (used for Vin in a transient simulation, set to:

voltage 1: 0
voltage 2: 5
rise time: 1ps
fall time: 1ps
pulse width: 5ns
period: 10ns

e) Position the instances in the schematic

- before wiring up the schematic, position all of the instances in a good

location around the INV. Note that we will be naming nets so leave
a lot of room to enter a net and give it a name (i.e., don’t put the instances
on top of each other)

- we are going to put the DC source for VIN in series with the PULSE
source. Put the vdc source below the vpulse source.

- you can copy an instance by selecting and hitting [c]

f) Wire up the instances

- use the Wire (narrow) icon on the left hand side of the schematic to
enter the wires for your schematic.

g) Name the wires

- on the left hand side of the schematic window, click on the Wire Name icon.

- this brings up the Add Wire Name dialog. You will enter a wire name
and then click on the wire in the schematic window to assign the name.
Enter the following wire names:

VIN, VOUT, VDD

Note that you can’t name the GND net as it is already named by connecting
it to the gnd instance.

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 h) Check and Save

Use the pull-down menus to perform:

Design – Check and Save

Keep the schematic window open for the next part.

Step 5: Running a SPICE Simulation

1) Setup the simulation

a) Open the Analog Design Environment

- In the schematic pull-down menus, perform:

Tools – Analog Environment

b) Choose the Spectre Simulator and the location of simulation files

- we will be using the Spectre simulator. This simulator generates

a large amount of temporary data that we don’t want to store on
ece-fileserver. If everybody in our class simulated at once and stored
the data on ece-fileserver we would fill its disks up very quickly.
Instead, we can direct the simulator to store the temporary information to
our local disk. On the machine you are logged into, there will be a directory
called /tmp. We will tell the simulator to put all of our results in a directory
called: /tmp/simulation

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 - In the Analog Design Environment window, use the pull-downs:

Setup – Simulator/Directory/Host

Simulator: spectre
Project Directory: /tmp/simulation

- Click “OK”

c) Setup the Model Path

- In the Analog Design Environment window, use the pull-downs:

Setup – AMI Set Model Path (defaults should be OK)

techLib: ami500hxkx
process corners: typ for all

- Click “OK”

d) Setup Temperature

- In the Analog Design Environment window, use the pull-downs:

Setup – Temperature (default should be OK)

Scale: Celsius
Degrees: 27

- Click “OK”

e) Setup DC Analysis

- Let’s first start with a DC simulation to plot the Voltage Transfer

Characteristics (VTC) of the inverter:

- In the Analog Design Environment window, use the pull-downs:

Analysis - Choose

Analysis: Check DC, uncheck all others

Sweep Variable: Check “Component Parameter”
Click on “Select Component”

No click on the Vin_dc instance

in the schematic:

In the Select Comp Param dialog that

comes up, highlight “dc” and
click “OK”
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 Sweep Range: Start = 0
Stop = 5

Sweep Type: Automatic

Click “OK”

f) Select Outputs to monitor

- In the Analog Design Environment window, use the pull-downs:

Outputs - Save All

Leave the Keep Options dialog defaults, click “OK”

g) Run the DC Simulation

- In the Analog Design Environment window, click on the Green Stoplight:

- a window will pop up with the VTC

h) Print or Save the results

- in the plot window, use the pull-downs to perform:

File – Print

- Click on the “Print” button. This will print to the printer in COB 625.

- You can also perform a:

File – Save as Image

- this will give you a file that you can insert into your project report.

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i) Run a transient simulation

- Go back into the Analog Environment window:

- From the pull-down menus:

Analyses – Choose

- click the tran radio button

- enter a Stop Time of 20ns (you MUST put the “n” for nano)

- click the Green Stoplight to run the simulation

- a plot will come up showing 2 cycles of your 10ns period input. You
also will notice that the DC simulation still ran. This is handy when you are
altering the sizes of the inverter and monitoring Vth in addition to the delay.
If you don’t want to run the DC simulation anymore, you can click on the
“choose analysis” button in the analog environment window, select “dc”, then
uncheck the Enabled radio button at the bottom of the window. This will
disable the simulation but keep all of your setup information for the DC
analysis.

j) Save your session

- in addition to saving your schematics, you want to save your simulation

environment. Using the pull-down menus in the analog environment, perform:

Session – Save State

- give a descriptive name such as “test_INV_DC_and_TRAN”

- you can retrieve this state the next time you run cadence by performing:

Session – Load State

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Step 6: Creating a Layout for the Inverter

1) Create a layout Cell view for the inverter

a) In the Library Manager window, use the pull-down menus to create a new cell:

File – New – Cell View

- In the Create New File window, select:

Library Name: EE414_Library (this is the library of your cell)

Cell Name: INV

View Name: layout (this will updated when you choose

the tool)

Tool: Virtuoso (this is the name of the layout editor)

Library Path file: verify this is set to: /home/username/work/cds.lib

This will bring up the Virtuoso Layout Editing window and the layers menu.

2) Setup your display options

a) If you’d like, you can modify the grid and snap attributes

- use the Pull-down menu:

Options – Display Options

- Set the following: Minor Spacing = 0.1

Major Spacing =1
X Snap Spacing = 0.1
Y Snap Spacing = 0.1

3) Create the layout for the NMOS transistor

NOTE: our process assumes that we are using a p-type substrate.

a) Enter Active/Diffusion Region

- we use the DIF layer to accomplish two things. The first is to define the active
region for our NMOS transistor. The second is to define where the n+ implants
will occur.

- In the X-direction, we need the DIF rectangle to be large enough for the following
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(described from left-to-right)

- the source contact-to-active spacing (0.4um minimum)

- the source contact window (0.5um fixed)
- the source contact-to-poly spacing (0.4um minimum)
- the poly gate (0.6um minimum)
- the drain contact-to-poly spacing (0.4um minimum)
- the drain contact window (0.5um fixed)
- the drain contact-to-active spacing (0.4um minimum)

Total > 3.2um (+ margin)

- In the Y-direction, we make DIF the size of our desired W, which in this
example is 5um.

- in the Layer menu, click on DIF

- in the Layout window (you may have to click on it to make it active), start a
rectangle by:

- Create – Rectangle (or use the hotkey [r])

- draw a rectangle that is at least 3.4 x 5.

- resize if necessary. You can put your mouse over an edge and it will turn into
a dotted line. You can then click [s] to stretch the shape.

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b) Enter the polysilicon gate

- we use the POLY1 layer to enter the gate. We will make the gate rectangle
0.6um in the X-direction. You’ll need to overlap the POLY1 over the diffusion
region by at least 0.5um on each side. We’ll resize it later when we hook up
the PMOS.

- in the Layer menu, click on POLY1

- in the Layout window (you may have to click on it to make it active), start a
rectangle by:

- Create – Rectangle (or click the hotkey [r])

- put the rectangle directly in the middle of the DIF rectangle

c) Enter the Active Contacts

- we insert contacts using an automatic command in Cadence. As we insert the

contacts, we can tell the command how many and of what type.

- In the file pull-down menus, perform:

- Create – Contact

- a window will appear and a contact will snap to your mouse. Since our NMOS
is 5um wide, we can put more than 1 contact on each terminal. It is a good design
practice to put as many contacts as will fit.

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 - in the dialog window, set the number of rows to 4. Now click back
in the layout window and you’ll see 4 contacts attached to your mouse.

- in the dialog window, we also need to define what type of contact we are
inserting. Since this is an active region contact, we choose DIFCT in the
“contact type” pull-down.

- it is mandatory for the process that the size of the contacts be 0.5um x 0.5um.

- Click in the diffusion regions to place your source and drain contacts.

d) Enter the Body Contacts

- In the file pull-downs, perform:

Create – Contact

- again, select 4 rows of contacts. Since this is a Body contact for an NMOS, we
need to select PDIFCT. This will tell the tool that we need to implant a p+ region
beneath the contact to form an Ohmic contact to the p-type substrate.

- the minimum active-to-active spacing is 0.9um so the body contacts will need to
be at least this distance away from the DIF region.

- Click in the layout window to add the Body contacts.

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 NOTE: This is all we can do on the NMOS for now. We will move on to entering
the PMOS and then we’ll hook everything up.

It is a good idea to run DRC right now. Step 7 in this tutorial will walk you
through how to run the DRC check.

4) Create the layout for the PMOS transistor

NOTE: the process for the PMOS is similar to the NMOS. Remember that we need to
create an N-well for the PMOS substrate.

a) Enter N-well

- we create the N-well using a combination of 2 layers (TUB and NFIELD)

- key spacing’s for the N-well are:

- minimum N-well to N+ Active spacing = 1.5um

- minimum N-well width = 2.5um

- enter a rectangle using the TUB that is large enough to accommodate our PMOS
and still have at least 1.5um between the edges of active regions.

- create the exact same sized rectangle using NFIELD and place directly on top
of the TUB rectangle

NOTE: you can copy the TUB rectangle and then perform a [q] to change
its layer to NFIELD. This makes duplicating shapes very easy.

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b) Enter the PMOS Active Region

- this is accomplished using 3 layers (DIF, NPLS, and PPLS)

- first create a DIF region that has the same X-dimensions as your NMOS and a
Y-dimension of 10um (Wp=10um)

- now you will overlap this DIF region with both an NPLS and an PPLS rectangle..
The sizes of the NPLS and PPLS shapes must extend beyond the edges of the DIF
region by 0.3um. The combination of these three regions tells the tool that we are
going to create an Active region that is p+ doped in an N-well.

c) Enter the polysilicon Gate

- use POLY1 just as in the NMOS. The size should be 0.6um in the X-dimension
and in the Y-dimension it should overlap the DIF rectangle by 0.5um

d) Add the active contacts

- just as in the NMOS, we add the active contacts using the Create – Contact
pull-down. We again choose DIFCT as the type of contact. There should be room
to add 9 contacts to both the Drain and Source

e) Add the body contacts

- we now add the body contacts. Use the Create-Contact pull-down. However,
you will choose NDIFCT as the type of contact to indicate an n+ diffusion contact.

At this point, it is a good time to run DRC. We want to make sure the
transistors are correct prior to connecting them up.

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5) Connect the nodes of the inverter

a) Create the Input node using Polysilicon

- Use the POLY1 layer to connect the gates of the PMOS and NMOS in addition
to creating a region for a signal to enter the circuit from Metal1.

- Click on the POLY1 layer and then add a rectangle (or polygon) in the layout
to complete the connection

- Add a Poly-to-Metal1 using the pull-down menus in the layout window:

Create – Contact

- in the dialog window, select M1PLY as the contact type. This will allow
a single from Metal1 to change layers to POLY1 in order to drive the input of
in the inverter.

b) Create the output node using Metal1

- Use the M1 layer to connect the drains of the PMOS and NMOS transistors
together to form the output of the inverter

- In the layer menu, click on M1.

- in the layout window, create a rectangle using [r]

- also add some metal over the M1PLY contact so that when this INV is
instantiated in high-level layout, the input and output can be accessed on M1.

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c) Create the VSS and VDD rates using Metal 1

- Use the M1 layer to create the VSS and VDD notes of the inverter. Remember
that these connections must also pick up the body contacts of the transistors

- a good layout practice is to keep a consistent pattern of the VSS and VDD traces
so that when you interface with other circuits, the VSS/VDD rails will line up.
We will create a horizontal trace above the inverter for VDD. We will create a
horizontal trace below the inverter for VSS. We can choose a pitch of 25um for
the VSS and VDD rails.

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6) Add Pins and Labels to the Labels and Pins to the Device

In order to be able to run the Layout vs. Schematic (LVS) check, we need to add the
net names of our circuit in the schematic. This is a two step process that involves
first adding a Pin and then adding a Label to a given Metal or Poly shape in your layout.
This is a manual process and requires to type in the net names EXACTLY as you
defined them in your schematic.

a) Adding Pins

- in the layout window, use the pull-down menus to perform:

- Create – Pin

- in the create pin dialog, set the following:

Terminal Names = Type in the EXACT name of the pin that you
used in the schematic
I/O Type = Use the EXACT type that you used in the
schematic (input, output, inputOutput)
Pin Type = M1PIN (Metal 1 Pin, this assumes that all of
your inputs and outputs of your layout are on
Metal 1. If they are on poly, you should select
the poly pin type.
Click “OK

- you will see the pin attached to your mouse in the layout editor window. Click
in the layout window to drop your pin. Place this pin within the metal of your
layout in the appropriate spot. Repeat for all pins (VDD,VSS,IN,OUT).

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b) Adding Labels

- in the layout window, use the pull-down menus to perform:

Create – Label

- in the dialog box, set the following:

Label = Type in the EXACT name of the pin that you

just created
Height = this is the size of the font that the label will have.
If you click in the layout window, you’ll see the
text attached to your mouse. Make this size
something readable, but not so large it will
clutter the layout. Remember that this layout
will be used in higher-level blocks

- now we need to change the layer of the Label we just added. We need to put
the label on the same layer as our Pin Type and the layer in our layout that is
our node we are naming (in this case, Meta l 1)

- in the layout window, select the Label you just put in

- bring up the properties of the label and change the layer to M1. “OK” the
properties dialog.

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Step 7: Running Design Rule Check (DRC)

DRC will check your layout against the layout design rules for the process. You do not
need to wait until your design is complete to run DRC. You can run it periodically to
make sure that each step meets the design rules:

1) Run DRC

- in the Virtuoso Layout Editor window, use the pull-down menus:

- Assura – Run DRC

- in the popup window, you need to first select the technology file you
are going to check against.

View Rules Files: ami500hxkx

- click “OK”

- if a popup comes up saying that the DRC data already exists, click “OK” to
overwrite:

- a small window will appear that says DRC is running, it will take a few moments
to complete.

- when complete, a window will appear saying the DRC has successfully ran. This
is just telling you that the DRC ran, not that you passed DRC. Click “Yes” to view
the errors.

- errors will be highlighted in the layout window

2) End DRC

- in the error layer window, perform

- File – Close ELW

- in the layout window, perform:

- Assura – Stop Run

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Step 8: Running Layout versus Schematic (LVS)

LVS will check your layout against your schematic to verify that the gates you’ve created are what
you intended. This includes the sizes of your transistors. LVS works by creating a netlist of your
schematic and then one of your layout. It compares the two to make sure that each net is correct
and the number of transistors you intended are present.

In order for the nets to be identified by name in the layout, you will need to have added a Pin and a
Label to each node. If you don’t add the Pin and Label, you won’t be able to run LVS. Also if
your label is not on the correct layer, it will not pass LVS.

LVS should be successfully run on each block prior to including it in a higher level schematic.

1) Run LVS

- in the Virtuoso Layout Editor window, use the pull-down menus:

- Assura – Run VLS

- in the popup window, you need to first select the technology file you
are going to check against (you only need to do this once)

View Rules Files: ami500hxkx

- click “OK”

- if a popup comes up saying that the LVS data already exists, click “OK” to
overwrite:

- a small window will appear that says LVS is running, it will take a few moments
to complete.

- when complete, a window will appear saying the LVS has successfully ran. This
is just telling you that the LVS ran, not that you passed LVS. Click “Yes” to view
the errors.

- a report window will be given that shows the results of LVS. You can scroll
through the report to see what errors and warning (if any) occurred.

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2) View LVS Results

- in the LVS Debug window, highlight the results in the Cell List. The top one will
be your design.

- using the pull-downs, perform

View - Layout VNL Netlist

- this netlist gives the SPICE deck of what it found in your layout. You should see your
n and p devices, including the node names and the sizes.

- if you has errors, you will also be able to view the Schematic VNL Netlist. You can view
both of these netlist to see what information LVS is or isn’t seeing in your design.

3) End LVS

- in the LVS Debug window, perform

- File – Close

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Appendix A: Cadence Hot Keys

Schematic Entry (and other windows where applicable):

c copy
e descend (read only)
E descend (edit mode)
^e ascend up one level
f zoom to fit design to window
i add instance
l label wire
m move
p add pin
q edit parameters
r rotate
u undo
U redo
w add wire
z zoom to box using left-mouse clicks
[] zoom in and out
arrow keys move around window
F3 Command options
left-mouse select/click
middle-mouse over object brings up typical properties
right-mouse repeat last operation

Layout Entry (and other windows where applicable):

c copy
m move
r add rectangle
R add polygon
Cntl+p add a pin
l label a wire
L label a wire
z zoom in to area
Z zoom out 2x
f fit in window
[TAB] pan toward mout
cntl+f convert instantiated instance to block view
shift+f convert instantiated instance to layer view
s stretch the side of a rectangle if mouse is over it

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Appendix B: UNIX / LINUX Commands

Useful commands:

>> cd : this takes you to your working directory

>> cd ~/. : a “~” is a shortcut for your home directory

>> cd <directory name> : change into a directory

: you can type the first few letters of the directory name
: and then click [TAB] to have the rest of the name
: automatically filled in for you

>> cd .. : go UP one directory

>> pwd : check your present working directory, i.e., what directory
: you’re in

>> ls : get a list of the files and directories in your current directory

>> ls –al : get a list of all files and directories, including hidden files
: NOTE: files that start with “.”, are hidden and can only
: be seen with ls –al.

>> mkdir <name> : make a directory

>> rm <name> : remove a file

>> mv <name> <path> : move a file to <path>

>> mv –r <name> <path> : move a directory and all of its subfolders and files to <path>

>> cp <name> <path> : copy a file to <path>

>> cp –r <name> <path> : copy a directory and all of its subfolders and files to <path>

>> more : shows you the contents of a file

>> whoami : tells you the username you are logged in as

>> hostname : tells you the computer that you are logged into

>> man <topic> : displays the manual (or help file) for a given command

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