Search Results (169)

Figure 1
<p>The simulation model of the gate driver–MOSFET transistor subcircuit.</p> Full article ">Figure 2
<p>Waveforms of the voltages and currents in the gate circuit: <span class="html-italic">v</span>_G, <span class="html-italic">v</span>_GS, <span class="html-italic">v</span>_CG and <span class="html-italic">i</span>_G current for frequencies: (<b>a</b>) 1 MHz, (<b>b</b>) 5 MHz, (<b>c</b>) 10 MHz, (<b>d</b>) 15 MHz, (<b>e</b>) 20 MHz.</p> Full article ">Figure 2 Cont.
<p>Waveforms of the voltages and currents in the gate circuit: <span class="html-italic">v</span>_G, <span class="html-italic">v</span>_GS, <span class="html-italic">v</span>_CG and <span class="html-italic">i</span>_G current for frequencies: (<b>a</b>) 1 MHz, (<b>b</b>) 5 MHz, (<b>c</b>) 10 MHz, (<b>d</b>) 15 MHz, (<b>e</b>) 20 MHz.</p> Full article ">Figure 2 Cont.
<p>Waveforms of the voltages and currents in the gate circuit: <span class="html-italic">v</span>_G, <span class="html-italic">v</span>_GS, <span class="html-italic">v</span>_CG and <span class="html-italic">i</span>_G current for frequencies: (<b>a</b>) 1 MHz, (<b>b</b>) 5 MHz, (<b>c</b>) 10 MHz, (<b>d</b>) 15 MHz, (<b>e</b>) 20 MHz.</p> Full article ">Figure 3
<p>Power loss characteristics of the <span class="html-italic">P</span>_DR driver, <span class="html-italic">P</span>_G transistor gate and total <span class="html-italic">P</span>_DR+<span class="html-italic">P</span>_G driver–transistor circuit.</p> Full article ">Figure 4
<p>Power loss characteristics of the <span class="html-italic">P</span>_DR driver, <span class="html-italic">P</span>_G transistor gate and total <span class="html-italic">P</span>_DR + <span class="html-italic">P</span>_G driver–transistor circuit at a limited voltage (<span class="html-italic">V</span>_CGmax = 12 V) on the equivalent gate capacitance <span class="html-italic">C</span>_G of the MOSFET transistor.</p> Full article ">Figure 5
<p>The schematic diagram of the internal structure of the IXRFD631 MOSFET gate driver [<a href="#B19-electronics-13-03225" class="html-bibr">19</a>].</p> Full article ">Figure 6
<p>The real photo of integrated driver IXRFD631 with description.</p> Full article ">Figure 7
<p>The schematic diagram of discrete driver 8xUCC27526.</p> Full article ">Figure 8
<p>The photo of discrete driver 8xUCC27526 with description.</p> Full article ">Figure 9
<p>The structure of IMS material in thermal clad technology [<a href="#B21-electronics-13-03225" class="html-bibr">21</a>].</p> Full article ">Figure 10
<p>The diagram of the measurement system used to determine power losses and efficiency of all tested MOSFET drivers. Explanation: point (a) is the driver’s no-load operation, point (b) is the work under load of the DE275-501N16A transistor gate.</p> Full article ">Figure 11
<p>The characteristics of power losses at idle state (no load) in integrated and discrete drivers designed by oneself.</p> Full article ">Figure 12
<p>The characteristics of power losses at load by the MOSFET transistor in integrated and discrete drivers designed by oneself.</p> Full article ">Figure 13
<p>The output voltage waveforms for integrated driver IXRFD631: (<b>a</b>) at idle state (no load); (<b>b</b>) at load of gate MOSFET.</p> Full article ">Figure 13 Cont.
<p>The output voltage waveforms for integrated driver IXRFD631: (<b>a</b>) at idle state (no load); (<b>b</b>) at load of gate MOSFET.</p> Full article ">Figure 14
<p>The output voltage waveforms for discrete driver 8xUCC27526: (<b>a</b>) at idle state (no load); (<b>b</b>) at load of gate MOSFET.</p> Full article ">Figure 14 Cont.
<p>The output voltage waveforms for discrete driver 8xUCC27526: (<b>a</b>) at idle state (no load); (<b>b</b>) at load of gate MOSFET.</p> Full article ">Figure 15
<p>The photograph of thermal camera for two tested drivers: (<b>a</b>) integrated driver IXRFD631; (<b>b</b>) discrete driver 8xUCC27526 designed by oneself.</p> Full article ">Figure 16
<p>The simplified measurement scheme of basic parasitic parameters of drivers.</p> Full article ">Figure 17
<p>The efficiency characteristics of the tested drivers.</p> Full article ">

Figure 1
<p>Basic principles of the TMS system.</p> Full article ">Figure 2
<p>Stimulation protocols. (<b>a</b>) Traditional theta burst stimulation. (<b>b</b>) Proposed high-frequency stimulation.</p> Full article ">Figure 3
<p>Simulation of the electric field intensity in human gray matter. (<b>a</b>) Simulation structure. (<b>b</b>) Normalized <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>E</mi> </mrow> <mrow> <mi>m</mi> <mi>a</mi> <mi>x</mi> </mrow> </msub> </mrow> </semantics></math> as a function of frequency. (<b>c</b>) Penetration depth of the electric field as a function of frequency.</p> Full article ">Figure 4
<p>Block diagram of the proposed HF magnetic pulse generator.</p> Full article ">Figure 5
<p>Schematic of the full-bridge circuit with boot-strapped gate driver.</p> Full article ">Figure 6
<p>Simulated waveforms for the control signal (<math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>C</mi> <mn>1</mn> </mrow> </msub> </mrow> </semantics></math>–<math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>C</mi> <mn>4</mn> </mrow> </msub> </mrow> </semantics></math>), the coil current (<math display="inline"><semantics> <mrow> <msub> <mrow> <mi>I</mi> </mrow> <mrow> <mi>L</mi> </mrow> </msub> </mrow> </semantics></math>), and the voltage across the coil (<math display="inline"><semantics> <mrow> <mo>Δ</mo> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>L</mi> </mrow> </msub> </mrow> </semantics></math>). (<b>a</b>) Triangular current wave. (<b>b</b>) Trapezoidal current wave.</p> Full article ">Figure 7
<p>Simulated waveforms in the full-bridge circuit with (solid) and without (dot) bypass capacitor and damping resistor for <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>D</mi> <mi>D</mi> <mo>,</mo> <mi>F</mi> </mrow> </msub> </mrow> </semantics></math> = 10 V and <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>D</mi> <mi>D</mi> <mo>,</mo> <mi>G</mi> <mi>D</mi> </mrow> </msub> </mrow> </semantics></math> = 5.5 V. (<b>a</b>) <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>D</mi> <mi>D</mi> <mo>,</mo> <mi>F</mi> <mi>i</mi> </mrow> </msub> </mrow> </semantics></math>, (<b>c</b>) <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>G</mi> <mi>S</mi> <mo>,</mo> <mi>U</mi> </mrow> </msub> </mrow> </semantics></math>, and (<b>e</b>) <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>I</mi> </mrow> <mrow> <mi>L</mi> <mo>,</mo> <mi>c</mi> <mi>o</mi> <mi>i</mi> <mi>l</mi> </mrow> </msub> </mrow> </semantics></math> at 100 kHz. (<b>b</b>) <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>D</mi> <mi>D</mi> <mo>,</mo> <mi>F</mi> <mi>i</mi> </mrow> </msub> </mrow> </semantics></math>, (<b>d</b>) <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>G</mi> <mi>S</mi> <mo>,</mo> <mi>U</mi> </mrow> </msub> </mrow> </semantics></math>, and (<b>f</b>) <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>I</mi> </mrow> <mrow> <mi>L</mi> <mo>,</mo> <mi>c</mi> <mi>o</mi> <mi>i</mi> <mi>l</mi> </mrow> </msub> </mrow> </semantics></math> at 1 MHz.</p> Full article ">Figure 8
<p>(<b>a</b>) Fabricated HF magnetic pulse generator. (<b>b</b>) Fabricated stimulation coil.</p> Full article ">Figure 9
<p>Measurement setup for the induced electric field intensity.</p> Full article ">Figure 10
<p>Measured waveforms for the inductor load with DC bias voltages, <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>D</mi> <mi>D</mi> <mo>,</mo> <mi>F</mi> </mrow> </msub> </mrow> </semantics></math> = 10 V and <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>D</mi> <mi>D</mi> <mo>,</mo> <mi>G</mi> <mi>D</mi> </mrow> </msub> </mrow> </semantics></math> = 5.5 V. (<b>a</b>) <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>I</mi> </mrow> <mrow> <mi>L</mi> <mo>,</mo> <mi>c</mi> <mi>o</mi> <mi>i</mi> <mi>l</mi> </mrow> </msub> </mrow> </semantics></math> and (<b>c</b>) <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>E</mi> </mrow> <mrow> <mi>i</mi> <mi>n</mi> <mi>d</mi> </mrow> </msub> </mrow> </semantics></math> at 100 kHz. (<b>b</b>) <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>I</mi> </mrow> <mrow> <mi>L</mi> <mo>,</mo> <mi>c</mi> <mi>o</mi> <mi>i</mi> <mi>l</mi> </mrow> </msub> </mrow> </semantics></math> and (<b>d</b>) <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>E</mi> </mrow> <mrow> <mi>i</mi> <mi>n</mi> <mi>d</mi> </mrow> </msub> </mrow> </semantics></math> at 1 MHz.</p> Full article ">Figure 11
<p>Measured waveforms for the quasi-resonant LC load at the frequency of 1 MHz with DC bias voltages, <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>D</mi> <mi>D</mi> <mo>,</mo> <mi>F</mi> </mrow> </msub> <mo>=</mo> </mrow> </semantics></math> 1.8 V and <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>V</mi> </mrow> <mrow> <mi>D</mi> <mi>D</mi> <mo>,</mo> <mi>G</mi> <mi>D</mi> </mrow> </msub> <mo>=</mo> </mrow> </semantics></math> 5.5 V. (<b>a</b>) <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>I</mi> </mrow> <mrow> <mi>L</mi> <mo>,</mo> <mi>L</mi> <mi>C</mi> </mrow> </msub> </mrow> </semantics></math> and (<b>b</b>) <math display="inline"><semantics> <mrow> <msub> <mrow> <mi>E</mi> </mrow> <mrow> <mi>i</mi> <mi>n</mi> <mi>d</mi> </mrow> </msub> </mrow> </semantics></math>.</p> Full article ">

Figure 1
<p>The development history diagram of HVDC transmission.</p> Full article ">Figure 2
<p>Structural diagram of the Wudongde–Kunliulong hybrid HVDC transmission project.</p> Full article ">Figure 3
<p>Power router based on the IGCT for the Ulanqab source–grid–load–storage integrated industrial park.</p> Full article ">Figure 4
<p>Comparison diagram of the IGCT and IGBT cell structures.</p> Full article ">Figure 5
<p>Electromagnetic transient simulation platform joint CPU-GPU.</p> Full article ">Figure 6
<p>Interface interaction in hybrid simulation. (<b>a</b>) Serial mode; (<b>b</b>) parallel mode; (<b>c</b>) iterative mode; and (<b>d</b>) hybrid mode.</p> Full article ">

Figure 1
<p>Schematic diagram of hidden relationships in multiple parking lots.</p> Full article ">Figure 2
<p>Overall framework of DSTAGCRN.</p> Full article ">Figure 3
<p>Construction of spatio-temporal embeddings.</p> Full article ">Figure 4
<p>Schematic diagram of the PLGCRM module.</p> Full article ">Figure 5
<p>The specific process of the multihead attention mechanism.</p> Full article ">Figure 6
<p>Prediction results for six models per prediction layer on three parking datasets.</p> Full article ">Figure 7
<p>Comparison of the prediction results between the proposed DSTAGCRN model and the STGNCDE model on the Guangzhou parking dataset.</p> Full article ">Figure 8
<p>Changes in the number of vacant parking spaces in two parking lots in one day.</p> Full article ">Figure 9
<p>Changes in the spatial weights of two parking lots in one day.</p> Full article ">Figure 10
<p>Impact of different embedding dimensions.</p> Full article ">Figure 11
<p>Impact of different parameters on the model.</p> Full article ">

Figure 1
<p>Concept diagram of scanning pulse generation with one-type TFTs.</p> Full article ">Figure 2
<p>Schematic and timing diagram of a basic shift register at an N-type enhancement-mode TFT backplane.</p> Full article ">Figure 3
<p>Signal connections between basic shift registers.</p> Full article ">Figure 4
<p>Fluctuation-reduced shift register by applying another high floating node voltage to the gate nodes of pulling-down TFTs at an enhancement-mode TFT backplane.</p> Full article ">Figure 5
<p>Fluctuation-reduced shift register by including an internal inverter to generate Qb at an enhancement-mode TFT backplane.</p> Full article ">Figure 6
<p>Low power shift register by removing the shoot-through current path in an internal inverter at an enhancement-mode TFT backplane [<a href="#B62-micromachines-15-00823" class="html-bibr">62</a>].</p> Full article ">Figure 7
<p>Reliability-enhanced shift register by the line-by-line alternation of discharging paths for Q and G at an enhancement-mode TFT backplane [<a href="#B67-micromachines-15-00823" class="html-bibr">67</a>].</p> Full article ">Figure 8
<p>Four-phase clock shift register for reliability enhancement and power reduction at an enhancement-mode TFT backplane [<a href="#B72-micromachines-15-00823" class="html-bibr">72</a>].</p> Full article ">Figure 9
<p>Reliability-enhanced shift register by the frame-by-frame alternation of discharging paths for Q and G at an enhancement-mode TFT backplane.</p> Full article ">Figure 10
<p>Shift register based on P-type enhancement-mode TFTs [<a href="#B78-micromachines-15-00823" class="html-bibr">78</a>].</p> Full article ">Figure 11
<p>Approaches to deal with depletion-mode TFTs.</p> Full article ">Figure 12
<p>Shift register based on N-type depletion-mode oxide TFTs [<a href="#B82-micromachines-15-00823" class="html-bibr">82</a>].</p> Full article ">Figure 13
<p>Small area shift register with a Qb-sharing structure at an enhancement-mode TFT backplane [<a href="#B87-micromachines-15-00823" class="html-bibr">87</a>].</p> Full article ">Figure 14
<p>Small area shift register with a direct Q-sharing structure at a depletion-mode TFT backplane [<a href="#B88-micromachines-15-00823" class="html-bibr">88</a>].</p> Full article ">Figure 15
<p>Small area shift register with a Q-sharing structure by separating TFTs at an enhancement-mode TFT backplane [<a href="#B90-micromachines-15-00823" class="html-bibr">90</a>].</p> Full article ">Figure 16
<p>Threshold voltage compensation pixel circuit example [<a href="#B104-micromachines-15-00823" class="html-bibr">104</a>].</p> Full article ">Figure 17
<p>Emission pulse generation circuit based on P-type enhancement-mode TFTs [<a href="#B103-micromachines-15-00823" class="html-bibr">103</a>].</p> Full article ">Figure 18
<p>Foveation-based driving schemes with the vertical resolution reduction [<a href="#B108-micromachines-15-00823" class="html-bibr">108</a>].</p> Full article ">Figure 19
<p>Timing diagram of display scanning and touch sensing at TDDM [<a href="#B112-micromachines-15-00823" class="html-bibr">112</a>].</p> Full article ">Figure 20
<p>Shift register schematic and timing diagram at an enhancement-mode TFT backplane for a TDDM touch sensing scheme [<a href="#B115-micromachines-15-00823" class="html-bibr">115</a>].</p> Full article ">Figure 21
<p>Pixel circuit with a sensing TFT (N3) for the external compensation [<a href="#B125-micromachines-15-00823" class="html-bibr">125</a>].</p> Full article ">Figure 22
<p>Random sensing line selection during the vertical blank period [<a href="#B125-micromachines-15-00823" class="html-bibr">125</a>].</p> Full article ">Figure 23
<p>Random sensing pulse generation at a depletion-mode oxide TFT backplane: (<b>a</b>) schematic; (<b>b</b>) timing diagram [<a href="#B125-micromachines-15-00823" class="html-bibr">125</a>].</p> Full article ">Figure 24
<p>Selective scan driver circuit at an enhancement-mode TFT backplane to enable the gate pulse generation only for the specific region [<a href="#B132-micromachines-15-00823" class="html-bibr">132</a>].</p> Full article ">

Figure 1
<p>Time series of monthly values of the PDO, Niño3.4, AMO, AO, NPI, SSH_KOE, and Ther_KOE indices from 1871 to 2010. All indices were smoothed by calculating the 6-month running mean and normalized by their standard deviation.</p> Full article ">Figure 2
<p>Flow diagram of machine learning for the model prediction. (<b>a</b>) Data Pre-processing: Preparing the raw data for analysis by cleaning, transforming, and selecting relevant features; (<b>b</b>) Data Splitting: Splitting the dataset into training, and testing sets to ensure unbiased evaluation of the model; (<b>c</b>) Modelling Process: Applying the machine learning model to the data to build a predictive model; (<b>d</b>) Model Explanation: Providing insights into how and why the model makes its predictions using the SHAP analysis.</p> Full article ">Figure 3
<p>(<b>a</b>) Correlation matrix among the indices, and (<b>b</b>) the <math display="inline"><semantics> <mrow> <mi>V</mi> <mi>I</mi> <mi>F</mi> </mrow> </semantics></math> values of dependent variables.</p> Full article ">Figure 4
<p>The observed and predicted PDO indices in six ML models: (<b>a</b>) ANN, (<b>b</b>) SVR, (<b>c</b>) XGBoost, (<b>d</b>) CNN, (<b>e</b>) LSTM, and (<b>f</b>) GRU from January 1982 to December 2010. The error is represented as the difference between predicted values and observed values. Pink indicates positive errors, while purple represents negative errors.</p> Full article ">Figure 5
<p>Taylor diagram for the PDO index amplitude, the centered RMSE, and coefficient correlation between the model and observations. The REF point represents zero RMSE compared to the observations. The model standard deviations were normalized to the scale of the observation data. Different legend shapes represent the six different ML models.</p> Full article ">Figure 6
<p>The (<b>left</b>) correlation coefficient and (<b>right</b>) RMSE between the observed and predicted SSTAs in six ML models from January 1982 to December 2010.</p> Full article ">Figure 7
<p>Performing sequential forward selection analysis for the GRU model in terms of the correlation coefficient and RMSE as each predictor is added. Histograms and lines represent the correlation coefficient and RMSE, respectively. The error bars and pink shading indicate the standard deviation from the mean of 10 ensemble runs.</p> Full article ">Figure 8
<p>SHAP force plot results for PDO prediction of samples for 1976/1977 and 1998/1999 regime shifts: (<b>a</b>) Winter, 1975; (<b>b</b>) Winter, 1976; (<b>c</b>) Winter, 1997; and (<b>d</b>) Winter, 1998.</p> Full article ">Figure 9
<p>(<b>a</b>) SHAP feature importance plot and (<b>b</b>) SHAP summary plot for each dependent variable.</p> Full article ">Figure 10
<p>SHAP dependence plot for each dependent variable: (<b>a</b>) Niño3.4 (°C), (<b>b</b>) AO (hPa), (<b>c</b>) AMO (°C), (<b>d</b>) NPI (hPa), (<b>e</b>) SSH_KOE (m), and (<b>f</b>) Ther_KOE (m). The black circles represent the SHAP values associated with different features. Red lines represent the polynomial regression of scatter points. The shaded area around each line indicates the range of a 95% confidence interval. Dashed lines represent the SHAP values equal to zero. The histograms on the top and right of each subplot indicate the distribution of feature and SHAP values.</p> Full article ">Figure 11
<p>SHAP interaction plot for the GRU model with respect to (<b>a</b>) the Niño3.4 and SSH_KOE indices, (<b>b</b>) the Niño3.4 index and the NPI, and (<b>c</b>) the SSH_KOE index and the NPI. Each point represents an example of the testing set.</p> Full article ">

Figure 1
<p>Proposed topology: (<b>a</b>) proposed circuit−I topology; (<b>b</b>) generalized proposed circuit−I topology.</p> Full article ">Figure 2
<p>Proposed topology: (<b>a</b>) proposed circuit−II topology; (<b>b</b>) generalized proposed circuit−II topology.</p> Full article ">Figure 3
<p>Different types of configurations of bi-directional switches (<b>a</b>) Common Emitter; IGBT (<b>b</b>) Diode Bridge with one Power Switch (<b>c</b>) Common Collector IGBT.</p> Full article ">Figure 4
<p>Different ways to generate DC voltages for the capacitors.</p> Full article ">Figure 5
<p>Operating modes for the fundamental structural topology (circuit−I or circuit−II).</p> Full article ">Figure 6
<p>Generated pulse pattern for the proposed inverter (circuit−I and circuit−II) for 9-level output voltage.</p> Full article ">Figure 7
<p>Circuits of the compared topologies proposed in (<b>a</b>) [<a href="#B24-electronics-13-01975" class="html-bibr">24</a>]; (<b>b</b>) [<a href="#B25-electronics-13-01975" class="html-bibr">25</a>]; (<b>c</b>) [<a href="#B26-electronics-13-01975" class="html-bibr">26</a>]; (<b>d</b>) [<a href="#B27-electronics-13-01975" class="html-bibr">27</a>]; (<b>e</b>) [<a href="#B28-electronics-13-01975" class="html-bibr">28</a>]; (<b>f</b>) [<a href="#B29-electronics-13-01975" class="html-bibr">29</a>]; (<b>g</b>) [<a href="#B30-electronics-13-01975" class="html-bibr">30</a>].</p> Full article ">Figure 8
<p>Comparison of the proposed topology with existing topologies in terms of (<b>a</b>) total number of switches required for different voltage level; (<b>b</b>) level-per-switch ratio [<a href="#B24-electronics-13-01975" class="html-bibr">24</a>,<a href="#B25-electronics-13-01975" class="html-bibr">25</a>,<a href="#B26-electronics-13-01975" class="html-bibr">26</a>,<a href="#B27-electronics-13-01975" class="html-bibr">27</a>,<a href="#B29-electronics-13-01975" class="html-bibr">29</a>].</p> Full article ">Figure 9
<p>Experimental set-up in the laboratory for the proposed MLI.</p> Full article ">Figure 10
<p>Blocking voltages across the switches: (<b>a</b>) S₁, S₂, and S₃; (<b>b</b>) S₄, S₅, and S₆; (<b>c</b>) S₇, S₈, and S₉.</p> Full article ">Figure 11
<p>Gate driver circuit for a power switch.</p> Full article ">Figure 12
<p>Simulation results for the 9-level inverter: (<b>a</b>) output voltage and current; (<b>b</b>) %THD of output phase voltage.</p> Full article ">Figure 12 Cont.
<p>Simulation results for the 9-level inverter: (<b>a</b>) output voltage and current; (<b>b</b>) %THD of output phase voltage.</p> Full article ">Figure 13
<p>Switching pulses fed to the power switches of the proposed circuit−I topology: (<b>a</b>) S₁, S₂ and S₃; (<b>b</b>) S₃, S₄, and S₅; (<b>c</b>) S₆, S₇, and S₈.</p> Full article ">Figure 14
<p>Load voltage and current for the 9-level inverter: (<b>a</b>) 2.5 cycles; (<b>b</b>) 1 cycle.</p> Full article ">Figure 15
<p>Total harmonic distortion of the output voltage of the proposed inverters: (<b>a</b>) 11−level inverter; (<b>b</b>) 13−level inverter.</p> Full article ">Figure 16
<p>Load voltage and current for the 11-level inverter; (<b>a</b>) 2.5 cycles; (<b>b</b>) different modulation indices.</p> Full article ">Figure 17
<p>Load voltage and current for the 13-level inverter: (<b>a</b>) 2.5 cycles; (<b>b</b>) different modulation indices.</p> Full article ">

Figure 1
<p>IGBT gate driver: (<b>a</b>) photo and (<b>b</b>) functional diagram.</p> Full article ">Figure 1 Cont.
<p>IGBT gate driver: (<b>a</b>) photo and (<b>b</b>) functional diagram.</p> Full article ">Figure 2
<p>Timing diagrams of the optical communication signals (blue—input; red—feedback): (<b>a</b>) input signal; (<b>b</b>) normal operation feedback; (<b>c</b>) no gate current or gate voltage exceeding fault feedback; (<b>d</b>) short-circuit or overload current protection feedback; and (<b>e</b>) power supply failure feedback.</p> Full article ">Figure 3
<p>States and substates of the finite-state machine (green—turned on state; red—turned off state; blue—occurs in both states).</p> Full article ">Figure 4
<p>Timing diagrams of algorithm implementation in the microcontroller (blue—control command; red—feedback signal).</p> Full article ">Figure 5
<p>Timing diagram of feedback signal implementation by PWM module (blue—control command; red—feedback signal).</p> Full article ">Figure 6
<p>Functional diagram of the test bench.</p> Full article ">Figure 7
<p>Transient signals of the gate driver in normal operation mode: yellow—control signal; blue—gate voltage; red—collector–emitter voltage; green—driver feedback signal. (<b>a</b>) Enlarged picture. (<b>b</b>) Narrowed picture.</p> Full article ">Figure 8
<p>Transient signals in the short-circuit operation mode: yellow—control signal; blue—gate voltage; red—collector-emitter voltage; green—driver feedback signal.</p> Full article ">Figure 9
<p>(<b>a</b>) Transient signals of the gate driver in normal operation mode. (<b>b</b>) Transient signals of the gate driver in the case of disconnecting the driver pin from the gate of the transistor: yellow—control signal; blue—driver output gate voltage; red—gate current; green—driver feedback signal.</p> Full article ">Figure 9 Cont.
<p>(<b>a</b>) Transient signals of the gate driver in normal operation mode. (<b>b</b>) Transient signals of the gate driver in the case of disconnecting the driver pin from the gate of the transistor: yellow—control signal; blue—driver output gate voltage; red—gate current; green—driver feedback signal.</p> Full article ">Figure 10
<p>(<b>a</b>) The driver feedback signal sets the fault in the case of a voltage supply, +15 V, that is out of range: blue—supply voltage; green—driver feedback signal. (<b>b</b>) The process of establishing the voltage supply, +15 V, and resetting the driver fault: blue—supply voltage; green—driver feedback signal.</p> Full article ">Figure 10 Cont.
<p>(<b>a</b>) The driver feedback signal sets the fault in the case of a voltage supply, +15 V, that is out of range: blue—supply voltage; green—driver feedback signal. (<b>b</b>) The process of establishing the voltage supply, +15 V, and resetting the driver fault: blue—supply voltage; green—driver feedback signal.</p> Full article ">

Figure 1
<p>Assessing the thyristor’s parasitic capacitance. (<b>a</b>) Setup to measure the parasitic capacitance of a thyristor in relation to bias voltage using an RLC meter. (<b>b</b>) Voltage dependance of the MPPCT750D240 thyristor’s parasitic capacitance.</p> Full article ">Figure 2
<p>Schematic of the six SiC MOSFETs (<span class="html-italic">SiC2</span> _1 to _6), with the corresponding microstrips, in parallel.</p> Full article ">Figure 3
<p>PCB 3D rendering representing the six SiC MOSFETs and microstrip branches of the pulse generator. The propagation delay of the individual SiC gate driving signal is mostly compensated for by the geometry of their drain transmission lines layout and the placement of the output feeding point on the opposite extremity.</p> Full article ">Figure 4
<p>Schematic of the previous version of the SiC MOSFET gate-boosting driver.</p> Full article ">Figure 5
<p>Output voltage of the gate-boosting driver on <a href="#applsci-14-04196-f004" class="html-fig">Figure 4</a>, on a 50 <math display="inline"><semantics> <mo>Ω</mo> </semantics></math> load at a charging voltage of 320 V. Maximum amplitude of 300 V and <math display="inline"><semantics> <mrow> <msub> <mi>t</mi> <mi>r</mi> </msub> <mo>=</mo> <mn>1</mn> <mrow> <mi>ns</mi> </mrow> </mrow> </semantics></math>, measured between 10–90%.</p> Full article ">Figure 6
<p>Schematic of the driver with its main stages: <math display="inline"><semantics> <mrow> <mi>N</mi> <mi>M</mi> <mn>1</mn> <mo>_</mo> <mn>1</mn> </mrow> </semantics></math> and <math display="inline"><semantics> <mrow> <mi>P</mi> <mi>M</mi> <mn>1</mn> <mo>_</mo> <mn>1</mn> </mrow> </semantics></math> as the fist level-shifting step, then the two-stage Marx generator with <math display="inline"><semantics> <mrow> <mi>A</mi> <mi>v</mi> <mn>1</mn> <mo>_</mo> <mn>1</mn> </mrow> </semantics></math> and <math display="inline"><semantics> <mrow> <mi>A</mi> <mi>v</mi> <mn>1</mn> <mo>_</mo> <mn>2</mn> </mrow> </semantics></math>, and finally the normally-off <math display="inline"><semantics> <mrow> <mi>G</mi> <mi>H</mi> <mn>1</mn> <mo>_</mo> <mn>1</mn> </mrow> </semantics></math> in source-follower configuration.</p> Full article ">Figure 7
<p>Dimensions of the driver. A more compact layout allows for a reduced stray impedance.</p> Full article ">Figure 8
<p>The triggering pulse. (<b>a</b>) Schematic of the pulse booster for the Philips PM5786B pulse generator. (<b>b</b>) Output pulse on a 50 <math display="inline"><semantics> <mo>Ω</mo> </semantics></math> load, labeled “<math display="inline"><semantics> <mrow> <mi>B</mi> <mi>o</mi> <mi>o</mi> <mi>s</mi> <mi>t</mi> <mi>e</mi> <msub> <mi>r</mi> <mrow> <mi>o</mi> <mi>u</mi> <mi>t</mi> </mrow> </msub> </mrow> </semantics></math>”, with a charging voltage of 50 V. Maximum amplitude of 45 V, with a 10–90% rise time of 425 ps.</p> Full article ">Figure 9
<p>Output voltages obtained on a single IMBF170R450M1 SiC MOSFET on a 50 <math display="inline"><semantics> <mo>Ω</mo> </semantics></math> load, at different charging voltages.</p> Full article ">Figure 10
<p>Output voltage of the six parallel IMBF170R450M1 SiC MOSFETs on a 50 <math display="inline"><semantics> <mo>Ω</mo> </semantics></math> load (TP5, <a href="#applsci-14-04196-f003" class="html-fig">Figure 3</a>), different charging voltages. At a <math display="inline"><semantics> <mrow> <mn>1.7</mn> </mrow> </semantics></math> kV charging voltage, the maximum voltage amplitude is <math display="inline"><semantics> <mrow> <mn>3.2</mn> </mrow> </semantics></math> kV and a 10–90% slew rate of 2 kV/ns.</p> Full article ">Figure 11
<p>The output voltage of the six parallel IMBF170R450M1 SiC MOSFETs on a 4 <math display="inline"><semantics> <mo>Ω</mo> </semantics></math> load (TP5, <a href="#applsci-14-04196-f003" class="html-fig">Figure 3</a>), charging voltage <math display="inline"><semantics> <mrow> <mn>1.7</mn> </mrow> </semantics></math> kV. The maximum voltage amplitude is <math display="inline"><semantics> <mrow> <mn>1.6</mn> </mrow> </semantics></math> kV; hence, there is a calculated output current of 400 A.</p> Full article ">Figure 12
<p>Output voltage of the FMMT413 (pink, TP1, <a href="#applsci-14-04196-f006" class="html-fig">Figure 6</a>) and FMMT417 (green, TP2 <a href="#applsci-14-04196-f006" class="html-fig">Figure 6</a>) avalanche transistors, charging voltages 150 V and 320 V, respectively, and for the GS66508T GaN HEMT (blue, TP3, <a href="#applsci-14-04196-f006" class="html-fig">Figure 6</a>), all measurements are on a 50 <math display="inline"><semantics> <mo>Ω</mo> </semantics></math> load. The final output has a maximum amplitude of 620 V and a maximum slew rate of 1 kV/ns.</p> Full article ">Figure 13
<p>Lifetime test. (<b>a</b>) Driver lifetime test, total <math display="inline"><semantics> <mrow> <mn>2</mn> <mo>×</mo> <msup> <mn>10</mn> <mn>6</mn> </msup> </mrow> </semantics></math> pulses. Loaded with 180 pF and <math display="inline"><semantics> <mrow> <mn>3.5</mn> </mrow> </semantics></math> <math display="inline"><semantics> <mo>Ω</mo> </semantics></math> to reproduce the six SiC MOSFET loading; charging voltage 640 V. (<b>b</b>) 6× SiC MOSFET lifetime test, total <math display="inline"><semantics> <mrow> <mn>1</mn> <mo>×</mo> <msup> <mn>10</mn> <mn>6</mn> </msup> </mrow> </semantics></math> pulses. Loaded with 4 <math display="inline"><semantics> <mo>Ω</mo> </semantics></math> to reproduce the condition of an output current &gt;220 A (calculated output current &gt;300 A); charging voltage <math display="inline"><semantics> <mrow> <mn>1.3</mn> </mrow> </semantics></math> kV.</p> Full article ">

Figure 1
<p>System Architecture Diagram.</p> Full article ">Figure 2
<p>FPGA Circuit Architecture Diagram.</p> Full article ">Figure 3
<p>DPU with Processing System Hardware Architecture.</p> Full article ">Figure 4
<p>Camera and FPGA Pinout Diagram.</p> Full article ">Figure 5
<p>PetaLinux Building Process.</p> Full article ">Figure 6
<p>The Pavement Defects Sample in TPDID. (<b>a</b>) Puddle; (<b>b</b>) expansion joint; and (<b>c</b>) deceleration ramp.</p> Full article ">Figure 7
<p>CPU Program Data Flow Diagram.</p> Full article ">Figure 8
<p>Training and testing results of YOLOv3 on multiple images in this study. (<b>a</b>) Original image and (<b>b</b>) test result.</p> Full article ">Figure 9
<p>System Verification Environment.</p> Full article ">Figure 10
<p>Deceleration ramp detection.</p> Full article ">Figure 11
<p>UART to CAN System.</p> Full article ">Figure 12
<p>Recognition results and PCAN-viewer UI.</p> Full article ">

Figure 1
<p>A schematic of a single-phase active T-Type converter.</p> Full article ">Figure 2
<p>Switching modulation of T-Type.</p> Full article ">Figure 3
<p>The equivalent circuit for Q₂ false turn-on demonstration considering parasitic capacitances.</p> Full article ">Figure 4
<p>Simple circuit model of Q₂ in the OFF state.</p> Full article ">Figure 5
<p><span class="html-italic">C_gd dV/dt</span> test; (<b>a</b>) circuit model with all possible parasitic elements, (<b>b</b>) complete circuit model.</p> Full article ">Figure 6
<p>(<b>a</b>) PM simulated in Ansys Q3D, (<b>b</b>) middle track, (<b>c</b>) upper side (+) track, and (<b>d</b>) lower side (−) track.</p> Full article ">Figure 6 Cont.
<p>(<b>a</b>) PM simulated in Ansys Q3D, (<b>b</b>) middle track, (<b>c</b>) upper side (+) track, and (<b>d</b>) lower side (−) track.</p> Full article ">Figure 7
<p>Step response of (<b>a</b>) <span class="html-italic">V_ds</span> across Q₂, and (<b>b</b>) <span class="html-italic">V_gs</span> of Q₂ during Q₁ turn-on.</p> Full article ">Figure 8
<p>Damping ratio of ringing across the switch in terms of parasitic capacitor values; (<b>a</b>) C_ds2, (<b>b</b>) C_gd2, and (<b>c</b>) C_gs2.</p> Full article ">Figure 9
<p>Natural frequency of oscillation across the switch in terms of parasitic capacitor values; (<b>a</b>) C_ds2, (<b>b</b>) C_gd2, and (<b>c</b>) C_gs2.</p> Full article ">Figure 10
<p><span class="html-italic">V_ds</span> oscillation for <span class="html-italic">C_gd</span> = 2 nF.</p> Full article ">Figure 11
<p>Damping ratio of ringing voltage across the switch in terms of the stray inductances in the circuit; (<b>a</b>) L_total, (<b>b</b>) L_G, and (<b>c</b>) L_l−.</p> Full article ">Figure 12
<p>Natural frequency of oscillation across the switch (Drain–Source) in terms of the stray inductances in the circuit; (<b>a</b>) L_total, (<b>b</b>) L_G, and (<b>c</b>) L_l−.</p> Full article ">Figure 13
<p>Effect of each parasitic capacitance of the switch on the induced gate–source voltage; (<b>a</b>) C_ds, (<b>b</b>) C_gd, and (<b>c</b>) C_gs.</p> Full article ">Figure 14
<p>V_gs of the OFF switch in case that C_gs = 13 nF.</p> Full article ">Figure 15
<p>V_gs of the OFF switch in case that C_ds = 5 nF.</p> Full article ">Figure 16
<p>Three-phase T-Type converter.</p> Full article ">Figure 17
<p>Switching state changes and the resulted phase voltage.</p> Full article ">Figure 18
<p>Simplified circuit considering switching state changes of legs 2 and 3 in form of pulse voltage.</p> Full article ">Figure 19
<p>Voltage oscillation of V_ph1 because of switching state changes for other phases (Ph₂ and Ph₃) for; (<b>a</b>) θ₁ = 0°; (<b>b</b>) θ₁ = 30°; and (<b>c</b>) θ₁ = 60°.</p> Full article ">Figure 20
<p>The experimental setup for result verification by DPT test.</p> Full article ">Figure 21
<p>Current flow of the system under DPT test in practice.</p> Full article ">Figure 22
<p>The equivalent circuit model under DPT test for (<b>a</b>) upper side half-bridge of T-type converter (case 1), (<b>b</b>) lower side half-bridge of T-type converter (case 2), and (<b>c</b>) T-type leg (case 3).</p> Full article ">Figure 23
<p>Induced gate–source voltage of switches with possibility of false turning on in DPT test; (<b>a</b>) case 1, (<b>b</b>) case 2, (<b>c</b>) case 3.</p> Full article ">Figure 24
<p>Enlarged view of the induced gate–source voltage of Q₂ in DPT test of case 3; (<b>a</b>) first turn-on of Q₁, (<b>b</b>) second turn-on of Q₁.</p> Full article ">Figure 25
<p>(<b>a</b>) V_ds and V_gs of the switches in case 2, and (<b>b</b>) V_ds and V_gs of the switches in case 3.</p> Full article ">Figure 26
<p>(<b>a</b>) V_ds across switches Q₂ and Q₄ for case 2 and 3 during first turning-on, and (<b>b</b>) V_ds across switches Q₂ and Q₄ for case 2 and 3 during second turning-on.</p> Full article ">Figure 27
<p>Comparison results of different voltage changes rate using different R_G,on; (<b>a</b>) first turn-on of switch Q₁and (<b>b</b>) second turn-on of switch Q₁.</p> Full article ">Figure 28
<p>Induced V_gs of Q₂ in case 3 for different <span class="html-italic">R_G,on</span>; (<b>a</b>) <span class="html-italic">R_G,on</span> = 11.5 Ω and (<b>b</b>) <span class="html-italic">R_G,on</span> = 15.6 Ω.</p> Full article ">Figure 29
<p>The overall key waveforms of DPT test with replacing R_G = 15.6 Ω by R_G = 11.5 Ω.</p> Full article ">

Figure 1
<p>Properties for different types of HV switches (<b>left</b>) and their possible applications (<b>right</b>) [<a href="#B1-electronics-13-01481" class="html-bibr">1</a>,<a href="#B2-electronics-13-01481" class="html-bibr">2</a>,<a href="#B3-electronics-13-01481" class="html-bibr">3</a>,<a href="#B4-electronics-13-01481" class="html-bibr">4</a>,<a href="#B5-electronics-13-01481" class="html-bibr">5</a>,<a href="#B6-electronics-13-01481" class="html-bibr">6</a>,<a href="#B7-electronics-13-01481" class="html-bibr">7</a>,<a href="#B8-electronics-13-01481" class="html-bibr">8</a>,<a href="#B9-electronics-13-01481" class="html-bibr">9</a>,<a href="#B10-electronics-13-01481" class="html-bibr">10</a>,<a href="#B11-electronics-13-01481" class="html-bibr">11</a>,<a href="#B12-electronics-13-01481" class="html-bibr">12</a>,<a href="#B13-electronics-13-01481" class="html-bibr">13</a>,<a href="#B14-electronics-13-01481" class="html-bibr">14</a>,<a href="#B15-electronics-13-01481" class="html-bibr">15</a>,<a href="#B16-electronics-13-01481" class="html-bibr">16</a>,<a href="#B17-electronics-13-01481" class="html-bibr">17</a>,<a href="#B18-electronics-13-01481" class="html-bibr">18</a>].</p> Full article ">Figure 2
<p>Basic schematic for testing two series-connected SiC MOSFETs.</p> Full article ">Figure 3
<p>Measured unbalanced <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> sharing of the SiC MOSFET string without (<b>left</b>) and with (<b>right</b>) the identical balancing resistors (500 kΩ).</p> Full article ">Figure 4
<p>Schematic of the <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> measurement of the three series-connected MOSFETs (<b>left</b>) and the corresponding resistance ladder network (<b>right</b>).</p> Full article ">Figure 5
<p>Measured overall <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> sharing of the MOSFET string with tuned balancing resistors.</p> Full article ">Figure 6
<p>Schematic of the two series-connected SiC MOSFETs using the GBC method.</p> Full article ">Figure 7
<p>Schematic of the multiple series-connected SiC MOSFETs using the GBC method.</p> Full article ">Figure 8
<p>Set-up of the series-connected SiC MOSFETs using the GBC method.</p> Full article ">Figure 9
<p>Measured <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>G</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> waveforms of the two series-connected MOSFETs during the turn-off period without (<b>left</b>) and with the gate-coupled inductor with simulation verifications (<b>right</b>).</p> Full article ">Figure 10
<p>Measured <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> of the MOSFET string with (<b>left</b>) and without coupled inductor with simulation verifications (<b>right</b>).</p> Full article ">Figure 11
<p>Equivalent gate circuits of the two series-connected SiC MOSFETs using GBC method.</p> Full article ">Figure 12
<p><math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>G</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> curves of the MOSFET string during the turn-off delay with coupled inductor (<math display="inline"><semantics> <mrow> <mi>k</mi> <mo>=</mo> <mn>1</mn> </mrow> </semantics></math>).</p> Full article ">Figure 13
<p>The MATLAB Simulink model (gate circuits of two series-connected SiC MOSFETs) built based on the schematic of <a href="#electronics-13-01481-f011" class="html-fig">Figure 11</a>.</p> Full article ">Figure 14
<p><math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>G</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> waveforms of the two series-connected SiC MOSFETs using GBC method during off-period with inductor <math display="inline"><semantics> <mrow> <mi>k</mi> <mo>=</mo> <mn>0.9822</mn> </mrow> </semantics></math> (<b>left</b>) and <math display="inline"><semantics> <mrow> <mi>k</mi> <mo>=</mo> <mn>0.9999</mn> </mrow> </semantics></math> (<b>right</b>) performed in MATLAB Simulink.</p> Full article ">Figure 15
<p><math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> waveforms of the SiC MOSFET string using GBC method during off-period with coupled inductor <math display="inline"><semantics> <mrow> <mi>k</mi> <mo>=</mo> <mn>0.9822</mn> </mrow> </semantics></math> (<b>left</b>) and <math display="inline"><semantics> <mrow> <mi>k</mi> <mo>=</mo> <mn>0.9999</mn> </mrow> </semantics></math> (<b>right</b>) in case of <math display="inline"><semantics> <mrow> <mi>δ</mi> <msub> <mi>t</mi> <mrow> <mi>d</mi> <mrow> <mo>(</mo> <mrow> <mi>o</mi> <mi>f</mi> <mi>f</mi> </mrow> <mo>)</mo> </mrow> </mrow> </msub> </mrow> </semantics></math> = 500 ns (LTspice).</p> Full article ">Figure 16
<p>RC snubber circuit (<b>left</b>) and RCD snubber circuit (<b>right</b>).</p> Full article ">Figure 17
<p><math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> and <math display="inline"><semantics> <mrow> <msub> <mi>i</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> waveform of a IGBT during turn-off period.</p> Full article ">Figure 18
<p>Schematic of two types of passive clamping snubber circuit.</p> Full article ">Figure 19
<p>Schematic of two series-connected MOSFETs using improved RC snubber method (a).</p> Full article ">Figure 20
<p><math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> sharing of the SiC MOSFET string using a passive RC snubber with an extra 200 ns turn-off delay in the bottom switch without snubber (<b>left</b>) and with snubber (<b>right</b>).</p> Full article ">Figure 21
<p><math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> (<b>left</b>) and <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>G</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> during turn-off period (<b>right</b>) sharing of the SiC MOSFET string using the improved RC snubber method (a) with an extra 200 ns turn-off delay in the bottom switch with inductor.</p> Full article ">Figure 22
<p>Schematic of the two series-connected MOSFETs using improved RC snubber method (b).</p> Full article ">Figure 23
<p><math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> sharing of the SiC MOSFET string using the improved RC snubber method (b) with an extra 200 ns turn-off delay in the bottom switch without snubber (<b>left</b>) and with snubber without inductor (<b>right</b>). Repeated from <a href="#electronics-13-01481-f020" class="html-fig">Figure 20</a> for better comparison with <a href="#electronics-13-01481-f024" class="html-fig">Figure 24</a>.</p> Full article ">Figure 24
<p><math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> (<b>left</b>) and <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> during off-period (<b>right</b>) sharing of the SiC MOSFET string using improved RC snubber method (b) with a 200 ns turn-off delay in the bottom switch with inductor.</p> Full article ">Figure 25
<p>Schematic of four series-connected MOSFETs using improved RC snubber method (b).</p> Full article ">Figure 26
<p><math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> sharing of the SiC MOSFET string using the improved RC snubber method (b) with snubber but without inductors (<b>left</b>) and with snubber and inductor (<b>right</b>).</p> Full article ">Figure 27
<p>Experimental set-up of the four series-connected SiC MOSFETs (<b>left</b>) using improved RC snubber method (b) and measured <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>G</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> waveforms during off-period (<b>right</b>).</p> Full article ">Figure 28
<p>Measured <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> sharing of the four series-connected SiC MOSFETs using the improved RC snubber (b) without coupled inductors (<b>left</b>) and with coupled inductors (<b>right</b>).</p> Full article ">Figure 29
<p>Schematic of the SiC MOSFET string using the basic (<b>left</b>) and optimized (<b>right</b>) Zener clamping circuits.</p> Full article ">Figure 30
<p>Operation principle of two series-connected MOSFETs for optimized Zener clamping method.</p> Full article ">Figure 31
<p>Set-up of the three series-connected MOSFETs using Zener clamping method.</p> Full article ">Figure 32
<p><math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> overall waveforms (left) and <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> waveforms during off-period of the SiC MOSFET string with optimized Zener clamping circuits (<math display="inline"><semantics> <mrow> <mi>δ</mi> <msub> <mi>t</mi> <mrow> <mi>d</mi> <mrow> <mo>(</mo> <mrow> <mi>o</mi> <mi>f</mi> <mi>f</mi> </mrow> <mo>)</mo> </mrow> </mrow> </msub> <mo>=</mo> <mn>560</mn> <mo> </mo> <mi>ns</mi> </mrow> </semantics></math>).</p> Full article ">Figure 33
<p><math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> overall waveforms (<b>left</b>) and <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> waveforms during off-period (<b>right</b>) of the SiC MOSFET string with optimized Zener clamping circuits (<math display="inline"><semantics> <mrow> <mi>δ</mi> <msub> <mi>C</mi> <mrow> <mi>i</mi> <mi>s</mi> <mi>s</mi> <mrow> <mo>(</mo> <mn>2</mn> <mo>)</mo> </mrow> </mrow> </msub> <mo>=</mo> <mn>85</mn> <mo> </mo> <mi>pF</mi> </mrow> </semantics></math>).</p> Full article ">Figure 34
<p>Schematic of multiple (<math display="inline"><semantics> <mi>N</mi> </semantics></math>) series-connected SiC MOSFETs.</p> Full article ">Figure 35
<p>Schematic of the SiC MOSFET string driven by the optically isolated HV gate drivers.</p> Full article ">Figure 36
<p>The prototype of three series-connected MOSFETs controlled by HV gate driving circuit.</p> Full article ">Figure 37
<p>Measured <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> waveforms during off-period (<b>left</b>) and overall <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> waveforms (<b>right</b>).</p> Full article ">Figure 38
<p>Measured <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> waveform of the entire SiC MOSFET string with a voltage of 2.8 kV.</p> Full article ">Figure 39
<p>Schematic of the magnetically isolated gate driver based two series-connected MOSFETs (<b>left</b>) and two gate-coupled transformers (<b>right</b>).</p> Full article ">Figure 40
<p>Modulation waveforms for the generation of the transformer input pulses. The desired output waveform (in green) is modulated with on–off keying.</p> Full article ">Figure 41
<p>The desired bipolar and complementary modulation waveforms (gate-coupled transformer input pulses).</p> Full article ">Figure 42
<p>Schematic of the magnetically isolated HV gate driver based three series-connected SiC MOSFETs.</p> Full article ">Figure 43
<p><math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> overall waveforms (<b>left</b>) and <math display="inline"><semantics> <mrow> <msub> <mi>V</mi> <mrow> <mi>D</mi> <mi>S</mi> </mrow> </msub> </mrow> </semantics></math> during turn-off period (<b>right</b>) of the magnetically isolated gate driver based SiC MOSFET string.</p> Full article ">

Figure 1
<p>Equivalent circuit and flow of ringing conditions in inverter including parasitic elements.</p> Full article ">Figure 2
<p>Equivalent circuit and flow of ringing conditions in inverter including parasitic elements: (<b>a</b>) typical configuration; (<b>b</b>) configuration with capacitance in the high and low side; (<b>c</b>) configuration with a ringing suppression circuit of proposed systems.</p> Full article ">Figure 3
<p>Relationship between rotor position and speed of the motor in three reference frames.</p> Full article ">Figure 4
<p>Architecture of the motor control device.</p> Full article ">Figure 5
<p>Amplified and isolated PWM.</p> Full article ">Figure 6
<p>Configuration of IC GDC using IR2110PBF: (<b>a</b>) typical configuration; (<b>b</b>) improved configuration with conditioning signal achieved through amplification and isolation side.</p> Full article ">Figure 7
<p>Schematic of gate driver circuit using IR2110PBF with a conditioning and isolated side: (<b>a</b>) typical configuration; (<b>b</b>) configuration with capacitance in the high and low side; (<b>c</b>) configuration with a ringing suppression circuit of the proposed systems.</p> Full article ">Figure 8
<p>Effect of ringing switching behavior in the semiconductor material: (<b>a</b>) the behavior of ringing in power switching component; (<b>b</b>) voltage spike in typical configuration; (<b>c</b>) voltage spike of configuration using capacitance in the high and low side; (<b>d</b>) voltage spike of configuration using a ringing suppression circuit of the proposed systems.</p> Full article ">Figure 9
<p>Laboratory prototype of motor control devices.</p> Full article ">Figure 10
<p>Experimental setup.</p> Full article ">Figure 11
<p>Observation results for motor control devices using GDC with a typical configuration IR2110: (<b>a</b>) current phase A in 3A; (<b>b</b>) current phase B in 3A; (<b>c</b>) rotor position estimation in 3A.</p> Full article ">Figure 12
<p>Observation results for motor control devices using GDC and IR2110 with a capacitance filter in the high and low side: (<b>a</b>) current phase A in 3A; (<b>b</b>) current phase B in 3A; (<b>c</b>) rotor position estimation in 3A.</p> Full article ">Figure 13
<p>Observation results of motor control devices using the proposed GDC and IR2110 with the proposed improvement circuit: (<b>a</b>) current phase A in 3A; (<b>b</b>) current phase B in 3A; (<b>c</b>) rotor position estimation in 3A.</p> Full article ">Figure 14
<p>Result of noise reduction in motor current signals with different damping values.</p> Full article ">

Figure 1
<p>Single-task learning model (base model).</p> Full article ">Figure 2
<p>LSTM cell structure.</p> Full article ">Figure 3
<p>(<b>a</b>) Multi-task learning model, (<b>b</b>) Gated Sharing Unit [<a href="#B44-sustainability-16-02065" class="html-bibr">44</a>].</p> Full article ">Figure 4
<p>Demand correlation of taxis and TNCs at different temporal levels. (<b>a</b>) Monthly demand correlation, (<b>b</b>) Daily correlation for day of the week, (<b>c</b>) Hourly correlation for weekdays, (<b>d</b>) Hourly correlation for weekends.</p> Full article ">Figure 5
<p>Total temporal demand for taxis and TNCs. (<b>a</b>) Total monthly demand, (<b>b</b>) Total daily demand for day of the week, (<b>c</b>) Total hourly demand on weekdays, (<b>d</b>) Total hourly demand for weekends.</p> Full article ">Figure 6
<p>Demand correlation for taxis and TNCs.</p> Full article ">Figure 7
<p>Real and forecasted demand for (<b>a</b>) taxis, (<b>b</b>) TNCs.</p> Full article ">

Figure 1
<p>Schematic representation of the proposed inverter.</p> Full article ">Figure 2
<p>Switch (<math display="inline"><semantics> <msub> <mi>S</mi> <mn>1</mn> </msub> </semantics></math>) is conducting a positive current. (<b>a</b>) Positive current direction in a single-phase half-bridge inverter. (<b>b</b>) Highlighted switch current direction in the TCM of the filter inductor.</p> Full article ">Figure 3
<p>Blanking time-I. (<b>a</b>) Current directions during charging of <math display="inline"><semantics> <msub> <mi>C</mi> <mn>1</mn> </msub> </semantics></math> and discharging of <math display="inline"><semantics> <msub> <mi>C</mi> <mn>2</mn> </msub> </semantics></math> in a single-phase half-bridge inverter. (<b>b</b>) Highlighted blanking time (<math display="inline"><semantics> <msub> <mi>t</mi> <mrow> <mi>b</mi> <mn>1</mn> </mrow> </msub> </semantics></math>) in the TCM of the filter inductor.</p> Full article ">Figure 4
<p>Body diode (<math display="inline"><semantics> <msub> <mi>D</mi> <mn>2</mn> </msub> </semantics></math>) is conducting a positive current. (<b>a</b>) Positive current direction in a single-phase half-bridge inverter. (<b>b</b>) Highlighted diode current direction in the TCM of the filter inductor.</p> Full article ">Figure 5
<p>Switch (<math display="inline"><semantics> <msub> <mi>S</mi> <mn>2</mn> </msub> </semantics></math>) is conducting a positive current. (<b>a</b>) Positive current direction in a single-phase half-bridge inverter. (<b>b</b>) Highlighted switch current direction in the TCM of the filter inductor.</p> Full article ">Figure 6
<p>Switch (<math display="inline"><semantics> <msub> <mi>S</mi> <mn>2</mn> </msub> </semantics></math>) is conducting a negative current. (<b>a</b>) Negative current direction in a single-phase half-bridge inverter. (<b>b</b>) Highlighted switch current direction in the TCM of the filter inductor.</p> Full article ">Figure 7
<p>Blanking time-II. (<b>a</b>) Current directions during discharging of <math display="inline"><semantics> <msub> <mi>C</mi> <mn>1</mn> </msub> </semantics></math> and charging of <math display="inline"><semantics> <msub> <mi>C</mi> <mn>2</mn> </msub> </semantics></math> in a single-phase half-bridge inverter. (<b>b</b>) Highlighted blanking time (<math display="inline"><semantics> <msub> <mi>t</mi> <mrow> <mi>b</mi> <mn>2</mn> </mrow> </msub> </semantics></math>) in the TCM of the filter inductor.</p> Full article ">Figure 8
<p>Body diode (<math display="inline"><semantics> <msub> <mi>D</mi> <mn>1</mn> </msub> </semantics></math>) is conducting a negative current. (<b>a</b>) Negative current direction in a single-phase half-bridge inverter. (<b>b</b>) Highlighted diode current direction in the TCM of the filter inductor.</p> Full article ">Figure 9
<p>Switch (<math display="inline"><semantics> <msub> <mi>S</mi> <mn>1</mn> </msub> </semantics></math>) is conducting a negative current. (<b>a</b>) Negative current direction in a single-phase half-bridge inverter. (<b>b</b>) Highlighted switch current direction in the TCM of the filter inductor.</p> Full article ">Figure 10
<p>Schematic diagram of AGDs.</p> Full article ">Figure 11
<p>Motor control scheme for generation of reference currents.</p> Full article ">Figure 12
<p>Operation of the proposed AGD. (<b>a</b>) Generation of turn-on signal. (<b>b</b>) Generation of turn-off signal. (<b>c</b>) Generation of <math display="inline"><semantics> <msub> <mi>V</mi> <mrow> <mi>g</mi> <mi>s</mi> </mrow> </msub> </semantics></math> signal.</p> Full article ">Figure 13
<p>Adaptive blanking time for high-side (<math display="inline"><semantics> <msub> <mi>S</mi> <mn>1</mn> </msub> </semantics></math>) and low-side (<math display="inline"><semantics> <msub> <mi>S</mi> <mn>2</mn> </msub> </semantics></math>) switches. The dark blue rectangle represents <math display="inline"><semantics> <msub> <mi>V</mi> <mrow> <mi>g</mi> <mi>s</mi> </mrow> </msub> </semantics></math> of the low-side switch (<math display="inline"><semantics> <msub> <mi>S</mi> <mn>2</mn> </msub> </semantics></math>), while the light blue rectangle represents <math display="inline"><semantics> <msub> <mi>V</mi> <mrow> <mi>g</mi> <mi>s</mi> </mrow> </msub> </semantics></math> of the high-side switch (<math display="inline"><semantics> <msub> <mi>S</mi> <mn>1</mn> </msub> </semantics></math>). The red curve represents the filter inductor current.</p> Full article ">Figure 14
<p>Filter inductor current with (<b>a</b>) reference currents and (<b>b</b>) average output current.</p> Full article ">Figure 15
<p>Variations in switching frequency based on filter inductor current (red) and impact of filter inductor current on capacitor voltage ripples (dark blue) in one line cycle from 20 ms to 40 ms at (<b>a</b>) 20 ms, (<b>b</b>) 25 ms, (<b>c</b>) 30 ms, (<b>d</b>) 35 ms.</p> Full article ">Figure 16
<p>Turn-on ZVS analysis.</p> Full article ">Figure 17
<p>Turn-off switching losses for one line cycle (50 Hz, 20 ms): (<b>a</b>) 20 ms, (<b>b</b>) 22 ms, (<b>c</b>) 24 ms, (<b>d</b>) 26 ms, (<b>e</b>) 28 ms, (<b>f</b>) 30 ms, (<b>g</b>) 32 ms, (<b>h</b>) 34 ms, (<b>i</b>) 36 ms, (<b>j</b>) 38 ms.</p> Full article ">Figure 18
<p>Estimation of switching energies for one line cycle (50 Hz, 20 ms) with equally distributed 10 points. (<b>a</b>) Turn-on switching energy. (<b>b</b>) Turn-off switching energy.</p> Full article ">Figure 19
<p>Inverter power losses breakdown.</p> Full article ">Figure 20
<p>Sinusoidal output waveforms of phase currents, phase voltages, and line voltages.</p> Full article ">Figure 21
<p>Harmonic spectrum: (<b>a</b>) phase current (<math display="inline"><semantics> <msub> <mi>I</mi> <mi>an</mi> </msub> </semantics></math>) and (<b>b</b>) line voltage (<math display="inline"><semantics> <msub> <mi>V</mi> <mi>ab</mi> </msub> </semantics></math>).</p> Full article ">Figure 22
<p>Variation in filter inductor current ripples due to changes in reference currents: (<b>a</b>) 140 A, (<b>b</b>) 124 A, (<b>c</b>) 104 A, (<b>d</b>) 80 A.</p> Full article ">Figure 23
<p>Variation in phase current (average inductor current) due to changes in reference currents: (<b>a</b>) 35 A, (<b>b</b>) 31 A, (<b>c</b>) 26 A, (<b>d</b>) 20 A.</p> Full article ">Figure 24
<p>Variation in phase voltages due to changes in reference currents: (<b>a</b>) 225 V, (<b>b</b>) 200 V, (<b>c</b>) 170 V, (<b>d</b>) 134 V.</p> Full article ">Figure 25
<p>Variation in efficiency with changes in load power.</p> Full article ">Figure 26
<p>Impact of die area on conduction losses (red dash curve) and switching losses (black dash-dotted curve) for the hard-switched converter.</p> Full article ">