VCO

The PLL is a feedback system used to generate clock signal in microprocessors, and frequency multiplication (FM) etc., The PLL consists of several components such as Phase frequency detector (PFD), Charge pump (CP), low pass filter (LPF), voltage controlled oscillator (VCO) and frequency divider (FD) circuits. The struck at single-event-effects (SEEs) such as latch-up, single-event-transient and multiple bit upsets which affect the PLL performance. PFD and FD which are free from dead zone due to their digital characteristics but the CP are affected by SEEs which causes the CP output to be degraded and which affect the VCO input hence PLL will lose lock. The PLL and its components are implemented in cadence virtuoso tool using 180nm technology.

Designing of an analog circuit satisfying the design constraints for desired application is a challenging job. Phase Lock Loop (PLL) is an important analog circuit used in various communication applications such as frequency synthesizer, radio, computer, clock generation, clock recovery, global positioning system, etc. Since all these applications are operating at different frequency, satisfying design constraints for PLL with respect to type of PLL operating frequency, Bandwidth, Settling time and other parameters is an critical and time consuming issue. In this paper, selection and design for Second order and third order PLL suggested using MATLAB, Simulink as a simulation tool. The simulated results for the design PLL at 450 MHz indicates good accuracy when the behavior model is compared with the mathematical model. Finally the performance of PLL is tested and calculated for parameters like lock time, lock range, Bandwidth.

This paper presents a new technique to improve frequency performance of CMOS ring oscillator. It is based on the addition of MOS transistor to boost switching speed of the oscillator delay cell. The method can be used for simple and differential oscillator and offers a simple way to implement frequency tuning without introduction of any additional phase noise. Using 0.35 μm CMOS technology, simulation results show that applying the technique to the simple ring oscillator allows a frequency oscillation improvement of 80%. Also, simulations show that frequency improvement can reach 300 % if the technique is associated to a positive feedback.

This paper presents an improved design of voltage
controlled oscillator (VCO)  utilizing the three differential cell
CMOS inverters for forming the ring oscillator. The differential
cell reduces the power supply fluctuations impact on the
oscillator jitter while the negative feedback from frequency to
voltage converter reduces the jitter at high frequencies. Finally
the proposed model is designed using CMOS 0.18um foundry
technology and simulated using P-Spice software. The result
shows that the proposed design improves the jitter attenuation at
different offset frequencies up to 40dB.

In this article innovative low jitter low phase noise 7.47 GHz DPLL with self-aligned
DLL in 180 nm CMOS technology is implemented and analyzed. Based on proposed
innovative concept, phase difference between injection signal and SILVCO in PLL can be
aligned to reduce jitter and phase noise over all variations. Hence it can be achieved low
phase noise and low jitter.
At 7.47 GHz, the measured phase noise of proposed DPLL with self-aligned injection
at 1-MHz offset is 124.40 dBc/Hz with a rms jitter of 110 fs. The total dc power
consumption is 27.72 mW. With self-aligned injection, proposed DPLL features the lowest
jitter, phase noise, and best figure of merit among reported CMOS PLLs.

In this paper, a 4.2–5.4 GHz, −Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35 μm SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). According to post-layout simulation results, phase noise is −110.7 dBc/Hz at 1 MHz offset from 5.4 GHz carrier frequency and −113.4 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained from the simulations, utilizing accumulation-mode varactors. Phase noise was also found to be relatively low because of taking advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. Based on the simulation results, the circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit layout occupies an area of 0.6 mm2 on Si substrate, including DC and RF pads. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.

This letter presents a low phase noise triple-band voltage-controlled oscillator (VCO). The designed circuit consists of a dual-resonance LC-tank VCO and a single-resonance LC-tank VCO. The two sub-VCOs are coupled via transformers and varactors. The net LC resonator has three main resonant frequencies selectable by controlling the bias of varactors. The proposed VCO has been fabricated with the TSMC 0.18 $mu$m 1P6M CMOS technology. The VCO can generate differential signals in the frequency range of 2.80–3.57, 7.43–7.65, and 8.23–8.77 GHz with core power consumption of 3.3, 4, and 4.2 mW at the dc drain-source bias of 0.65 V, respectively. At 3.49, 7.53, and 8.52 GHz phase noises at 1 MHz offset are ${-}123.06$ dBc/GHz, ${-}119.62$ dBc/Hz, and ${-}118.34$ dBc/Hz, respectively. The die area of the triple-band VCO is 0.626$, times ,$0.912 mm$^{2}$.

In conventional receivers, carrier recovery and timing recovery are performed in the analog domain by controlling the frequency and phase of voltage controlled oscillators (VCO) in their respective phase locked loop (PLL). When the control signal for these loops are generated in the sampled data domain by DSP techniques the digital samples must be brought to the analog domain by a pair of digital-to-analog converters (DAC). It is more cost effective to perform the entire signal processing function of the PLL in the digital domain and avoid the cost of the DAC and analog smoothing filter in the processing loops. In the full DSP implementation the receiver performs an initial complex down conversion with an asynchronous local oscillator set to the nominal final conversion frequency and then absorbs the residual carrier and phase uncertainty by data dependent control of a digital complex rotator. In a similar fashion sample timing is performed by the sampling the input signal with an asynchronous sampling clock operating at nominally twice the symbol rate and then absorbs residual frequency and phase of the sampling clock by resampling the data with a polyphase filter bank

This paper proposes a dual-conduction class-C CMOS VCO for ultra-low supply voltages. Two cross-coupled NMOS pairs with different bias points are employed, which realize impulselike current waveform to improve the phase noise in the low supply conditions. The proposed VCO was implemented in a standard 0.18 μm CMOS technology, which oscillates at a carrier frequency of 4.5GHz with a 0.2-V

In conventional receivers, carrier recovery and timing recovery are performed in the analog domain by controlling the frequency and phase of voltage controlled oscillators (VCO) in their respective phase locked loop (PLL). When the control signal for these loops are generated in the sampled data domain by DSP techniques the digital samples must be brought to the analog domain by a pair of digital-to-analog converters (DAC). It is more cost effective to perform the entire signal processing function of the PLL in the digital domain and avoid the cost of the DAC and analog smoothing filter in the processing loops. In the full DSP implementation the receiver performs an initial complex down conversion with an asynchronous local oscillator set to the nominal final conversion frequency and then absorbs the residual carrier and phase uncertainty by data dependent control of a digital complex rotator. In a similar fashion sample timing is performed by the sampling the input signal with an asynchronous sampling clock operating at nominally twice the symbol rate and then absorbs residual frequency and phase of the sampling clock by resampling the data with a polyphase filter bank

— A low phase noise, power efficient VCO using UMC 0.18µm CMOS technology has been proposed in this paper. The proposed VCO has a tuning range of 9.71GHz to 9.9GHz, with a phase noise of-79.88 dBc/Hz @ 600kHz offset. The Vtune ranging between 1V- 1.5V generates sustained oscillations. The maximum power consumption of the VCO is 11.9mW using a supply voltage of 1.8V with ±10 % variation.