Boundary Scan

The requirements on tools to support the debugging work flow in embedded systems designs have increased drastically. Analysis shows  that every  five years  we are faced with processors  which have doubled their pin count.  Looking at  the count of  transistors  within a chip we find  a two year doubling  rate (Moors’s Law). This evolution not only brings us Systems on Chip (SoC) devices with  an increased complexity but also  raises the  chance of bugs. Multicore-SoC and the trend  to replace hardware by  software only serve to increase this phenomenon.  Every manufacturer of  microcontrollers or SoC  devices tries to find a  solution to  this problem with their own created Integrated Development  Environment (IDE) and their specially defined debug interfaces. The user is put in an almost  helpless situation, flooded by information on technical advantages and disadvantages of  each privileged system. This situation is reinforced by  products  from software and hardware providers specialized on  debugging tools.  This thesis researches the present hardware and software debug concepts,  their key features and preferred areas of application. The work shows a path through the forest of debug concepts and may help designers to make their system decision more assured.

In this paper, we describe a training environment based on multi-functional software system called “Trainer 1149”. It provides simulation and demonstration functionality for learning, research, and development related to IEEE 1149.1 Boundary Scan (BS) standard. The software supports both the analytic and synthetic learning process. Trainer 1149 is the main component of a recent goJTAG initiative that aims at creating of an open-source platform for learning and working with BS. Trainer 1149 provides a cozy graphical design and simulation environment of BS-enabled chips and non-BS clusters. It is also possible to simulate the behaviour of various interconnect faults and inspect them using interactive tools. Using a convenient low-cost USB-JTAG cable, one can test real defects in real hardware. The system is implemented using multi-platform Java environment and distributed as an open-source freeware. Such combination of features is unique for public domain BS software.

An implementation of IEEE 1149.1 TAP controller is presented in this paper. JTAG is an established technology and industry standard for on-chip boundary scan testing of SoCs. JTAG TAP controllers are becoming a delivery and control mechanism for Design For Test. The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications.

Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC.

Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is, however, still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed, and a corresponding set of testability blocks is proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs (programmable logic devices), using a simple and powerful HDL (hardware design language)

In this paper we address the problem of verifying the equivalence of two sequential circuits. State-of-the-art sequential optimization techniques such as retiming and sequential redundancy removal can handle designs with up to hundreds or even thousands of flip-flops. However, the BDD-based approaches for verifying sequential equivalence can easily run into memory explosion for such designs. In an attempt to handle larger circuits, we modify test pattern-generation techniques for verification. The suggested approach utilizes the popular efficient backward-justification technique used in most sequential ATPG programs. We present several techniques to enhance the efficiency of this approach by (1) identifying equivalent flip-flop pairs using an induction-based algorithm, and (2) generalizing the idea of exploring the structural similarity between circuits to perform verification in stages. This ATPG-based framework is suitable for verifying circuits either with or without a reset stat...

In this paper we address the problem of verifying the equivalence of two sequential circuits. State-of-the-art sequential optimization techniques such as retiming and sequential redundancy removal can handle designs with up to hundreds or even thousands of flip-flops. However, the BDD-based approaches for verifying sequential equivalence can easily run into memory explosion for such designs. In an attempt to handle larger circuits, we modify test pattern-generation techniques for verification. The suggested approach utilizes the popular efficient backward-justification technique used in most sequential ATPG programs. We present several techniques to enhance the efficiency of this approach by (1) identifying equivalent flip-flop pairs using an induction-based algorithm, and (2) generalizing the idea of exploring the structural similarity between circuits to perform verification in stages. This ATPG-based framework is suitable for verifying circuits either with or without a reset stat...