ABSTRACT Spintronic memories are promising candidates for future on-chip storage due to their high density, non-volatility and near-zero leakage. However, the energy consumed by read and write operations presents a major challenge to... more
ABSTRACT Spintronic memories are promising candidates for future on-chip storage due to their high density, non-volatility and near-zero leakage. However, the energy consumed by read and write operations presents a major challenge to their use as energy-efficient on-chip memory. Leveraging the ability of many applications to tolerate impreciseness in their underlying computations and data, we explore approximate storage as a new approach to improving the energy efficiency of spintronic memories. We identify and characterize mechanisms in STT-MRAM bit-cells that provide favorable energy-quality trade-offs, i.e., disproportionate energy improvements at the cost of small probabilities of read/write failures. Based on these mechanisms, we design a quality-configurable memory array in which data can be stored to varying levels of accuracy based on application requirements. We integrate the quality-configurable array as a scratchpad in the memory hierarchy of a programmable vector processor and expose it to software by introducing quality-aware load/store instructions within the ISA. We evaluate the energy benefits of our proposal using a device-to-architecture modeling framework and demonstrate 40% and 19.5% improvement in memory energy and overall application energy respectively, for negligible (< 0.5%) quality loss across a suite of recognition and vision applications.
ABSTRACT Memory-based physical unclonable functions (PUFs) have been studied and developed as powerful primitives to generate device-specific random keys, which can be used for various security applications. However, the existing... more
ABSTRACT Memory-based physical unclonable functions (PUFs) have been studied and developed as powerful primitives to generate device-specific random keys, which can be used for various security applications. However, the existing memory-based PUFs need to safely buffer the data bits in the memory before it is used to produce random bits, resulting in additional area/energy consumption and potential data security issues. In this paper, we propose a new memory-based PUF that exploits the nonvolatility and random variability of emerging memory technologies to produce random bits. Unlike conventional implementations, the random bit generation process of our proposed PUF does not disturb the data bits already stored in the memory. To satisfy the quality requirements for both memory and PUF applications, we also propose a general method to find the optimal design point of emerging nonvolatile memory (eNVM)-based PUF. An illustrative design using spin-transfer torque magnetic RAM exhibits desirable results using our method. Compared to the conventional types of memory-based PUFs, eNVM-based PUFs features enhanced security as cryptographic primitives and lower area and energy cost as data storage.
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ABSTRACT Memory-based physical unclonable function (MemPUF) has gained tremendous popularity in the recent years to securely preserve secret information in computing systems. Most MemPUFs in the literature have unreliable bit generation... more
ABSTRACT Memory-based physical unclonable function (MemPUF) has gained tremendous popularity in the recent years to securely preserve secret information in computing systems. Most MemPUFs in the literature have unreliable bit generation and/or are incapable of generating more than one response-bit per cell. Hence, we propose a novel MemPUF exploiting the unique characteristics of spin-transfer torque magnetic RAM (STT-MRAM) that can overcome these issues. Bit generation in our STT-MRAM-based MemPUF is stabilized using a novel automatic write-back technique. In addition, the alterability of the magnetic tunneling junction state is exploited to expand the response-bit capacity per cell. Our analysis demonstrated the advantage of our scheme in reliability enhancement (bit-error rate from to in the worst case under varying conditions) and response-bit capacity per cell improvement (from 1 to 1.48 bit). In comparison with the conventional MemPUFs, our approach is also better in terms of the average chip area and energy for producing a response-bit.
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ABSTRACT Nanoelectronic devices that mimic the functionality of synapses are a crucial requirement for performing cortical simulations of the brain. In this work we propose a ferromagnet-heavy metal heterostructure that employs spin-orbit... more
ABSTRACT Nanoelectronic devices that mimic the functionality of synapses are a crucial requirement for performing cortical simulations of the brain. In this work we propose a ferromagnet-heavy metal heterostructure that employs spin-orbit torque to implement Spike-Timing Dependent Plasticity. The proposed device offers the advantage of decoupled spike transmission and programming current paths, thereby leading to reliable operation during online learning. Possible arrangement of such devices in a crosspoint architecture can pave the way for ultra-dense neural networks. Simulation studies indicate that the device has the potential of achieving pico-Joule level energy consumption (maximum 2 pJ per synaptic event) which is comparable to the energy consumption for synaptic events in biological synapses.
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ABSTRACT This paper reviews the potential of spin-transfer torque devices as an alternative to complementary metal-oxide-semiconductor for non-von Neumann and non-Boolean computing. Recent experiments on spin-transfer torque devices have... more
ABSTRACT This paper reviews the potential of spin-transfer torque devices as an alternative to complementary metal-oxide-semiconductor for non-von Neumann and non-Boolean computing. Recent experiments on spin-transfer torque devices have demonstrated high-speed magnetization switching of nanoscale magnets with small current densities. Coupled with other properties, such as nonvolatility, zero leakage current, high integration density, we discuss that the spin-transfer torque devices can be inherently suitable for some unconventional computing models for information processing. We review several spintronic devices in which magnetization can be manipulated by current induced spin transfer torque and explore their applications in neuromorphic computing and reconfigurable memory-based computing.
... Joo Lee Boeing Seema Bhandari Cisco Fese Joy Epie Cisco Rebika Getachew Yitna Cisco Sujata Sen Hewlett-Packard Ana Maria Yepes Hewlett ... 0 Ph.D. students graduated 9 students received doctorates - a new record Summer 2006 Mubashir... more
... Joo Lee Boeing Seema Bhandari Cisco Fese Joy Epie Cisco Rebika Getachew Yitna Cisco Sujata Sen Hewlett-Packard Ana Maria Yepes Hewlett ... 0 Ph.D. students graduated 9 students received doctorates - a new record Summer 2006 Mubashir Alam McClellan Localization of ...
ABSTRACT In this paper, we present two multilevel spin-orbit torque magnetic random access memories (SOT-MRAMs). A single-level SOT-MRAM employs a three-terminal SOT device as a storage element with enhanced endurance, close-to-zero read... more
ABSTRACT In this paper, we present two multilevel spin-orbit torque magnetic random access memories (SOT-MRAMs). A single-level SOT-MRAM employs a three-terminal SOT device as a storage element with enhanced endurance, close-to-zero read disturbance, and low write energy. However, the three-terminal device requires the use of two access transistors per cell. To improve the integration density, we propose two multilevel cells (MLCs): 1) series SOT MLC and 2) parallel SOT MLC, both of which store two bits per memory cell. A detailed analysis of the bit-cell suggests that the S-MLC is promising for applications requiring both high density and low write-error rate, and P-MLC is particularly suitable for high-density and low-write-energy applications. We also performed iso-bit-cell area comparison of our MLC designs with previously proposed MLCs that are based on spin-transfer torque MRAM and show 3-16× improvement in write energy.
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ABSTRACT This paper proposes a domain-wall-coupling-based magnetic device for high-speed and robust on-chip cache applications. The read and write current paths are magnetically coupled and electrically isolated, which significantly... more
ABSTRACT This paper proposes a domain-wall-coupling-based magnetic device for high-speed and robust on-chip cache applications. The read and write current paths are magnetically coupled and electrically isolated, which significantly improves the reliability of the read and write operations. Our proposed device makes use of fast and energy-efficient domain wall motion for write operation. A complementary polarizer structure is used to achieve low-power, high-speed, and high-sensing margin read operations. A device-to-circuits simulation framework was also developed to evaluate our proposed multiterminal domain-wall-coupling-based spin-transfer torque (DWCSTT) magnetic random access memory (MRAM) cell. Compared with the conventional 1T-1MTJ STT-MRAM bit cell, the proposed DWCSTT bit cell achieves > 3.5× improvement in write power under iso-area and iso-write margin conditions, and 3× better sensing margin with low read power consumption and higher read disturb margin.
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ABSTRACT Optical interconnect has emerged as the front-runner to replace electrical interconnect especially for off-chip communication. However, a major drawback with optical interconnects is the need for photodetectors and amplifiers at... more
ABSTRACT Optical interconnect has emerged as the front-runner to replace electrical interconnect especially for off-chip communication. However, a major drawback with optical interconnects is the need for photodetectors and amplifiers at the receiver, implemented usually by direct bandgap semiconductors and analog CMOS circuits, leading to large energy consumption and slow operating time. In this article, we propose a new optical interconnect architecture that uses a magnetic tunnel junction (MTJ) at the receiver side that is switched by femtosecond laser pulses. The state of the MTJ can be sensed using simple digital CMOS latches, resulting in significant improvement in energy consumption. Moreover, magnetization in the MTJ can be switched on the picoseconds time-scale and our design can operate at a speed of 5 Gbits/sec for a single link.
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ABSTRACT The feasibility and quality of Memory-based Physical Unclonable Functions (MemPUFs) based on emerging Non-Volatile Memory (eNVM) technologies (Spin-Transfer Torque Magnetic Random Access Memory, Phase Change RAM, and Resistive... more
ABSTRACT The feasibility and quality of Memory-based Physical Unclonable Functions (MemPUFs) based on emerging Non-Volatile Memory (eNVM) technologies (Spin-Transfer Torque Magnetic Random Access Memory, Phase Change RAM, and Resistive RAM) are studied in this paper. MemPUFs using the three technologies were evaluated in terms of reliability, uniqueness and randomness using different sensing modes and under varying operating conditions. Our results show that eNVM based MemPUFs with differential sensing mode exhibit good randomness and reliability. As compared to conventional MemPUFs, eNVM based MemPUFs are better in terms of area cost.
ABSTRACT In recent years, Physical Unclonable Function (PUF) based on the inimitable and unpredictable disorder of physical devices has emerged to address security issues related to cryptographic key generation. In this paper, a novel... more
ABSTRACT In recent years, Physical Unclonable Function (PUF) based on the inimitable and unpredictable disorder of physical devices has emerged to address security issues related to cryptographic key generation. In this paper, a novel memory-based PUF based on Spin-Transfer Torque (STT) Magnetic RAM, named as STT-PUF, is proposed as a key generation primitive for embedded computing systems. By comparing the resistances of STT-MRAM memory cells which are initialized to the same state, response bits can be generated by exploiting the inherent random mismatches between them. To enhance the robustness of response bits regeneration, an Automatic Write-Back (AWB) technique is proposed without compromising the resilience of STT-PUF against possible attacks. Simulations show that the proposed STT-PUF is able to produce raw response bits with uniqueness of 50.1% and entropy of 0.985 bit per cell. The worst-case Bit-Error Rate (BER) under varying operating conditions is 6.6 × 10-6.
ABSTRACT Multiferroic tunnel junctions (MFTJs) consisting of ferromagnetic contacts sandwiching a ferroelectric tunnel barrier have been proposed as possible data storage elements. However, a simulation framework is needed for evaluating... more
ABSTRACT Multiferroic tunnel junctions (MFTJs) consisting of ferromagnetic contacts sandwiching a ferroelectric tunnel barrier have been proposed as possible data storage elements. However, a simulation framework is needed for evaluating and analyzing the design and performance of memory cells based on MFTJs. In this paper, we propose a spin-charge mixed-mode simulation framework that captures the device physics of the MFTJ for SPICE circuit simulations.
ABSTRACT A spin-transfer torque MRAM with complementary polarizers, suitable for on-chip caches, is proposed in this paper. The average critical current for write in our proposed structure is lower than standard STT-MRAM, improving... more
ABSTRACT A spin-transfer torque MRAM with complementary polarizers, suitable for on-chip caches, is proposed in this paper. The average critical current for write in our proposed structure is lower than standard STT-MRAM, improving write-ability and reliability. Our proposed structure also has self-referencing differential read operation having subnanosecond read delay, and lower read disturb torque, improving sensing margin and disturb margin by 20%-60% and 55%-70% over standard STT-MRAM, respectively.
ABSTRACT Emerging spin-torque phenomena, like Spin Hall Effect (SHE), may lead to high-speed, low-voltage current-mode switches based on nano-scale magnets. In this work we propose and analyze the application of such spin-torque switches... more
ABSTRACT Emerging spin-torque phenomena, like Spin Hall Effect (SHE), may lead to high-speed, low-voltage current-mode switches based on nano-scale magnets. In this work we propose and analyze the application of such spin-torque switches in the design of energy-efficient and high-performance current-mode on-chip global-interconnects. Simulations show the possibility of achieving up to two order of magnitude higher energy-efficiency as compared to conventional CMOS techniques, for optimal spin-device parameters. A case study for on-chip MRAM cache simulation shows ~90% reduction in energy for on-chip memory access, using the proposed interconnect design.
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Transistor scaling has enabled more memory to be embedded on-chip to accelerate large scale applications. However, increased leakage current in scaled technologies resulted in higher standby power consumption in volatile memories.... more
Transistor scaling has enabled more memory to be embedded on-chip to accelerate large scale applications. However, increased leakage current in scaled technologies resulted in higher standby power consumption in volatile memories. Nonvolatile memories have been researched and developed as solutions to these problems. However, non-volatile memories such as Flash or magnetic spin torque memories require large drive currents. On the
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ABSTRACT In this paper we have presented a comprehensive analysis of multi-valued STT-MRAM and their benefits and drawbacks. Results shows that in order to reduce read failures in scaled geometries, self-reference reading scheme is... more
ABSTRACT In this paper we have presented a comprehensive analysis of multi-valued STT-MRAM and their benefits and drawbacks. Results shows that in order to reduce read failures in scaled geometries, self-reference reading scheme is necessary. We have also shown that by choosing appropriate RA1 and RA2 (we define the feasible RA1-RA2 region in the design space), one can reduce both read and write failures. However, in order to achieve higher reliability, a thicker T ox is needed, which can further constrain the RA1-RA2 design space of multi-valued STT-MRAMs.
ABSTRACT Bi-directional write current for writing '1' and '0', and shared read and write current paths severely limit the design space of spin-transfer torque MRAMs (STT-MRAM). Failure mitigation techniques... more
ABSTRACT Bi-directional write current for writing '1' and '0', and shared read and write current paths severely limit the design space of spin-transfer torque MRAMs (STT-MRAM). Failure mitigation techniques proposed in the literature may be insufficient for realizing the full potential of STT-MRAMs at scaled MTJ dimensions due to asymmetries in MTJ characteristics and in access transistor drive-ability. This paper shows how STT-MRAM based on multi-terminal structures can overcome some of the above design constraints, leading to robust low-power STT-MRAM suitable for on-chip cache applications.
ABSTRACT Random numbers are useful in Monte Carlo simulations, cryptographic key generation and many other security applications. A spin dice was proposed as a 1-bit true random number generator implemented using conventional... more
ABSTRACT Random numbers are useful in Monte Carlo simulations, cryptographic key generation and many other security applications. A spin dice was proposed as a 1-bit true random number generator implemented using conventional spin-transfer torque (STT) MRAM, shown in Fig. 1 (we call this cSD), and an m-bit random number may be generated by concatenating m spin dies. The operation of cSD requires three sequential steps as illustrated in Fig. 2: 1) reset the cSD to a known state; 2) stochastic programming of the cSD by current-driven STT (rolling the dice); and 3) sensing the final state of the cSD. However, several design issues limit the efficacy of cSD. Steps 1 and 2 are required to randomize the state of the cSD. The final state of cSD is sensed by passing a current through the magnetic tunnel junction (MTJ) in the cSD. Under thermal fluctuations and process variations, the current flowing through the MTJ during sensing may bias the final state of the cSD in a similar way that STT MRAM is affected by read disturbance problem. Hence, the randomness cSD is degraded because the current paths for programming and sensing are shared. Increasing the activation energy (EA) of the MTJ increases the current required to flip the MTJ state during sensing operations and mitigates the sensing bias in cSD. However, doing so increases the critical switching current (IC) needed to program the MTJ and hence, increase the power consumed by the cSD.
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AbstractSpin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However,... more
AbstractSpin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future embedded applications. It provides desirable memory attributes such as fast access time, low cost, high density and non-volatility. However, variations in process parameters can lead ...
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ABSTRACT Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) is a promising candidate for future on-chip memory, owing to its high-density, zero-leakage and energy efficiency. In a conventional STT-MRAM cache write operations... more
ABSTRACT Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) is a promising candidate for future on-chip memory, owing to its high-density, zero-leakage and energy efficiency. In a conventional STT-MRAM cache write operations consume larger energy as compared to read, due to relatively large write-current requirement. In recent years novel spin-torque based write schemes have been proposed for MRAM that can bring large reduction in write energy, such that the read-energy now becomes dominant. Conventional read schemes based on CMOS sense amplifiers may not offer commensurate reduction in read energy, owing to their poor scalability and limited speed. We propose a spin-torque based sensing technique for MRAM that employs nano-scale spin-torque switches for low-voltage, low-current read-operations in STT-MRAM. Such a sensing-scheme can achieve improved-scalability, simplified-design for read-peripherals, high-speed read-operations and 90% lower read-energy. As a result more than ~80% reduction in overall energy can be obtained for STT-MRAM based caches.
ABSTRACT Reducing the energy dissipation for on-chip memory access and the associated data transport is critical for emerging chip multiprocessors (CMP). STT-MRAM is a promising technology for future on-chip memories, owing to its... more
ABSTRACT Reducing the energy dissipation for on-chip memory access and the associated data transport is critical for emerging chip multiprocessors (CMP). STT-MRAM is a promising technology for future on-chip memories, owing to its attractive features like non-volatility, zero-leakage and high-density. In an MRAM, read-access and data-transport can dominate the energy-dissipation (owing to negligible leakage power and more frequent read as compared to write operations). We propose the application of nano-scale spin-torque switches for low energy MRAM access. Such spin torque switches can act as fast, compact and ultra-low voltage current-sensors that can be used to perform low-power read operations in MRAM. Such spin-torque sensors (STS) can also facilitate ultra-low voltage, current-mode data transport over global interconnects, thereby reducing the energy dissipation on data buses by more than 99%. Simulation results for 2-level MRAM-cache design using such a STS device shows the possibility of ~90% reduction in memory access power as compared to conventional techniques.
Super cut-off devices with sub-60mV/decade subthreshold swings have recently been demonstrated and being extensively studied. This paper presents a feasibility analysis of such tunneling devices for ultralow power subthreshold logic.... more
Super cut-off devices with sub-60mV/decade subthreshold swings have recently been demonstrated and being extensively studied. This paper presents a feasibility analysis of such tunneling devices for ultralow power subthreshold logic. Analysis shows that this device can deliver 800X higher performance (@iso-IOFF) compared to a MOSFET. The possible use of this device as a sleep transistor in conjunction with the regular
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ABSTRACT The emergence of spin-transfer torque magnetic RAM (STT-MRAM) as a leading candidate for future high-performance nonvolatile memory has led to increased research interest. Current STT-MRAM technology faces several major obstacles... more
ABSTRACT The emergence of spin-transfer torque magnetic RAM (STT-MRAM) as a leading candidate for future high-performance nonvolatile memory has led to increased research interest. Current STT-MRAM technology faces several major obstacles in attaining its potential. One of the major issues is in the design of 1T-1MTJ STT-MRAM bit-cells under process variations: the bit-cells need to be significantly upsized to improve bit-cell failure, resulting in increased bit-cell area and power dissipation. In this paper, we analyze four circuit-level solutions that enable smaller 1T-1MTJ STT-MRAM bit-cells with improved yield, namely, bit-line voltage boosting, word-line voltage boosting, access transistor body biasing, and an applied external magnetic field. Results from simulation using 45-nm bulk CMOS access transistor and 40-nm magnetic tunneling junction technology show that word-line voltage boosting can be the best failure mitigation technique. Bit-cells designed with word-line boosting for write has a bit-cell area reduced by ${>}{75%}$ at iso-failure probability, compared to bit-cells without any failure mitigation technique. When bit-cell failure probability is optimized instead, 5 Oe of applied external magnetic field assisted write reduces power consumption by ${>}{15%}$, compared to bit-cells designed without failure mitigation techniques.
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Research Interests: Nanotechnology, Architecture and Memory, Reading and writing, Magnetic Random Access Memory, Mixed Mode, and 11 moreSilicon on Insulator, Current Density, Low Power, Non-Volatile Memory Technologies, Mathematical Model, High Speed, OPTIMIZATION TECHNIQUE, High Density Concrete, Electrical And Electronic Engineering, Simulation Framework, and Circuit Optimization
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ABSTRACT A novel nonvolatile flip-flop (NVFF) using a magnetic tunnel junction (MTJ) is presented for power gating architecture. The proposed NVFF exploits spin Hall effect (SHE) for fast and low-power data backup into MTJs before the... more
ABSTRACT A novel nonvolatile flip-flop (NVFF) using a magnetic tunnel junction (MTJ) is presented for power gating architecture. The proposed NVFF exploits spin Hall effect (SHE) for fast and low-power data backup into MTJs before the power is gated off. Owing to the high spin injection efficiency of SHE, the estimated write current for ${<}{rm 10}hbox{-}{rm ns}$ backup operation is lower than 40 $mu{rm A}$. Due to the low write current requirement, we do not introduce a dedicated write driver circuit. Instead, we utilize the cross-coupled inverters in the slave latch to perform the backup operation, resulting in low area overhead. The simulation results show $10times$ improvement in backup energy when compared with previous works on spin transfer torque-based NVFFs.
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ABSTRACT We present a new spin-transfer torque magnetic random access memory (STT MRAM) bit-cell that is embedded with read-only memory (ROM) functionality. The proposed ROM-embedded STT MRAM (R-MRAM) bit-cells include one extra bit-line.... more
ABSTRACT We present a new spin-transfer torque magnetic random access memory (STT MRAM) bit-cell that is embedded with read-only memory (ROM) functionality. The proposed ROM-embedded STT MRAM (R-MRAM) bit-cells include one extra bit-line. ROM data is stored by selectively connecting the magnetic tunnel junction (MTJ) to one of the two bit-lines. For normal RAM-mode operations, both bit-lines are driven and sensed to switch and read the MTJ state. When reading ROM data, only one read current source is turned on and the corresponding sense amplifier is used to monitor which bit-line is connected to the bit-cell (the MTJ state can be ignored).
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ABSTRACT Spin-transfer torque magnetic random access memory devices (STT-MRAMs) show great promise as a candidate technology for on-chip caches. In this letter, we propose a new STT-MRAM bit-cell structure that is suitable for on-chip... more
ABSTRACT Spin-transfer torque magnetic random access memory devices (STT-MRAMs) show great promise as a candidate technology for on-chip caches. In this letter, we propose a new STT-MRAM bit-cell structure that is suitable for on-chip caches compared with the standard STT-MRAM bit-cell (SSC). Scalability of our proposed structure is studied with the aid of micromagnetic and circuit simulators. Results show that our proposed bit-cell is more scalable than the SSC, achieving $>hbox4times$ better write margin, $>$ 65% better sensing margin, lower read disturb failures, and subnanosecond sensing delays.