Chun et al., 2020 - Google Patents

Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write (R-W) circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
  • G11C29/44—Indication or identification of errors, e.g. for repair
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by G11C11/00
  • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
  • G11C5/04—Supports for storage elements, Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING; COUNTING
  • G06F—ELECTRICAL DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by G11C11/00
  • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/70—Masking faults in memories by using spares or by reconfiguring
  • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
  • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
  • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
  • G11C29/818—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for dual-port memories
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output (I/O) data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output (I/O) data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1072—Input/output (I/O) data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

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