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Goswami et al., 2007 - Google Patents

Test generation in the presence of timing exceptions and constraints

Goswami et al., 2007

Document ID
8843420718449002326
Author
Goswami D
Tsai K
Kassab M
Rajski J
Publication year
Publication venue
Proceedings of the 44th annual Design Automation Conference

External Links

Snippet

Generating test patterns without considering timing exceptions and constraints can lead to invalid test responses, resulting in false failures on the tester or yield loss. A path-oriented approach to handle timing exception paths with setup violations during at-speed test …
Continue reading at dl.acm.org (other versions)

Classifications

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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
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    • G01R31/318594—Timing aspects
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    • G01R31/318583—Design for test
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    • G06F2217/70—Fault tolerant, i.e. transient fault suppression

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