Krishna et al., 2004 - Google Patents
Achieving high encoding efficiency with partial dynamic LFSR reseedingKrishna et al., 2004
View PDF- Document ID
- 6249961974530072205
- Author
- Krishna C
- Jas A
- Touba N
- Publication year
- Publication venue
- ACM Transactions on Design Automation of Electronic Systems (TODAES)
External Links
Snippet
Previous forms of LFSR reseeding have been static (ie, test application is stopped while each seed is loaded) and have required full reseeding (ie, the length of the seed is equal to the length of the LFSR). A new form of LFSR reseeding is described here that is dynamic (ie …
- 230000003068 static 0 abstract description 18
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318385—Random or pseudo-random test pattern
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuit
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31919—Storing and outputting test patterns
- G01R31/31921—Storing and outputting test patterns using compression techniques, e.g. patterns sequencer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318335—Test pattern compression or decompression
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/31813—Test pattern generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/582—Pseudo-random number generators
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
- G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
- G01R31/318547—Data generators or compressors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R33/00—Arrangements or instruments for measuring magnetic variables
- G01R33/20—Arrangements or instruments for measuring magnetic variables involving magnetic resonance
- G01R33/44—Arrangements or instruments for measuring magnetic variables involving magnetic resonance using nuclear magnetic resonance [NMR]
- G01R33/48—NMR imaging systems
- G01R33/54—Signal processing systems, e.g. using pulse sequences, Generation or control of pulse sequences ; Operator Console
- G01R33/56—Image enhancement or correction, e.g. subtraction or averaging techniques, e.g. improvement of signal-to-noise ratio and resolution
- G01R33/561—Image enhancement or correction, e.g. subtraction or averaging techniques, e.g. improvement of signal-to-noise ratio and resolution by reduction of the scanning time, i.e. fast acquiring systems, e.g. using echo-planar pulse sequences
- G01R33/5611—Parallel magnetic resonance imaging, e.g. sensitivity encoding [SENSE], simultaneous acquisition of spatial harmonics [SMASH], unaliasing by Fourier encoding of the overlaps using the temporal dimension [UNFOLD], k-t-broad-use linear acquisition speed-up technique [k-t-BLAST], k-t-SENSE
- G01R33/5612—Parallel RF transmission, i.e. RF pulse transmission using a plurality of independent transmission channels
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Krishna et al. | Test vector encoding using partial LFSR reseeding | |
| US5991898A (en) | Arithmetic built-in self test of multiple scan-based integrated circuits | |
| US6807646B1 (en) | System and method for time slicing deterministic patterns for reseeding in logic built-in self-test | |
| Hellebrand et al. | Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers | |
| US7610539B2 (en) | Method and apparatus for testing logic circuit designs | |
| Krishna et al. | Achieving high encoding efficiency with partial dynamic LFSR reseeding | |
| US6611933B1 (en) | Real-time decoder for scan test patterns | |
| Wang et al. | Test data compression for IP embedded cores using selective encoding of scan slices | |
| Krishna et al. | Adjustable width linear combinational scan vector decompression | |
| Bayraktaroglu et al. | Concurrent application of compaction and compression for test time and data volume reduction in scan designs | |
| US7225376B2 (en) | Method and system for coding test pattern for scan design | |
| Krishna et al. | 3-stage variable length continuous-flow scan vector decompression scheme | |
| Balakrishnan et al. | Improving linear test data compression | |
| US7340496B2 (en) | System and method for determining the Nth state of linear feedback shift registers | |
| Muthyala et al. | Improving test compression with scan feedforward techniques | |
| Kim et al. | Test-decompression mechanism using a variable-length multiple-polynomial LFSR | |
| Li et al. | Area-efficient high-coverage LBIST | |
| Czysz et al. | On deploying scan chains for data storage in test compression environment | |
| Muthyala et al. | Improving test compression by retaining non-pivot free variables in sequential linear decompressors | |
| Balakrishnan et al. | Improving encoding efficiency for linear decompressors using scan inversion | |
| Gizdarski et al. | A new paradigm for synthesis of linear decompressors | |
| Novák | Pseudorandom, weighted random and pseudoexhaustive test patterns generated in universal cellular automata | |
| Novák et al. | Sequential test decompressors with fast variable wide spreading | |
| Bellos et al. | Test set embedding based on phase shifters | |
| Souza et al. | Mixed test pattern generation using a single parallel LFSR |