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Liu et al., 2004 - Google Patents

Electrical properties of sputter deposited SrTiO3 gate dielectrics

Liu et al., 2004

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Document ID
5367490949898142526
Author
Liu C
Tseng T
Publication year
Publication venue
Journal of the European Ceramic Society

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We report the electrical properties of gate dielectric SrTiO3 (STO) thin films on Si substrates grown by radio-frequency magnetron sputtering. The interfacial layer between STO and Si degrades the performance of the gate dielectric. We used SiON as a sacrificial layer for …
Continue reading at ir.lib.nycu.edu.tw (PDF) (other versions)

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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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