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Mehdipour et al., 2006 - Google Patents

Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework

Mehdipour et al., 2006

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Document ID
16648327972999015607
Author
Mehdipour F
Zamani M
Ahmadifar H
Sedighi M
Murakami K
Publication year
Publication venue
Proceedings 20th IEEE International Parallel & Distributed Processing Symposium

External Links

Snippet

In reconfigurable systems, reconfiguration latency is a very important factor which impact the system performance. In this paper, a framework is proposed that integrates the temporal partitioning and physical design phases to perform a static compilation process for …
Continue reading at www.academia.edu (PDF) (other versions)

Classifications

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    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
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    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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    • G—PHYSICS
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    • G06F7/52—Multiplying; Dividing
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