WO2025175032A1 - An in-situ ruthenium or cobalt liner for improved high aspect ratio etch with bow control - Google Patents

Abstract

A method of etching recessed features in a stack below a mask is provided. An etch gas is provided comprising a halogen containing component. A sidewall passivation gas is provided comprising at least one of a ruthenium and cobalt containing component. The etch gas and sidewall passivation gas are transformed into a plasma, wherein the etch gas provides species for etching the stack and wherein the sidewall passivation gas provides species for depositing an electrically conductive sidewall passivation comprising at least one of ruthenium and cobalt.

Description

AN IN-SITU RUTHENIUM OR COBALT LINER FOR IMPROVED HIGH ASPECT RATIO ETCH WITH BOW CONTROL CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of U.S. Application No. 63/554,527, filed February 16, 2024, which is incorporated herein by reference for all purposes.

BACKGROUND

[0002] One process frequently employed during the fabrication of semiconductor devices is the formation of a recessed feature in a stack below a carbon containing mask. The stack may be alternating/repeating layers into which the recessed feature is formed or a thick film of a single layer of material. One example context where such a process may occur is memory applications, such as dynamic random access memory (DRAM) and “not and” devices (NAND). In the manufacturing of some semiconductor devices, metal or other materials may be etched below a carbon containing mask. As the semiconductor industry advances and device dimensions become smaller, such recessed features become increasingly harder to etch in a uniform manner, especially for high aspect ratio features having narrow widths and/or deep depths.

[0003] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

SUMMARY

[0004] To achieve the foregoing and in accordance with the purpose of the present disclosure, a method of etching recessed features in a stack below a mask is provided. An etch gas is provided comprising a halogen containing component. A sidewall passivation gas is provided comprising at least one of a ruthenium and cobalt containing component. The etch gas and sidewall passivation gas are transformed into a plasma, wherein the etch gas provides species for etching the stack and wherein the sidewall passivation gas provides species for depositing an electrically conductive sidewall passivation comprising at least one of ruthenium and cobalt.

[0005] In another manifestation, a method of etching recessed features in a stack below a patterned mask forming mask features is provided. An etch gas comprising a halogen containing component is provided. A sidewall passivation gas comprising at least one of a ruthenium and cobalt containing component is provided. The etch gas and sidewall passivation gas are transformed into a plasma by providing a multistate pulsed RF power with at least two states, wherein the etch gas provides species for etching the stack and wherein the sidewall passivation gas provides species for depositing an electrically conductive sidewall passivation comprising at least one of ruthenium and cobalt.

These and other features of the present disclosure will be described in more detail below in the detailed description and in conjunction with the following figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0007] FIG. 1 depicts a flow chart describing a method of etching recessed features into a stack below a carbon containing mask according to various embodiments.

[0008] FIGS. 2A-2E illustrate a schematic cross-sectional illustration of a stack processed according to some embodiments.

[0009] FIG. 3 shows a semiconductor processing system that may be used in some embodiments.

[0010] FIG. 4 illustrates a computer system for implementing a controller used in some embodiments.

[0011] In the drawings, like reference numerals are sometimes used to designate like structural elements. It should also be appreciated that the depictions in the figures are diagrammatic and not to scale.

DETAILED DESCRIPTION

[0012] The present disclosure will now be described in detail with reference to a few preferred embodiments thereof, as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present disclosure. [0013] Fabrication of certain semiconductor devices involves etching features into a stack of materials. In some embodiments, the stack of materials includes one or more layers of one or more materials below a carbon containing mask. In some embodiments, at least one layer of the stack contains at least one of silicon, germanium, and metal. Silicon containing layers may contain silicon nitride, silicon oxide, silicon carbide, silicon oxy-nitride, silicon oxy-carbide, polysilicon, or silicon germanium. In one example, the stack includes alternating layers of silicon oxide and polysilicon (OPOP). In some embodiments, the stack comprises an alternating silicon oxide film with silicon nitride films (ONON), a single silicon oxide layer, or a single silicon layer. In some embodiments, the stack may be a conductive or dielectric layer that may be a metal or silicon containing layer below a carbon containing mask. In some embodiments, the carbon containing mask is a carbon containing at least one of a photoresist, a doped carbon, and an amorphous carbon mask.

[0014] The features etched into a stack may be cylinders, trenches, or other recessed features. The aspect ratio of such a feature is defined as the ratio of the depth to the lateral critical dimension. As the aspect ratio of such features continues to increase, several issues arise, including (1) insufficient mask selectivity, (2) etch resolution, (3) twisting of the features, (4) non-circularity of the features, (5) aspect-ratio dependent etch rate, (6) bowing etch profile, and (7) low etch rate.

[0015] Insufficient mask selectivity is problematic when the etch process removes an excessive amount of the carbon containing mask, so that no mask remains at the end of the process, or when the amount of mask remaining is insufficient to properly transfer the pattern from the mask to the stack. One common result of insufficient mask selectivity is the degradation of the feature profile near the top of the recessed features. In order to compensate for insufficient mask selectivity, a thicker mask may be formed. However, a thicker mask results in lower mask resolution and an overall higher aspect ratio, which causes more issues during the etching of both mask and underlayer materials.

[0016] Twisting refers to random deviations between the intended bottom locations of the features and the actual final bottom locations of the features (e.g., with the final location of a feature corresponding to the position of the bottom of the feature after the feature is etched). For instance, in some cases, it is intended that cylindrical features are etched in a regular array. When some or all features randomly deviate at the bottom away from this array, they are understood to have twisted.

[0017] Non-circularity of the features refers to deviations of the bottom hole shape away from a circular hole shape. This issue is relevant when etching circular features such as cylinders, where it is desired that the bottoms of the recessed features are circular. When the bottom hole shape deviates away from a circular shape, it often forms a shape closer to an ellipse, triangle, or irregular polygon. In many cases, these non-circular shapes are not desirable.

[0018] Aspect-ratio dependent etch rate refers to an issue where the etch rate slows down as the aspect ratio of the features increases. In other words, as the features are etched further into the stack, the etching process slows down. This issue is problematic because it can lead to low throughput and associated high processing costs.

[0019] Bowing etch profile refers to the tendency for the features to etch laterally in the stack such that the final profile bows outwards excessively somewhere along the depth of the features. In other words, the actual maximum critical dimension of the features exceeds the desired maximum critical dimension of the features, which can compromise the integrity of the structures being formed or limit the electrical performance of the final devices.

[0020] Low etch rate refers to an etch rate that is slower than desired for a particular application. Low etch rate is problematic because it leads to long etch times, reduced throughput, and high processing costs.

[0021] Unfortunately, techniques that improve some of these issues, such as insufficient mask selectivity, often make other issues worse. As such, these issues are balanced against one another when designing an etching operation. For example, conventional commercially practiced dielectric etch processes often result in substantial bowing. Previously, such tradeoffs have been difficult to avoid.

[0022] Current high aspect ratio contact (HARC) etch processes in both DRAM and NAND applications require more side wall protection with increasing aspect ratios. Traditional carbon polymer protection is not self-limiting and has aspect ratio dependence due to neutral shadowing. Thus, more protection is provided on mask tops rather than on HARC feature sidewalls. The resulting HARC bow CD can be large due to ion scattering in deep features.

[0023] High aspect ratio etching of dielectric material is the most challenging application in memory. The recent development of cryogenic etching developed for 3D NAND memory pillar etch applications substantially speeds up the etch process. With that, the demand for better control of the sidewall passivation in an attempt to control the CD of the HARC process becomes even more difficult. This is mostly due to the fact that a lower degree of sidewall passivation is reported. In the previous versions of cryogenic etch, fluorocarbon (FC) type deposition was commonly used to control sidewalls. More recent cryogenic processes rely less on FC deposition but rather on ammonia salts and other types of inorganic materials deposited on the sidewalls. This new passivation is susceptible to plasma spattering and thus protects less CD from erosion.

[0024] One of the most useful ways to control CD from erosion is by providing a carbon liner deposition. This process does show significant benefits for bow control with small spattering properties. Unfortunately, this is an ex-situ process that requires the wafer to be moved to a different tool or even a different platform to enable carbon liner deposition. This increases the cost and time for wafer processing. In the past, multiple attempts were made to enable in-situ type deposition. One of the most prominent attempts provides a metal liner deposition. In the lab, few attempts were made to enable tungsten and molybdenum in-situ deposition.

Unfortunately, tungsten and molybdenum show little resistance to certain etch chemistries where highly fluorinated plasma is used. Tungsten hexafluoride (WFe) and molybdenum hexafluoride (MoFe) products are volatile and thus do not provide sufficient support.

[0025] The techniques described herein may be used to etch recessed features into a stack without some or all of the issues identified above. In other words, the disclosed techniques may be used to etch recessed features into a stack below a mask with a high stack to mask selectivity and with reduced mask twisting, reasonably circular features, an acceptable degree of aspect ratio dependent etch rate, acceptable bowing, with reduced non-uniformity, reduced asymmetric mask shadowing, and sufficient etch rate. Some embodiments provide a method and apparatus for providing at least one of a ruthenium and cobalt containing sidewall passivation. Such sidewall passivation reduces bowing.

Flow Chart

[0026] To facilitate understanding, FIG. 1 is a high level flow chart of a method that may be used in some embodiments. A stack with a mask is provided in a process chamber (step 104). FIG. 2A is a schematic cross-sectional view of a stack 204 that may be processed according to some embodiments, where the stack is under a patterned mask 216, such as an organic mask, one example of which would be an amorphous carbon mask. The amorphous carbon mask may also include some amount of hydrogen and/or oxygen. The mask 216 has mask features. In some embodiments, the stack 204 may be formed over a substrate 208. In some embodiments, the stack 204 may comprise a silicon containing layer, such as silicon oxide, silicon nitride, or silicon. In some embodiments, the stack 204 may be a metal containing layer such as a pure or alloy conductive metal layer or a metal nitride or metal oxide. In some embodiments, the stack 204 may comprise a germanium containing layer. In some embodiments, the stack is a single bulk layer. In some embodiments, the stack is a plurality of layers. In some embodiments, the stack is a plurality of bilayers, trilayers, or more multiple layers. In some embodiments, the stack 204 comprises a plurality of bilayers 212, where each bilayer 212 includes a layer of silicon oxide 224 and a layer of silicon nitride 228.

Partial Etch

[0027] In some embodiments, the stack is partially etched (step 108). In some embodiments, the stack is cooled to a temperature in the range of -100° C to 100° C. In some embodiments, an etch gas is provided and transformed into a plasma. In some embodiments, radio frequency (RF) power is used to transform the etch gas into a plasma. In some embodiments, the plasma is formed in a process chamber. In some embodiments, the plasma is formed remotely outside of the process chamber and then provided into the process chamber. In some embodiments, the etch gas comprises hydrogen fluoride (HF) and a phosphorous containing component. In some embodiments, the etch gas comprises a phosphorous containing component comprising at least one of phosphorous trifluoride (PF3) and phosphorous pentafluoride (PF5).

[0028] In some embodiments, the plasma may be generated at a radio frequency (RF) power between about 5-200 kilowatts (kW), for example, between about 10-100 kW, or between about 10-65 kW in some embodiments. In some cases, a dual-frequency RF may be used to generate the plasma. Thus, the RF power may be provided at two or more frequency components, for example, a first frequency component at about 400 kilohertz (kHz) and a second frequency component at about 60 megahertz (MHz). Different powers may be provided at each frequency component. For instance, the first frequency component (e.g., about 400 kHz) may be provided at a power between about 10-65 kW, and the second frequency component (e.g., about 60 MHz) may be provided at a different power, for example between about 0.5-8 kW. In some embodiments, the first frequency component (e.g., about 400 kHz) may be provided at a power higher than 65 kW. These power levels assume that the RF power is delivered to a single 300 millimeter (mm) wafer. The power levels can be scaled linearly based on substrate area for additional substrates and/or substrates of other sizes (thereby maintaining a uniform power density delivered to the substrate). In other cases, three- frequency RF power may be used to generate the plasma.

[0029] In some embodiments, the applied RF power is a continuous RF power. In some embodiments, the applied RF power may be pulsed. In some embodiments, the pulsed RF may have two or three states, providing multistate pulsed RF power. A three state pulsing pulses between three different (high, medium, low) power levels. In some embodiments, the high power level has a 1% to 20% duty cycle, the medium power level has a 10% to 90% duty cycle, and the low power level has a 20% to 90% duty cycle. In some embodiments, the low power level is 0 Watts. In some embodiments, the high power level is 2 to 20 times the low power levels, and the medium power level is between the high power level and the low power level. In some embodiments, the RF power is pulsed at repetition rates of 1-50,000 Hz. The RF power may be pulsed between two non-zero values (e.g., between higher power and lower power states) or between zero and a non-zero value (e.g., between off and on states). Where the RF power is pulsed between two non-zero values, the powers may be a higher power state and a lower power state. The lower power state may correspond to an RF power of about 4 kW or lower. A pulsing duty cycle may be in the range of 1-50%. The pulsing may be at a repetition rate in the range of 100 Hz to 20 kHz. The maximum ion energy at the substrate may be relatively high, for example, between about 1-10 kilovolts (kV). The maximum ion energy is determined by the applied RF power in combination with the details of RF excitation frequencies, electrode sizes, electrode placement, chamber geometry, and plasma interactions. In some embodiments, the pulsing may facilitate the deposition of neutrals.

[0030] In some embodiments, a bias in the range of 0 Watts (W) to 100 kilowatts (kW) is provided to accelerate ions toward the top surfaces of the stack 204. In some embodiments, a bias in the range of 100 W to 1 kW is provided. In some embodiments, the partial etch etches to a feature depth of about 2 to 8 microns.

[0031] The stack 204 is exposed to the plasma, causing recessed features to be partially etched into the stack 204. FIG. 2B is a schematic cross-sectional view of a stack 204 after the recessed features 240 have been partially etched. Sidewall Passivation

[0032] Next, a ruthenium or cobalt containing sidewall deposition is deposited on the sidewalls of the recessed features (step 112). In some embodiments, the stack is cooled to a temperature in the range of -100° C to 100° C. The deposition of the ruthenium or cobalt containing passivation comprises providing a ruthenium or cobalt containing gas. In some embodiments, the ruthenium or cobalt containing gas comprises at least one of bis(ethylcyclopentadienyl)ruthenium(II), hexafluoro-2-butynetetracarbonylruthenium, and dicobalt octacarbonyl. These examples of ruthenium or cobalt containing gas are more volatile, allowing them to be provided as a gas at low temperatures. Other ruthenium and cobalt compounds that are less volatile could be used if the hardware allows solid precursors to be delivered to the etch chamber. In some embodiments, the ruthenium or cobalt containing gas further comprises Hi and/or Ni.

[0033] In some embodiments, the ruthenium or cobalt containing passivation gas is transformed into a plasma. In some embodiments, radio frequency (RF) power is used to transform the passivation gas into a plasma. In some embodiments, the plasma is formed in a process chamber. In some embodiments, the plasma is formed remotely outside of the process chamber and then provided into the process chamber. In some embodiments, the ruthenium or cobalt containing passivation gas is provided at a pressure in the range of 10 millitorr (mTorr) and 800 mTorr.

[0034] In some embodiments, the plasma may be generated at a radio frequency (RF) power between about 10 Watts (W) to 1 kilowatt (kW). In some cases, a dual-frequency RF may be used to generate the plasma. Thus, the RF power may be provided at two or more frequency components, for example, a first frequency component at about 400 kilohertz (kHz) and a second frequency component at about 60 megahertz (MHz). Different powers may be provided at each frequency component. For instance, the first frequency component (e.g., about 400 kHz) may be provided at a power between about 0-500 W, and the second frequency component (e.g., about 60 MHz) may be provided at a different power, for example between about 10 W to 1 kW. These power levels assume that the RF power is delivered to a single 300 millimeter (mm) wafer. The power levels can be scaled linearly based on substrate area for additional substrates and/or substrates of other sizes (thereby maintaining a uniform power density delivered to the substrate). In other cases, three-frequency RF power may be used to generate the plasma. In some embodiments, 500 watts of RF is provided at a frequency of 60 MHz.

[0035] In some embodiments, the applied RF power is a continuous RF power. In some embodiments, the applied RF power may be pulsed. In some embodiments, the pulsed RF may have two or three states, providing multistate pulsed RF power. A three state pulsing pulses between three different (high, medium, low) power levels. In some embodiments, the high power level has a 1% to 20% duty cycle, the medium power level has a 10% to 90% duty cycle, and the low power level has a 20% to 90% duty cycle. In some embodiments, the low power level is 0 Watts. In some embodiments, the high power level is 2 to 20 times the low power levels, and the medium power level is between the high power level and the low power level. In some embodiments, the RF power is pulsed at repetition rates of 1-50,000 Hz. The RF power may be pulsed between two non- zero values (e.g., between higher power and lower power states) or between zero and a non-zero value (e.g., between off and on states). Where the RF power is pulsed between two non-zero values, the powers may be a higher power state and a lower power state. The lower power state may correspond to an RF power of about 4 kW or lower. A pulsing duty cycle may be in the range of 1-50%. The pulsing may be at a repetition rate in the range of 100 Hz to 20 kHz. The maximum ion energy at the substrate may be relatively low, for example, between about 0-100 electron volts (eV). The maximum ion energy is determined by the applied RF power in combination with the details of RF excitation frequencies, electrode sizes, electrode placement, chamber geometry, and plasma interactions. In some embodiments, the pulsing may facilitate the deposition of neutrals.

[0036] In some embodiments, a bias in the range of 0 Watts (W) to 1 kilowatt (kW) is provided to accelerate ions toward the top surfaces of stack 204.

[0037] The stack 204 is exposed to the plasma formed from the ruthenium or cobalt containing passivation gas, creating a ruthenium or cobalt containing passivation layer along the sidewalls of the recessed features 240. FIG. 2C is a schematic cross-sectional view of a stack 204 after depositing the ruthenium or cobalt containing sidewall passivation layer (step 112). The ruthenium or cobalt containing passivation layer 248 is schematically illustrated in order to facilitate understanding. In some embodiments, the ruthenium or cobalt containing passivation layer 248 is deposited nonconformally with more deposition where bowing is the greatest near the top surface of the stack 204 and less deposition near the etch front near the bottom of the features, as shown. In some embodiments, the ruthenium or cobalt containing passivation layer 248 has a maximum thickness in the range of 1 nm to 20 nm. In some embodiments, although less ruthenium or cobalt containing passivation layer 248 is deposited near the etch front, some ruthenium or cobalt containing passivation is deposited near the etch front in order to provide an electrically conductive passivation layer. The electrically conductive passivation layer is able to reduce or distribute an electrostatic charge at the etch front. The reduction or distribution of the electrostatic charge at the etch front reduces distortions or roughening caused by the electrostatic charge. In addition, the flow of the ruthenium or cobalt containing gas is kept low in order to reduce the amount of ruthenium or cobalt deposited at the etch front.

[0038] In some embodiments, a plasma is not formed, providing a plasmaless process. Instead, the stack is exposed to the passivation gas at a pressure in the range of 10 mTorr to 1 Torr. A substrate support is kept at a temperature below 100° C during the plasmaless metal passivation deposition process. In some embodiments, where no plasma is formed, no RF power and no bias power is provided. Instead, the passivation gas provides a reaction that deposits the metal passivation without requiring ions, energetic neutrals, or radicals.

Further Etch

[0039] The stack is further etched (step 116). In some embodiments, an etch gas is provided and transformed into a plasma. In some embodiments, radio frequency (RF) power is used to transform the etch gas into a plasma. In some embodiments, the plasma is formed in a process chamber. In some embodiments, the plasma is formed remotely outside of the process chamber and then provided into the process chamber. In some embodiments, the further etch of the stack (step 116) uses the same recipe as the recipe for the partial etch of the stack (step 108). In some embodiments, the further etch of the stack (step 116) uses a different recipe than the recipe for the partial etch of the stack (step 108), since the further etch of the stack (step 116) etches at a different depth than the partial etch of the stack (step 108) and/or the further etch of the stack (step 116) may etch a different material than the partial etch of the stack (step 108).

[0040] The ruthenium or cobalt containing passivation layer 248 prevents or reduces the further etch of the stack (step 116) from etching the sidewalls of the recessed features 240 in order to prevent or reduce bowing. FIG. 2D is a schematic cross-sectional view of the stack 204 after the stack 204 is further etched (step 116). The ruthenium or cobalt containing passivation layer 248 (shown in FIG. 2C) has been etched away. In some embodiments, the ruthenium or cobalt containing passivation layer 248 may be removed before the etch is completed. In such cases, it is determined that in order to etch more (step 120), the process returns back to the ruthenium or cobalt containing sidewall deposition (step 112). If the etch of the stack 204 is complete so that there is no further etch (step 120), then the stack 204 may be removed from the substrate support of the process chamber (step 124). In some embodiments, additional steps, such as removing the ruthenium or cobalt containing passivation layer 248, may be performed before the stack 204 is removed from the process chamber (step 124). In some embodiments, the ruthenium or cobalt containing passivation layer 248 is removed using a wet cleaning of the electrically conductive sidewall passivation. FIG. 2E is a schematic cross-sectional view of the stack 204 after the stack 204 has been completely etched and the stack 204 is removed from the process chamber. In some embodiments, the ruthenium or cobalt containing side wall deposition (step 112) and the further etch of the stack (step 116) are cyclically performed in the range of 2 to five times.

[0041] In some embodiments, the substrate is placed on a substrate support in a process chamber. In some embodiments, the substrate support is cooled to a temperature below 0° C. In some embodiments, the partial etch (step 108), the ruthenium or cobalt containing sidewall deposition (step 112), and the further etch of the stack (step 116) are performed in-situ in the same chamber and mounted on the same substrate support. The ability to perform the process in- situ allows for faster throughput, less contamination, and a wider process window.

[0042] Some embodiments largely widen the current process window without triggering other tradeoffs by providing more robust sidewall protection. Ruthenium and cobalt containing passivation species are more sticky than some other metal containing passivation species. If the metal containing passivation species is not sticky enough, then the metal containing passivation species may not quickly stick to the sidewalls but instead bounce down the sidewalls of the features towards the etch front so that the metal containing passivation species is more uniformly deposited along the depth of the sidewalls of the features. Because ruthenium or cobalt containing passivation species are more sticky, the ruthenium or cobalt containing passivation species more quickly stick to the sidewalls and nonconformally deposit so that there is more deposition near the tops of the features where bowing occurs most and less deposition nearer to the bottom of the features where tapering is more of a concern. It has been found that ruthenium containing passivation species are more sticky than cobalt containing passivation species. As a result, ruthenium containing passivation species may provide improved bow protection over cobalt containing passivation species.

[0043] One application for the disclosed methods is in the context of forming a vertical NAND. In this case, the material into which the feature is etched may have a repeating layered structure. For instance, the material may include alternating layers of silicon oxide and silicon nitride. In other embodiments, the stack may comprise alternating layers of silicon oxide and polysilicon. The alternating layers form pairs or repeating groups of materials. In various cases, the number of pairs or repeating groups may be between about 10-500 (e.g., between about 20- 1000 individual layers). The feature etched into the stack of layers may have a depth between about 2-15 pm, for example, between about 5-9 pm. The feature may have a CD width between about 3-500 nm, for example, between about 50-100 nm or between about 40-85 nm. In some embodiments, the features have a width of less than 100 nm. In some embodiments, the features have a width of less than 85 nm. In some embodiments, the stack comprises at least one of a layer of SiO, SiN, and SiON.

[0044] As used herein, “high aspect ratio,” as applied to features in a substrate, refers to a depth to width aspect ratio on the order of approximately 60:1 or higher. More preferably, this range may include ratios greater than 100:1, 120: 1, 140: 1, etc., or higher. However, the processes described herein may be beneficial for lower aspect ratios, such as 30:1 or 10: 1. In some embodiments, the features may have a depth from 3 nm to 10 pm.

[0045] The dimensional/parametric details provided herein, such as high aspect ratio, thickness, width, depth, etc., are for example and illustration only. Based on the disclosure described herein, it should be understood that varying dimensions/parameters may also be applicable or used.

[0046] In some embodiments, ultraviolet (UV) light, such as extreme ultraviolet (EUV) light, is used for processing semiconductor devices. In some embodiments, ruthenium containing layers are transparent to UV light. In some embodiments, the ruthenium containing layer is able to pass UV light so that the UV light is able to react with layers below the ruthenium containing passivation layer without being attenuated by the ruthenium containing passivation layer. In some embodiments, the sidewall passivation gas comprises a ruthenium containing component wherein the sidewall passivation gas is free of all non-ruthenium metals so that the only metal that is deposited is ruthenium in order for the sidewall passivation to be transparent to UV light.

Simultaneous Embodiments

[0047] In some embodiments, the depositing of the ruthenium or cobalt containing sidewall layer (step 112) is performed simultaneously with the further etch of the stack (step 116). In some embodiments, the partial etch of the stack (step 108) is performed before the simultaneous ruthenium or cobalt containing sidewall deposition (step 112) and the further etch of the stack (step 116). In some embodiments, the partial etch etches features to a depth in the range of 2 microns to 8 microns. In some embodiments, the partial etch of the stack (step 108) is not performed. The simultaneous process may be faster than a cyclical process. However, a simultaneous process may cause necking, resulting in a feature taper. A cyclical process is able to reduce necking and tapering.

APPARATUS

[0048] The various hardware and method embodiments described above may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such tools/processes will be used or conducted together in a common fabrication facility.

[0049] Lithographic patterning of a film typically comprises some or all of the following steps, each step enabled with a number of possible tools: (1) application of photoresist on a workpiece, e.g., a substrate having a silicon containing film formed thereon, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or other suitable curing tool; (3) exposing the photoresist to visible or ultraviolet (UV) or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove the resist and thereby pattern it using a tool such as a wet bench or a spray developer; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In some embodiments, an ashable hard mask layer (such as an amorphous carbon layer) and another suitable hard mask (such as an antireflective layer) may be deposited prior to applying the photoresist.

[0050] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, 300 mm, or 450 mm. The above detailed description assumes the embodiments are implemented on a wafer. However, the embodiments are not so limited. The workpiece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0051] Unless otherwise defined for a particular parameter, the terms “about” and “approximately” as used herein are intended to mean ±10% with respect to a relevant value. [0052] FIG. 3 is a schematic view of an etch reactor system 300 that may be used in some embodiments. In some embodiments, an etch reactor system 300 comprises a gas distribution plate 306 providing a gas inlet and an electrostatic chuck (ESC) 308 within an etch (or process) chamber 309, enclosed by a chamber wall 352. Within the etch chamber 309, a stack 204 is positioned over the ESC 308 that is used as a substrate support. A bias may be provided to the ESC 308 from an ESC source 348. A gas source 310 is connected to the etch chamber 309 through the gas distribution plate 306. In some embodiments, the gas source 310 comprises an etch gas source 312, an activation gas source 316, and a passivation gas source 318. An ESC temperature controller 350 is connected to the ESC 308. A radio frequency (RF) source 330 provides RF power to a lower electrode and/or an upper electrode, which in this embodiment are the ESC 308 and the gas distribution plate 306, respectively. In some embodiments, 400 kilohertz (kHz), 60 megahertz (MHz), and optionally, 2 MHz or 27 MHz power sources make up the RF source 330 and the ESC source 348. In some embodiments, the upper electrode is grounded. In some embodiments, one generator is provided for each frequency. In some embodiments, the generators may be in separate RF sources, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have inner and outer electrodes connected to different RF sources. Other arrangements of RF sources and electrodes may be used in other embodiments. A controller 335 is controllably connected to the RF source 330, the ESC source 348, an exhaust pump 320, and the gas source 310. An example of such an etch chamber is the Vantex® etch system manufactured by Lam Research Corporation of Fremont, CA. The process chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0053] FIG. 4 is a high level block diagram showing a computer system 400, which is suitable for implementing the controller 335 used in embodiments. The computer system 400 may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge supercomputer. The computer system 400 includes one or more processors 402 and further can include an electronic display device 404 (for displaying graphics, text, and other data), a main memory 406 (e.g., random access memory (RAM)), storage device 408 (e.g., hard disk drive), removable storage device 410 (e.g., optical disk drive), user interface devices 412 (e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and a communications interface 414 (e.g., wireless network interface). The communications interface 414 allows software and data to be transferred between the computer system 400 and external devices via a link. The system may also include a communications infrastructure 416 (e.g., a communications bus, cross-over bar, or network) to which the aforementioned devices/modules are connected.

[0054] Information transferred via communications interface 414 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 414 via a communications link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and/or other communications channels. With such a communications interface 414, it is contemplated that the one or more processors 402 might receive information from a network or might output information to the network in the course of performing the abovedescribed method steps. Furthermore, method embodiments may execute solely upon the processors or may execute over a network, such as the Internet, in conjunction with remote processors that share a portion of the processing.

[0055] The term “non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM, and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that is executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor. [0056] In some embodiments, the controller 335 is configured to a) provide an etch gas comprising a halogen containing component, b) provide a sidewall passivation gas comprising at least one of a ruthenium and cobalt containing component, and c) transform the etch gas and sidewall passivation gas into a plasma, wherein the etch gas provides species for etching the stack and wherein the sidewall passivation gas provides species for depositing an electrically conductive sidewall passivation comprising at least one of ruthenium and cobalt. The controller 335 may be further configured to repeat steps a-c a plurality of times.

[0057] It is to be understood that the configurations and/or approaches described herein are exemplary in nature and that these specific embodiments or examples are not to be considered in a limiting sense because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, various acts illustrated may be performed in the sequence illustrated, in other sequences, in parallel, or in some cases omitted. Likewise, the order of the above described processes may be changed. Certain references have been incorporated by reference herein. It is understood that any disclaimers or disavowals made in such references do not necessarily apply to the embodiments described herein. Similarly, any features described as necessary in such references may be omitted in the embodiments herein. The subject matter of the present disclosure includes all novel and nonobvious combinations and sub-combinations of the various processes, systems and configurations, and other features, functions, acts, and/or properties disclosed herein, as well as any and all equivalents thereof.

CONCLUSION

[0058] While this disclosure has been described in terms of several preferred embodiments, there are alterations, modifications, permutations, and various substitute equivalents which fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. It is, therefore, intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present disclosure. As used herein, the phrase “A, B, or C” should be construed to mean a logical (“A OR B OR C”), using a non-exclusive logical “OR,” and should not be construed to mean ‘only one of A or B or C. Each step within a process may be an optional step and is not required. Different embodiments may have one or more steps removed or may provide steps in a different order. In addition, various embodiments may provide different steps simultaneously instead of sequentially.

Claims

CLAIMS What is claimed is:

1. A method of etching recessed features in a stack below a mask, comprising: a. providing an etch gas comprising a halogen containing component; b. providing a sidewall passivation gas comprising at least one of a ruthenium and cobalt containing component; and c. transforming the etch gas and sidewall passivation gas into a plasma, wherein the etch gas provides species for etching the stack and wherein the sidewall passivation gas provides species for depositing an electrically conductive sidewall passivation comprising at least one of ruthenium and cobalt.

2. The method of claim 1, wherein the sidewall passivation gas comprises a ruthenium containing component.

3. The method of claim 1, wherein the providing the etch gas and the providing the sidewall passivation gas are performed sequentially.

4. The method of claim 3, wherein transforming the etch gas and sidewall passivation gas transforms the etch gas into a plasma and transforms the sidewall passivation gas into a plasma sequentially.

5. The method of claim 1, wherein the providing the etch gas and the providing the sidewall passivation gas are performed simultaneously.

6. The method of claim 1, wherein the sidewall passivation gas comprises a ruthenium containing component and wherein the sidewall passivation gas is free of all non-ruthenium metals.

7. The method of claim 6, further comprising providing UV light.

8. The method of claim 1 , wherein the mask is a carbon containing mask.

9. The method of claim 1, further comprising wet cleaning the electrically conductive sidewall passivation.

10. The method of claim 1, wherein the sidewall passivation gas comprises at least one of Bis(ethylcyclopentadienyl)ruthenium(II), hexafluoro-2-butynetetracarbonylruthenium, and dicobalt octacarbonyl.

11. The method of claim 1 , further comprising transforming the sidewall passivation gas into a plasma comprising providing a multistate pulsed RF power with two or three states.

12. The method, as recited in claim 1, further comprising transforming the sidewall passivation gas into a plasma comprising providing a pulsed RF power with a duty cycle in a range of 1% to 50%.

13. The method, as recited in claim 1, further comprising cooling the stack to a temperature below 100° C.

14. The method, as recited in claim 1 , wherein the stack comprises at least one of a layer of SiO, SiN, and SiON.

15. A method of etching recessed features in a stack below a patterned mask forming mask features, comprising: a. providing an etch gas comprising a halogen containing component; b. providing a sidewall passivation gas comprising at least one of a ruthenium and cobalt containing component; and c. transforming the etch gas and sidewall passivation gas into a plasma by providing a multistate pulsed RF power with at least two states, wherein the etch gas provides species for etching the stack and wherein the sidewall passivation gas provides species for depositing an electrically conductive sidewall passivation comprising at least one of ruthenium and cobalt.

16. The method of claim 15, wherein the sidewall passivation gas comprises a ruthenium containing component.

17. The method of claim 15, wherein the sidewall passivation gas comprises a ruthenium containing component and wherein the sidewall passivation gas is free of all non-ruthenium metals.

18. The method of claim 17, further comprising providing UV light.

19. The method of claim 15, further comprising wet cleaning the electrically conductive sidewall passivation.

20. The method of claim 15, wherein the sidewall passivation gas comprises at least one of Bis(ethylcyclopentadienyl)ruthenium(II), hexafluoro-2-butynetetracarbonylruthenium, and dicobalt octacarbonyl.