WO2025163445A1 - Semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device that is easily scaled down. The present invention also provides a semiconductor device that enables a higher level of integration. The semiconductor device comprises a first conductive layer, a pair of second conductive layers, a pair of third conductive layers, a pair of semiconductor layers, a first insulating layer having an opening, and a pair of second insulating layers. Each of the pair of semiconductor layers includes a first metal oxide. Each of the pair of semiconductor layers has a first region and a second region, and the second region has higher resistivity than the first region. The first conductive layer extends in a first direction. The pair of third conductive layers, the pair of semiconductor layers, the pair of second insulating layers, and the opening extend in a second direction intersecting the first direction. The first region and the second region are alternately arranged in the second direction. The first insulating layer is provided on the first conductive layer. Each of the pair of semiconductor layers has a vertical portion in contact with a side wall of the opening and a horizontal portion in contact with an upper surface of the first conductive layer. Each of the pair of semiconductor layers is in contact with the upper surface of the first conductive layer in the first region, and each of the pair of second conductive layers is in contact with the vertical portion. Each of the pair of second insulating layers covers the vertical portion and the horizontal portion, and each of the pair of third conductive layers covers the vertical portion and the horizontal portion with the second insulating layer interposed therebetween.

Description

Semiconductor Devices

One aspect of the present invention relates to a semiconductor device. One aspect of the present invention relates to a transistor. One aspect of the present invention relates to a memory device.

Note that one embodiment of the present invention is not limited to the above technical field. Examples of technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input/output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

In recent years, semiconductor device development has progressed, and CPUs, memory, and other large-scale integrated circuits (LSIs) are primarily used in semiconductor devices. A CPU is a collection of semiconductor elements processed from a semiconductor wafer, containing chipped semiconductor integrated circuits (at least transistors and memory), and on which electrodes serving as connection terminals are formed.

CPUs, memories, and other LSI semiconductor circuits (IC chips) are mounted on circuit boards, such as printed wiring boards, and used as components in a variety of electronic devices.

In addition, technology that constructs transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

In addition, transistors using oxide semiconductors are known to have extremely low leakage current when they are off. For example, Patent Document 1 discloses a low-power CPU that utilizes the property of low leakage current. Furthermore, for example, Patent Document 2 discloses a memory device that can retain stored content for a long period of time.

Furthermore, in recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for even higher density integrated circuits. There is also a need for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 discloses a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby providing multiple memory cells in a superimposed manner. Furthermore, Patent Document 4 discloses a vertical transistor in which the side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator.

Furthermore, Patent Document 5 discloses a semiconductor memory device having a channel pattern with a vertical channel portion on a bit line, and a word line arranged on the channel pattern so as to cross the bit line.

JP 2012-257187 A JP 2011-151383 A International Publication No. 2021/053473 JP 2013-211537 A US Patent Application Publication No. 2023/0055499

An object of one embodiment of the present invention is to provide a semiconductor device that can be easily miniaturized. Another object is to provide a semiconductor device that enables high integration. Another object is to provide a semiconductor device in which the wiring load is reduced. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device that exhibits favorable electrical characteristics. Another object is to provide a semiconductor device with high operating speed.

An object of one embodiment of the present invention is to provide a semiconductor device, memory device, or electronic device having a novel structure. An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

Note that the description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment of the present invention to solve all of these problems. It is possible to extract problems other than these from the description in the specification, drawings, claims, etc.

One aspect of the present invention is a semiconductor device comprising a first conductive layer, a pair of second conductive layers, a pair of third conductive layers, a pair of semiconductor layers, a first insulating layer having an opening, and a pair of second insulating layers, each of the pair of semiconductor layers including a first metal oxide, each of the pair of semiconductor layers having a first region and a second region, at least a portion of the first region functioning as a channel formation region, the second region having a higher resistivity than the first region, the first conductive layer extending in a first direction, the pair of third conductive layers, the pair of semiconductor layers, the pair of second insulating layers, and the opening extending in a second direction intersecting the first direction, and the pair of third conductive layers, the pair of semiconductor layers, and the pair of second insulating layers The semiconductor device has a first insulating layer disposed symmetrically within the opening, the first and second regions alternately arranged in the second direction, a first insulating layer disposed on the first conductive layer, the opening reaching the top surface of the first conductive layer, a pair of semiconductor layers each having a vertical portion in contact with the sidewall of the opening and a horizontal portion in contact with the top surface of the first conductive layer, each of the pair of semiconductor layers in contact with the top surface of the first conductive layer in the first region, a pair of second conductive layers each having a portion located above the first insulating layer and in contact with the vertical portion, each of the pair of second insulating layers covering the vertical portion and the horizontal portion, and a pair of third conductive layers covering the vertical portion and the horizontal portion via the second insulating layer.

In the above, it is preferable that the second region contains either aluminum or hafnium, or both.

Furthermore, in the above, it is preferable that the second region has a higher concentration of either or both of aluminum and hafnium than the first region.

Furthermore, in the above, it is preferable that the first conductive layer has a first conductive film and a second conductive film on the first conductive film, that each of the pair of semiconductor layers is in contact with the second conductive film, that the second conductive film contains a second metal oxide, and that the first conductive film contains a metal.

Furthermore, in the above, it is preferable that the first metal oxide and the second metal oxide contain one or more of the same elements selected from In, Sn, Zn, Ga, and Ti.

Furthermore, in the above, it is preferable that the second conductive film has a recess, and the pair of semiconductor layers have portions located within the recess and contact the side and top surfaces of the second conductive film within the recess.

Furthermore, in the above, it is preferable that the device has a pair of third insulating layers, each covering the vertical portion and the horizontal portion via the second insulating layer and the third conductive layer, and that the third insulating layers have the function of capturing or fixing hydrogen.

Furthermore, in the above, it is preferable that a capacitive element is provided on the second conductive layer, and that the capacitive element has a fourth conductive layer in contact with the second conductive layer, a fifth conductive layer, and a fourth insulating layer therebetween.

Furthermore, in the above, it is preferable that the fourth conductive layer has a recess, the fourth insulating layer has a portion that is provided along the recess, and the fifth conductive layer has a portion that is located within the recess via the fourth insulating layer and that contacts the side and top surfaces of the fourth insulating layer within the recess.

Furthermore, in the above, it is preferable that the fourth conductive layer has a columnar shape, the fourth insulating layer covers the fourth conductive layer, and the fifth conductive layer is provided so as to cover the top and side surfaces of the fourth conductive layer via the fourth insulating layer.

Furthermore, in the above, it is preferable that a transistor is provided below the first conductive layer, the transistor contains silicon in the semiconductor in which the channel is formed, and one of the source electrode and drain electrode of the transistor is connected to the first conductive layer.

According to one aspect of the present invention, a semiconductor device that can be easily miniaturized can be provided. Alternatively, a semiconductor device that enables high integration can be provided. Alternatively, a semiconductor device with reduced wiring load can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device that exhibits favorable electrical characteristics can be provided. Alternatively, a semiconductor device with high operating speed can be provided.

According to one aspect of the present invention, it is possible to provide a semiconductor device, memory device, or electronic device having a novel configuration. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have to have all of these effects. Note that other effects can be extracted from the description in the specification, drawings, claims, etc.

1A and 1B show examples of the configuration of a semiconductor device.
2A and 2B show examples of the configuration of a semiconductor device.
3A and 3B show examples of the configuration of a semiconductor device.
4A and 4B show examples of the configuration of a semiconductor device.
FIG. 5 shows an example of the configuration of a semiconductor device.
FIG. 6 shows an example of the configuration of a semiconductor device.
7A and 7B show examples of the configuration of a semiconductor device.
8A and 8B show examples of the configuration of a semiconductor device.
9A to 9D show examples of the configuration of a semiconductor device.
10A to 10D show examples of the configuration of a semiconductor device.
11A to 11D show examples of the configuration of a semiconductor device.
12A to 12C are diagrams illustrating an example of a method for manufacturing a semiconductor device.
13A and 13B are diagrams illustrating an example of a method for manufacturing a semiconductor device.
14A and 14B are diagrams illustrating an example of a method for manufacturing a semiconductor device.
15A and 15B are diagrams illustrating an example of a method for manufacturing a semiconductor device.
16A and 16B are diagrams illustrating an example of a method for manufacturing a semiconductor device.
17A to 17C are diagrams illustrating an example of a method for manufacturing a semiconductor device.
18A to 18C are diagrams illustrating an example of a method for manufacturing a semiconductor device.
19A to 19C are diagrams illustrating an example of a method for manufacturing a semiconductor device.
20A and 20B are diagrams illustrating an example of a method for manufacturing a semiconductor device.
21A to 21C are diagrams illustrating an example of a method for manufacturing a semiconductor device.
FIG. 22 is a block diagram illustrating an example of the configuration of a semiconductor device.
23A to 23H are diagrams illustrating examples of the circuit configuration of a memory cell.
24A and 24B are perspective views illustrating a configuration example of a semiconductor device.
FIG. 25 is a block diagram illustrating the CPU.
26A and 26B are perspective views of a semiconductor device.
27A and 27B are perspective views of a semiconductor device.
28A and 28B show examples of the configuration of electronic components.
29A to 29C show examples of the configuration of a mainframe computer.
Fig. 30A is a configuration example of space equipment, and Fig. 30B is a configuration example of a storage system.

The following describes embodiments with reference to the drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

In the configuration of the invention described below, the same parts or parts with similar functions will be denoted by the same reference numerals in different drawings, and repeated explanations will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

Note that in the figures described in this specification, the size of each component, layer thickness, or area may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale.

In addition, ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components and do not imply any numerical limitation.

A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage, and switching to control conduction or non-conduction. In this specification, the term "transistor" includes IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).

Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an electrical potential interaction occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Furthermore, even if there is a time during the operation of the circuit when no electrical signal exchange or electrical potential interaction occurs between A and B, if there is a time during the operation of the circuit when an electrical signal exchange or electrical potential interaction occurs between A and B, then it can still be defined that "A and B are indirectly connected."

An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, this would be the case when a capacitive element is connected between A and B, or when a transistor gate insulating film or the like is present between A and B. Therefore, it cannot be said that "the transistor gate (A) and the transistor source or drain (B) are indirectly connected."

Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another from a power supply, GND, etc.

In this specification, "top surface shapes that roughly match" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where only a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer; in these cases, the term "top surface shapes that roughly match" may also be used.

In this specification, the top surface shape of a certain component refers to the contour shape of that component when viewed from a plan view. Furthermore, a plan view refers to a view from the normal direction of the surface on which the component is formed, or the surface of the support (e.g., substrate) on which the component is formed.

In the following, expressions indicating directions such as "up" and "down" will generally be used in accordance with the directions in the drawings. However, for purposes such as ease of explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (formed surface, support surface, adhesive surface, flat surface, etc.) is located above the laminate in the drawings, the formed surface side may be expressed as "down" and the laminate side as "up."

In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region over the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in the on state. The channel width direction refers to the direction perpendicular to the channel length direction. Note that, depending on the structure or shape of the transistor, the channel length direction and channel width direction may not be defined as a single direction.

Furthermore, in this specification, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

Furthermore, in this specification, unless otherwise specified, off-state current refers to the drain current when a transistor is in an off state (also called a non-conducting state or cut-off state). Unless otherwise specified, the off state refers to a state in which the voltage Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor).

(Embodiment 1)
In this embodiment, a configuration example of a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device exemplified below can be applied to a memory device.

A semiconductor device according to one embodiment of the present invention has a plurality of memory cells. Each memory cell has one transistor and one memory element. Various elements capable of retaining stored information can be used as the memory element, such as a capacitor, a variable resistance element, a ferroelectric element, a charge trap element, or a floating gate element. Below, an example in which a capacitor is used as the memory element is described.

In the transistors of memory cells, the source and drain electrodes are located at different heights, and current flows in the height direction through the semiconductor layer. In other words, the channel length direction can be said to have a component in the height direction (vertical direction). Therefore, one aspect of the present invention can be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, vertical channel transistor, etc.

More specifically, a first insulating layer having an opening and functioning as a spacer is provided on a lower electrode (first conductive layer), which is one of the source and drain electrodes. The upper electrode (second conductive layer), which is the other of the source and drain electrodes, is provided so as to have a portion located above the first insulating layer. The opening in the first insulating layer has a sidewall that is approximately perpendicular to the upper surface of the lower electrode, and is provided so that a portion of the sidewall overlaps with the lower electrode. The semiconductor layer has a vertical portion (also referred to as a vertical portion) along the sidewall, a portion that contacts the upper electrode, and a portion that contacts the lower electrode. The portion of the semiconductor layer that contacts the lower electrode may have a portion (also referred to as a horizontal portion or lateral portion) that is parallel to the upper surface of the lower electrode. A gate insulating layer (second insulating layer) is provided covering the vertical and horizontal portions of the semiconductor layer, and a gate electrode (third conductive layer) is provided covering the vertical and horizontal portions via the gate insulating layer. In addition, a third insulating layer is provided covering the vertical and horizontal portions via the gate insulating layer and gate electrode.

It is preferable that the two transistors in two adjacent memory cells are arranged symmetrically within the opening. In other words, a pair of semiconductor layers, a pair of gate insulating layers, a pair of gate electrodes, a pair of third insulating layers, and a pair of upper electrodes can be arranged along a pair of side surfaces of the opening. This allows for even higher density arrangement of transistors.

The semiconductor layer preferably uses a metal oxide (oxide semiconductor) that exhibits semiconducting properties. Along the opening in the semiconductor layer, first regions that function as channel formation regions and second regions that function as element isolation regions are alternately arranged. The second regions are metal oxides to which metal elements (aluminum, hafnium, etc.) have been added, and have a higher resistivity than the first regions.

For example, when isolating elements by patterning a semiconductor layer into islands, the etching process may not be sufficient at the bottom of the openings, etc. This can lead to the risk of electrical conduction between adjacent first regions. In response to this, sufficient element isolation can be achieved by forming the semiconductor layer to cover the openings and alternately forming the first and second regions. This allows transistors with a three-dimensional structure to be manufactured with a high yield.

Furthermore, the second region may have lower crystallinity and more oxygen vacancies than the first region. This allows the second region to capture or fix the hydrogen and excess oxygen contained in the first region. This reduces the hydrogen and excess oxygen in the first region, which functions as a channel formation region. By reducing the hydrogen concentration in the first region, it is possible to suppress a negative shift in the transistor's initial characteristics and achieve normally-off characteristics. It is also possible to suppress negative drift degradation in a +GBT (Gate Bias-Temperature) stress test. It is also possible to suppress excessive positive shift in the transistor's initial characteristics by reducing the concentration of excess oxygen in the first region. It is also possible to suppress excessive positive drift degradation in a +GBT stress test.

More specific examples will be explained below with reference to the drawings.

[Configuration example]
FIG. 1A shows a schematic top view of the semiconductor device 10. FIGS. 2A and 2B show perspective views of the semiconductor device 10. FIGS. 3A, 3B, 4A, and 4B show schematic cross-sectional views taken along the cutting lines A1-A2, B1-B2, C1-C2, and D1-D2 shown in FIG. 1A, respectively. Each figure also shows arrows indicating the X, Y, and Z directions (hereinafter sometimes referred to as the X direction, Y direction, and Z direction). The X direction, Y direction, and Z direction intersect with each other. For example, the X direction, Y direction, and Z direction are preferably perpendicular to each other.

The semiconductor device 10 has a configuration in which multiple memory cells 15 are arranged in the X and Y directions (this can also be referred to as a matrix arrangement or a row-and-row arrangement). In the semiconductor device 10, conductive layers 24 that function as bit lines extend in the X direction, and conductive layers 23 that function as word lines extend in the Y direction. As shown in Figure 3A, the memory cell 15 has a transistor 20 and a capacitive element 30 thereon.

FIG. 1B shows a circuit diagram corresponding to semiconductor device 10. FIG. 1B shows multiple bit lines BL, multiple word lines WL that intersect each bit line at right angles, and wiring CL. While FIG. 1B shows an example in which the wiring CL is parallel to the bit lines BL, it is also possible for the wiring CL to be parallel to the word lines WL, or to be arranged in a grid pattern. Alternatively, the wiring CL may be a flat conductive film.

Memory cell 15 consists of one transistor 20 and one capacitor 30. The gate of transistor 20 is connected to word line WL, one of the source and drain is connected to bit line BL, and the other is connected to one electrode of capacitor 30. The other electrode of capacitor 30 is connected to wiring CL.

As shown in Figures 1A and 1B, multiple memory cells 15 arranged along the X direction are arranged so that the orientations of the transistors 20 are staggered. In other words, two transistors 20 adjacent along the X direction are arranged symmetrically with respect to the Y-Z plane.

The bit line BL functions as wiring for writing and reading data. The word line WL functions as wiring for controlling the on/off (conducting or non-conducting) of the transistor 20, which functions as a switch. The wiring CL functions as a constant potential line connected to the capacitance element 30.

It is also possible to configure the device so that a conductive layer to which a constant potential is applied is placed between each conductive layer 24. By placing such a conductive layer, it is possible to block the transmission of signals between two adjacent bit lines.

As shown in Figure 3A and other figures, the transistor 20 and the capacitor 30 are provided on an insulating layer 11 provided on a substrate (not shown). The insulating layer 11 functions as a base insulating layer.

Figure 7A shows an enlarged view of the transistor 20 and its vicinity in Figure 3A. The transistor 20 has a semiconductor layer 21, an insulating layer 22 that functions as a gate insulating layer, a conductive layer 23 that functions as a gate electrode, a conductive layer 24 that functions as one of a source electrode and a drain electrode, and a conductive layer 25 that functions as the other. Here, an example is shown in which the conductive layer 24 has a conductive film 24a and a conductive film 24b located thereon.

An insulating layer 41 is provided on insulating layer 11, and a conductive layer 24 and an insulating layer 42 are provided on insulating layer 41. The conductive layer 24 extends in the X direction and is embedded in the insulating layer 42. It is preferable that the heights of the upper surfaces of the conductive layer 24 and insulating layer 42 (heights from the upper surface of insulating layer 11) are roughly the same.

The insulating layer 41 functions as a protective insulating layer, preventing impurities such as hydrogen from diffusing into the semiconductor layer 21 from the insulating layer 11 side. For example, a film that is less susceptible to hydrogen diffusion than silicon oxide film (has barrier properties against hydrogen), such as a silicon nitride film, silicon nitride oxide film, aluminum oxide film, magnesium oxide film, hafnium oxide film, or gallium oxide film, can be used. It is particularly preferable to use a silicon nitride film or silicon nitride oxide film. Note that the insulating layer 41 need not be provided if it is not required.

In this specification and elsewhere, oxynitride refers to a material whose composition contains more oxygen than nitrogen, and nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

The conductive layer 24 has a conductive film 24a and a conductive film 24b located thereon. The conductive film 24a is preferably made of a conductive material with lower resistance than the conductive film 24b. It is particularly preferable for the conductive film 24a to contain a metal material. The conductive film 24b is preferably made of a conductive metal oxide (oxide conductor).

Using a conductive metal oxide for the conductive film 24b that contacts the semiconductor layer 21 containing a metal oxide reduces the contact resistance between them, thereby reducing the load on the wiring, which is preferable. In particular, it is preferable for the conductive film 24b to contain the same metal element as the metal element contained in the semiconductor layer 21, as this further reduces the contact resistance. Specifically, it is preferable that both the semiconductor layer 21 and the conductive film 24b contain the same one or more elements selected from In, Sn, Zn, Ga, and Ti. Furthermore, using a metal material with a lower resistance than the conductive film 24b for the conductive film 24a reduces both the contact resistance and the wiring resistance, thereby further reducing the load on the wiring.

An insulating layer 43 is provided on the conductive layer 24 and the insulating layer 42. The insulating layer 43 has an opening 47 extending in the Y direction. The shape of the opening 47 can be described as a groove, trench, slit, or the like. The opening 47 reaches the upper surface of the conductive film 24b and the upper surface of the insulating layer 42. It is preferable that the side surface of the opening 47 in the insulating layer 43 (which can also be called the sidewall of the opening 47) is approximately perpendicular to the surface on which it is formed (the upper surface of the conductive layer 24 or the insulating layer 42). It is also preferable that the depth of the opening 47 is greater than the width between adjacent openings 47 in the insulating layer 43.

Furthermore, although the above describes an example in which the insulating layer 43 has an opening 47, the present invention is not limited to this. For example, the insulating layer 43 may be a structure having a strip-shaped upper surface extending in the Y direction. In this case, the insulating layer 43 has a pair of side surfaces perpendicular to the X direction, with portions of these side surfaces overlapping the conductive layer 24. Furthermore, it is preferable that these side surfaces of the insulating layer 43 are approximately perpendicular to the surface on which they are formed. Furthermore, it is preferable that the height of the insulating layer 43 is greater than its width in the X direction.

In this specification, "two surfaces are perpendicular" means that the interior angle between them is between 80 degrees and 100 degrees. "Two surfaces are approximately perpendicular" means that the interior angle between them is between 60 degrees and 120 degrees. "Two surfaces are parallel" means that the interior angle between them is between -10 degrees and 10 degrees (including parallel). "Two surfaces are approximately parallel" means that the interior angle between them is between -30 degrees and 30 degrees (including parallel).

Here, it is preferable that the bottom edge of the opening 47 has a curved shape (which can also be called a rounded shape) with an arbitrary curvature, as shown in FIG. 7A. By using such a structure, the edges of the recesses in the semiconductor layer 21, insulating layer 22, and conductive layer 23 can also be similarly curved. This makes it possible to alleviate electric field concentration at the edges of the recesses in the conductive layer 23. This makes it possible to suppress the occurrence of dielectric breakdown in the transistor 20.

The semiconductor layer 21 extends in the Y direction. The semiconductor layer 21 has a vertical portion that contacts the sidewall of the opening 47 and a horizontal portion that contacts the top surface of the conductive layer 24. Note that the vertical portion is not limited to being strictly vertical; if the sidewall of the opening 47 is inclined with respect to the Z direction, the vertical portion of the semiconductor layer 21 is also inclined along the sidewall. Similarly, if the top surface of the conductive layer 24 is inclined with respect to the X-Y plane (e.g., the substrate surface), the horizontal portion of the semiconductor layer 21 is also inclined along the top surface.

More specifically, the vertical portion of the semiconductor layer 21 refers to a portion that is provided along the sidewall of the opening 47, and whose surface (either or both of the surface of the semiconductor layer 21 facing the insulating layer 43 or the surface of the insulating layer 22) is perpendicular or approximately perpendicular to the upper surface of the conductive layer 24 or the insulating layer 42. Furthermore, the horizontal portion of the semiconductor layer 21 refers to a portion that is provided along the upper surface of the conductive layer 24 or the insulating layer 42, and whose surface (the surface of the semiconductor layer 21 facing the conductive layer 24 or the surface of the insulating layer 22) is parallel or approximately parallel to the upper surface of the conductive layer 24 or the insulating layer 42.

The semiconductor layer 21 is also provided across the two transistors 20 provided in the opening 47. That is, the semiconductor layer 21 has a pair of vertical portions along the two opposing side walls of the opening 47, and one horizontal portion connected to these and in contact with the top surface of the conductive layer 24.

In transistor 20, the source electrode and drain electrode are located at different heights, so the current flowing through the semiconductor flows in the height direction. In other words, the channel length direction can be said to have a component in the height direction (vertical direction), and therefore a transistor according to one embodiment of the present invention can also be called a VFET, vertical transistor, vertical channel transistor, etc. Because transistor 20 allows two or more of the source electrode, semiconductor, and drain electrode to be stacked, it can occupy a significantly smaller area than a so-called planar transistor (which can also be called a lateral transistor, LFET (Lateral FET), etc.) in which the semiconductor is arranged on a flat surface.

Furthermore, the channel length of the transistor 20 can be precisely controlled by the thickness of the insulating layer 43 (which can also be referred to as the depth of the opening 47), which functions as a spacer. This allows for extremely small variations in channel length compared to planar transistors. Furthermore, by thinning the insulating layer 43, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more, can be fabricated. This allows for the realization of transistors with extremely short channel lengths that could not be achieved using mass-production exposure equipment. Furthermore, transistors with channel lengths of less than 10 nm can be fabricated without using the extremely expensive exposure equipment used in cutting-edge LSI technology.

The semiconductor layer 21 has at least a portion that exhibits semiconductivity. As shown in Figures 1A, 2A, and 2B, the semiconductor layer 21 has multiple regions 21a and multiple regions 21b. Figure 2B shows the structure above regions 21a and 21b removed from Figure 2A to make regions 21a and 21b easier to see. Region 21a is a region that exhibits semiconductivity, and region 21b is a region that exhibits insulation. In the semiconductor layer 21 provided within the opening 47, multiple regions 21a and multiple regions 21b are arranged alternately in the Y direction. In other words, among the multiple transistors 20 arranged in the opening 47, the transistors 20 that include region 21a are each isolated by region 21b. For this reason, region 21b can also be called an isolation region.

At least a portion of region 21a functions as a channel formation region. As shown in FIG. 7A, part of the vertical portion of region 21a functions as a channel formation region. The upper end of the vertical portion of region 21a contacts the lower end of conductive layer 25 and functions as either a source region or a drain region. The lower surface of the horizontal portion of region 21a contacts the upper surface of conductive film 24b and functions as the other of the source region or the drain region.

Region 21b has a higher resistivity than region 21a. For example, the resistivity of region 21b is preferably at least 10 times that of region 21a. Region 21b contains either aluminum or hafnium, or both. Region 21b has a higher concentration of either aluminum or hafnium, or both, than region 21a. One or more of aluminum oxide, hafnium oxide, and hafnium aluminate are formed in region 21b. Region 21b is also less crystalline than region 21a, and preferably has an amorphous structure.

As shown in FIG. 8A, region 21b, like region 21a, has vertical and horizontal portions. The upper end of the vertical portion of region 21b contacts the lower end of insulating layer 44. The lower surface of the horizontal portion of region 21b contacts the upper surface of insulating layer 42.

For example, when isolating elements by patterning the semiconductor layer into islands, the etching process may not be sufficient at the bottom of the opening 47, etc. This can lead to the risk of adjacent regions 21a becoming conductive. In response to this, forming the semiconductor layer 21 to cover the opening 47 and alternately forming regions 21a and 21b can achieve sufficient element isolation. This can improve the yield of semiconductor devices.

Insulating layer 22 is provided to cover the vertical and horizontal portions of semiconductor layer 21. Conductive layer 23 is located on insulating layer 22 and is provided to cover the vertical and horizontal portions of semiconductor layer 21 via insulating layer 22. Insulating layer 31 is provided on conductive layer 23. Insulating layer 31 is provided to cover the vertical and horizontal portions of semiconductor layer 21 via insulating layer 22 and conductive layer 23. Insulating layer 22, conductive layer 23, and insulating layer 31 are provided to extend in the Y direction within opening 47.

The insulating layer 31 is preferably made of an insulating film that has the function of capturing or fixing hydrogen. This allows the insulating layer 31 to capture or fix hydrogen that may diffuse into the semiconductor layer 21 due to heat or other factors applied during the manufacturing process of the transistor 20 or memory cell 15, thereby reducing the concentration of hydrogen contained in the semiconductor layer 21. This makes it possible to achieve a transistor 20 or semiconductor device 10 with good electrical characteristics and high reliability. It is preferable to use a hafnium oxide film, hafnium silicate film, aluminum oxide film, or the like as an insulating film that can be used for the insulating layer 31 and that can capture or fix hydrogen.

Slits are provided in insulating layer 31, conductive layer 23, and insulating layer 22 that reach semiconductor layer 21, dividing them at the slits. Furthermore, within the slits, insulating layer 32 is provided along and in contact with the side surfaces of insulating layer 31, conductive layer 23, and insulating layer 22, as well as the top surface of semiconductor layer 21. Furthermore, insulating layer 33 is provided on insulating layer 32 so as to fill the slits. Insulating layer 32 and insulating layer 33 are provided within opening 47, extending in the Y direction.

As with insulating layer 41, insulating layer 32 is preferably made of an insulating film that has barrier properties against hydrogen. This prevents hydrogen contained in insulating layer 33 and the like from diffusing toward semiconductor layer 21. For insulating layer 32, it is preferable to use a silicon nitride film, silicon nitride oxide film, aluminum oxide film, magnesium oxide film, hafnium oxide film, gallium oxide film, or the like. It is particularly preferable to use a silicon nitride film or silicon nitride oxide film.

It is preferable to use an insulating material with a low dielectric constant for the insulating layer 33. This reduces the parasitic capacitance between the pair of conductive layers 23 sandwiching the insulating layer 33. For example, inorganic insulating materials such as silicon oxide and silicon oxynitride can be used for the insulating layer 33.

Insulating layer 34 is provided in contact with the upper surfaces of conductive layer 23, insulating layer 31, insulating layer 32, and insulating layer 33. Insulating layer 34 can also be provided in contact with the side surface of insulating layer 22 (the side surface on the insulating layer 33 side). Insulating layer 34 is provided within opening 47, extending in the Y direction.

As with insulating layers 32 and 41, it is preferable to use an insulating film that has barrier properties against hydrogen as insulating layer 34. This makes it possible to prevent hydrogen from diffusing from above insulating layer 34 toward semiconductor layer 21. It is preferable to use a silicon nitride film, silicon nitride oxide film, aluminum oxide film, magnesium oxide film, hafnium oxide film, gallium oxide film, or the like for insulating layer 34. In particular, it is preferable to use a silicon nitride film or silicon nitride oxide film.

Furthermore, it is preferable to use an insulating film for the insulating layer 34 that has the function of capturing or fixing hydrogen, similar to the insulating layer 31. This makes it possible for the insulating layer 34 to capture or fix hydrogen that may diffuse into the semiconductor layer 21 due to heat or other factors applied during the manufacturing process of the transistor 20 or memory cell 15, thereby reducing the concentration of hydrogen contained in the semiconductor layer 21. This makes it possible to realize a transistor 20 or semiconductor device 10 with good electrical characteristics and high reliability. It is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, or the like as an insulating film that can capture or fix hydrogen and that can be used for the insulating layer 34.

An insulating layer 44 is provided to cover insulating layers 43, 22, and 34. The insulating layer 44 functions as an interlayer insulating film. For the insulating layer 44, an inorganic insulating material such as silicon oxide or silicon oxynitride can be used.

Furthermore, a conductive layer 25 is provided on the insulating layer 34, the insulating layer 22, and the semiconductor layer 21. Here, the upper surface of the vertical portion of the semiconductor layer 21 can be located below the upper surface of the insulating layer 22, and a portion of the conductive layer 25 can be provided in the gap surrounded by the insulating layer 43, the insulating layer 22, and the semiconductor layer 21. In this case, the upper surface of the semiconductor layer 21 is preferably located below the upper surface of the conductive layer 23. If the upper surface of the semiconductor layer 21 is located above the upper surface of the conductive layer 23, a so-called offset region, where no gate electric field is applied, may be formed. Therefore, by processing the upper surface of the semiconductor layer 21 so that it is located below the upper surface of the conductive layer 23, the formation of an offset region in the semiconductor layer 21 can be prevented, and the current that the transistor 20 can pass can be increased. This makes it possible to realize a semiconductor device 10 with high operating speed.

Note that while Figure 7A and other figures show a case where the sidewall of the opening 47 and the side surface of the insulating layer 44 are flush with each other, in a plan view, the side surface of the insulating layer 44 can be positioned outside the sidewall of the opening 47. In this case, a portion of the conductive layer 25 will be in contact with the upper surface of the insulating layer 43.

Furthermore, as shown in FIG. 8A, in areas where conductive layer 25 is not provided, a portion of insulating layer 44 is provided in the gap surrounded by insulating layer 43, insulating layer 22, and semiconductor layer 21. Note that in the cross section shown in FIG. 7A, region 21a of semiconductor layer 21 contacts conductive layer 25, and in the cross section shown in FIG. 8B, region 21b of semiconductor layer 21 contacts insulating layer 44. In this manner, at least a portion of region 21a contacts conductive layer 25, and at least a portion of region 21b contacts insulating layer 44. However, there are cases where another portion of region 21a contacts insulating layer 44. There are also cases where another portion of region 21b contacts conductive layer 25.

Here, two transistors 20 are provided symmetrically in the opening 47 when viewed cross-sectionally in the Y direction. More specifically, the semiconductor layer 21, a pair of conductive layers 25, a pair of conductive layers 23, a pair of insulating layers 22, a pair of insulating layers 31, etc. are provided symmetrically in the opening 47 with respect to the Y-Z plane. In this way, providing the transistors 20 along each of the two opposing sidewalls of the opening 47 is preferable because it increases the integration density of the transistors 20.

An insulating layer 45 is provided covering the conductive layer 25 and the insulating layer 44. Similar to the insulating layers 34, 32, and 41, it is preferable to use an insulating film that has barrier properties against hydrogen for the insulating layer 45. This makes it possible to prevent hydrogen from diffusing from above the insulating layer 45 toward the semiconductor layer 21. It is preferable to use a silicon nitride film, silicon nitride oxide film, aluminum oxide film, magnesium oxide film, hafnium oxide film, gallium oxide film, or the like for the insulating layer 45. It is particularly preferable to use a silicon nitride film or a silicon nitride oxide film.

Insulating layer 46 is provided on insulating layer 45. Insulating layer 46 functions as an interlayer insulating layer. As with insulating layer 44, insulating layer 46 can be made of an inorganic insulating material such as silicon oxide or silicon oxynitride.

As shown in FIG. 3A, insulating layers 45 and 46 have openings that reach conductive layer 25. Capacitive element 30 is provided in the openings provided in insulating layers 45 and 46. Here, the openings in insulating layers 45 and 46 are vertical holes, and, unlike opening 47, preferably do not extend in the X or Y directions.

The capacitor element 30 has a conductive layer 51 that functions as a lower electrode, a conductive layer 53 that functions as an upper electrode, and an insulating layer 52 disposed therebetween and that functions as a dielectric. The conductive layer 51 has a vertical portion that is provided along the side surfaces of the openings in the insulating layers 45 and 46, and a horizontal portion that contacts the upper surface of the conductive layer 25. In other words, the conductive layer 51 has a cylindrical (also called cup-shaped) shape with a bottom and a recess. The insulating layer 52 has a portion that is provided along the recess of the conductive layer 51, a portion that contacts the upper surface of the conductive layer 51, and a portion that contacts the upper surface of the insulating layer 46. The conductive layer 53 is provided so as to fill the recess of the conductive layer 51 via the insulating layer 52. The conductive layer 53 also has a portion that is provided on the insulating layer 46 via the insulating layer 52. The conductive layer 51 is provided individually for each memory cell, while the conductive layer 53 is provided in common to multiple memory cells. Here, the upper part of the conductive layer 53 also serves as the wiring CL.

Here, as shown in FIG. 7A, it is preferable that the edges of the bottom surfaces of the openings in insulating layer 45 and insulating layer 46 have a curved shape with an arbitrary curvature. The curved shape may be formed only in insulating layer 45, or may be formed across insulating layer 45 and insulating layer 46. By using such a structure, the edges of the recesses in insulating layer 52 and the edges of the protrusions in conductive layer 53 can also be similarly curved. This makes it possible to alleviate electric field concentration at the edges of the protrusions in conductive layer 53. This makes it possible to suppress dielectric breakdown in capacitive element 30.

Furthermore, as shown in FIG. 7A, the upper end of the conductive layer 51 can be configured to be lower than the upper surface of the insulating layer 46. The upper end of the conductive layer 51 can also be tapered. Here, the upper end of the conductive layer 51 and the upper end of the insulating layer 46 preferably have a curved shape with an arbitrary curvature, as shown in FIG. 7A. By using such a structure, the insulating layer 52 can also be similarly curved. This makes it possible to alleviate electric field concentration at the upper end of the conductive layer 51. Therefore, it is possible to prevent dielectric breakdown from occurring in the capacitance element 30.

In Figure 1A, an example is shown in which the outline of the conductive layer 51 in a planar view is circular, but this is not limited to this. For example, the shape of the outline of the conductive layer 51 in a planar view is not limited to a circle, and can be an ellipse, a rectangle with rounded corners, or the like. It may also be a regular polygon such as an equilateral triangle, square, or regular pentagon, or a polygon other than a regular polygon. Furthermore, if the outline is a concave polygon, such as a star-shaped polygon, with at least one interior angle exceeding 180 degrees, the capacitance of the capacitive element 30 can be increased. Other shapes include a polygon with rounded corners, or a closed curve that combines straight lines and curves.

Furthermore, as shown in FIG. 1A, the horizontal cross-sectional shape of the conductive layer 51 can also be considered to be annular. However, the horizontal cross-sectional shape of the conductive layer 51 is not limited to annular, and can be any shape as long as it is annular. For example, it can be an annular, elliptical, regular polygonal, polygonal other than a regular polygonal, concave polygonal, polygonal with rounded corners, etc.

The capacitive element 30 illustrated in Figure 3A and elsewhere is a so-called cylinder-type or trench-type capacitive element. The configuration of the capacitive element 30 is not limited to this, and a pillar-type capacitive element, for example, may also be used. Figure 5 shows an example in which a pillar-type capacitive element 30a is used.

In Figure 5, a columnar conductive layer 51 is provided on conductive layer 25, and an insulating layer 52 is provided covering the top and side surfaces of conductive layer 51. A conductive layer 53 is further provided to cover the top and side surfaces of conductive layer 51 via insulating layer 52. The outline shape of conductive layer 51 in a plan view is typically circular, but can also be any of the various shapes described above.

Here, it is preferable that the semiconductor device 10 be provided with a layer in which the memory cells 15 are provided, stacked on top of a layer in which the functional circuits are provided. The functional circuits may include, for example, a drive circuit for driving the memory cells 15, as well as an arithmetic circuit and a power supply circuit. The drive circuit may include, for example, one or more of a row decoder, column decoder, row driver, column driver, input circuit, output circuit, sense amplifier, etc. This not only reduces the footprint of the semiconductor chip including the semiconductor device 10, but also shortens the wiring length compared to when the functional circuits and memory cells 15 are arranged side by side, thereby achieving high-speed operation and low power consumption.

Figure 6 shows an example in which a transistor 90 that constitutes a functional circuit is placed below the insulating layer 11. In this example, one of the source electrode and drain electrode of the transistor 90 is connected to a conductive layer 24 that functions as a bit line.

Transistor 90 is a transistor in which a channel is formed in a portion of substrate 91, which is a single-crystal semiconductor substrate. Substrate 91 is typically made of single-crystal silicon. Substrate 91 can also be made of a semiconductor made of a single element such as germanium, or a compound semiconductor made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride. Alternatively, substrate 91 can be a semiconductor substrate having an insulator region within the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.

Transistor 90 is provided on substrate 91 and has a conductive layer 94 that functions as a gate, an insulating layer 93 that functions as a gate insulating layer, a semiconductor region 92 that is part of substrate 91, and low-resistance regions 95a and 95b that function as source and drain regions. Transistor 90 may be either a p-channel or n-channel type. An element isolation layer 98 is provided on substrate 91 between two adjacent transistors 90.

In the transistor 90, the semiconductor region 92 in which the channel is formed has a convex shape (fin shape). Also, although not shown in FIG. 6, in the X direction, the side and top surfaces of the semiconductor region 92 are covered with a conductive layer 94 via an insulating layer 93. Such a transistor 90 is also called a FIN-type transistor.

An insulating layer 85 is provided covering the transistor 90, an insulating layer 86 is provided on the insulating layer 85, and an insulating layer 87 is provided on the insulating layer 86. A conductive layer 81 is provided so as to be embedded in the insulating layer 87. An insulating layer 11 is provided covering the conductive layer 81 and the insulating layer 87. A plug 82 is provided inside an opening provided in the insulating layer 85 and the insulating layer 86, and the plug 82 connects the conductive layer 81 to the low-resistance region 95b. A plug 83 is provided inside an opening provided in the insulating layer 41 and the insulating layer 11, and the plug 83 connects the conductive layer 24 (specifically, the conductive film 24a) to the conductive layer 81.

Note that although an example in which a conductive layer 81 is provided as a wiring layer has been shown here, a structure in which interlayer insulating layers and wiring layers are alternately stacked (also called a multilayer wiring layer) can also be used between the layer in which the transistor 90 is provided and the layer in which the memory cell 15 is provided.

The above is an explanation of an example configuration of a semiconductor device.

[About the components]
<substrate>
Substrates on which transistors are formed may be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates having an insulating region within the aforementioned semiconductor substrate include silicon-on-insulator (SOI) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Substrates containing metal nitrides and substrates containing metal oxides can also be used. Examples of substrates include an insulating substrate having a conductive layer or semiconductor layer provided thereon, a semiconductor substrate having a conductive layer or insulating layer provided thereon, and a conductive substrate having a semiconductor layer or insulating layer provided thereon. Alternatively, a substrate provided with elements may be used, such as a capacitor, a resistor, a switch (including a transistor), a light-emitting element, a memory element, or the like.

Semiconductor layer
The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

Examples of metal oxides that can be used for the semiconductor layer 21 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. Element M is a metal or semimetal element with a high bond energy with oxygen, such as a metal or semimetal element with a higher bond energy with oxygen than indium. Specific examples of element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, and is preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide having In, M, and Zn may be referred to as an In-M-Zn oxide. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the term "metal elements" used in this specification may include metalloid elements.

When the metal oxide is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide be equal to or greater than the atomic ratio of M. For example, the atomic ratios of the metal elements in such an In-M-Zn oxide may be In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions close to these. Note that a composition close to these may include a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

Furthermore, the atomic ratio of In in In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of the metal elements in such In-M-Zn oxide may be In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, or compositions close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

The semiconductor layer 21 can be made of, for example, In oxide, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, or In-Ga-Al-Zn oxide. Ga-Zn oxide may also be used. A material that does not contain Zn, such as indium oxide, is preferred because it increases compatibility with LSI manufacturing processes. On the other hand, a material that contains Zn is preferred because it facilitates high crystallinity.

Note that, instead of or in addition to indium, the metal oxide may contain one or more metal elements with higher period numbers in the periodic table. The greater the overlap of the orbitals of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

Furthermore, the metal oxide may contain one or more non-metallic elements. The presence of non-metallic elements in the metal oxide may increase the field-effect mobility of the transistor. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

Metal oxides can be formed preferably using sputtering or atomic layer deposition (ALD). It is particularly preferable to form metal oxide films using the ALD method, which has excellent coating properties. When forming metal oxides using the sputtering method, the composition of the metal oxide film after formation may differ from the composition of the target. In particular, the zinc content in the metal oxide film after formation may be reduced to around 50% of that of the target.

In this specification, the content of a certain metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, when a metal oxide contains metal element X, metal element Y, and metal element Z, and the numbers of atoms of metal element X, metal element Y, and metal element Z contained in the metal oxide are _Ax , _Ay , and _Az , respectively, the content of metal element X can be expressed as _Ax /( _Ax + _Ay + _Az ). Furthermore, when the ratio of the numbers of atoms of metal element X, metal element Y, and metal element Z in the metal oxide (atomic number ratio) is expressed as _Bx :By _{: Bz} , the content of metal element X can be expressed as _Bx /( _Bx + _By + _Bz ).

For example, in the case of metal oxides containing In, increasing the In content can produce transistors with large on-state currents.

By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, it is possible to create a transistor that is highly reliable when a positive bias is applied. In other words, it is possible to create a transistor with a small amount of threshold voltage variation in a PBTS (Positive Bias Temperature Stress) test. Furthermore, when using a metal oxide that contains Ga, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor that is both highly reliable and highly mobile.

On the other hand, by increasing the Ga content, it is possible to create a transistor with high reliability against light. In other words, it is possible to create a transistor with small threshold voltage fluctuations in NBTIS (Negative Bias Temperature Illumination Stress) testing. Specifically, metal oxides in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In have a larger band gap, which makes it possible to reduce the threshold voltage fluctuations in NBTIS testing of transistors.

Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide. This therefore suppresses fluctuations in the transistor's electrical characteristics and improves reliability.

The semiconductor layer 21 may have a stacked structure having two or more metal oxide layers. The two or more metal oxide layers of the semiconductor layer 21 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs. A stacked structure may also be used in which two or more oxide semiconductor layers with different compositions are stacked. Furthermore, by using the ALD method, it is possible to form metal oxide layers whose compositions vary continuously in the thickness direction. This not only broadens the range of design options compared to using films with fixed compositions, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical properties and reliability. Furthermore, a metal oxide layer with a stacked structure may be formed using both the sputtering method and the ALD method.

When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (higher conductivity) for the second layer, i.e., the side closer to the gate electrode, than for the first layer. This allows for a normally-off transistor with a large on-current. This makes it possible to achieve both low power consumption and high performance. Alternatively, a material with higher mobility than the second layer may be used for the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a large on-current.

Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers. This makes it possible to realize a transistor with a high on-state current and high reliability.

The differences in high mobility and high conductivity mentioned above can be expressed, for example, by the high indium content. Furthermore, whether or not an element other than indium that contributes to improved conductivity is included, as well as the content of that element, also affects mobility and conductivity. Examples of high-mobility materials include In:Ga:Zn = 4:3:2 [atomic ratio] and materials in the vicinity, In:Zn = 1:1 [atomic ratio] and materials in the vicinity, In:Zn = 2:1 [atomic ratio] and materials in the vicinity, In:Zn = 4:1 [atomic ratio] and materials in the vicinity, In:Sn:Zn = 40:X:10 [atomic ratio] (X is 0.1 or greater and 5 or less, typically X = 1) and materials in the vicinity. On the other hand, materials with lower mobility or conductivity than the above-mentioned materials include materials with an atomic ratio of In:Ga:Zn = 1:3:2 and similar materials, materials with an atomic ratio of In:Ga:Zn = 1:3:4 and similar materials, materials with an atomic ratio of In:Ga:Zn = 2:2:1 and similar materials, materials with an atomic ratio of In:Ga:Zn = 1:1:1 and similar materials, and materials with an atomic ratio of In:Ga:Zn = 1:1:2 and similar materials.

It is preferable to use a crystalline metal oxide layer for the semiconductor layer 21. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, or a nanocrystalline (nc) structure can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the defect level density in the semiconductor layer 21 can be reduced, resulting in a highly reliable semiconductor device.

The higher the crystallinity of the metal oxide layer used in the semiconductor layer 21, the more the defect level density in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, it is possible to realize a transistor that can pass a large current.

Region 21a of semiconductor layer 21 preferably has the above-described configuration. Meanwhile, region 21b of semiconductor layer 21 is a metal oxide obtained by adding a metal element (either aluminum or hafnium, or both) to the above-described metal oxide. By adding either aluminum or hafnium, or both, to a metal oxide such as In-Ga-Zn oxide, the insulating properties can be improved, allowing region 21b to function as an element isolation region. The resistivity of region 21b is preferably at least 10 times that of region 21a.

Region 21b has a higher concentration of either aluminum or hafnium, or both, than region 21a. The composition of the metal oxides in regions 21b and 21a was analyzed using secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), and Auger electron spectroscopy (AES). Methods that can be used include Auger Electron Spectroscopy, Inductively Coupled Plasma Mass Spectrometry (ICP-MS), and Inductively Coupled Plasma Atomic Emission Spectrometry (ICP-AES). Alternatively, a combination of these methods may be used for analysis.

Either or both of the aluminum and hafnium added to region 21b may combine with oxygen and exist in region 21b as aluminum oxide, hafnium oxide, or hafnium aluminate. While aluminum and hafnium are described above as elements to be added to region 21b, the present invention is not limited to this. The element to be added to region 21b may be any element that at least increases the resistivity of region 21b. For example, silicon or gallium may be added to region 21b. In this case, the concentration of silicon or gallium in region 21b will be higher than in region 21a.

The crystallinity of region 21b may decrease due to the addition of the above-mentioned metal elements. In this case, the crystallinity of region 21b may be lower than that of region 21a. For example, region 21a may have a CAAC structure, while region 21b may have an amorphous structure. The crystallinity of the metal oxides in regions 21b and 21a can be analyzed using, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED).

Region 21b has low crystallinity and contains more oxygen vacancies than region 21a, and therefore has the function of capturing or fixing (this can also be called gettering) the hydrogen and excess oxygen contained in region 21a. For example, by performing a heat treatment, the hydrogen and excess oxygen contained in region 21a can be captured or fixed in region 21b. In this case, when the oxygen or hydrogen profile is measured using SIMS, the oxygen or hydrogen concentration is higher in region 21b than in region 21a. Note that in this specification, excess oxygen refers to oxygen in an amount greater than that which satisfies the stoichiometric composition.

By gettering hydrogen contained in region 21a in region 21b, the hydrogen concentration in region 21a, which functions as a channel formation region, can be reduced, thereby suppressing a negative shift in the initial characteristics of transistor 20 and achieving normally-off characteristics. Furthermore, negative drift degradation during +GBT stress testing can be suppressed.

Furthermore, by gettering the excess oxygen contained in region 21a in region 21b, the excess oxygen in region 21a, which functions as a channel formation region, can be reduced, and the formation of electron traps caused by the excess oxygen can be suppressed. This makes it possible to suppress an excessive positive shift in the initial characteristics of transistor 20 caused by the electron traps. It also makes it possible to suppress excessive positive drift degradation in a +GBT stress test. As described above, by gettering the hydrogen and excess oxygen contained in region 21a to region 21b, the electrical characteristics and reliability of transistor 20 can be improved.

Transistors using an oxide semiconductor (hereinafter referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors have extremely low source-drain leakage current in an off state (hereinafter also referred to as off-state current), and can retain charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of OS transistors can reduce the power consumption of semiconductor devices.

A semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. A transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, thereby enabling high-speed circuit operation and low power consumption at the same time.

A semiconductor device according to one embodiment of the present invention can also be applied to a display device, for example. To increase the light-emitting luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Because an OS transistor has a higher source-drain breakdown voltage than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the light-emitting luminance of the light-emitting device.

When the transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current in response to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a greater number of gray levels in the pixel circuit. Furthermore, a stable current can be supplied even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary.

As mentioned above, by using an OS transistor for the drive transistor included in the pixel circuit, it is possible to achieve things like "suppression of black floating," "increase in light emission brightness," "multiple gray levels," and "suppression of the effects of manufacturing variations in light-emitting devices."

OS transistors exhibit little change in electrical characteristics due to radiation exposure, meaning they have high radiation resistance, making them suitable for use in environments where radiation may be present. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be used favorably in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be used favorably in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

Note that the semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of single elements or compound semiconductors can be used. Examples of semiconductors made of single elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. Note that these semiconductor materials may contain impurities as dopants.

Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. Layered materials have high electrical conductivity within each layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, it is possible to provide a transistor with a large on-current.

Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (typically MoS ₂ ), molybdenum selenide (typically MoSe ₂ ), molybdenum tellurium (typically MoTe 2 ), tungsten sulfide (typically WS ₂ ), tungsten selenide (typically WSe ₂ ), tungsten tellurium (typically WTe _{2 )} , hafnium sulfide (typically HfS ₂ ), hafnium selenide (typically HfSe ₂ ), zirconium sulfide (typically ZrS ₂ ), and zirconium selenide (typically ZrSe ₂ ).

The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, or a semiconductor with crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor with a crystalline region in part) may be used. The use of a crystalline semiconductor is preferable because it can suppress degradation of the transistor characteristics.

<Gate insulating layer>
The insulating layer 22 functions as a gate insulating layer of the transistor. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least a film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

Furthermore, the insulating layer 22 is preferably made of a laminated insulating material made of a high-k material, and preferably has a laminated structure of a material with a high dielectric constant (high-k) and a material with a higher dielectric strength than the high-k material. For example, the insulating layer 22 can be made of an insulating film (also called ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order. Alternatively, the insulating film (also called ZAZA) can be made of an insulating film (also called hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide) in this order. Alternatively, the insulating film can be made of an insulating film (also called hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide) in this order. By using a laminated insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitance element can be suppressed.

Alternatively, a material exhibiting ferroelectricity may be used for the insulating layer 22. Examples of materials exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO _x (X is a real number greater than 0). Alternatively, a metal oxide obtained by adding Y (yttrium) to HfZrO _x (X is a real number greater than 0) may be used. Adding Y (yttrium) to _HfZrO x (X is a real number greater than 0) can enhance the ferroelectricity.

When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film that has the function of capturing or fixing hydrogen as the film in contact with the semiconductor layer 21, and to use an insulating film that has barrier properties against hydrogen as the film located on the conductive layer 23 side that functions as the gate electrode. This makes it possible to prevent hydrogen from diffusing from the conductive layer 23 side to the semiconductor layer 21, resulting in a highly reliable transistor.

As an insulating film that captures or fixes hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, etc. Furthermore, as an insulating film that has barrier properties against hydrogen, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, etc.

Alternatively, an insulating film that releases oxygen when heated may be used for the film in contact with the semiconductor layer 21, and an insulating film that has barrier properties against hydrogen may be used for the film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen when heated may be used for the film in contact with the semiconductor layer 21, and an insulating film that has the function of capturing or fixing hydrogen may be used for the film located on the conductive layer 23 side.

When the insulating layer 22 has a three-layer structure, it is preferable to use an insulating film made of a material with a lower dielectric constant than the other films for the film in contact with the semiconductor layer 21, an insulating film with barrier properties against hydrogen and oxygen for the film on the conductive layer 23 side, and an insulating film with the function of capturing or fixing hydrogen for the film between them. Silicon oxide or silicon oxynitride can be used as a material with a low dielectric constant. With this configuration, oxygen can be supplied to the semiconductor layer 21 from the film in contact with the semiconductor layer 21. Furthermore, the film on the conductive layer 23 side prevents oxygen from diffusing toward the conductive layer 23, suppressing oxidation of the conductive layer 23.

As an insulating film having barrier properties against oxygen, it is preferable to use an aluminum oxide film, silicon nitride film, hafnium oxide film, hafnium silicate film, etc. As an insulating film having barrier properties against oxygen and hydrogen, it is preferable to use an aluminum oxide film, silicon nitride film, hafnium oxide film, etc.

When the insulating layer 22 has a four-layer structure, it is preferable to use an insulating film with oxygen barrier properties for the film in contact with the semiconductor layer 21, an insulating film made of a material with a lower dielectric constant than the other films for the film next closest to the semiconductor layer 21, an insulating film with the function of capturing or fixing hydrogen for the film next closest to the semiconductor layer 21, and an insulating film with hydrogen and oxygen barrier properties for the film closest to the conductive layer 23. That is, in addition to the three-layer structure described above, a configuration can be achieved in which a film in contact with the semiconductor layer 21 is added. By using an insulating film with oxygen barrier properties for the film in contact with the semiconductor layer 21, oxygen desorption from the semiconductor layer 21 can be suppressed. In this case, it is preferable to use an aluminum oxide film for the film in contact with the semiconductor layer 21. Aluminum oxide not only has oxygen barrier properties, but also has the function of capturing or fixing hydrogen, which effectively prevents hydrogen from diffusing into the semiconductor layer 21.

When the insulating layer 22 has a layered structure, each insulating film is preferably a thin film. For example, by making the thickness of the insulating layer 22 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also known as the S value) of the transistor can be reduced. Furthermore, the thickness of each insulating film is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less.

As a specific example, a four-layer structure is used in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 21 side, and the thicknesses of these films are preferably 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 21 side.

In this specification and the like, the term "barrier property" refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). When hydrogen is described as a corresponding substance, it refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen, such as a water molecule or OH ⁻ . Furthermore, when impurities are described as a corresponding substance, unless otherwise specified, they refer to impurities in a channel formation region or a semiconductor layer, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (such as N ₂ O, NO, or NO ₂ ), a copper atom, and the like. Furthermore, when oxygen is described as a corresponding substance, it refers to at least one of, for example, an oxygen atom, an oxygen molecule, and the like.

Here, the electrical characteristics of a transistor using a metal oxide film can be stabilized by surrounding it with an insulating film that has the function of suppressing the permeation of impurities and oxygen. The insulating film that has the function of suppressing the permeation of impurities and oxygen can be, for example, an insulating film containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, the insulating film that has the function of suppressing the permeation of impurities and oxygen can be made of metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or nitrides such as aluminum nitride, silicon nitride oxide, or silicon nitride.

Specific examples of insulating film materials that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Also, examples of insulating film materials that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Also, examples of insulating film materials that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include nitrides such as aluminum nitride, aluminum titanium nitride, silicon nitride oxide, and silicon nitride.

Insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may also contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and/or grain boundaries in some areas.

<Conductive layer>
The conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of the conductive layer 24 or the conductive layer 25 in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portion of the conductive layer 24 and the conductive layer 25 in contact with the semiconductor layer 21.

For the conductive film 24b and conductive layer 25 in contact with the semiconductor layer 21, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. These are preferable because they are conductive materials that are resistant to oxidation or materials that maintain their conductivity even when oxidized.

Alternatively, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, and Ga-Zn oxide can be used. Conductive oxides containing indium are particularly preferred due to their high conductivity. Alternatively, oxide materials such as In-Ga-Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

For example, conductive layer 24 and conductive layer 25 can each be a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are laminated in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is laminated on tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is laminated on the above-mentioned conductive oxide film, or a two-layer structure in which the above-mentioned conductive oxide film is laminated on a ruthenium film or a ruthenium oxide film.

The conductive layer 23 functions as a gate electrode and can be made of a variety of conductive materials. For the conductive layer 23, it is preferable to use a metal element selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing such a metal element. Nitrides of the above metals or alloys, or oxides of the above metals or alloys, may also be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable. Highly conductive semiconductors, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

In addition, the nitrides and oxides that can be used for the conductive layers 24 and 25 may also be applied to the conductive layer 23.

Because conductive layer 23, conductive film 24a, and conductive layer 25 also function as wiring, it is preferable to use a laminate of low-resistance conductive materials. For example, the upper layer of conductive film 24a and conductive layer 25 can be made of a low-resistance conductive material that can be used for conductive layer 23 described above.

<Insulating layer>
The insulating layer 43 can be used as an interlayer insulating film. For example, it is preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, by forming the insulating layer 43 by a sputtering method without using hydrogen gas as a film formation gas, a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 20 can be stabilized.

Since the insulating layer 43 is in contact with the channel formation region of the semiconductor layer 21, it is preferable to use an oxide insulating film. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. The oxide insulating film that can be used for the gate insulating layer described above can be used as the insulating layer 43.

Furthermore, since the insulating layer 43 functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a higher film formation rate than other insulating layers. For example, the insulating layer 43 can be formed by a plasma CVD method. When forming the insulating _layer 43 by the plasma CVD method, it is preferable to use TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si( _OC2H5 ) ₄ ). This can improve productivity.

Insulating layer 11, insulating layer 42, insulating layer 44, and insulating layer 46 each function as an interlayer insulating layer. The insulating materials that can be used for insulating layer 43 above can be used for insulating layer 11, insulating layer 42, insulating layer 44, and insulating layer 46.

The insulating layer 52 functions as a dielectric for the capacitance element 30. The same insulating material as the insulating layer 22 can be used for the insulating layer 52. Furthermore, by using a material exhibiting ferroelectricity as described above for the insulating layer 52, the capacitance element 30 can be made into a ferroelectric capacitor, thereby realizing a non-volatile memory device. Note that a resistance change type memory element that utilizes the electric field induced giant resistance change (CER: Colossal Electro-Resistance) effect can also be used as the capacitance element 30.

This concludes the explanation of the components.

[Modification]
An example in which the configuration is partially different from the above configuration example will be described below. Note that the same reference numerals are used to designate the same parts as those described above, and the description thereof will be omitted.

[Variation 1]
The configuration shown in FIG. 8B differs from the above example configuration mainly in that the shape of the conductive layer 24 is different.

A recess is formed in the conductive film 24b of the conductive layer 24. More specifically, the thickness of the non-overlapping area of the conductive film 24b is thinner than the area where the conductive film 24b overlaps with the insulating layer 43. Furthermore, the semiconductor layer 21 contacts not only the top surface of the recess in the conductive film 24b but also the side surfaces. This configuration increases the contact area between the semiconductor layer 21 and the conductive film 24b, further reducing the contact resistance between them.

Here, it is preferable that the end of the recess in the conductive film 24b has a curved shape (which can also be called a rounded shape) with an arbitrary curvature, as shown in Figure 8B. By using such a structure, the ends of the recesses in the insulating layer 22 and conductive layer 23 can also be made similarly curved. This makes it possible to alleviate electric field concentration at the end of the recess in the conductive layer 23. This makes it possible to suppress the occurrence of dielectric breakdown in the transistor 20.

Also, as shown in Figure 7B, conductive layer 25 can have a layered structure of conductive film 25a and conductive film 25b on conductive film 25a. In this case, a recess can be formed in conductive film 25b, similar to conductive film 24b shown in Figure 8B. Here, conductive layer 51 contacts not only the top surface of conductive film 25b in the recess, but also the side surfaces. With this configuration, the contact area between conductive layer 51 and conductive film 25b can be increased, further reducing the contact resistance between them.

Furthermore, by making the ends of the recesses in the conductive film 25b curved with an arbitrary curvature as shown in Figure 7B, the ends of the recesses in the insulating layer 52 and the ends of the protrusions in the conductive layer 53 can also be made similarly curved. This makes it possible to alleviate electric field concentration at the ends of the protrusions in the conductive layer 53. This makes it possible to prevent dielectric breakdown in the capacitive element 30.

[Variation 2]
The configuration shown in FIG. 9A differs from the above-described configuration example mainly in that the insulating layer 31 is not provided.

In Figure 9A, insulating layer 32 is provided in contact with the surface of conductive layer 23 on the insulating layer 33 side. A portion of insulating layer 32 covers the horizontal portion of semiconductor layer 21 via conductive layer 23 and insulating layer 22. In addition, insulating layer 33 has a portion that covers the horizontal portion of semiconductor layer 21 via insulating layer 32, conductive layer 23, and insulating layer 22. By not providing insulating layer 31, the step of forming insulating layer 31 can be omitted, which is preferable because it simplifies the manufacturing process.

Furthermore, Figure 9B shows an example in which the conductive film 24b having the recesses illustrated in Variation 1 above is applied to this configuration.

In the configuration shown in Figures 9A and 9B, it is preferable to use an insulating film that has the function of capturing or fixing hydrogen as insulating layer 32 or insulating layer 33 instead of insulating layer 31. It is preferable to use a hafnium oxide film, hafnium silicate film, aluminum oxide film, etc. as an insulating film that can capture or fix hydrogen and that can be used as insulating layer 32 or insulating layer 33.

[Variation 3]
The configuration shown in FIG. 9C differs from the second modification mainly in that it does not have the insulating layer 33 and that the shape of the insulating layer 32 is different.

Insulating layer 32 is provided so as to fill the area surrounded by conductive layer 23, insulating layer 22, semiconductor layer 21, and insulating layer 34. This configuration eliminates the need for steps to form insulating layers 31 and 33, thereby simplifying the manufacturing process.

Furthermore, Figure 9D shows an example in which the conductive film 24b having the recesses illustrated in Variation 1 above is applied to this configuration.

In the configuration shown in Figures 9C and 9D, it is preferable to use an insulating film that has the function of capturing or fixing hydrogen as insulating layer 32 instead of insulating layer 31. Examples of insulating films that can be used for insulating layer 32 and that have the function of capturing or fixing hydrogen include hafnium oxide film, hafnium silicate film, and aluminum oxide film.

[Modification 4]
The configuration shown in FIG. 10A differs from the above-described configuration example mainly in that an insulating layer 22 is provided between an insulating layer 32 and a semiconductor layer 21 .

With this configuration, the top surface of the semiconductor layer 21 is not exposed during the process of forming the insulating layer 32 and is covered by the insulating layer 22, thereby reducing damage to the semiconductor layer 21 and improving reliability.

Furthermore, Figure 10B shows an example in which the conductive film 24b having the recesses exemplified in Variation 1 above is applied to this configuration. Furthermore, Figures 10C and 10D show an example in which the insulating layer 31 is not provided, as in Variation 2 above. Although not shown here, a configuration in which the insulating layer 31 and insulating layer 33 are not provided may also be used, as in Variation 3 above.

[Modification 5]
The configuration shown in FIG. 11A differs from the above-described configuration example mainly in that a region 21b is disposed between a pair of regions 21a in a cross-sectional view of the semiconductor layer 21 in the Y direction.

A pair of regions 21a separated by region 21b is formed between two transistors 20 provided in opening 47. Furthermore, insulating layer 32 is provided in contact with the upper surface of region 21b. In this case, it is preferable that the boundary between region 21a and region 21b is roughly flush with the side surfaces of insulating layer 22, conductive layer 23, and insulating layer 31. In other words, it is preferable that region 21b is provided so as to overlap the region between the pair of insulating layers 22, the region between the pair of conductive layers 23, and the region between the pair of insulating layers 31.

Furthermore, Figure 11B shows an example in which the conductive film 24b having the recesses exemplified in Variation 1 above is applied to this configuration. Furthermore, Figures 11C and 11D show an example in which the insulating layer 31 is not provided, as in Variation 2 above. Although not shown here, a configuration in which the insulating layer 31 and insulating layer 33 are not provided may also be used, as in Variation 3 above.

The above is an explanation of the modified version.

[Example of manufacturing method]
An example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described below, taking the semiconductor device 10 including the memory cell 15 exemplified in the above structure example as an example.

The thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is preferable for depositing films using insulating targets. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also be used to form insulating films through reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma; thermal CVD (TCVD), which uses heat; and photo-CVD (photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and MOCVD, depending on the source gas used.

Plasma CVD can produce high-quality films at relatively low temperatures. Furthermore, because thermal CVD does not use plasma, it is possible to minimize plasma damage to the workpiece. Furthermore, because thermal CVD does not cause plasma damage during film formation, it can produce films with fewer defects.

ALD methods that can be used include thermal ALD, in which the reaction between the precursor and reactant is carried out using only thermal energy, and PEALD, which uses plasma-excited reactants.

Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. ALD, in particular, has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

The CVD method allows for the deposition of films of any composition by adjusting the flow rate ratio of the raw material gases. For example, the CVD method allows for the deposition of films with continuously changing compositions by changing the flow rate ratio of the raw material gases while the film is being deposited. When depositing films while changing the flow rate ratio of the raw material gases, the time required for film deposition can be shortened compared to when multiple deposition chambers are used, as no time is required for transport or pressure adjustment. This can potentially increase the productivity of semiconductor devices.

With the ALD method, films of any desired composition can be deposited by simultaneously introducing multiple different types of precursors. Alternatively, when multiple different types of precursors are introduced, films of any desired composition can be deposited by controlling the number of cycles of each precursor. Also, as with the CVD method, films with continuously changing compositions can be deposited.

Furthermore, the thin films that make up the semiconductor device can be processed using methods such as photolithography. Alternatively, the thin films may be processed using methods such as nanoimprinting, sandblasting, and lift-off. Furthermore, island-shaped thin films may be directly formed using a film-forming method that uses a shielding mask such as a metal mask.

There are two typical photolithography methods. One is to form a resist mask on the thin film to be processed, process the thin film by etching or other methods, and then remove the resist mask. The other is to form a photosensitive thin film, then expose and develop it to process it into the desired shape.

In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed using immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as light for exposure. Electron beams can also be used instead of light for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

Methods such as dry etching, wet etching, and sandblasting can be used to etch thin films.

FIGS. 12A to 21 are schematic cross-sectional views corresponding to each step in the exemplary fabrication method described below. FIGS. 12A to 12C, 13A, 14A, 15A, 16A, and 17A to 21 correspond to cross sections taken along the line O-P-Q in FIG. 1A. Also, FIGS. 13B, 14B, 15B, and 16B correspond to cross sections taken along the line R-S in FIG. 1A.

First, a substrate (not shown) is prepared, an insulating layer 11 is formed on the substrate, and an insulating layer 41 is formed on the insulating layer 11.

The substrate used can be one that is heat-resistant enough to withstand at least the subsequent heat treatment.

Insulating layer 11 can be an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film. Insulating layer 41 can be an inorganic insulating film such as a silicon nitride film or a silicon nitride oxide film. The insulating layers 11 and 41 can be formed by sputtering, CVD, MBE, PLD, ALD, or other methods. If the surface on which insulating layer 11 is to be formed is not flat, a planarization process may be performed after insulating layer 11 is formed to flatten the top surface of insulating layer 11.

Next, a conductive film that will become conductive film 24a and a conductive film that will become conductive film 24b are formed in this order on insulating layer 41. Each conductive film can be formed using a film formation method such as sputtering, ALD, or CVD. Next, a resist mask is formed on the conductive film that will become conductive film 24b, and unnecessary portions of each conductive film are removed by etching, thereby forming conductive layer 24 including conductive film 24a and conductive film 24b. Here, conductive layer 24 is formed to extend in the X direction.

Next, an insulating film that will become insulating layer 42 is formed to cover conductive layer 24, and then planarization is performed until the top surface of conductive film 24b is exposed, thereby forming insulating layer 42 (Figure 12A). The insulating film that will become insulating layer 42 can be formed using a film formation method such as sputtering, ALD, or CVD.

Note that although an example has been shown in which insulating layer 42 is formed after conductive layer 24 has been formed, conductive layer 24 may also be formed after insulating layer 42 has been formed. In this case, after depositing an insulating film that will become insulating layer 42, an opening (or recess) for burying conductive layer 24 is formed to form insulating layer 42. Thereafter, two conductive films that will become conductive film 24a and conductive film 24b are deposited in order, and then a planarization process is performed until the top surface of insulating layer 42 is exposed, thereby forming conductive layer 24.

Next, an insulating layer 43 is formed on the conductive layer 24 and the insulating layer 42 (Figure 12B). First, an insulating film that will become the insulating layer 43 is deposited. Next, the insulating film is etched using photolithography to form an opening 47 extending in the Y direction. The opening 47 is formed so as to reach the conductive film 25b and the insulating layer 42. In this way, the insulating layer 43 having the opening 47 can be formed. After the insulating layer 43 is formed, the upper surfaces of the conductive film 24b and the insulating layer 42 are exposed in the opening 47. Here, it is preferable that the edge of the bottom surface of the opening 47 has a curved shape with an arbitrary curvature, as shown in Figure 7A, etc.

It should be noted that when processing insulating layer 43, there is a risk that insulating layer 42 may be etched and become thinner. In such cases, an insulating layer that functions as an etching stop film can be provided below the insulating film that will become insulating layer 43. After forming insulating layer 43 by etching, the etching stop film can be subsequently etched to expose the top surface of insulating layer 42, etc.

Here, since the thickness of the insulating layer 43 affects the channel length of the transistor, it is important to ensure that the thickness of the insulating layer 43 does not vary.

When processing the insulating layer 43, it is preferable to use anisotropic dry etching so that the side surfaces are roughly vertical. However, depending on the processing conditions, the side surfaces of the insulating layer 43 may be inclined relative to the direction perpendicular to the surface on which they are formed, resulting in a tapered shape.

Furthermore, when processing the insulating layer 43, a portion of the upper part of the conductive film 24b can be etched to reduce the thickness of the area that does not overlap with the insulating layer 43. This allows the conductive film 24b with a recess, as shown in Figure 8B, etc., to be formed. At this time, it is preferable to determine the etching conditions so that the conductive film 24b does not disappear, or to form the conductive film 24b thick in advance. Here, it is preferable that the end of the recess in the conductive film 24b has a curved shape with an arbitrary curvature, as shown in Figure 8B.

The insulating film that becomes insulating layer 43 is preferably an oxide film that contains enough oxygen to release oxygen when heated and has a low hydrogen content. The insulating film that becomes insulating layer 43 can be formed by a film formation method such as PECVD, sputtering, or ALD, but sputtering is particularly preferred. In particular, by forming the film using a gas that does not contain hydrogen and instead contains oxygen, an insulating film with an extremely low hydrogen content and excess oxygen can be formed. By forming the insulating film that becomes insulating layer 43 in this way, oxygen can be supplied from insulating layer 43 to the channel formation region of semiconductor layer 21, reducing oxygen vacancies.

Subsequently, heat treatment may be performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be approximately 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to replenish desorbed oxygen. By performing the above-described heat treatment, impurities such as water and hydrogen contained in the insulating layer 43 or the like can be reduced before the formation of an oxide semiconductor film that serves as a semiconductor layer.

Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the amount of moisture contained in the gas used in the heat treatment should be 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using highly purified gas to perform the heat treatment, it is possible to prevent moisture and other substances from being absorbed into the insulating layer 43, etc., as much as possible.

After forming the insulating film that will become insulating layer 43, or after processing it into insulating layer 43, a process for supplying oxygen may be carried out. This allows oxygen to be supplied from insulating layer 43 to semiconductor film 21f later, due to heat or other factors applied after the formation of semiconductor film 21f.

Examples of treatments for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Here, microwave plasma treatment may refer to treatment using, for example, an apparatus having a power source that generates high-density plasma using microwaves. Alternatively, oxygen may be supplied to the insulating layer by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The deposited oxide film may be removed immediately or may be left as is. Note that the oxygen-containing atmosphere includes not only oxygen gas (O ₂ ) but also atmospheres containing gases of oxygen-containing compounds such as ozone (O ₃ ) and dinitrogen monoxide (N ₂ O).

Next, a semiconductor film 21f, which will later become the semiconductor layer 21, is deposited to cover the insulating layer 43, the conductive film 24b, and the insulating layer 42 (Figure 12C).

A metal oxide (oxide semiconductor) film with semiconductor properties can be used as the semiconductor film 21f. The metal oxide film can be formed using a suitable method, such as sputtering, CVD, MBE, PLD, or ALD. It is preferable that the metal oxide film be formed in contact with the substantially vertical side surfaces of the insulating layer 43. Therefore, it is preferable to use a film formation method with good coverage for forming the metal oxide film, and it is more preferable to use the ALD method.

The metal oxide film preferably has crystallinity. In one embodiment of the present invention, the metal oxide film preferably has a metal oxide having a CAAC structure.

It is preferable to perform a treatment to increase the crystallinity of the metal oxide film during or after the formation of the metal oxide film. Examples of treatments to increase the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that several of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

Furthermore, it is more preferable to perform the treatment to increase the crystallinity of the metal oxide film multiple times during the formation of the metal oxide film. For example, when forming a metal oxide film using the ALD method, it is preferable to perform microwave plasma treatment after each atomic layer is formed. Alternatively, it is preferable to perform the treatment to increase the crystallinity after each metal oxide film of a predetermined thickness is formed, as this increases productivity. Specifically, it is preferable to form a first metal oxide film of 1 nm to 10 nm in thickness, perform the first microwave plasma treatment, and then form a second metal oxide film of 1 nm to 10 nm in thickness, and perform the second microwave plasma treatment.

There are no particular limitations on the deposition method for the first metal oxide film and the second metal oxide film; ALD or sputtering may be used, respectively. Depositing the first metal oxide film by ALD is particularly preferable because it prevents elements from the layers constituting the surface to be formed from being mixed into the first metal oxide film and the second metal oxide film (also known as mixing). This is particularly suitable when the elements contained in the layers constituting the surface to be formed inhibit the crystallization of the metal oxide (e.g., when silicon, carbon, etc. are included). The first metal oxide film and the second metal oxide film may have different compositions. While a stacked structure of a first metal oxide film and a second metal oxide film is illustrated here, this is not a limitation. Similar processing can be applied to metal oxide films with a single layer or a stacked structure of three or more layers.

Furthermore, treatment to increase the crystallinity of the metal oxide film may be performed after the metal oxide film is formed. Specifically, this treatment may be performed directly on the formed metal oxide film, or may be performed via another film, such as an insulating film, formed on the metal oxide film. For example, microwave plasma treatment may be performed after the metal oxide film is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.) may be formed after the metal oxide film is formed, and then heat treatment or microwave plasma treatment may be performed on the metal oxide film via the insulating film.

The above-mentioned treatment to increase the crystallinity of the metal oxide film can also serve as a treatment to remove impurities contained in the metal oxide film. For example, carbon, hydrogen, nitrogen, and the like contained in the metal oxide film can be preferably removed. Alternatively, by performing the treatment to increase the crystallinity of the metal oxide film in an oxygen gas atmosphere, oxygen vacancies in the metal oxide film can be reduced.

When performing a process to increase the crystallinity of a metal oxide film, it is preferable to set the temperature of the heat treatment (substrate temperature) to room temperature (e.g., 25°C) or higher, 100°C or higher and 700°C or lower, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower.

By improving the crystallinity of the metal oxide film, it is possible to create highly reliable transistors.

Metal oxide films can be formed, for example, by sputtering using a metal oxide target.

It is preferable that the metal oxide film be a dense film with as few defects as possible. It is also preferable that the metal oxide film be a highly pure film with as little impurities as possible, such as hydrogen and water. It is particularly preferable to use a crystalline metal oxide film as the metal oxide film.

Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total film-forming gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the more highly crystallinity the metal oxide film can be, resulting in a highly reliable transistor. On the other hand, the lower the oxygen flow ratio, the less highly crystallinity the metal oxide film can be, resulting in a transistor with a higher on-state current.

When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the resulting metal oxide film. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the resulting metal oxide film.

The conditions for forming the metal oxide film are that the substrate temperature be between room temperature and 250°C, preferably between room temperature and 200°C, and more preferably between room temperature and 140°C. For example, a substrate temperature between room temperature and less than 140°C is preferred, as this increases productivity. Furthermore, by forming the metal oxide film at room temperature or without intentionally heating the substrate, the crystallinity can be reduced.

When using the ALD method, it is preferable to use a film formation method such as thermal ALD (Atomic Layer Deposition) or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferred because it exhibits extremely high step coverage. The PEALD method is also preferred because it not only exhibits high step coverage but also allows for low-temperature film formation.

For example, if a metal oxide is used for the semiconductor layer 21, it can be deposited by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.

For example, when depositing an In-Ga-Zn oxide film, three precursors can be used: a precursor containing indium, a precursor containing gallium, and a precursor containing zinc. Alternatively, two precursors can be used: a precursor containing indium and a precursor containing gallium and zinc.

Indium-containing precursors that can be used include trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

Furthermore, precursors containing gallium that can be used include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

Furthermore, zinc-containing precursors that can be used include dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc.

Examples of oxidizing agents that can be used include ozone, oxygen, and water.

Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the raw material gases, the time for which the raw material gases are flowed, and the order in which the raw material gases are flowed. Adjusting these also makes it possible to deposit a film whose composition changes continuously. It is also possible to deposit two or more films with different compositions in succession.

After the metal oxide film is formed, it is preferable to perform heat treatment. The heat treatment may be performed within a temperature range in which the metal oxide film does not polycrystallize, such as 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration should be approximately 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after heat treatment in a nitrogen gas or inert gas atmosphere, heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the amount of moisture contained in the gas used in the heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and other substances from being incorporated into the metal oxide film, etc., as much as possible.

In the drawings, semiconductor film 21f is shown as a single layer, but it may also have a laminated structure. For example, it may have a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer is formed by sputtering, or a three-layer structure in which the first layer is formed by the ALD method, the second layer is formed by sputtering, and the third layer is formed by either the ALD method or the sputtering method. Forming the first layer by the ALD method is preferable because it can suppress mixing, but it can also be formed by sputtering. Semiconductor film 21f may also have a laminated structure of four or more layers.

Next, a sacrificial layer 61 and a resist mask 65 are formed (Figures 13A and 13B). The resist mask 65 and the sacrificial layer 61 function as masks for forming the above-mentioned region 21b in the semiconductor film 21f. Therefore, the opening in the resist mask 65 is formed so as to overlap with region 21b of the semiconductor layer 21, which will be formed in a later step. Therefore, as shown in Figures 13A and 13B, the top of the conductive layer 24, in other words, the portion where region 21a will be formed in a later step, is covered by the resist mask 65.

The sacrificial layer 61 can be made of an organic or inorganic material formed by a coating method. More specific examples include coated insulating films such as SOC (Spin On Carbon) and SOG (Spin On Glass). The sacrificial layer 61 can also be formed by film formation methods such as sputtering and CVD. It is preferable that the material used for the sacrificial layer 61 satisfy certain conditions, such as being able to be formed thick, being able to be formed or processed vertically, and being easy to remove (leaving no residue and causing minimal damage to the surface on which it is formed). The sacrificial layer 61 need not be provided if it is not required.

Next, the portions of the sacrificial layer 61 that are not covered by the resist mask 65 are removed by etching to form openings (Figures 14A and 14B). In other words, the openings in the sacrificial layer 61 are formed so as to overlap region 21b of the semiconductor layer 21, which will be formed in a later step.

Next, it is preferable to remove the resist mask 65. The resist mask 65 can be removed by wet etching or dry etching. After dry etching, dry cleaning using plasma or wet cleaning using a chemical solution (including acid or alkali) or water (including carbonated water) may also be performed.

Next, a sacrificial layer 67 is formed to cover the semiconductor film 21f and the sacrificial layer 61 (Figures 15A and 15B). The sacrificial layer 67 functions as a layer for adding a metal element to the semiconductor film 21f in a later process. As described above, the metal element is preferably either aluminum or hafnium, or both. Therefore, the sacrificial layer 67 is preferably an oxide film containing either aluminum or hafnium, or both. For example, aluminum oxide, hafnium oxide, or hafnium aluminate can be used as the sacrificial layer 67. Here, to prevent excessive oxygen from being added to the semiconductor film 21f in a later process, the amount of oxygen contained in the sacrificial layer 67 is preferably less than the amount that satisfies the stoichiometric composition.

As shown in Figures 15A and 15B, the sacrificial layer 67 is formed so as to contact the semiconductor film 21f located at the bottom of the opening in the sacrificial layer 61. For this reason, it is preferable to use a film formation method with good coverage for forming the sacrificial layer 67. It is also preferable that the sacrificial layer 67 has a thin film thickness. For example, it is preferable to make the film thickness thinner than the semiconductor film 21f, and specifically, the film thickness can be set to 0.5 nm or more and 1.0 nm or less. Therefore, it is preferable to form the sacrificial layer 67 using the ALD method, which has good coverage and can form an ultra-thin film with a precise thickness.

Subsequently, plasma treatment is performed to add the metal elements contained in the sacrificial layer 67 to the semiconductor film 21f, forming regions 21fa and 21fb (Figures 16A and 16B). By performing plasma treatment on the thin sacrificial layer 67, the metal elements contained in the sacrificial layer 67 are impacted, allowing the metal elements to be added to the semiconductor film 21f in the region where the sacrificial layer 67 and the semiconductor film 21f contact each other. The region of the semiconductor film 21f in contact with the sacrificial layer 67 is doped with the metal elements and becomes region 21fb, while the region of the semiconductor film 21f covered by the sacrificial layer 61 is not doped with the metal elements and becomes region 21fa. Therefore, region 21fb contains either aluminum or hafnium, or both. Furthermore, region 21fb has a higher concentration of either aluminum or hafnium than region 21fa. Here, one or more of aluminum oxide, hafnium oxide, and hafnium aluminate are formed in region 21fb.

Furthermore, by adding metal elements as described above, oxygen vacancies are formed in region 21fb, resulting in a decrease in crystallinity. In this way, region 21fb has an amorphous structure. Therefore, region 21fb has more oxygen vacancies and lower crystallinity than region 21fa. Such region 21fb has a higher resistivity than region 21fa. Preferably, the resistivity of region 21fb is 10 times or more the resistivity of region 21fa. In this way, region 21fb, which functions as an element isolation region, can be formed.

As the plasma treatment, for example, reverse sputtering is preferably performed. Here, reverse sputtering refers to a method of modifying a surface by bombarding ions onto a surface to be treated, as opposed to the conventional sputtering method of bombarding a sputter target with ions. One method of bombarding ions onto the surface to be treated is to apply a high-frequency voltage to the surface to be treated in an argon atmosphere to generate plasma near the substrate. When reverse sputtering is used, argon is added to region 21fb in addition to the metal elements. In this case, the argon concentration in region 21b is higher than that in region 21a. In addition to argon gas, helium gas, nitrous oxide (N ₂ O) gas, nitrogen gas, or oxygen gas can also be used.

Furthermore, the above-mentioned plasma treatment is not limited to reverse sputtering treatment. For example, the above-mentioned microwave plasma treatment may be performed. Furthermore, for example, plasma treatment may be performed without applying a bias voltage to the treatment surface. For the above treatment, a sputtering device, a CVD device, a dry etching device, a CVD device using a high-density plasma source, or a dry etching device using a high-density plasma source may be used.

Furthermore, heat treatment may be performed instead of the plasma treatment, during the plasma treatment, before the plasma treatment, or after the plasma treatment. For the conditions of the heat treatment, please refer to the heat treatment for gettering described below.

Furthermore, the addition of metal elements to semiconductor film 21f is not limited to the above. For example, the metal elements may be added using ion implantation or ion doping without providing a sacrificial layer 67.

Next, a heat treatment is performed to capture or fix (this can also be called gettering) the hydrogen and excess oxygen contained in region 21fa in region 21fb. As mentioned above, region 21fb contains more oxygen vacancies than region 21fa. Therefore, by performing the heat treatment, the hydrogen and excess oxygen contained in the adjacent region 21fa can be captured or fixed.

This reduces the hydrogen concentration in region 21fa, which functions as a channel formation region in transistor 20, thereby suppressing a negative shift in the initial characteristics of transistor 20 and enabling normally-off characteristics. It also suppresses negative drift degradation during +GBT stress testing.

Furthermore, in the transistor 20, excess oxygen in the region 21fa, which functions as a channel formation region, can be reduced, and the formation of electron traps due to the excess oxygen can be suppressed. This can suppress an excessive positive shift in the initial characteristics of the transistor 20 due to the electron traps. Furthermore, excessive positive drift degradation in a +GBT stress test can be suppressed. As described above, by capturing or fixing the hydrogen and excess oxygen contained in the region 21fa in the region 21fb, the electrical characteristics and reliability of the transistor 20 can be improved.

The heat treatment is preferably performed at a substrate temperature of 200°C or higher and 500°C or lower, preferably 400°C or higher and 450°C or lower. The heat treatment is preferably performed for a treatment time of 1 hour or higher and 8 hours or lower. The heat treatment is preferably performed in an atmosphere that does not contain oxygen gas or has a low oxygen gas content. For example, the heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. The gas used in the heat treatment is preferably highly purified. For example, the moisture content of the gas used in the heat treatment should be 1 ppb or lower, preferably 0.1 ppb or lower, and more preferably 0.05 ppb or lower.

Next, the sacrificial layers 67 and 61 are removed (Figure 17A). The sacrificial layers 67 and 61 can be removed by wet etching or dry etching. After dry etching, dry cleaning using plasma or wet cleaning using a chemical solution (including acid or alkali) or water (including carbonated water) may be performed. The sacrificial layer 67 may remain near region 21fb. The plasma treatment and heat treatment may make the interface between the sacrificial layer 67 and the semiconductor film 21f unclear, in which case the sacrificial layer 67 may remain near region 21fb.

Next, a new sacrificial layer 62 is formed (Figure 17B). The sacrificial layer 62 can be formed using the same method as the sacrificial layer 61 described above.

Next, a planarization process is performed until the top surface of insulating layer 43 is exposed (Figure 17C). As a result, the portion of semiconductor film 21f located on top of insulating layer 43 is removed, leaving the portion located inside opening 47. In this way, semiconductor layer 21 can be formed that is arranged along the inside of opening 47. Furthermore, the remaining portion of region 21fa becomes region 21a, and the remaining portion of region 21fb becomes region 21b. As shown in Figure 17C, regions 21a and 21b are arranged alternately within opening 47.

The planarization process can be performed using, for example, CMP (Chemical Mechanical Polishing) or dry etching. After the semiconductor layer 21 is formed, the sacrificial layer 62 is removed. The sacrificial layer 62 can be removed in the same manner as the sacrificial layer 61 described above.

Next, an insulating film 22f, which will later become insulating layer 22, is formed to cover semiconductor layer 21, insulating layer 43, insulating layer 42, conductive layer 24, etc.

The insulating film 22f can be formed by a film formation method such as sputtering, ALD, or CVD. It is preferable to provide the insulating film 22f with as uniform a thickness as possible on the surface of the vertical portion of the semiconductor layer 21. For this reason, it is particularly preferable to form the insulating film 22f by the ALD method, which is a film formation method with extremely excellent coverage. Note that if the sidewalls of the insulating layer 43 are tapered, the insulating film 22f can be formed using a film formation method such as sputtering or CVD.

Next, a conductive film 23f, which will later become the conductive layer 23, is formed to cover the insulating film 22f. The conductive film 23f can be formed using a method such as CVD, ALD, or sputtering. From the standpoint of coverage, it is particularly preferable to form it by the CVD method.

Next, an insulating film 31f, which will later become the insulating layer 31, is deposited to cover the conductive film 23f (Figure 18A). The insulating film 31f can be formed using a deposition method such as sputtering, ALD, or CVD.

Next, the insulating film 31f is anisotropically etched to form a pair of insulating layers 31 that are arranged along the vertical portions of the conductive film 23f and are symmetrically disposed with respect to the Y-Z plane within the opening 47. Next, the conductive film 23f is anisotropically etched using the insulating layer 31 as a mask to form a pair of conductive layers 23 that are symmetrically disposed with respect to the Y-Z plane within the opening 47. Next, the insulating film 22f is anisotropically etched to form a pair of insulating layers 22 that are symmetrically disposed with respect to the Y-Z plane within the opening 47, sandwiching the insulating layer 43 therebetween (Figure 18B). In this way, a pair of insulating layers 31, a pair of conductive layers 23, and a pair of insulating layers 22 that are arranged along the interior of the opening 47 can be formed.

Note that the insulating film 31f, conductive film 23f, and insulating film 22f may be etched in order using different etching methods, or two or more films may be etched simultaneously in a single etching process. For example, in the etching process for conductive film 23f, insulating film 22f may be etched subsequently under the same conditions after conductive film 23f.

As shown in Figure 11A, etc., region 21b can be formed in the region overlapping the region between a pair of conductive layers 23. In this case, after the step shown in Figure 18B, a method similar to the method shown in Figures 13 to 16 can be used.

Next, an insulating film that will become insulating layer 32 is deposited. Next, an insulating film that will become insulating layer 33 is formed so as to fill the recesses in the insulating film. These insulating films can be formed independently using film deposition methods such as sputtering, ALD, and CVD. For example, the insulating film that will become insulating layer 32 can be formed using ALD, and the insulating film that will become insulating layer 33 can be formed using CVD. Next, the insulating film that will become insulating layer 33 and the insulating film that will become insulating layer 32 are anisotropically etched in order to expose the top surfaces of semiconductor layer 21, insulating layer 22, conductive layer 23, and insulating layer 31.

Next, an insulating film that will become insulating layer 34 is deposited, and a planarization process is performed until the top surface of insulating layer 43 is exposed, thereby forming insulating layer 34 that contacts the top surfaces of conductive layer 23, insulating layer 31, insulating layer 32, and insulating layer 33 (Figure 18C). The insulating film that will become insulating layer 34 can be formed by a deposition method such as sputtering, ALD, or CVD.

Next, the semiconductor layer 21 is etched so that the top surface of the semiconductor layer 21 is lower than the top surface of the conductive layer 23 (Figure 19A). At this time, a recess is formed that is surrounded by the side surfaces of the insulating layer 43, the side surfaces of the insulating layer 22, and the top surface of the semiconductor layer 21. Next, a conductive film is deposited to fill the recess, and unnecessary portions of the conductive film are etched and removed using photolithography to form the conductive layer 25 (Figure 19B).

As shown in Figure 7B, a laminated structure of conductive film 25a and conductive film 25b can also be used. In this case, a laminated conductive film similar to the above-mentioned conductive film 24b and conductive film 24a is formed, and the laminated conductive film is processed to form conductive layer 25.

At this point, transistor 20 can be formed.

Then, an insulating film that will become insulating layer 44 is deposited and planarized until the top surface of conductive layer 25 is exposed, thereby forming insulating layer 44 (Figure 19C). The insulating film that will become insulating layer 44 can be formed by a film deposition method such as sputtering, ALD, or CVD. Note that in areas where conductive layer 25 is not provided, as shown in Figure 3B, part of insulating layer 44 is embedded in a recess surrounded by the side surfaces of insulating layer 43, insulating layer 22, and the top surface of semiconductor layer 21 (e.g., region 21b).

Next, insulating layer 45 is formed, and insulating layer 46 is formed on insulating layer 45. Insulating layers 45 and 46 can be formed independently by a film formation method such as sputtering, ALD, or CVD.

Next, openings are formed in insulating layer 46 and insulating layer 45, reaching conductive layer 25 (Figure 20A). Here, it is preferable that the bottom edge of the opening has a curved shape with an arbitrary curvature, as shown in Figure 7A, etc. Note that part of the top surface of conductive layer 25 may be etched. To prevent this, insulating layer 45 can be used as an etching stop film when etching insulating layer 46.

Furthermore, when the conductive layer 25 has a layered structure of conductive films 25a and 25b, it is possible to thin the thickness of the central portion of the conductive film 25b by etching a portion of the upper portion of the conductive film 25b. This makes it possible to form the conductive film 25b with a recess, as shown in Figure 7B, etc. In this case, it is preferable to determine the etching conditions so that the conductive film 25b does not disappear, or to form the conductive film 25b thick in advance. Here, it is preferable that the end of the recess in the conductive film 25b has a curved shape with an arbitrary curvature, as shown in Figure 7B.

Next, a conductive film that will become conductive layer 51 is formed to cover the top surface of insulating layer 46, the side surfaces of insulating layer 46 within the opening, the side surfaces of insulating layer 45, and the top surface of conductive layer 25. This conductive film can be formed using a method such as CVD, ALD, or sputtering. From the standpoint of coverage, it is particularly preferable to form it by CVD.

Next, a sacrificial layer is formed on the conductive film so as to cover the recessed portion of the opening, and a planarization process is performed until the top surface of the insulating layer 46 is exposed. The sacrificial layer is then removed, thereby forming a conductive layer 51 that is located only inside the opening (Figure 20B).

The conductive film can also be etched to form the conductive layer 51. In this case, as shown in FIG. 7A, the upper end of the conductive layer 51 can be configured to be lower than the upper surface of the insulating layer 46. The upper end of the conductive layer 51 can also be tapered. Here, it is preferable that the upper end of the conductive layer 51 and the upper end of the insulating layer 46 have a curved shape with an arbitrary curvature, as shown in FIG. 7A.

Next, an insulating layer 52 is formed along the surfaces of the insulating layer 46 and the conductive layer 51. The insulating layer 52 can be formed using a film formation method such as sputtering, ALD, or CVD, but ALD is preferable from the perspective of coverage. Next, a conductive layer 53 is formed on the insulating layer 52 so as to fill the recesses in the openings of the insulating layer 46 (Figure 21). Thereafter, the top surface of the conductive layer 53 may be planarized if necessary.

Through the above steps, a semiconductor device having a transistor 20 and a capacitor 30 can be manufactured.

The above is an explanation of an example production method.

This embodiment can be implemented by appropriately combining at least a portion of it with other embodiments described in this specification.

(Embodiment 2)
In this embodiment, a semiconductor device 900 according to one embodiment of the present invention, which is different from the above embodiment, will be described. The semiconductor device 900 can function as a memory device.

FIG. 22 is a block diagram showing an example configuration of a semiconductor device 900. The semiconductor device 900 shown in FIG. 22 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. FIG. 22 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

Memory cell 15, as exemplified in the above embodiment, can be applied to memory cell 950.

The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

In semiconductor device 900, each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside. Signal CLK is a clock signal.

Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by control circuit 912.

The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

Voltage generation circuit 928 has the function of generating a negative voltage. Signal WAKE has the function of controlling the input of signal CLK to voltage generation circuit 928. For example, when a high-level signal is given as signal WAKE, signal CLK is input to voltage generation circuit 928, and voltage generation circuit 928 generates a negative voltage.

The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

The row decoder 941 and column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying the row to be accessed, and the column decoder 942 is a circuit for specifying the column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cell 950, reading data from the memory cell 950, and retaining the read data.

The input circuit 925 has the function of holding the signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is the data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has the function of holding Dout. The output circuit 926 also has the function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is the signal RDA.

PSW931 has the function of controlling the supply of VDD to the peripheral circuit 915. PSW932 has the function of controlling the supply of VHM to the row driver 923. Here, the high power supply voltage of the semiconductor device 900 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on/off of PSW931 is controlled by signal PON1, and the on/off of PSW932 is controlled by signal PON2. In Figure 22, the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but there can be multiple. In this case, a power switch can be provided for each power domain.

Other memory cell configuration examples that can be applied to memory cell 950 will be described using Figures 23A to 23H.

[DOSRAM]
23A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 951 includes a transistor M1 and a capacitor CA.

Transistor M1 may have a front gate (sometimes simply referred to as the gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and back gate may be connected.

The first terminal of transistor M1 is connected to the first terminal of capacitance element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitance element CA is connected to wiring CAL.

The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitance element CA into a conductive state (a state in which current can flow).

Furthermore, the memory cell that can be used for memory cell 950 is not limited to memory cell 951, and the circuit configuration can be changed. For example, the configuration of memory cell 952 shown in FIG. 23B may also be used. Memory cell 952 is an example in which the capacitor element CA and the wiring CAL are not included. The first terminal of transistor M1 is in an electrically floating state.

In memory cell 952, the potential written via transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and gate, indicated by the dashed line. This configuration significantly simplifies the memory cell configuration.

Note that it is preferable to use an OS transistor as transistor M1. OS transistors have the characteristic of having an extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made extremely low. That is, written data can be held by transistor M1 for a long time, reducing the frequency of refreshing the memory cell. Alternatively, refreshing the memory cell can be made unnecessary. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in memory cell 951 and memory cell 952.

[NOSRAM]
23C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a memory device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

Data is written by applying a high-level potential to the wiring WOL, turning on transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitance element CB. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and this potential is written to the first terminal of the capacitance element CB and the gate of transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off transistor M2, thereby maintaining the potential of the first terminal of the capacitance element CB and the potential of the gate of transistor M3.

Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate of transistor M3 and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held in the first terminal of capacitor CB (or the gate of transistor M3) can be read. In other words, the information written in this memory cell can be read from the potential held in the first terminal of capacitor CB (or the gate of transistor M3).

Furthermore, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in Figure 23D. Memory cell 954 is configured such that the wiring WBL and the wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. In other words, memory cell 954 is configured to operate with the write bit line and the read bit line as a single wiring BIL.

Memory cell 955 shown in Figure 23E is an example in which the capacitance element CB and wiring CAL in memory cell 953 have been omitted. Furthermore, memory cell 956 shown in Figure 23F is an example in which the capacitance element CB and wiring CAL in memory cell 954 have been omitted. This type of configuration allows for increased integration of the memory cells.

Note that it is preferable to use an OS transistor for at least transistor M2. In particular, it is preferable to use OS transistors for transistors M2 and M3.

Since OS transistors have an extremely low off-state current, written data can be retained by transistor M2 for a long time, reducing the frequency of refreshing the memory cells. Alternatively, refresh operations of the memory cells can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be retained in memory cells 953, 954, 955, and 956.

Memory cell 953, memory cell 954, memory cell 955, and memory cell 956, in which an OS transistor is used as transistor M2, are one embodiment of NOSRAM.

It should be noted that a Si transistor may also be used as transistor M3. Si transistors can increase field-effect mobility and can also be used as p-channel transistors, allowing for greater freedom in circuit design.

Furthermore, when an OS transistor is used as transistor M3, the memory cell can be composed of only n-type transistors.

Figure 23G shows a three-transistor, one-capacitor gain cell type memory cell 957. Memory cell 957 has transistors M4 to M6 and a capacitative element CC.

The first terminal of transistor M4 is connected to the first terminal of capacitance element CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitance element CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitance element CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

Data is written by applying a high-level potential to the wiring WOL, turning on transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitance element CC. Specifically, when transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and this potential is written to the first terminal of the capacitance element CC and the gate of transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off transistor M4, thereby maintaining the potential of the first terminal of the capacitance element CC and the potential of the gate of transistor M5.

Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, the information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

It is preferable to use an OS transistor for at least transistor M4.

Note that Si transistors may be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of the silicon used in the semiconductor layer.

Furthermore, when OS transistors are used as transistors M5 and M6, the memory cell can be composed of only n-type transistors.

[OS-SRAM]
23H shows an example of a static random access memory (SRAM) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an oxide semiconductor SRAM (OS-SRAM). Note that a memory cell 958 shown in FIG. 23H is a memory cell of an SRAM capable of backing up data.

Memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

The first terminal of transistor M7 is connected to wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

The second terminal of transistor MS1 is connected to the wiring VDL. The second terminal of transistor MS2 is connected to the wiring VDL. The second terminal of transistor MS3 is connected to the wiring GNDL. The second terminal of transistor MS4 is connected to the wiring GNDL.

The second terminal of transistor M9 is connected to the first terminal of capacitor CD1, and the gate of transistor M9 is connected to wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitor CD2, and the gate of transistor M10 is connected to wiring BRL.

The second terminal of the capacitance element CD1 is connected to the wiring GNDL, and the second terminal of the capacitance element CD2 is connected to the wiring GNDL.

Wiring BIL and wiring BILB function as bit lines, wiring WOL functions as a word line, and wiring BRL is a wiring that controls the on/off states of transistors M9 and M10.

The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and this potential is written to the second terminal of the transistor M10.

Meanwhile, since memory cell 958 forms an inverter loop using transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of transistor M8. Because transistor M8 is on, the potential applied to wiring BIL, i.e., the inverted signal of the signal input to wiring BIL, is output to wiring BILB. Furthermore, because transistors M9 and M10 are on, the potentials of the second terminals of transistors M7 and M8 are held in the first terminals of capacitors CD2 and CD1, respectively. Thereafter, a low-level potential is applied to wiring WOL and a low-level potential is applied to wiring BRL, turning off transistors M7 to M10, thereby holding the potentials of the first terminals of capacitors CD1 and CD2.

When reading data, the wiring BIL and wiring BILB are precharged to a predetermined potential, and then a high-level potential is applied to the wiring WOL and a high-level potential is applied to the wiring BRL. As a result, the potential of the first terminal of the capacitance element CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitance element CD2 is also refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. The potentials of the wiring BIL and wiring BILB change from their precharged potentials to the potential of the first terminal of the capacitance element CD2 and the potential of the first terminal of the capacitance element CD1, respectively, so the potential held in the memory cell can be read from the potential of the wiring BIL or wiring BILB.

Note that it is preferable to use OS transistors as transistors M7 to M10. This allows written data to be held for a long time by transistors M7 to M10, thereby reducing the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be made unnecessary.

In addition, Si transistors may be used as transistors MS1 to MS4.

The drive circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in Figure 24A, the drive circuit 910 and memory array 920 may be provided overlapping each other. By providing the drive circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in Figure 24B, the memory array 920 may be provided in multiple layers on top of the drive circuit 910.

Next, we will explain an example of a processing device that can be equipped with a semiconductor device such as the above-mentioned memory device.

Figure 25 shows a block diagram of the arithmetic unit 960. The arithmetic unit 960 shown in Figure 25 can be applied to, for example, a CPU (Central Processing Unit). The arithmetic unit 960 can also be applied to processors such as a GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), or NPU (Neural Processing Unit), which have a larger number (tens to hundreds) of processor cores capable of parallel processing than a CPU.

The arithmetic device 960 shown in FIG. 25 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and cache interface 989 may also be provided on separate chips.

The cache 999 is connected to the main memory provided on a separate chip via a cache interface 989. The cache interface 989 has the function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has the function of outputting part of the data held in the cache 999 to the ALU 991 or register 996, etc. via the bus interface 998.

As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have the function of supplying data held in the memory array 920 to the cache 999. In this case, it is also preferable that a drive circuit 910 be included as part of the cache interface 989.

It is also possible to use only the memory array 920 as a cache without providing the cache 999.

The arithmetic device 960 shown in FIG. 25 is merely one example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 25 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The more cores there are, the higher the arithmetic performance can be. The more cores there are, the better, and it is preferable to have, for example, two, preferably four, more preferably eight, even more preferably 12, and even more preferably 16 or more cores. Furthermore, when extremely high arithmetic performance is required, such as for server applications, it is preferable to have a multi-core configuration with 16 or more, preferably 32 or more, and even more preferably 64 or more cores. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal arithmetic circuits, data buses, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, while the arithmetic unit 960 is executing a program, the interrupt controller 994 determines and processes interrupt requests from external input/output devices, peripheral circuits, etc. based on their priority, mask status, etc. The register controller 997 generates the address of the register 996 and performs read and write operations on the register 996 depending on the state of the arithmetic unit 960.

The timing controller 995 also generates signals that control the timing of the operations of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits mentioned above.

In the arithmetic unit 960 shown in FIG. 25, the register controller 997 selects the holding operation in the register 996 in accordance with instructions from the ALU 991. That is, it selects whether the memory cells in the register 996 will hold data using flip-flops or capacitive elements. If holding data using flip-flops is selected, power supply voltage is supplied to the memory cells in the register 996. If holding data in capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.

The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Figures 26A and 26B show perspective views of a semiconductor device 970A. The semiconductor device 970A has a layer 930 on which a memory array is provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping areas. To make the configuration of the semiconductor device 970A easier to understand, Figure 26B shows the arithmetic unit 960 and layer 930 separated.

By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened. This increases the communication speed between them. In addition, the short connection distance reduces power consumption.

As a method for stacking the layer 930 having the memory array and the arithmetic unit 960, a method of stacking the layer 930 having the memory array directly on the arithmetic unit 960 (also known as monolithic stacking) may be used, or a method may be used in which the arithmetic unit 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using through-vias or conductive film bonding technology (such as Cu-Cu bonding). The former method does not require consideration of misalignment during bonding, and therefore not only can the chip size be reduced, but manufacturing costs can also be reduced.

Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, memory array 920L1 can be used as an L1 cache (also called a level 1 cache), memory array 920L2 can be used as an L2 cache (also called a level 2 cache), and memory array 920L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, memory array 920L3 has the largest capacity and is accessed least frequently. Furthermore, memory array 920L1 has the smallest capacity and is accessed most frequently.

Note that when the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in layer 930 can be used as a lower-level cache or main memory. Main memory has a larger capacity than the cache and is accessed less frequently.

Furthermore, as shown in FIG. 26B, drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connection electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connection electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connection electrode 940L3.

Note that while three memory arrays functioning as caches are shown here, the number may be one, two, or even four or more.

When the memory array 920L1 is used as a cache, the drive circuit 910L1 may function as part of the cache interface 989, or the drive circuit 910L1 may be configured to be connected to the cache interface 989. Similarly, the drive circuit 910L2 and the drive circuit 910L3 may also function as part of the cache interface 989, or may be configured to be connected to it.

Whether the memory array 920 functions as a cache or as main memory is determined by the control circuit 912 of each drive circuit 910. Based on a signal supplied from the arithmetic device 960, the control circuit 912 can cause some of the multiple memory cells 950 in the semiconductor device 900 to function as RAM.

The semiconductor device 900 can cause some of the multiple memory cells 950 to function as cache, and the other part to function as main memory. In other words, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one aspect of the present invention can function as, for example, a universal memory.

Alternatively, a layer 930 having one memory array 920 may be provided over the computing device 960. Figure 27A shows a perspective view of the semiconductor device 970B.

In semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for different functions. Figure 27A shows an example in which area L1 is used as an L1 cache, area L2 as an L2 cache, and area L3 as an L3 cache.

Furthermore, in semiconductor device 970B, the capacity of each of areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of area L1. With this configuration, it is possible to improve the efficiency of calculation processing and increase processing speed.

Alternatively, multiple memory arrays may be stacked. Figure 27B shows a perspective view of semiconductor device 970C.

Semiconductor device 970C has a layer 930L1 having memory array 920L1 stacked on top of which is a layer 930L2 having memory array 920L2, and a layer 930L3 having memory array 920L3 stacked on top of that. Memory array 920L1, which is physically closest to the arithmetic device 960, can be used as a higher-level cache, and memory array 920L3, which is the farthest, can be used as a lower-level cache or main memory. With this configuration, the capacity of each memory array can be increased, thereby further improving processing power.

The configuration examples illustrated in this embodiment and the corresponding drawings, etc., can be combined, at least in part, with other configuration examples or drawings, etc., as appropriate.

(Embodiment 3)
In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). The electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[Electronic Components]
FIG. 28A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 28A has a semiconductor device 710 inside a mold 711. FIG. 28A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

Semiconductor device 710 also has a drive circuit layer 715 and a memory layer 716. The memory layer 716 is configured with multiple memory cell arrays stacked on top of each other. The stacked configuration of drive circuit layer 715 and memory layer 716 can be a monolithic stacked configuration. A monolithic stacked configuration allows connections between the layers without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring drive circuit layer 715 and memory layer 716 as a monolithic stacked configuration, it is possible to achieve a so-called on-chip memory configuration, in which memory is formed directly on a processor, for example. An on-chip memory configuration enables faster operation of the interface between the processor and memory.

Furthermore, by configuring the memory on-chip, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also known as memory bandwidth).

Furthermore, it is preferable that the multiple memory cell arrays included in the memory layer 716 are formed using OS transistors and that the multiple memory cell arrays are monolithically stacked. By configuring the multiple memory cell arrays as a monolithic stack, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to achieve a monolithic stack configuration than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stack configuration.

Semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

Next, Figure 28B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.

Electronic component 730 shows an example in which semiconductor device 710 is used as a high bandwidth memory (HBM). Semiconductor device 735 can also be used in integrated circuits such as a CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Processing Unit), or FPGA (Field Programmable Gate Array).

The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and package substrate 732 are electrically connected using these through electrodes. In addition, with silicon interposers, TSVs can also be used as through electrodes.

In an HBM, many wiring connections are required to achieve a wide memory bandwidth. For this reason, the interposer on which the HBM is mounted must be able to form fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

Furthermore, in SiPs and MCMs that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is less likely. Furthermore, because the surface of a silicon interposer is highly flat, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are less likely to occur. It is particularly preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSV, or the like, space is required to accommodate the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may become difficult to provide the large number of wirings required to achieve a wide memory bandwidth. Therefore, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure may also be used that combines a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

Furthermore, a heat sink (heat sink) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the semiconductor device 735.

Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. Figure 28B shows an example in which electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[Large computer]
29A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

Figure 29B shows a perspective view of an example of a computer 5620. Computer 5620 is mounted on a motherboard 5630. Motherboard 5630 has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into slot 5631. In addition, PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to motherboard 5630.

Figure 29C shows an example of a PC card 5621. PC card 5621 is a processing board equipped with, for example, a CPU, GPU, and storage device. PC card 5621 has board 5622 and, mounted on board 5622, connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629. Note that Figure 29C also shows components other than electronic components 5626, 5627, and 5628.

The connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. The connection terminal 5629 may conform to, for example, PCIe.

Connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to PC card 5621, inputting signals, etc. They can also be, for example, interfaces for outputting signals calculated by PC card 5621. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Also, when outputting video signals from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).

Electronic component 5626 has terminals (not shown) for inputting and outputting signals, and by inserting these terminals into sockets (not shown) provided on board 5622, electronic component 5626 and board 5622 can be electrically connected.

Electronic component 5627 and electronic component 5628 have multiple terminals, and can be mounted to wiring on board 5622 by, for example, reflow soldering the terminals. Examples of electronic component 5627 include FPGAs, GPUs, and CPUs. Electronic component 5627 can be, for example, electronic component 730. Electronic component 5628 can be, for example, a memory device. Electronic component 5628 can be, for example, electronic component 700.

The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, artificial intelligence learning and inference.

[Space equipment]
The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

A semiconductor device according to one embodiment of the present invention includes an OS transistor. The change in electrical characteristics of an OS transistor due to radiation exposure is small. That is, the OS transistor has high radiation resistance and can be suitably used in environments where radiation may be incident. For example, an OS transistor can be suitably used in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, but the outer space described in this specification may include one or more of the thermosphere, mesosphere, and stratosphere.

Figure 30A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Figure 30A also shows a planet 6804 in space.

Although not shown in Figure 30A, the secondary battery 6805 may be provided with a battery management system (also referred to as BMS) or a battery control circuit. Using an OS transistor in the battery management system or battery control circuit described above is preferable because it consumes low power and has high reliability even in space.

In addition, outer space is an environment with radiation levels more than 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

When sunlight is irradiated onto the solar panel 6802, the power required for the satellite 6800 to operate is generated. However, for example, in situations where sunlight is not irradiated onto the solar panel, or where the amount of sunlight irradiating the solar panel is low, the amount of power generated will be small. Therefore, there is a possibility that the power required for the satellite 6800 to operate will not be generated. In order to operate the satellite 6800 even in situations where the amount of power generated is low, it is recommended that a secondary battery 6805 be provided on the satellite 6800. Note that the solar panel is sometimes called a solar cell module.

Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received, for example, by a receiver located on the ground or by another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be determined. As described above, satellite 6800 can constitute a satellite positioning system.

The control device 6807 also has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The electrical characteristics of an OS transistor change less when exposed to radiation than those of a Si transistor. In other words, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

Furthermore, the artificial satellite 6800 can be configured to include a sensor. For example, by configuring it to include a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground. Or, by configuring it to include a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an Earth observation satellite.

Note that although an artificial satellite is used as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, a semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

As explained above, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance compared to Si transistors.

[Data Center]
The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage devices and servers for storing a huge amount of data, a stable power source for storing the data, or cooling equipment required for storing the data.

By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, the power required to store data can be reduced and the semiconductor device that stores data can be made smaller. This allows for the storage system to be made smaller, the power supply for storing data to be made smaller, and cooling equipment to be made smaller. This allows for space savings in the data center.

Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, and therefore heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

Figure 30B shows a storage system applicable to a data center. The storage system 6000 shown in Figure 30B has multiple servers 6001sb as hosts 6001 (illustrated as Host Computers). It also has multiple storage devices 6003md as storage 6003 (illustrated as Storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as Storage Controller).

The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 may be connected to each other via a network.

Storage 6003 uses flash memory to reduce data access speed, i.e., the time required to store and output data, but this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the slow access speed of storage 6003, storage systems typically provide cache memory within the storage to reduce the time required to store and output data.

The aforementioned cache memory is used within the storage control circuit 6002 and storage 6003. Data exchanged between the host 6001 and storage 6003 is stored in the cache memory within the storage control circuit 6002 and storage 6003, and then output to the host 6001 or storage 6003.

By using OS transistors as transistors for storing data in the cache memory and maintaining a potential corresponding to the data, the frequency of refreshes can be reduced, lowering power consumption. Furthermore, by stacking the memory cell array, miniaturization is possible.

Note that the application of a semiconductor device of one embodiment of the present invention to one or more selected from electronic components, electronic devices, mainframes, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of a semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases, typified by carbon dioxide (CO ₂ ). Furthermore, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming due to its low power consumption.

This embodiment can be implemented by appropriately combining at least a portion of it with other embodiments described in this specification.

10: Semiconductor device, 11: Insulating layer, 15: Memory cell, 20: Transistor, 21: Semiconductor layer, 21a: Region, 21b: Region, 21f: Semiconductor film, 21fa: Region, 21fb: Region, 22: Insulating layer, 22f: Insulating film, 23: Conductive layer, 23f: Conductive film, 24: Conductive layer, 24a: Conductive film, 24b: Conductive film, 25: Conductive layer, 25a: Conductive film, 25b: Conductive film, 30: Capacitor element, 30a: capacitor element, 31: insulating layer, 31f: insulating film, 32: insulating layer, 33: insulating layer, 34: insulating layer, 41: insulating layer, 42: insulating layer, 43: insulating layer, 44: insulating layer, 45: insulating layer, 46: insulating layer, 47: opening, 51: conductive layer, 52: insulating layer, 53: conductive layer, 61: sacrificial layer, 62: sacrificial layer, 65: resist mask, 67: sacrificial layer, 81: conductive layer, 82 : plug, 83: plug, 85: insulating layer, 86: insulating layer, 87: insulating layer, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low resistance region, 95b: low resistance region, 98: element isolation layer, 700: electronic component, 702: printed circuit board, 704: mounting substrate, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 900: semiconductor device, 910: drive circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver , 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 960: arithmetic unit, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: instruction decoder, 994: interrupt controller, 995: timing controller, 996: register, 997: Register controller, 998: Bus interface, 999: Cache, 5600: Mainframe, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Electronic component, 5627: Electronic component, 5628: Electronic component, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6000: Storage system, 6001: Host, 6001sb: Server, 6002: Storage control circuit, 6003: Storage, 6003md: Storage device, 6800: Satellite, 6801: Airframe, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device

Claims (11)

a first conductive layer, a pair of second conductive layers, a pair of third conductive layers, a pair of semiconductor layers, a first insulating layer having an opening, and a pair of second insulating layers;
each of the pair of semiconductor layers includes a first metal oxide;
each of the pair of semiconductor layers has a first region and a second region;
at least a portion of the first region functions as a channel formation region;
the second region has a higher resistivity than the first region;
the first conductive layer extends in a first direction;
the pair of third conductive layers, the pair of semiconductor layers, the pair of second insulating layers, and the opening extend in a second direction intersecting the first direction;
the pair of third conductive layers, the pair of semiconductor layers, and the pair of second insulating layers are respectively provided symmetrically within the opening;
the first regions and the second regions are alternately arranged in the second direction,
the first insulating layer is provided on the first conductive layer;
the opening reaches the top surface of the first conductive layer;
each of the pair of semiconductor layers has a vertical portion in contact with a sidewall of the opening and a horizontal portion in contact with an upper surface of the first conductive layer;
each of the pair of semiconductor layers contacting an upper surface of the first conductive layer in the first region;
each of the pair of second conductive layers has a portion located above the first insulating layer and in contact with the vertical portion;
the pair of second insulating layers respectively covering the vertical portion and the horizontal portion;
the pair of third conductive layers respectively cover the vertical portion and the horizontal portion via the second insulating layer;
Semiconductor device. In claim 1,
the second region includes either or both of aluminum and hafnium;
Semiconductor device. In claim 2,
the second region has a higher concentration of either or both of aluminum and hafnium than the first region;
Semiconductor device. In claim 1,
the first conductive layer includes a first conductive film and a second conductive film on the first conductive film;
the pair of semiconductor layers are each in contact with the second conductive film;
the second conductive film includes a second metal oxide;
the first conductive film contains a metal;
Semiconductor device. In claim 4,
the first metal oxide and the second metal oxide contain one or more of the same elements selected from In, Sn, Zn, Ga, and Ti;
Semiconductor device. In claim 4,
the second conductive film has a recess;
the pair of semiconductor layers have portions located within the recess and in contact with the side surface and the top surface of the second conductive film within the recess;
Semiconductor device. In claim 1,
a pair of third insulating layers;
the pair of third insulating layers respectively cover the vertical portion and the horizontal portion via the second insulating layer and the third conductive layer;
the third insulating layer has a function of capturing or fixing hydrogen;
Semiconductor device. In any one of claims 1 to 7,
a capacitance element on the second conductive layer;
the capacitive element includes a fourth conductive layer in contact with the second conductive layer, a fifth conductive layer, and a fourth insulating layer therebetween;
Semiconductor device. In claim 8,
the fourth conductive layer has a recess;
the fourth insulating layer has a portion provided along the recess,
the fifth conductive layer has a portion located within the recess with the fourth insulating layer interposed therebetween, and is in contact with a side surface and an upper surface of the fourth insulating layer within the recess;
Semiconductor device. In claim 8,
the fourth conductive layer has a columnar shape,
the fourth insulating layer covers the fourth conductive layer;
the fifth conductive layer is provided to cover an upper surface and side surfaces of the fourth conductive layer via the fourth insulating layer;
Semiconductor device. In any one of claims 1 to 7,
a transistor below the first conductive layer;
The transistor includes silicon as a semiconductor in which a channel is formed,
one of a source electrode and a drain electrode of the transistor is connected to the first conductive layer;
Semiconductor device.