WO2025082490A1 - Electro-optical modulation chip capable of monolithically integrating active optical device, and preparation method - Google Patents

Abstract

An electro-optical modulation chip (100) capable of monolithically integrating an active optical device, and a preparation method. The electro-optical modulation chip (100) comprises, from top to bottom, a compound semiconductor active layer (103), a germanium thin film layer (104) and an electro-optical material waveguide layer (105), wherein the electro-optical material waveguide layer (105) forms corresponding waveguide structures (12) by means of photoetching and etching; the germanium thin film layer (104) forms a germanium absorption layer (104-2) and a germanium substrate growth layer (104-1) by means of photoetching and etching; and the germanium thin film layer (104) is prepared by the ion scissors technology. On the one hand, high-speed and high-responsivity O/C waveband optical detection can be achieved, and on the other hand, a growth substrate matching the lattice of a compound semiconductor is provided for the compound semiconductor, achieving simultaneous integration of an optical gain semiconductor device.

Description

An electro-optic modulation chip capable of monolithically integrating active optical devices and a preparation method thereof Technical Field

The present invention belongs to the field of semiconductor optoelectronic chips, and in particular relates to an electro-optical modulation chip capable of monolithically integrating active optical devices and a preparation method thereof.

Background Art

Electro-optical material crystals represented by lithium niobate have large nonlinear optical coefficients, excellent photorefractive, piezoelectric and acoustic properties, and can be used as frequency doubling/difference crystal materials. They have excellent physical and mechanical properties, high damage threshold, wide transparent spectrum and very low light transmission loss. In addition, the cost of electro-optical materials is relatively low, so they are very suitable for the preparation of optical modulators. Compared with the traditional electro-optical modulation chips represented by silicon (Si) based on CMOS (complementary metal oxide semiconductor) technology, the nonlinear characteristics of electro-optical material crystals make them show attractive prospects in the research and related applications of optical frequency combs that have emerged in recent years. With the development of technology, this type of electro-optical crystal can also be integrated in the form of thin films on the surface of 6-inch or even larger wafers. Taking lithium niobate thin film on insulating layer (LNOI) as an example, its appearance solves the low integration density and easy polarization crosstalk problems of traditional electro-optical material waveguides, and further simplifies the conditions for the generation of nonlinear effects in electro-optical material waveguides. However, the existing lithium niobate thin film technology is difficult to introduce into the preparation of active devices other than modulation. Currently, erbium-doped lithium niobate thin films can solve the problem of integrated optical gain on lithium niobate thin film systems to a certain extent, but it limits its own modulation function and therefore still has great limitations. In general, there is an urgent need for an electro-optical material system on an insulating layer that can simultaneously integrate optical gain, optical modulation, and optical detection functions on a single chip.

Summary of the invention

The object of the present invention is to provide an electro-optic modulation chip capable of monolithically integrating active optical devices and a preparation method thereof in view of the deficiencies of the prior art.

According to the first part of the present invention, an electro-optic modulation chip capable of monolithically integrating active optical devices is provided, which comprises, from top to bottom, a compound semiconductor active layer, a germanium thin film layer and an electro-optic material waveguide layer; the electro-optic material waveguide layer is formed into a corresponding waveguide structure by photolithography and etching; the germanium thin film layer is formed into a corresponding waveguide structure by photolithography and etching forming a germanium absorption layer and a germanium substrate growth layer;

The electro-optic material waveguide layer serves as a coupling medium for optical signals, and together with the compound semiconductor active layer grown on the germanium substrate growth layer, forms a waveguide, which constitutes the optical gain part of the electro-optic modulation chip;

The electro-optic material waveguide layer serves as a coupling medium for optical signals and together with the germanium absorption layer forms a waveguide, which constitutes the optical detection part of the electro-optic modulation chip;

The electro-optic material waveguide layer serves as a propagation medium for optical signals and constitutes the optical modulation part of the electro-optic modulation chip.

According to the second part of the present invention, there is provided a method for preparing an electro-optic modulation chip capable of monolithically integrating active optical devices, comprising the following steps:

preparing an electro-optic material wafer having an electro-optic material waveguide layer, etching the electro-optic material waveguide layer to form a waveguide structure, depositing an insulating substrate layer and flattening the surface;

A germanium wafer is prepared, and after hydrogen ion implantation, a germanium thin film layer, a germanium defect-enriched layer, a germanium cracked layer and a residual germanium substrate are formed on the surface of the germanium wafer;

Bonding a germanium wafer to the surface of the upper insulating substrate layer, and retaining only the germanium thin film layer of the germanium wafer by annealing and grinding;

Etching the germanium thin film layer to form a germanium substrate growth layer of the optical gain part and a germanium absorption layer of the optical detection part; continuing to deposit an insulating substrate layer, and opening a growth window in the optical gain part to grow a compound semiconductor active layer on the germanium substrate growth layer;

The insulating substrate layer is continuously deposited, and a via electrode and a contact electrode are formed.

Furthermore, the impurity doping concentration of the germanium wafer should be in the range of 10 ¹⁶ cm ^-3 to 5×10 ¹⁶ cm ^-3 , the doping type should be n-type or p-type, and the surface roughness should be below 0.5 nm/100 μm ² .

Furthermore, the preparation process of the germanium wafer is specifically as follows:

Cleaning and drying the germanium wafer; depositing an oxide layer film on the germanium wafer to form a protective layer;

The germanium wafer is implanted with hydrogen ions at room temperature, with an implantation angle of 7°, an implantation dose of 4×10 ¹⁶ cm ^-3 to 1×10 ¹⁷ cm ^-3 , an implantation energy of 60keV to 250keV, and an implantation beam current of less than or equal to 1000μA/cm ² ;

After the implantation is completed, the germanium wafer is cleaned and dried again to obtain a finished germanium wafer.

Furthermore, the cleaning and drying are specifically as follows: using a buffered hydrofluoric acid solution or a diluted hydrofluoric acid solution to clean the oxide layer on the surface of the germanium wafer for 3 to 5 minutes; after the acid cleaning is completed, cleaning in deionized ultrapure water to remove the residual hydrofluoric acid solution on the surface; after the water washing is completed, nitrogen blowing or vacuum back adsorption and drying are used to remove the surface ultrapure water.

Furthermore, the bonding process of the germanium wafer is specifically as follows:

The surface of the germanium wafer and the surface of the upper insulating substrate layer are processed, specifically: a thin film of an oxide layer having a thickness of several nanometers is deposited on the surface of the germanium wafer and the upper insulating substrate layer, or the surface of the germanium wafer and the upper insulating substrate layer is activated by plasma, and the gas atmosphere is nitrogen or oxygen with argon as a carrier;

After surface treatment, the germanium wafer and the upper insulating substrate layer are pre-bonded;

Strengthen the bond energy of the electro-optical modulation chip formed by pre-bonding;

In a vacuum environment, the germanium wafer is uniformly heated until the temperature rises to 300°C to 400°C for annealing, and is maintained for a sufficiently long time until the germanium cracked layer and the residual germanium substrate are peeled off;

The germanium defect-rich layer on the surface is removed by grinding, and the germanium thin film layer is retained;

Annealing is performed again in a vacuum environment at a temperature of 500 to 550° C. for 10 to 60 minutes to further repair the remaining defects in the germanium thin film layer.

Furthermore, the bond energy enhancement is specifically as follows: a uniform pressure of 5-20N/ ^cm2 is applied longitudinally to the electro-optic modulation chip, and the temperature is slowly increased and maintained for 0.5-2 hours and then slowly cooled down in a vacuum atmosphere of less than ^10-5 mbar and an ambient temperature of 150℃-250℃, so that the bond energy is enhanced to more than 2J/ ^m2 .

Furthermore, the annealing method for stripping the germanium cracking layer and the residual germanium substrate is as follows: when the size of the electro-optical modulation chip is less than or equal to 6 inches, a furnace tube heating annealing method is adopted; when the size of the electro-optical modulation chip is greater than 6 inches, a laser annealing method is adopted.

Furthermore, the etching of the germanium thin film layer is specifically as follows:

For the optical gain part, the thickness of the germanium thin film layer is reduced, and a germanium substrate growth layer is formed by photolithography and etching to facilitate the growth of the compound semiconductor active layer;

For the light modulation part, the germanium thin film layer needs to be completely etched;

For the light detection part, the germanium thin film layer is used as the light absorption layer. First, the germanium absorption layer is formed by photolithography and etching, and then a pn junction is formed by doping or a photodetector is formed by forming interdigitated electrodes.

Furthermore, in the optical gain part, a growth window is opened by etching the upper insulating substrate layer on the germanium substrate growth layer. It is necessary to ensure that no natural oxide is generated on the germanium substrate growth layer after the growth window is opened, and a compound semiconductor active layer is grown.

The beneficial effects of the present invention are as follows: the present invention provides an electro-optic modulation chip structure capable of simultaneously integrating optical gain, optical modulation and optical detection and a method for preparing the same. The integration of a single crystal germanium thin film layer on an electro-optical material waveguide is achieved through the ion scissor technology, which can realize the preparation of a high-speed, high-response communication band germanium detector on the one hand; on the other hand, germanium as a growth substrate matches the compound semiconductor lattice, which can realize high-quality crystal growth and high-performance optical gain devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of an electro-optic modulation chip capable of monolithically integrating active optical devices provided by the present disclosure;

FIG2 is a flow chart of the preparation of an electro-optic modulation chip capable of monolithically integrating active optical devices provided by the present disclosure;

FIG3 is a schematic diagram of the structure of the preparation step S1 provided in the present disclosure;

FIG4 is a schematic diagram of the structure of the preparation step S2 provided in the present disclosure;

FIG5 is a schematic diagram of the germanium wafer structure in the preparation step S4 provided by the present disclosure;

FIG6 is a schematic diagram of the structure after pre-bonding in the preparation step S5 provided in the present disclosure;

FIG7 is a schematic diagram of forming a germanium thin film layer in the preparation step S5 provided by the present disclosure;

FIG8 is a schematic diagram of the final structure in the preparation step S5 provided in the present disclosure;

FIG9 is a schematic diagram of the structure of the preparation step S6 provided in the present disclosure;

FIG10 is a schematic diagram of the structure of the preparation steps S7-S8 provided in the present disclosure;

FIG11 is a schematic diagram of the structure of the preparation step S9 provided in the present disclosure;

FIG12 is a schematic diagram of the structure of the preparation steps S10-S11 provided in the present disclosure;

FIG13 is a schematic diagram of the structure of the preparation step S12 provided in the present disclosure;

In the figure, 100 is an electro-optic modulation chip, 10 is an electro-optic material wafer, 101 is a contact electrode, 102 is a via electrode, 103 is a compound semiconductor active layer, 11 is a germanium wafer, 104 is a germanium thin film layer, 104-a is a germanium cracking layer, 104-b is a germanium defect enriched layer, 104-c is a residual germanium substrate, 104-1 is a germanium substrate growth layer, 104-2 is a germanium absorption layer, 105 is an electro-optic material waveguide layer, 12 is a waveguide structure, 106a is an upper insulating substrate layer, 106b is a lower insulating substrate layer, 107 is a chip substrate layer, 200 is an optical gain part, 300 is the light modulation part, and 400 is the light detection part.

DETAILED DESCRIPTION

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

For the sake of clarity, the following description of the embodiments of the present invention and related structures is mainly characterized by single chip structures formed on a semiconductor substrate and their preparation steps. However, in practice, various embodiments can be performed at the wafer level for efficiency considerations.

It should be noted that references to "one embodiment," "an embodiment," "exemplary embodiment," "some embodiments," etc. in an application document indicate that the described embodiment may include a particular feature, structure, or characteristic, but that every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, the phrase does not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether or not explicitly described, it is within the knowledge of those skilled in the art to implement the feature, structure, or characteristic in connection with other embodiments.

Typically, terminology is understood at least in part based on usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may again be understood to convey singular usage or to convey plural usage, depending at least in part on the context. Additionally, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, but rather may allow for the presence of additional factors that are not necessarily clearly described, again, depending at least in part on the context.

It will be readily understood that the meaning of “on”, “over”, and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on”, but also includes “on” with intervening features or layers therebetween, and “on” means “directly on”. "Above" or "over..." not only means "above (something)" or "on (something)", but can also include the meaning of "above (something)" or "on (something)" without the intervening features or layers (i.e., directly on something).

Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc. may be used for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. The substrate itself can be patterned. The material added atop the substrate can be patterned, or the material added atop the substrate can remain unpatterned. In addition, the substrate can contain a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be composed of a non-conductive material such as glass, plastic, or a sapphire wafer.

As used herein, the term "layer" refers to a material portion comprising an area having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a width smaller than the width of an underlying or overlying structure. In addition, a layer can be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between the top surface and the bottom surface of a continuous structure, between any pair of horizontal planes at the top surface and the bottom surface of a continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can contain one or more layers therein, and/or can have one or more layers thereon, above, and/or below. A layer can contain multiple layers. For example, an interconnect layer can contain one or more conductors and contact layers (wherein interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term "front side" of a structure refers to the surface of the structure that is used to form a device or that will subsequently be used to form a device.

As used herein, the term "semiconductor" of a structure refers to, but is not limited to, a material having a conductivity value that falls between the conductivity values of a conductor and an insulator. The material may be a single element material or a compound material. Conductors may include, but are not limited to, single elements, binary alloys, ternary alloys, and quaternary alloys. Structures formed using one or more semiconductors may include a single semiconductor material, two or more semiconductor materials, a single-composition semiconductor alloy, two or more discrete-composition semiconductor alloys, and a semiconductor alloy that grades from a first semiconductor alloy to a second semiconductor alloy. Semiconductors may be one of undoped (intrinsic), hole-doped, electron-doped, doped from a first doping level of one type to a third doping level of the same type, and doped from a first doping level of one type to a third doping level of a different type.

Further, the semiconductor may include, but is not limited to, Group IV semiconductors, such as those between carbon (C), silicon (Si), germanium (Ge), and tin (Sn).

Further, the semiconductor may include, but is not limited to, Group III-V semiconductors, such as those between aluminum (Al), gallium (Ga), indium (In), nitrogen (N), phosphorus (P), arsenic (As), and tin (Sb).

Further, the semiconductor may include, but is not limited to, Group II-VI semiconductors, such as those between zinc (Zn), cadmium (Cd), mercury (Hg), sulfur (S), selenium (Se), tellurium (Te), and oxygen (O).

As used herein, the term "metal" of the structure refers to, but is not limited to, materials (elements, compounds, and alloys) that have good electrical and thermal conductivity as a result of readily losing outer shell electrons. This may include, but is not limited to, gold, chromium, aluminum, silver, platinum, nickel, copper, rhodium, palladium, tungsten, and combinations of such materials.

As used herein, the terms "optical waveguide", "dielectric waveguide" or "waveguide" of a structure refer to, but are not limited to, a dielectric medium or combination of media that supports propagation of optical signals within a predetermined wavelength range and is constant along the propagation direction. The optical waveguide may be at least one of: an isolation structure and an optical waveguide comprising at least a core and a cladding (e.g., an optical fiber), formed as part of a carrier, formed within a substrate (e.g., a planar lightwave circuit, a photonic integrated circuit, an integrated optical device). This includes, but is not limited to, flexible optical waveguides formed of extruded glass, extruded doped quartz, extruded chalcogenide glass, and polymers. This further includes, but is not limited to, optical waveguides formed within: quartz on insulator, quartz on silicon, silicon oxynitride on silicon, polymer on silicon, polymer on polymer, etc.

As used herein, the term "optical waveguide layer" refers to a material portion including a region having a thickness. More specifically, it can have the function of confinement and conduction of light waves after subsequent processing, including but not limited to one or more layers of waveguide material.

As used herein, the term "dielectric layer" refers to a material portion having a region with a thickness. More specifically, it has the function of achieving electrical connection or transmitting carriers, including but not limited to one or more layers of metal or other conductive materials.

As used herein, the term "optical-electrical layer via structure" refers to a via structure connecting the dielectric layer and the electrical absorption layer, which has the effect of connecting the electrical connection in the dielectric layer with the electrical connection in the electrical absorption layer, so that light can be further transmitted to the dielectric layer after being converted into electrons in the electrical absorption layer for further signal processing. Its materials include but are not limited to the aforementioned metal materials or conductive polymer materials.

As shown in FIG. 1 , a cross-sectional structure diagram of an electro-optic modulation chip 100 capable of monolithically integrating active optical devices mentioned in the present invention is shown.

Specifically, the electro-optic modulation chip 100 capable of monolithically integrating active optical devices includes, from top to bottom, a compound semiconductor active layer 103, a germanium thin film layer 104, and an electro-optic material waveguide layer 105. The electro-optic material waveguide layer 105 is formed into a corresponding waveguide structure 12 by photolithography and etching to achieve light propagation in the electro-optic material waveguide layer 105. The germanium thin film layer 104 is formed into a germanium absorption layer 104-2 and a germanium substrate growth layer 104-1 by photolithography and etching.

The electro-optic material waveguide layer 105 serves as a coupling medium for optical signals, and together with the compound semiconductor active layer 103 grown on the germanium substrate growth layer 104-1, constitutes a waveguide. By means of electrical injection, the optical signal is amplified through the compound semiconductor active layer 103, thereby constituting the optical gain part 200 of the electro-optic modulation chip 100 capable of monolithically integrating active optical devices.

The electro-optical material waveguide layer 105 serves as a coupling medium for optical signals and together with the germanium absorption layer 104-2 constitutes a waveguide. Since germanium has strong absorption of light below 1600nm, the germanium absorption layer 104-2 can serve as a light detection medium. The electro-optical material waveguide layer 105 and the germanium absorption layer 104-2 together constitute the light detection part 400 of the electro-optical modulation chip 100 that can be monolithically integrated with active optical devices.

The electro-optic material waveguide layer 105 serves as a propagation medium for optical signals and constitutes the optical modulation part 300 of the electro-optic modulation chip 100 capable of monolithically integrating active optical devices.

FIG2 shows the preparation process of the electro-optic modulation chip 100 capable of monolithically integrating active optical devices. The following describes each process in detail:

S1: preparing an electro-optical material wafer 10;

Specifically, as shown in FIG. 3 , the electro-optic material wafer 10 includes a wafer having an electro-optic material waveguide layer 105 made of lithium niobate, lithium tantalate or other materials having a linear electro-optic effect, and having a lower insulating substrate layer 106 b and a chip substrate layer 107 .

In particular, such wafers can be provided by wafer manufacturers, and their specific preparation process is not within the scope of discussion of the patent of this invention.

Preferably, the thickness of the electro-optic material waveguide layer 105 in the electro-optic material wafer 10 is 400 nanometers, and more generally, the thickness ranges from 300 to 500 nm.

S2: etching the waveguide structure 12;

As shown in FIG4 , a waveguide structure 12 needs to be formed on the electro-optical material waveguide layer 105 . The specific design of the waveguide structure is beyond the scope of the present invention, but its types should include common strip waveguides, ridge waveguides, gap waveguides, and sub-wavelength grating waveguides.

Preferably, the waveguide structure shown in FIG4 is a ridge waveguide, the purpose of which is to move the localized light mode of the optical waveguide up to a region close to the top of the waveguide structure 12 to facilitate coupling with subsequent structures, while having lower propagation loss than a strip waveguide.

S3: depositing an insulating substrate layer 106a and leveling the surface;

After completing the waveguide etching, an oxide layer needs to be deposited to form an upper insulating substrate layer 106a. During the oxide layer deposition process, the geometric structure of the waveguide structure 12 will gradually transfer to the surface of the upper insulating substrate layer 106a as the deposition process proceeds. Therefore, the surface of the upper insulating substrate layer 106a needs to be polished and leveled.

In particular, in order to ensure that the waveguide structure 12 can support its upper structure when subsequently forming the optical gain part 200, the optical modulation part 300 and the optical detection part 400, it is necessary to limit the distance between the top surface of the upper insulating substrate layer 106a and the top surface of the waveguide structure 12.

Preferably, the spacing should be less than 100 nm, and the optimal spacing should be maintained at 50 nm.

S4: preparing germanium wafer;

Traditional Group IV semiconductor materials often do not have a linear electro-optic effect. Although compound semiconductor materials have a linear electro-optic effect, their production and processing costs are too high, and therefore they are not suitable for the preparation of a low-cost and high-performance electro-optic modulation chip 100.

Common electro-optical materials such as lithium niobate and lithium tantalate are very suitable for the preparation of the optical modulation part 300 in the electro-optic modulation chip 100, but since they are generally insulating materials, it is not possible to simply integrate the optical gain part 200 and the optical detection part 400 by doping and injection. Although in some studies, scientists have developed an integrated optical chip that uses erbium-doped lithium niobate materials to achieve optical amplification, its preparation process is complex and global, which is not conducive to monolithic integration.

The present invention uses a germanium wafer 11 as a medium for integrating an optical gain part 200 and an optical detection part 400 of an electro-optic modulation chip 100. The integration of a germanium thin film layer 104 made of a germanium wafer 11 on an electro-optical material waveguide layer 105 is achieved by ion scissor technology. To achieve this purpose, the germanium wafer 11 needs to be specially processed.

Specifically, a germanium wafer 11 needs to be prepared in advance, the impurity doping concentration of which should be in the range of 10 ¹⁶ cm ^-3 to 5×10 ¹⁶ cm ^-3 , the doping type can be n-type or p-type, and the surface roughness (RMS) should be guaranteed to be less than 0.5 nm/100 μm ² .

Subsequently, the germanium wafer 11 is cleaned. First, a 25% buffered hydrofluoric acid solution (BHF) or a diluted hydrofluoric acid solution (DHF) is used to clean the oxide layer on the surface of the germanium wafer 11 for 3 to 5 minutes. After the acid cleaning is completed, it is cleaned in deionized ultrapure water to remove the residual hydrofluoric acid solution on the surface. After the water washing is completed, it is necessary to ensure that the ultrapure water film on the surface of the germanium wafer 11 is evenly and flatly covered on the surface of the germanium wafer 11. The purpose of this step is to confirm that the dangling bond structure on the surface of the germanium wafer 11 is a hydrophilic structure. Afterwards, the surface ultrapure water is removed by nitrogen blowing or vacuum back adsorption and drying.

Next, a dense oxide film is deposited on the germanium wafer 11 by vapor deposition as a protective layer for subsequent processes. Preferably, the oxide film thickness should be 100nm, and the material is silicon dioxide. A wider range includes 50nm to 200nm.

Subsequently, hydrogen ion (H ⁺ ) is implanted into the germanium wafer 11 at room temperature, with an implantation angle of 7°, an implantation dose of 4×10 ¹⁶ cm ^-3 to 1×10 ¹⁷ cm ^-3 , an implantation energy of 60 keV to 250 keV, and an implantation beam current of less than or equal to 1000 μA/cm ² .

Preferably, in order to prevent the occurrence of self-heating effect and ensure that the germanium thin film layer 104 of sufficient thickness can be transferred to the surface of the electro-optical material waveguide layer 105 in the subsequent process, the injection conditions should be: injection angle of 7°, injection dose of 4×10 ¹⁶ cm ^-3 , injection energy of 80 keV, and injection beam current of 100 μA/cm ² .

After the injection is completed, use BHF or DHF solution to clean the surface oxide layer again for 3 to 5 minutes. After the acid cleaning is completed, clean it in deionized ultrapure water to remove the residual hydrofluoric acid solution on the surface. After the water washing is completed, it is necessary to ensure that the ultrapure water film on the surface of the germanium wafer 11 is evenly and flatly covered on the surface of the germanium wafer 11. The purpose of this step is to confirm that the dangling bond structure on the surface of the germanium wafer 11 is still a hydrophilic structure. Afterwards, the surface ultrapure water is removed by nitrogen blowing or vacuum back adsorption and drying, and finally the prepared germanium wafer 11 is obtained.

As shown in FIG. 5 , the surface of the germanium wafer 11 has a germanium thin film layer 104, which has a lower defect density and residual hydrogen ion concentration after ion implantation because it is close to the surface of the germanium wafer 11. As the depth increases, a germanium defect-enriched layer 104-b will be formed at a deeper position on the surface of the germanium wafer 11, and the position and thickness of the layer will change with the change of the implantation conditions. More specifically, by adjusting the implantation energy and implantation metering, the depth and thickness of the germanium defect-enriched layer 104-b can be changed. At the same time, for a certain specific implantation condition, the germanium defects will form a germanium cracking layer 104-a with a certain thickness at a certain depth during the enrichment process. There are a large number of germanium lattice defects in this layer, and hydrogen ions will passivate the dangling bonds on the defects and gather in the form of hydrogen molecules at the defect core. The deeper residual germanium substrate 104-c is much deeper than the depth that hydrogen ions can penetrate after acceleration, so its basic properties are similar to those of the germanium thin film layer 104, and both can be considered to be single crystal germanium materials.

S5: bonding germanium wafer;

In order to transfer the germanium thin film layer 104 onto the electro-optical material waveguide layer 105, the germanium wafer 11 needs to be firstly bonded by wafer bonding so that the upper surface of the germanium wafer 11 and the upper surface of the upper insulating substrate layer 106a formed on the electro-optical modulation chip 100 are tightly bonded together through intermolecular forces. To achieve this operation, the germanium wafer 11 and the electro-optical modulation chip 100 need to be surface treated.

Specifically, a thin oxide film several nanometers thick is deposited on the upper surface of the germanium wafer 11, and the material thereof may be silicon oxide, aluminum oxide, etc., and the deposition method includes plasma gas enhanced vapor deposition or ordinary vapor deposition, or is formed by an atomic layer deposition device. Similarly, a thin oxide film several nanometers thick also needs to be deposited on the electro-optical modulation chip 100. Preferably, the thickness of the thin oxide film is 5 nanometers, and the deposition method is atomic layer deposition.

Another approach is to use plasma surface activation, where a radio frequency power source of several hundred watts is used to The surface is treated for dangling bond activation, and the gas atmosphere can be nitrogen, oxygen or other common semiconductor process gases with argon as the carrier.

After surface treatment, the two need to be pre-bonded, and the pre-bonding operation does not require fine alignment. FIG6 shows the structure of the electro-optic modulation chip 100 after pre-bonding of the germanium wafer 11. At this time, the germanium thin film layer 104 is pre-transferred to the upper insulating substrate layer 106a, but the strength of its intermolecular bonding is still weak, and the germanium defect-enriched layer 104-b, the germanium cracked layer 104-a and the residual germanium substrate 104-c have not been removed.

Next, we use bonding equipment to enhance the bonding energy of the pre-bonded electro-optic modulation chip 100. Specifically, a uniform pressure of 5 to 20 N/cm ² is applied longitudinally to the electro-optic modulation chip 100, and the temperature is slowly increased and maintained for 0.5 to 2 hours under the conditions of a vacuum atmosphere of less than 10 ^{- 5} mbar and an ambient temperature of 150°C to 250°C, and then slowly cooled down, so that the bonding energy is enhanced to more than 2 J/m ² .

In particular, the selection of pressure and temperature needs to be adjusted according to the actual size of the electro-optic modulation chip 100 to avoid wafer fragmentation. In the present invention, the size of the electro-optic modulation chip 100 ranges from a single chip size (<1 inch wafer) to a 12 inch wafer size. The size of the corresponding germanium wafer 11 should also be consistent with the size of the electro-optic modulation chip 100.

Next, we need to peel off the germanium thin film layer 104. This step is called ion scissor technology. By raising the temperature and maintaining it for a sufficiently long time, the residual hydrogen ions in the germanium cracked layer 104-a are induced to gather into clusters and apply microscopic stress to the defects where they are located, so that the germanium cracked layer 104-a undergoes a large-scale fracture parallel to the wafer direction, thereby peeling off the germanium cracked layer 104-a and the residual germanium substrate 104-c together, leaving only the germanium thin film layer 104 and the germanium defect-enriched layer 104-b, as shown in Figure 7.

In particular, the heating process should ensure that the temperature changes slowly and is evenly distributed across the wafer to avoid wafer breakage due to stress differences.

Preferably, the wafer should be uniformly heated at a rate of 1°C per minute in a vacuum environment of less than 10 ^-5 mbar until the temperature reaches 300°C to 400°C for annealing, and maintained for a sufficiently long time until the germanium cracking layer 104 - a breaks.

Since the fracture process is very rapid, the stress conduction may cause the wafer to inevitably break. Another improved cracking method is to use high-energy laser-induced cracking. In this method, the focus of the laser is set near the germanium cracking layer 104-a, and annealing is performed through continuous single-point scanning to gradually induce The germanium cracking layer 104-a at various locations on the chip breaks, and finally the small break points at various locations spontaneously connect to each other to form a large-scale break effect.

Preferably, when the size of the electro-optic modulation chip 100 is less than or equal to 6 inches, furnace heating annealing may be used; when the size of the electro-optic modulation chip 100 is greater than 6 inches, laser annealing should be used.

Subsequently, the germanium defect-enriched layer 104-b on the surface is removed by chemical mechanical polishing, and the germanium thin film layer 104 is retained, as shown in FIG8. Finally, annealing is performed again in a vacuum environment of less than ^10-5 mbar, the annealing temperature is 500-550°C, and the annealing time is 10-60 minutes to further repair the remaining defects in the germanium thin film layer 104.

S6: etching the germanium thin film layer;

The germanium thin film layer 104, as a precursor of the germanium substrate growth layer 104-1 and the germanium absorption layer 104-2, has been transferred to the surface of the upper insulating substrate layer 106a as described above. Next, the optical gain part 200, the optical modulation part 300 and the optical detection part 400 of the present invention will be discussed separately.

For the optical gain part 200, the germanium thin film layer 104 has a light absorption effect in the target band, so it is necessary to reduce its thickness so as to reduce the absorption area. Since the lattice coefficient of germanium itself matches that of compound semiconductors, especially gallium arsenide (GaAs), it is very suitable as a precursor substrate for the growth of compound semiconductors. Therefore, its thickness should be guaranteed to provide sufficient seed crystal area for the growth of the compound semiconductor active layer 103. The present invention does not discuss its specific growth mode. In contrast, the present invention focuses on the need to keep a relatively thin thickness when processing the germanium thin film layer 104 in this step, and its typical thickness should be 50 nanometers to form a germanium substrate growth layer 104-1, as shown in Figure 9. In addition, by forming a grid-like structure array on the germanium substrate growth layer 104-1, it can also be used as a precursor for the growth of compound semiconductors.

For the light modulation part 300, the germanium thin film layer 104 needs to be completely etched to ensure that it does not affect the electro-optical material waveguide layer 105 and introduce excessive insertion loss during light modulation.

For the light detection part 400, the germanium thin film layer 104 can be used as a light absorption layer. First, a germanium absorption layer 104-2 is formed by photolithography and etching, as shown in Figure 9, and then a pn structure is formed by doping to form a PIN type photodetector, or an MSM type photodetector is formed by forming interdigitated electrodes, and its typical thickness should be 200 nanometers.

S7: Continue to deposit the upper insulating substrate layer 106a;

After the germanium substrate growth layer 104-1 and the germanium absorption layer 104-2 are prepared, an upper insulating substrate layer 106a needs to be deposited to ensure the passivation of the germanium material, as shown in Figure 10. Since the growth window still needs to be opened for the growth of compound semiconductors, the thickness of the upper insulating substrate layer 106a deposited in this step should not exceed 200 nanometers.

S8: Open the growth window;

A growth window is opened by etching the upper insulating substrate layer 106a on the germanium substrate growth layer 104-1, as shown in FIG10. This step needs to ensure that no natural oxide is generated on the germanium substrate growth layer 104-1 after the growth window is opened. Therefore, the sample needs to be stored in a vacuum after the etching is completed.

S9: growing compound semiconductors;

A compound semiconductor active layer 103 is grown on a germanium substrate growth layer 104-1 in a vapor phase epitaxial device, as shown in FIG11. The present invention does not protect the compound semiconductor growth environment and layer structure, but only protects the compound semiconductor growth method using the germanium substrate growth layer 104-1 as a seed layer.

S10: Continue to deposit the upper insulating substrate layer 106a;

As shown in FIG. 12 , the upper insulating substrate layer 106 a is continuously deposited to ensure airtight protection of the grown compound semiconductor.

S11: forming a via electrode 102;

Via structures are formed in the optical gain part 200 , the optical modulation part 300 and the optical detection part 400 by etching, and are filled with conductive materials (such as metal, transparent conductive oxide, etc.) to form via electrodes 102 , as shown in FIG. 12 .

S12: forming a contact electrode 101;

Finally, as shown in FIG. 13 , a contact electrode 101 is formed on the via electrode 102 by etching, electroplating or stripping, and the contact electrode 101 is generally made of metal.

The above is only a preferred embodiment of the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the art can make many possible changes and modifications to the technical solution of the present invention by using the above disclosed methods and technical contents without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment with equivalent changes. Therefore, any changes made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention are not intended to be construed as limiting the present invention. Simple modifications, equivalent changes and modifications still fall within the scope of protection of the technical solution of the present invention.

Claims (10)

An electro-optic modulation chip capable of monolithically integrating active optical devices, characterized in that it comprises, from top to bottom, a compound semiconductor active layer, a germanium thin film layer and an electro-optic material waveguide layer; the electro-optic material waveguide layer is formed into a corresponding waveguide structure by photolithography and etching; the germanium thin film layer is formed into a germanium absorption layer and a germanium substrate growth layer by photolithography and etching; The electro-optic material waveguide layer serves as a coupling medium for optical signals, and together with the compound semiconductor active layer grown on the germanium substrate growth layer, forms a waveguide, which constitutes the optical gain part of the electro-optic modulation chip; The electro-optic material waveguide layer serves as a coupling medium for optical signals and together with the germanium absorption layer forms a waveguide, which constitutes the optical detection part of the electro-optic modulation chip; The electro-optic material waveguide layer serves as a propagation medium for optical signals and constitutes the optical modulation part of the electro-optic modulation chip. A method for preparing an electro-optic modulation chip capable of monolithically integrating active optical devices, characterized in that it comprises the following steps: preparing an electro-optic material wafer having an electro-optic material waveguide layer, etching the electro-optic material waveguide layer to form a waveguide structure, depositing an insulating substrate layer and flattening the surface; A germanium wafer is prepared, and after hydrogen ion implantation, a germanium thin film layer, a germanium defect-enriched layer, a germanium cracked layer and a residual germanium substrate are formed on the surface of the germanium wafer; Bonding a germanium wafer to the surface of the upper insulating substrate layer, and retaining only the germanium thin film layer of the germanium wafer by annealing and grinding; Etching the germanium thin film layer to form a germanium substrate growth layer of the optical gain part and a germanium absorption layer of the optical detection part; continuing to deposit an insulating substrate layer, and opening a growth window in the optical gain part to grow a compound semiconductor active layer on the germanium substrate growth layer; The insulating substrate layer is continuously deposited, and a via electrode and a contact electrode are formed. The preparation method according to claim 2 is characterized in that the impurity doping concentration of the germanium wafer should be in the range of 10 ¹⁶ cm ^-3 to 5×10 ¹⁶ cm ^-3 , the doping type is n-type or p-type, and the surface roughness should be below 0.5 nm/100 μm ² . The preparation method according to claim 2 is characterized in that the preparation process of the germanium wafer is specifically as follows: Cleaning and drying the germanium wafer; depositing an oxide layer film on the germanium wafer to form a protective layer; The germanium wafer is implanted with hydrogen ions at room temperature, with an implantation angle of 7°, an implantation dose of 4×10 ¹⁶ cm ^-3 to 1×10 ¹⁷ cm ^-3 , an implantation energy of 60keV to 250keV, and an implantation beam current of less than or equal to 1000μA/cm ² ; After the implantation is completed, the germanium wafer is cleaned and dried again to obtain a finished germanium wafer. The preparation method according to claim 4 is characterized in that the cleaning and drying are specifically: using a buffered hydrofluoric acid solution or a diluted hydrofluoric acid solution to clean the oxide layer on the surface of the germanium wafer for 3 to 5 minutes; after the acid cleaning is completed, cleaning in deionized ultrapure water to remove the residual hydrofluoric acid solution on the surface; after the water washing is completed, nitrogen blowing or vacuum back adsorption and drying are used to remove the surface ultrapure water. The preparation method according to claim 2 is characterized in that the bonding process of the germanium wafer is specifically as follows: The surface of the germanium wafer and the surface of the upper insulating substrate layer are processed, specifically: a thin film of an oxide layer having a thickness of several nanometers is deposited on the surface of the germanium wafer and the upper insulating substrate layer, or the surface of the germanium wafer and the upper insulating substrate layer is activated by plasma, and the gas atmosphere is nitrogen or oxygen with argon as a carrier; After surface treatment, the germanium wafer and the upper insulating substrate layer are pre-bonded; Strengthen the bond energy of the electro-optical modulation chip formed by pre-bonding; In a vacuum environment, the germanium wafer is uniformly heated until the temperature rises to 300°C to 400°C for annealing, and is maintained for a sufficiently long time until the germanium cracked layer and the residual germanium substrate are peeled off; The germanium defect-rich layer on the surface is removed by grinding, and the germanium thin film layer is retained; Annealing is performed again in a vacuum environment at a temperature of 500 to 550° C. for 10 to 60 minutes to further repair the remaining defects in the germanium thin film layer. The preparation method according to claim 6 is characterized in that the bond energy enhancement is specifically: applying a uniform pressure of 5 to 20 N/cm ² to the electro-optical modulation chip longitudinally, slowly heating up and maintaining the temperature for 0.5 to 2 hours and then slowly cooling down the temperature under the conditions of a vacuum atmosphere of less than 10 ^-5 mbar and an ambient temperature of 150°C to 250°C. Temperature, so that the bond energy is enhanced to greater than 2J/ ^m2 . The preparation method according to claim 6 is characterized in that the annealing method when peeling off the germanium cracking layer and the residual germanium substrate is as follows: when the size of the electro-optical modulation chip is less than or equal to 6 inches, a furnace tube heating annealing method is adopted; when the size of the electro-optical modulation chip is greater than 6 inches, a laser annealing method is adopted. The preparation method according to claim 2 is characterized in that the etching of the germanium thin film layer is specifically: For the optical gain part, the thickness of the germanium thin film layer is reduced, and a germanium substrate growth layer is formed by photolithography and etching to facilitate the growth of the compound semiconductor active layer; For the light modulation part, the germanium thin film layer needs to be completely etched; For the light detection part, the germanium thin film layer is used as the light absorption layer. First, the germanium absorption layer is formed by photolithography and etching, and then a pn junction is formed by doping or a photodetector is formed by forming interdigitated electrodes. The preparation method according to claim 2 is characterized in that, in the optical gain part, a growth window is opened by etching an upper insulating substrate layer on the germanium substrate growth layer, it is necessary to ensure that no natural oxide is generated on the germanium substrate growth layer after the growth window is opened, and a compound semiconductor active layer is grown.