WO2025026895A1 - Detachable semiconductor substrate made of polycrystalline silicon carbide - Google Patents
Detachable semiconductor substrate made of polycrystalline silicon carbide Download PDFInfo
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- WO2025026895A1 WO2025026895A1 PCT/EP2024/071217 EP2024071217W WO2025026895A1 WO 2025026895 A1 WO2025026895 A1 WO 2025026895A1 EP 2024071217 W EP2024071217 W EP 2024071217W WO 2025026895 A1 WO2025026895 A1 WO 2025026895A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/36—Carbides
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/06—Joining of crystals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
Definitions
- the present application relates to the manufacture of semiconductor substrates, and more particularly to the manufacture of polycrystalline silicon carbide support layers for their use in high performance substrates.
- wideband semiconductor materials In the field of power electronics, it is known to use wideband semiconductor materials. These materials have a wider band gap than semiconductor materials such as silicon, which gives them electrical insulation properties between those of semiconductors and insulating materials. In particular, wideband semiconductors have the advantage of tolerating temperatures higher than those that conventional semiconductors are capable of withstanding. In addition, these materials have an increased power density compared to conventional semiconductors, allowing volume and mass gains in the electronic systems comprising them.
- SiC silicon carbide
- MOSFETs metal-oxide-semiconductor field-effect transistors
- SiC substrates with a certain thickness, generally of the order of 300 micrometers, giving them a mechanical resistance that allows the performance of front-end processes, i.e. the formation of electronic functions on the semiconductor substrate.
- the semiconductor substrates thus obtained are then placed on a metal support, in particular made of copper, and which has a Young's modulus and a thermal expansion coefficient different from those of the semiconductor substrate. Mechanical stresses can therefore be generated in the semiconductor substrate during thermal cycles to which it is subjected on the metal support.
- One way to overcome this problem is to reduce the thickness of the SiC layer, which is possible only after the front-end processes have been performed.
- a SiC substrate of a given thickness close to 300 micrometers, can be formed before mechanically etching a part of it in order to reduce its thickness, and therefore to reduce the mechanical constraints imposed on the metal support or on any welds between it and the SiC substrate during use and cycling. thermal resistance of the electronic component.
- a reduction in the thickness of the SiC substrate makes it possible to reduce the ON resistance and thermal resistance thereof, enabling better electrical performance, and makes it possible to bring the Young's modulus and the thermal expansion coefficient of the SiC substrate closer to those of the metal support.
- One aim sought is to remedy the aforementioned drawbacks.
- an intermediate substrate for manufacturing a semiconductor substrate, successively comprising: a. a first semiconductor layer, b. a first layer forming a thermal barrier, c. a support comprising an absorption layer configured to absorb laser radiation in a determined wavelength range, the temperature of the absorption layer increasing during absorption, and a separation zone adjacent to the absorption layer and configured to thermally degrade under the effect of the increase in temperature of the absorption layer, so as to separate at least part of the support from the rest of the intermediate substrate.
- the proposed substrate allows the separation, after completion of the front-end processes, of the semiconductor substrate into two distinct parts without mechanical etching, so as to retain only the desired thickness of the semiconductor layer before its integration into the metal support without compromising the flatness of the semiconductor layer.
- the use of a laser to divide the semiconductor substrate into two parts, and thus isolate the desired thickness of this substrate, allows it to be obtained more quickly and at a lower cost than by mechanical etching.
- the use of a thermal barrier layer makes it possible to limit the propagation of heat in the rest of the substrate and therefore promotes separation with reduced power and/or laser exposure time.
- the support comprises: a. a separation assembly comprising: i. the absorption layer, and ii.
- a separation layer adjacent to the absorption layer and comprising the separation zone, the degradation of the separation zone occurring when the absorption layer reaches a threshold temperature
- a second thermal barrier layer c. a support layer, the second thermal barrier layer being located between the separation assembly and the support layer.
- the support comprises: a. the absorption layer, and b. a support layer further forming a second thermal barrier, the separation zone being included in the support layer.
- the substrate further comprises a seed layer suitable for growing the first semiconductor layer, the seed layer preferably comprising graphite, the first semiconductor layer being interposed between the seed layer and the first thermal barrier layer.
- the separation layer is made of silicon nitride.
- the absorption layer is made of a material chosen from polycrystalline silicon carbide of the p-SiC type, titanium nitride or zirconium.
- the substrate further comprises a monocrystalline semiconductor layer, preferably comprising silicon carbide or gallium nitride, a first face of the monocrystalline semiconductor layer being adjacent to the first semiconductor layer.
- the first semiconductor layer is made of a broadband semiconductor material, in particular a material chosen from silicon carbide, aluminum nitride and gallium nitride.
- the support layer is a second semiconductor layer of lower quality than the first semiconductor layer, preferably made of a material chosen from silicon carbide and silicon nitride.
- the support layer has a thickness of between 100 and 200 nanometers.
- the first and/or second thermal barrier layer has a thermal conductivity of less than 25 W/mK, the second thermal barrier layer preferably being made of titanium dioxide or silicon nitride.
- the substrate further comprises a monocrystalline semiconductor layer disposed on a surface region of the first semiconductor layer, the first semiconductor layer being located between the first thermal barrier layer and the monocrystalline semiconductor layer.
- Another aspect relates to a method for manufacturing a semiconductor intermediate substrate, successively comprising steps of: a. growing a first electrically semiconductor layer on a seed layer, b. growing, on the first semiconductor layer, a first thermal barrier layer, c. growing, on the first thermal barrier layer, a support comprising an absorption layer configured to absorb laser radiation in a determined wavelength range, the temperature of the absorption layer increasing during absorption, the support further comprising a separation zone adjacent to the absorption layer and configured to thermally degrade under the effect of the increase in temperature of the absorption layer, so as to separate at least part of the support from the rest of the intermediate substrate, d. removing the seed layer, the growth steps being obtained in particular by gas phase deposition on the previously formed layers.
- the growth of the support comprises successive steps of: a. growth of a separation assembly consisting of the absorption layer and a separation layer, the growth of the separation assembly comprising: the growth of the absorption layer the growth of the separation layer, the separation layer comprising the separation zone, the separation zone being adjacent to the absorption layer, b. growth, on the separation assembly, of a second layer forming a thermal barrier: c. growth, on the second layer forming a thermal barrier, of a support layer, the growth steps being obtained in particular by gas phase deposition on the previously formed layers.
- the growth of the support comprising successive steps of: a. growth, on the first layer forming a thermal barrier, of the absorption layer b. growth, on the absorption layer, of a support layer also acting as a second thermal barrier, the separation zone being included in the support layer, the growth steps being obtained in particular by gas phase deposition on the previously formed layers.
- Another aspect relates to a method of manufacturing a substrate comprising a monocrystalline semiconductor layer on a polycrystalline semiconductor substrate, comprising implementing the method of manufacturing an intermediate semiconductor substrate as defined above, the first semiconductor layer being polycrystalline, and further comprising successive steps of: a. forming a weakening zone in a semiconductor donor substrate by implantation of species, so as to delimit a monocrystalline semiconductor layer to be transferred, b. bonding the monocrystalline semiconductor layer to be transferred to a surface region of the first semiconductor layer, c. detaching the donor substrate along the weakening zone to transfer the monocrystalline semiconductor layer to the first semiconductor layer.
- Another aspect relates to a method of manufacturing an electronic component, comprising successive steps of: a. Implementing the method of manufacturing a substrate as defined above, b. Carrying out front-end processes in the monocrystalline semiconductor layer to form said electronic component.
- the method comprises, after carrying out said frontal processes, a step of applying laser radiation in the determined wavelength range to the intermediate substrate, so as to thermally degrade the separation zone and to separate at least part of the support from the rest of the intermediate substrate.
- the method comprises, after the application of the laser radiation, a step of removing residual layers located on a face of the first semiconductor layer opposite the monocrystalline semiconductor layer, the residual layers resulting from the step of applying the laser radiation.
- Another aspect relates to an intermediate substrate for the manufacture of a semiconductor substrate, successively comprising:
- a first semiconductor layer made of polycrystalline silicon carbide (pSiC),
- a first layer forming a thermal barrier made of titanium dioxide (TiO 2 ),
- An absorption layer made of 3C-type polycrystalline silicon carbide (3C-pSiC),
- a separation layer made of silicon nitride (Sisl ⁇ ),
- a second layer forming a thermal barrier made of titanium dioxide (TiO 2 ),
- a support layer consisting of polycrystalline silicon carbide type 4H (4H-pSiC)
- Another aspect relates to an intermediate substrate for the manufacture of a semiconductor substrate, successively comprising:
- a first semiconductor layer made of polycrystalline silicon carbide (pSiC),
- a first layer forming a thermal barrier made of titanium dioxide (TiO 2 ),
- An absorption layer made of titanium nitride (TiN),
- a separation layer made of silicon nitride (Sisl ⁇ ),
- a second layer forming a thermal barrier made of titanium dioxide (TiO 2 ),
- a support layer made of polycrystalline silicon carbide type 4H (4H-pSiC).
- FIG. 1] schematically illustrate intermediate substrates for the manufacture of a semiconductor substrate, according to different embodiments of a first aspect
- FIG. 5 [Fig. 6], [Fig. 7] illustrate methods of manufacturing an intermediate substrate for subsequent manufacturing of a semiconductor substrate, according to different embodiments of a second aspect
- Figure 8 illustrates a method of manufacturing a substrate comprising a monocrystalline semiconductor layer on a polycrystalline semiconductor substrate, according to a third aspect.
- Figure 9 illustrates a method of manufacturing an electronic component, according to a fourth aspect.
- [Fig. 10], [Fig. 11], [Fig. 12] represent results of a simulation of the temperature evolution of an intermediate substrate during the application of laser radiation.
- an intermediate substrate 10 is shown in FIG. 1. It comprises an arrangement of layers, which can be formed successively from a seed layer 1 of graphite.
- the formation of the different layers of the intermediate substrate 10 can involve the successive injection of gases which make it possible to produce deposits by condensation.
- the first layer formed is a first semiconductor layer 2 called “high quality”, which is configured to support a layer from which components will be formed, in particular with a view to manufacturing power electronic components.
- the first semiconductor layer 2 is intended to remain in the final electronic component.
- the first semiconductor layer 2 may be a layer of polycrystalline silicon carbide, in particular of type 4H or 3C (also called p-pSiC). Alternatively, and depending on the applications, it may be made of monocrystalline silicon carbide of type 4H.
- the first semiconductor layer 2 may also be made of another broadband semiconductor material, such as aluminum nitride (AIN) or gallium nitride (GaN).
- the first semiconductor layer 2 is further configured to conduct an electric current.
- the first semiconductor layer 2 is doped.
- the first semiconductor layer 2 When the first semiconductor layer 2 is made of silicon carbide, it can be highly doped with nitrogen (N++ doping). It is also possible to envisage N-type doping with phosphorus or P-type doping with gallium or aluminium. This doping makes it possible to give the first semiconductor layer 2 a very low electrical resistivity, as well as a high thermal conductivity, close to that of bulk silicon carbide.
- the first semiconductor layer 2 is, on the other hand, formed of other materials, other forms of doping are conceivable: for example, for a first semiconductor layer 2 made of gallium nitride (GaN), silicon or magnesium doping can be used.
- the intermediate substrate 10 comprises a support 13 whose thickness is configured to give the substrate 10 a given mechanical strength, for example between approximately 100 and 400 pm.
- the first semiconductor layer 2 is also likely to be undoped, or even to be electrically insulating (for example, in the case of a silicon carbide layer, by vanadium doping).
- the support 13 comprises an absorption layer 3 and a separation zone 8 adjacent thereto.
- the absorption layer 3 is configured to absorb laser radiation in a determined wavelength range, so that its temperature increases.
- the wavelength range for the laser radiation is chosen so that the seed layer 1 and the first thermal barrier layer 5 (described below) are substantially transparent to this radiation, in order to ensure that a sufficient portion of the radiation reaches the absorption layer 3, and in order to avoid damage to these layers by the radiation.
- the separation zone 8 degrades, thus allowing the separation of the intermediate substrate 10 into two parts. It is thus possible to manufacture the intermediate substrate and then carry out the front processes from the semiconductor layer 2, the total thickness of the intermediate substrate 10 giving it sufficient mechanical strength to not be damaged by these processes, and finally apply a laser in the determined wavelength range so as to separate a thin part of the substrate which comprises the first semiconductor layer 2 from the rest of the substrate 10, without resorting to mechanical polishing or grinding which could damage the first semiconductor layer 2 and which would be longer and more expensive to implement.
- the absorption layer 3 may be made of a material selected from polycrystalline silicon carbide of the p-SiC type, titanium nitride (TiN) or zirconium (Zr). When it is made of p-SiC, the absorption layer 3 may be configured to absorb laser radiation whose wavelength is between 380 and 410 nanometers. Titanium nitride has the advantage of being able to absorb a wider range of radiation wavelengths, such that when the absorption layer is made of this material, it can be configured to absorb laser radiation whose wavelength is between 380 nanometers and 1.7 micrometers. Silicon carbide has the advantage of being a material that can be used for the manufacture of the first semiconductor layer 2, and therefore not to introduce any new chemical element during the manufacture of the intermediate substrate 10.
- the intermediate substrate further comprises, interposed between the first semiconductor layer 2 and the support 13, a first thermal barrier layer 5.
- This layer is configured to form a barrier to thermal conduction between the absorption layer 3 and the first semiconductor layer 2, so as to limit as much as possible an increase in temperature of the first semiconductor layer.
- the first thermal barrier layer 5 is configured to have a lower thermal conductivity than that of the first semiconductor layer 2, and the first semiconductor layer 2 would therefore undergo an increase in its temperature in the absence of the first thermal barrier layer 5.
- the first semiconductor layer 2 must have a low absorption coefficient over the wavelength range intended for the laser radiation, for example of a wavelength between 380 and 410 nanometers, so that it does not absorb the radiation intended to heat the absorption layer 3.
- the support 13 comprises a separation assembly 12 comprising, on the one hand, the absorption layer 3, and on the other hand a so-called sacrificial separation layer 4 adjacent to the absorption layer and comprising the separation zone 8.
- the separation layer 4 is configured so that the degradation of the separation zone 8 takes place when the absorption layer 3 reaches a threshold temperature, so as to be able to precisely control the separation of the intermediate substrate 10.
- the separation assembly 12 is arranged between the first layer 5 forming a thermal barrier and a second layer 6 forming a thermal barrier.
- the second thermal barrier layer 6 is adjacent, on its side opposite the separation assembly, to a support layer 7.
- the two thermal barriers 5, 6 make it possible to confine the temperature rise to the separation assembly so that only the separation assembly undergoes a significant temperature increase, allowing the separation of the substrate into two parts along the separation zone 8 without degradation of the rest of the substrate 10.
- the absorption layer 3 may be arranged, within the separation assembly 12, closer to the first thermal barrier layer 5 - as shown in FIG. 2 - or, alternatively, the separation layer 4 may be arranged closer to the first thermal barrier layer 5.
- the absorption coefficients of the absorption layer 3 and the separation layer 4 must allow heating of the absorption layer 3 and degradation of separation zone 8 of the separation layer
- the wavelength range for the laser radiation is chosen so that the second thermal barrier layer 6 and the support layer 7 are substantially transparent to this radiation, in order to avoid damage to these layers by the radiation.
- the separation layer 4 is advantageously very thin, for example less than 100 micrometers thick, so as not to weaken the intermediate substrate before separation. Providing a thin separation layer 4 also makes it possible to limit the manufacturing cost of this layer. It is not necessary to provide a thick separation layer 4 because the latter does not have the function of contributing to the mechanical strength of the substrate. It can be made of silicon nitride (of formula SisN ⁇ .
- the thermal barrier layers 5, 6 may have a thermal conductivity of less than 25 W/mK, preferably less than 10 W/mK. They may in particular be made of titanium dioxide (TiCh), or silicon nitride (SisN ⁇ .
- the main function of the support layer 7 is to increase the thickness of the intermediate substrate 10 so as to give it adequate mechanical strength for carrying out the front-end processes.
- the semiconductor properties of this layer are not important. It is therefore advantageous to minimize the cost of this layer as much as possible.
- the support layer 7 is therefore preferably of lower quality than that of the first semiconductor layer 2: the thermal resistivity and the electrical resistivity of the support layer 7 are, in particular, higher than those of the first semiconductor layer 2.
- the first semiconductor layer 2 has an electrical resistivity of less than 5 m ⁇ /cm while the support layer 7 has an electrical resistivity of greater than 5 m ⁇ /cm.
- the support layer 7 may be made of polycrystalline silicon carbide of the 4H-SiC type, or of silicon nitride (SisN ⁇ . It may have a thickness of between 100 and 200 nanometers. Furthermore, and like the first semiconductor layer 2, it is advantageous for the support layer 7 to have a low absorption coefficient over the wavelength range intended for the laser radiation, so that it does not absorb the radiation intended to heat the absorption layer 3.
- the intermediate substrate 10 does not comprise a second thermal barrier 6.
- the support layer 7 is made of a material having a low absorption coefficient. at the wavelengths intended for the laser radiation (i.e. transparent to the laser wavelength used), as well as low thermal conductivity. It may for example be silicon nitride (Sisl ⁇ ).
- silicon nitride has a coefficient of thermal expansion substantially close to that of polycrystalline silicon carbide, so that no additional mechanical stresses are introduced, compared with the embodiments previously described.
- This embodiment has the advantage of being compatible with the manufacturing process of layer 2 (silicon and nitrogen in the deposition reactor) and of simplifying the stacking of layers compared with the embodiments previously described.
- the intermediate substrate 10 comprises a monocrystalline semiconductor layer 14, a first face of which is adjacent to the first semiconductor layer 2 on its side opposite the first thermal barrier layer 5.
- the monocrystalline semiconductor layer may comprise silicon carbide or gallium nitride (GaN).
- a second aspect relates to a method for manufacturing a semiconductor intermediate substrate 10 as described above.
- the method comprises several layer growth phases, preferably implemented by successive gas depositions on the previously formed layers.
- all the successive layers can be deposited in the same enclosure and using the same deposition method.
- the first step 101 consists in growing, on a seed support 1, a first high-quality semiconductor layer 2.
- the method then comprises the growth 102 on this first semiconductor layer 2 of a first thermal barrier layer 5, then the growth 103 of a support 13 on the first thermal barrier layer 5.
- the method comprises the removal 104 of the seed layer, in particular by mechanical grinding or polishing.
- the support 13 comprises an absorption layer 3 and a separation zone 8 adjacent thereto.
- the absorption layer 3 is configured to absorb light radiation over a given wavelength range, the temperature of the absorption layer 3 then increasing by radiation, and the separation zone 8 is configured to become fragile and dissociate. under the effect of heating, and thus allow the separation of at least part of the support
- the growth 103 of the support 13 is divided into a plurality of successive sub-steps.
- a first sub-step consists in growing a separation assembly 12 comprising the absorption layer 3 as well as a separate adjacent separation layer 4, the separation layer 4 comprising the separation zone 8, the separation layer 4 being configured so that the separation zone 8 degrades when the absorption layer 3 reaches a threshold temperature.
- This first sub-step comprises the growth 1031 of the absorption layer 3, then the growth 1032 of the separation layer 4.
- a second sub-step 1033 comprises the growth 1033, on the separation assembly 12 thus formed, of a second thermal barrier layer 6, thus making it possible to contain the increase in temperature by irradiation between the two thermal barrier layers 5, 6, i.e.
- the growth step 103 of the support 13 comprises a third sub-step 1034 of growing a support layer 7 configured to give the intermediate substrate 10 a thickness and mechanical strength suitable for carrying out front-end processes.
- the growth 103 of the support 13 comprises a first growth step 1031 of the absorption layer 3 on the first thermal barrier layer 5, then a second growth step 1035 of a support layer 7 which comprises the separation zone 8.
- the support layer 7 is made of a material having a low thermal conductivity, and which is transparent to the wavelengths intended for the light radiation applied to the intermediate substrate 10 in order to separate the substrate 10 along the separation zone 8.
- the support layer 7 is of lower quality than the first semiconductor layer 2.
- the support layer 7 was deposited with a growth speed greater than that of the first semiconductor layer 2.
- a third aspect relates to a method for manufacturing a high-performance substrate.
- This method illustrated in FIG. 8 , comprises a first step of implementing the method for manufacturing an intermediate substrate 10 according to the second aspect. Then, the method comprises the formation 109 of a weakening zone in a semiconductor donor substrate 9 by implantation of species through a face of the donor substrate 9 so as to separate the donor substrate into two parts, one part defining a monocrystalline semiconductor layer 14. This is followed by a step 110 of bonding the donor substrate 9, at the level of the monocrystalline semiconductor layer 14, on a surface region of the first semiconductor layer 2 and a detachment step 111 of the donor substrate along the weakening zone.
- a semiconductor substrate is then obtained, comprising a monocrystalline semiconductor layer 14 arranged on a semiconductor layer 2, which can itself be monocrystalline or polycrystalline depending on the applications.
- a fourth aspect relates to a method for manufacturing an electronic component, as shown in FIG. 9.
- This method comprises a first step of implementing the method for manufacturing a semiconductor substrate according to the third aspect, as described in the preceding paragraph. Then, the method comprises a step 112 of performing front-end processes in the first layer in order to form the electronic component.
- Front-end processes also referred to by the English term “front-end” processes, mean the production of individual components - such as transistors, resistors, capacitors or others - integrated into the monocrystalline semiconductor layer 14 of the substrate.
- the method may further comprise, after the performance 112 of the front-end processes, the application 113 of laser radiation in a determined wavelength range to the intermediate substrate 10, thereby increasing the temperature of the absorption layer 4 and allowing the degradation of the separation zone 8 once the temperature of the absorption layer 4 reaches a threshold, and thus allowing the separation of at least part of the support 13 from the remainder of the intermediate substrate 10.
- the application 113 of laser radiation may in particular be done on the support layer 7.
- the method may further comprise a step 114 of removing residual layers 15 located on a face of the first semiconductor layer 2 opposite the monocrystalline semiconductor layer.
- the residual layers 15 come from the step 113 of applying the laser radiation, and comprise in particular the first thermal barrier layer 5, and possibly the absorption layer 3 as well as a portion of the separation layer 4.
- Figure 10 illustrates the temperature evolution in the intermediate substrate 10 during simulations of irradiation of the substrate by a laser radiation of 50 Watts and 125 micrometers in diameter, having a wavelength of 404 nanometers. Three curves I, II and III are shown, corresponding respectively to an irradiation duration of 47.2 milliseconds, 47.9 milliseconds and 50 milliseconds.
- the intermediate substrate 10 used for the simulation comprises two separate thermal barrier layers 5, 6 as well as a separation layer 4, and the laser radiation is applied to a free face of the support layer 7 opposite the other layers of the intermediate substrate 10. It can be seen that the temperature of the absorption layer exceeds 2000 °C while the temperatures of the first semiconductor layer 2 and the support layer 7 rise to a maximum of approximately 800 °C.
- Figure 11 shows a change in the maximum temperature in the separation layer 4 as a function of the diameter of the laser used, under the same simulation conditions as for Figure 10.
- the three curves I, II and III correspond respectively to exposure times of the intermediate substrate 10 of 50, 100 and 200 microseconds. It can be seen that it is necessary to provide a small laser radiation diameter in order to obtain a sufficiently high temperature rise in the separation layer 4. For an increase in the temperature in the separation layer 4 beyond 2000 °C, laser radiation of less than 150 micrometers in diameter is necessary under these simulation conditions.
- Figure 12 shows, for the same simulation conditions: the evolution of the maximum temperature in the separation layer 4, the latter being represented by the curves marked I to VI, the evolution of the surface temperature of the substrate, represented by the curve marked VII for laser radiation of 125 micrometers in diameter and for an exposure time of 200 microseconds.
- the diameter of the laser beam can vary depending on several factors, for example the laser power or the materials present in the substrate.
- the parameters of the laser used are listed, for each curve, in Table 1 below.
- the surface temperature of the substrate it is seen that it reaches a maximum of about 200 °C, much lower than the temperatures obtained in the separation layer, which demonstrates the effectiveness of the thermal barrier layers 5, 6.
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Abstract
Description
DESCRIPTION DESCRIPTION
Substrat semiconducteur détachable en carbure de silicium polycristallin Detachable polycrystalline silicon carbide semiconductor substrate
DOMAINE TECHNIQUE TECHNICAL AREA
La présente demande concerne la fabrication de substrats semiconducteurs, et plus particulièrement la fabrication de couches support en carbure de silicium polycristallin pour leur utilisation dans des substrats à hautes performances. The present application relates to the manufacture of semiconductor substrates, and more particularly to the manufacture of polycrystalline silicon carbide support layers for their use in high performance substrates.
ETAT DE LA TECHNIQUE STATE OF THE ART
Dans le domaine de l’électronique de puissance, il est connu d’utiliser des matériaux semiconducteurs à large bande. Ces matériaux présentent une bande interdite plus large que les matériaux semiconducteurs tels que le silicium, ce qui leur confère des propriétés d’isolation électrique entre celles des semiconducteurs et des matériaux isolants. Notamment, les semiconducteurs à large bande présentent l’avantage de tolérer des températures supérieures à celles que sont capables de supporter les semiconducteurs classiques. En outre, ces matériaux présentent une densité de puissance accrue par rapport aux semiconducteurs classiques, permettant des gains de volume et de masse dans les systèmes électroniques les comprenant. In the field of power electronics, it is known to use wideband semiconductor materials. These materials have a wider band gap than semiconductor materials such as silicon, which gives them electrical insulation properties between those of semiconductors and insulating materials. In particular, wideband semiconductors have the advantage of tolerating temperatures higher than those that conventional semiconductors are capable of withstanding. In addition, these materials have an increased power density compared to conventional semiconductors, allowing volume and mass gains in the electronic systems comprising them.
Un matériau semiconducteur à large bande fréquemment utilisé est le carbure de silicium (SiC). Pour la réalisation de composants électroniques de puissance, et en particulier de transistors à effet de champ à structure métal-oxyde-semiconducteur (ou MOSFET) il est nécessaire de disposer de substrats en SiC présentant une certaine épaisseur, généralement de l’ordre de 300 micromètres, leur conférant une résistance mécanique qui permet la réalisation de processus frontaux, c’est-à-dire la formation de fonctions électroniques sur le substrat semiconducteur. Les substrats semiconducteurs ainsi obtenus sont ensuite placés sur un support métallique, notamment constitué de cuivre, et qui présente un module de Young et un coefficient d’expansion thermique différents de ceux du substrat semiconducteur. Des contraintes mécaniques peuvent donc être générées dans le substrat semiconducteur lors de cycles thermiques auxquels il est soumis sur le support métallique. Une façon de pallier ce problème est de réduire l’épaisseur de la couche de SiC, ce qui est possible uniquement après la réalisation des processus frontaux. A frequently used broadband semiconductor material is silicon carbide (SiC). For the production of power electronic components, and in particular metal-oxide-semiconductor field-effect transistors (or MOSFETs), it is necessary to have SiC substrates with a certain thickness, generally of the order of 300 micrometers, giving them a mechanical resistance that allows the performance of front-end processes, i.e. the formation of electronic functions on the semiconductor substrate. The semiconductor substrates thus obtained are then placed on a metal support, in particular made of copper, and which has a Young's modulus and a thermal expansion coefficient different from those of the semiconductor substrate. Mechanical stresses can therefore be generated in the semiconductor substrate during thermal cycles to which it is subjected on the metal support. One way to overcome this problem is to reduce the thickness of the SiC layer, which is possible only after the front-end processes have been performed.
À cet effet, on peut former un substrat de SiC d’une épaisseur donnée, proche de 300 micromètres, avant de graver mécaniquement une partie de celui-ci afin de réduire son épaisseur, et donc de réduire les contraintes mécaniques imposées au support métallique ou aux éventuelles soudures entre celui-ci et le substrat de SiC durant l’utilisation et le cyclage thermique du composant électronique. En outre, une telle réduction de l’épaisseur du substrat de SiC permet de réduire la résistance ON et la résistance thermique de celui-ci, permettant de meilleures performances électriques, et permet de rapprocher le module de Young et le coefficient d’expansion thermique du substrat de SiC de ceux du support métallique. For this purpose, a SiC substrate of a given thickness, close to 300 micrometers, can be formed before mechanically etching a part of it in order to reduce its thickness, and therefore to reduce the mechanical constraints imposed on the metal support or on any welds between it and the SiC substrate during use and cycling. thermal resistance of the electronic component. In addition, such a reduction in the thickness of the SiC substrate makes it possible to reduce the ON resistance and thermal resistance thereof, enabling better electrical performance, and makes it possible to bring the Young's modulus and the thermal expansion coefficient of the SiC substrate closer to those of the metal support.
Cependant, la gravure mécanique est relativement chère et difficile à mettre en œuvre du fait de la dureté du SiC, et la partie restante du substrat peut présenter une planéité imparfaite. Il est donc nécessaire d’établir des procédés permettant l’obtention d’un substrat semiconducteur d’épaisseur faible et présentant une planéité régulière, tout en diminuant les coûts et le temps nécessaire à la mise en œuvre de tels procédés. However, mechanical etching is relatively expensive and difficult to implement due to the hardness of SiC, and the remaining part of the substrate may have imperfect flatness. It is therefore necessary to establish processes that allow obtaining a semiconductor substrate of low thickness and having regular flatness, while reducing the costs and time required to implement such processes.
EXPOSE EXPOSED
Un but recherché est de remédier aux inconvénients précités. One aim sought is to remedy the aforementioned drawbacks.
Il est à cet effet proposé, selon un premier aspect, un substrat intermédiaire pour la fabrication d’un substrat semiconducteur, comprenant successivement : a. une première couche semiconductrice, b. une première couche formant barrière thermique, c. un support comprenant une couche d’absorption configurée pour absorber un rayonnement laser dans une gamme de longueur d’onde déterminée, la température de la couche d’absorption augmentant lors de l’absorption, et une zone de séparation adjacente à la couche d’absorption et configurée pour se dégrader thermiquement sous l’effet de l’augmentation de température de la couche d’absorption, de sorte à séparer au moins une partie du support du reste du substrat intermédiaire. For this purpose, according to a first aspect, an intermediate substrate is proposed for manufacturing a semiconductor substrate, successively comprising: a. a first semiconductor layer, b. a first layer forming a thermal barrier, c. a support comprising an absorption layer configured to absorb laser radiation in a determined wavelength range, the temperature of the absorption layer increasing during absorption, and a separation zone adjacent to the absorption layer and configured to thermally degrade under the effect of the increase in temperature of the absorption layer, so as to separate at least part of the support from the rest of the intermediate substrate.
Ainsi, le substrat proposé permet la séparation, après achèvement des processus frontaux, du substrat semiconducteur en deux parties distinctes sans gravure mécanique, de sorte à ne conserver que l’épaisseur voulue de couche semiconductrice avant son intégration au support métallique sans compromettre la planéité de la couche semiconductrice. L’utilisation d’un laser pour diviser le substrat semiconducteur en deux parties, et ainsi isoler l’épaisseur voulue de ce substrat, permet son obtention plus rapidement et à moindre coût que par gravure mécanique. L’utilisation d’une couche barrière thermique permet de limiter la propagation de la chaleur dans le reste du substrat et favorise donc la séparation avec une puissance et/ou une durée d’exposition au laser réduites. Selon un mode de réalisation, le support comprend : a. un ensemble de séparation comprenant : i. la couche d’absorption, et ii. une couche de séparation adjacente à la couche d’absorption et comprenant la zone de séparation, la dégradation de la zone de séparation ayant lieu lorsque la couche d’absorption atteint une température seuil, b. une deuxième couche formant barrière thermique c. une couche support, la deuxième couche formant barrière thermique étant située entre l’ensemble de séparation et la couche support. Thus, the proposed substrate allows the separation, after completion of the front-end processes, of the semiconductor substrate into two distinct parts without mechanical etching, so as to retain only the desired thickness of the semiconductor layer before its integration into the metal support without compromising the flatness of the semiconductor layer. The use of a laser to divide the semiconductor substrate into two parts, and thus isolate the desired thickness of this substrate, allows it to be obtained more quickly and at a lower cost than by mechanical etching. The use of a thermal barrier layer makes it possible to limit the propagation of heat in the rest of the substrate and therefore promotes separation with reduced power and/or laser exposure time. According to one embodiment, the support comprises: a. a separation assembly comprising: i. the absorption layer, and ii. a separation layer adjacent to the absorption layer and comprising the separation zone, the degradation of the separation zone occurring when the absorption layer reaches a threshold temperature, b. a second thermal barrier layer c. a support layer, the second thermal barrier layer being located between the separation assembly and the support layer.
Selon un mode de réalisation, le support comprend : a. la couche d’absorption, et b. une couche support formant en outre une seconde barrière thermique, la zone de séparation étant comprise dans la couche support. According to one embodiment, the support comprises: a. the absorption layer, and b. a support layer further forming a second thermal barrier, the separation zone being included in the support layer.
Selon un mode de réalisation, le substrat comprend en outre une couche germe adaptée pour la croissance de la première couche semiconductrice, la couche germe comprenant préférentiellement du graphite, la première couche semiconductrice étant interposée entre la couche germe et la première couche formant barrière thermique. According to one embodiment, the substrate further comprises a seed layer suitable for growing the first semiconductor layer, the seed layer preferably comprising graphite, the first semiconductor layer being interposed between the seed layer and the first thermal barrier layer.
Selon un mode de réalisation, la couche de séparation est constituée de nitrure de silicium. According to one embodiment, the separation layer is made of silicon nitride.
Selon un mode de réalisation, la couche d’absorption est constituée d’un matériau choisi parmi le carbure de silicium polycristallin de type p-SiC, le nitrure de titane ou le zirconium. According to one embodiment, the absorption layer is made of a material chosen from polycrystalline silicon carbide of the p-SiC type, titanium nitride or zirconium.
Selon un mode de réalisation, le substrat comprend en outre une couche semiconductrice monocristalline, de préférence comprenant du carbure de silicium ou du nitrure de gallium, une première face de la couche semiconductrice monocristalline étant adjacente à la première couche semiconductrice. According to one embodiment, the substrate further comprises a monocrystalline semiconductor layer, preferably comprising silicon carbide or gallium nitride, a first face of the monocrystalline semiconductor layer being adjacent to the first semiconductor layer.
Selon un mode de réalisation, la première couche semiconductrice est constituée d’un matériau semiconducteur à large bande, notamment d’un matériau choisi parmi le carbure de silicium, le nitrure d’aluminium et le nitrure de gallium. Selon un mode de réalisation, la couche support est une deuxième couche semiconductrice de qualité inférieure à la première couche semiconductrice, préférentiellement constituée d’un matériau choisi parmi le carbure de silicium et le nitrure de silicium. According to one embodiment, the first semiconductor layer is made of a broadband semiconductor material, in particular a material chosen from silicon carbide, aluminum nitride and gallium nitride. According to one embodiment, the support layer is a second semiconductor layer of lower quality than the first semiconductor layer, preferably made of a material chosen from silicon carbide and silicon nitride.
Selon un mode de réalisation, la couche support présente une épaisseur comprise entre 100 et 200 nanomètres. According to one embodiment, the support layer has a thickness of between 100 and 200 nanometers.
Selon un mode de réalisation, la première et/ou la deuxième couche formant barrière thermique présente une conductivité thermique inférieure à 25 W/mK, la deuxième couche formant barrière thermique étant de préférence constituée de dioxyde de titane ou de nitrure de silicium. According to one embodiment, the first and/or second thermal barrier layer has a thermal conductivity of less than 25 W/mK, the second thermal barrier layer preferably being made of titanium dioxide or silicon nitride.
Selon un mode de réalisation, le substrat comprend en outre une couche semiconductrice monocristalline disposée sur une région superficielle de la première couche semiconductrice, la première couche semiconductrice étant située entre la première couche formant barrière thermique et la couche semiconductrice monocristalline According to one embodiment, the substrate further comprises a monocrystalline semiconductor layer disposed on a surface region of the first semiconductor layer, the first semiconductor layer being located between the first thermal barrier layer and the monocrystalline semiconductor layer.
Un autre aspect porte sur un procédé de fabrication d’un substrat intermédiaire semiconducteur, comprenant successivement des étapes de : a. croissance d’une première couche électriquement semiconductrice sur une couche germe, b. croissance, sur la première couche semiconductrice, d’une première couche formant barrière thermique, c. croissance, sur la première couche formant barrière thermique, d’un support comprenant une couche d’absorption configurée pour absorber un rayonnement laser dans une gamme de longueur d’onde déterminée, la température de la couche d’absorption augmentant lors de l’absorption, le support comprenant en outre une zone de séparation adjacente à la couche d’absorption et configurée pour se dégrader thermiquement sous l’effet de l’augmentation de température de la couche d’absorption, de sorte à séparer au moins une partie du support du reste du substrat intermédiaire, d. retrait de la couche germe, les étapes de croissance étant obtenues notamment par dépôt en phase gazeuse sur les couches précédemment formées. Selon une mise en œuvre du procédé, la croissance du support comprend des étapes successives de : a. croissance d’un ensemble de séparation constitué de la couche d’absorption et d’une couche de séparation, la croissance de l’ensemble de séparation comprenant : la croissance de la couche d’absorption la croissance de la couche de séparation, la couche de séparation comprenant la zone de séparation, la zone de séparation étant adjacente à la couche d’absorption, b. croissance, sur l’ensemble de séparation, d’une deuxième couche formant barrière thermique : c. croissance, sur la deuxième couche formant barrière thermique, d’une couche support, les étapes de croissance étant obtenues notamment par dépôt en phase gazeuse sur les couches précédemment formées. Another aspect relates to a method for manufacturing a semiconductor intermediate substrate, successively comprising steps of: a. growing a first electrically semiconductor layer on a seed layer, b. growing, on the first semiconductor layer, a first thermal barrier layer, c. growing, on the first thermal barrier layer, a support comprising an absorption layer configured to absorb laser radiation in a determined wavelength range, the temperature of the absorption layer increasing during absorption, the support further comprising a separation zone adjacent to the absorption layer and configured to thermally degrade under the effect of the increase in temperature of the absorption layer, so as to separate at least part of the support from the rest of the intermediate substrate, d. removing the seed layer, the growth steps being obtained in particular by gas phase deposition on the previously formed layers. According to one implementation of the method, the growth of the support comprises successive steps of: a. growth of a separation assembly consisting of the absorption layer and a separation layer, the growth of the separation assembly comprising: the growth of the absorption layer the growth of the separation layer, the separation layer comprising the separation zone, the separation zone being adjacent to the absorption layer, b. growth, on the separation assembly, of a second layer forming a thermal barrier: c. growth, on the second layer forming a thermal barrier, of a support layer, the growth steps being obtained in particular by gas phase deposition on the previously formed layers.
Selon une mise en œuvre du procédé, la croissance du support comprenant des étapes successives de : a. croissance, sur la première couche formant barrière thermique, de la couche d’absorption b. croissance, sur la couche d’absorption, d’une couche support agissant en outre comme seconde barrière thermique, la zone de séparation étant comprise dans la couche support, les étapes de croissance étant obtenues notamment par dépôt en phase gazeuse sur les couches précédemment formées. According to one implementation of the method, the growth of the support comprising successive steps of: a. growth, on the first layer forming a thermal barrier, of the absorption layer b. growth, on the absorption layer, of a support layer also acting as a second thermal barrier, the separation zone being included in the support layer, the growth steps being obtained in particular by gas phase deposition on the previously formed layers.
Un autre aspect porte sur un procédé de fabrication d’un substrat comprenant une couche semiconductrice monocristalline sur un substrat semiconducteur polycristallin, comprenant la mise en œuvre du procédé de fabrication d’un substrat semiconducteur intermédiaire tel que défini précédemment, la première couche semiconductrice étant polycristalline, et comprenant en outre des étapes successives de : a. formation d’une zone de fragilisation dans un substrat donneur semiconducteur par implantation d’espèces, de sorte délimiter une couche semiconductrice monocristalline à transférer, b. collage de la couche semiconductrice monocristalline à transférer sur une région superficielle de la première couche semiconductrice, c. détachement du substrat donneur le long de la zone de fragilisation pour transférer la couche semiconductrice monocristalline sur la première couche semiconductrice. Another aspect relates to a method of manufacturing a substrate comprising a monocrystalline semiconductor layer on a polycrystalline semiconductor substrate, comprising implementing the method of manufacturing an intermediate semiconductor substrate as defined above, the first semiconductor layer being polycrystalline, and further comprising successive steps of: a. forming a weakening zone in a semiconductor donor substrate by implantation of species, so as to delimit a monocrystalline semiconductor layer to be transferred, b. bonding the monocrystalline semiconductor layer to be transferred to a surface region of the first semiconductor layer, c. detaching the donor substrate along the weakening zone to transfer the monocrystalline semiconductor layer to the first semiconductor layer.
Un autre aspect porte sur un procédé de fabrication d’un composant électronique, comprenant des étapes successives de : a. Mise en œuvre du procédé de fabrication d’un substrat tel que défini précédemment, b. Réalisation de processus frontaux dans la couche semiconductrice monocristalline pour former ledit composant électronique. Another aspect relates to a method of manufacturing an electronic component, comprising successive steps of: a. Implementing the method of manufacturing a substrate as defined above, b. Carrying out front-end processes in the monocrystalline semiconductor layer to form said electronic component.
Selon une mise en œuvre, le procédé comprend, postérieurement à la réalisation desdits processus frontaux, une étape d’application d’un rayonnement laser dans la gamme de longueur d’onde déterminée au substrat intermédiaire, de sorte à dégrader thermiquement la zone de séparation et à séparer au moins une partie du support du reste du substrat intermédiaire. According to one implementation, the method comprises, after carrying out said frontal processes, a step of applying laser radiation in the determined wavelength range to the intermediate substrate, so as to thermally degrade the separation zone and to separate at least part of the support from the rest of the intermediate substrate.
Selon une mise en œuvre, le procédé comprend, postérieurement à l’application du rayonnement laser, une étape de retrait de couches résiduelles situées sur une face de la première couche semiconductrice opposée à la couche semiconductrice monocristalline, les couches résiduelles étant issues de l’étape d’application du rayonnement laser. According to one implementation, the method comprises, after the application of the laser radiation, a step of removing residual layers located on a face of the first semiconductor layer opposite the monocrystalline semiconductor layer, the residual layers resulting from the step of applying the laser radiation.
Un autre aspect porte sur un substrat intermédiaire pour la fabrication d’un substrat semiconducteur, comprenant successivement : Another aspect relates to an intermediate substrate for the manufacture of a semiconductor substrate, successively comprising:
Une première couche semiconductrice constituée de carbure de silicium polycristallin (pSiC), A first semiconductor layer made of polycrystalline silicon carbide (pSiC),
Une première couche formant barrière thermique, constituée de dioxyde de titane (TiO2), A first layer forming a thermal barrier, made of titanium dioxide (TiO 2 ),
Une couche d’absorption, constituée de carbure de silicium polycristallin de type 3C (3C-pSiC), An absorption layer, made of 3C-type polycrystalline silicon carbide (3C-pSiC),
Une couche de séparation, constituée de nitrure de silicium (Sisl^ ), A separation layer, made of silicon nitride (Sisl^ ),
Une deuxième couche formant barrière thermique, constituée de dioxyde de titane (TiO2), Une couche support, constituée de carbure de silicium polycristallin de type 4H (4H- pSiC) A second layer forming a thermal barrier, made of titanium dioxide (TiO 2 ), A support layer, consisting of polycrystalline silicon carbide type 4H (4H-pSiC)
Un autre aspect porte sur un substrat intermédiaire pour la fabrication d’un substrat semiconducteur, comprenant successivement : Another aspect relates to an intermediate substrate for the manufacture of a semiconductor substrate, successively comprising:
Une première couche semiconductrice constituée de carbure de silicium polycristallin (pSiC), A first semiconductor layer made of polycrystalline silicon carbide (pSiC),
Une première couche formant barrière thermique, constituée de dioxyde de titane (TiO2), A first layer forming a thermal barrier, made of titanium dioxide (TiO 2 ),
Une couche d’absorption, constituée de nitrure de titane (TiN), An absorption layer, made of titanium nitride (TiN),
Une couche de séparation, constituée de nitrure de silicium (Sisl^ ), A separation layer, made of silicon nitride (Sisl^ ),
Une deuxième couche formant barrière thermique, constituée de dioxyde de titane (TiO2), A second layer forming a thermal barrier, made of titanium dioxide (TiO 2 ),
Une couche support, constituée de carbure de silicium polycristallin de type 4H (4H- pSiC). A support layer, made of polycrystalline silicon carbide type 4H (4H-pSiC).
DESCRIPTION DES FIGURES DESCRIPTION OF FIGURES
D’autres caractéristiques, buts et avantages ressortiront de la description qui suit, qui est purement illustrative et non limitative, et qui doit être lue en regard des dessins. Other features, purposes and advantages will emerge from the following description, which is purely illustrative and not limiting, and which must be read in conjunction with the drawings.
Les [Fig. 1], [Fig. 2], [Fig. 3] et [Fig. 4] illustrent de façon schématique des substrats intermédiaires pour la fabrication d’un substrat semiconducteur, selon différents modes de réalisation d’un premier aspect ; [Fig. 1], [Fig. 2], [Fig. 3] and [Fig. 4] schematically illustrate intermediate substrates for the manufacture of a semiconductor substrate, according to different embodiments of a first aspect;
Les [Fig. 5], [Fig. 6], [Fig. 7] illustrent des procédés de fabrication d’un substrat intermédiaire pour la fabrication ultérieure d’un substrat semiconducteur, selon différents modes de réalisation d’un deuxième aspect, [Fig. 5], [Fig. 6], [Fig. 7] illustrate methods of manufacturing an intermediate substrate for subsequent manufacturing of a semiconductor substrate, according to different embodiments of a second aspect,
La figure 8 illustre un procédé de fabrication d’un substrat comprenant une couche semiconductrice monocristalline sur un substrat semiconducteur polycristallin, selon un troisième aspect. Figure 8 illustrates a method of manufacturing a substrate comprising a monocrystalline semiconductor layer on a polycrystalline semiconductor substrate, according to a third aspect.
La figure 9 illustre un procédé de fabrication d’un composant électronique, selon un quatrième aspect. Les [Fig. 10], [Fig. 11], [Fig. 12] représentent des résultats d’une simulation de l’évolution de température d’un substrat intermédiaire lors de l’application d’un rayonnement laser. Figure 9 illustrates a method of manufacturing an electronic component, according to a fourth aspect. [Fig. 10], [Fig. 11], [Fig. 12] represent results of a simulation of the temperature evolution of an intermediate substrate during the application of laser radiation.
Sur l’ensemble des figures, les éléments similaires portent des références identiques. In all figures, similar elements bear identical references.
DESCRIPTION DETAILLEE DE MODES DE REALISATION DETAILED DESCRIPTION OF EMBODIMENTS
Selon un premier aspect, un substrat intermédiaire 10 est représenté à la figure 1. Il comprend un agencement de couches, qui peuvent être formées successivement à partir d’une couche germe 1 de graphite. La formation des différentes couches du substrat intermédiaire 10 peut faire intervenir l’injection successive de gaz qui permettent de réaliser des dépôts par condensation. According to a first aspect, an intermediate substrate 10 is shown in FIG. 1. It comprises an arrangement of layers, which can be formed successively from a seed layer 1 of graphite. The formation of the different layers of the intermediate substrate 10 can involve the successive injection of gases which make it possible to produce deposits by condensation.
La première couche formée est une première couche semiconductrice 2 dite « de haute qualité », qui est configurée pour supporter une couche à partir de laquelle des composants seront formés, notamment en vue de fabriquer des composants électroniques de puissance. La première couche semiconductrice 2 est prévue pour subsister dans le composant électronique final. La première couche semiconductrice 2 peut être une couche de carbure de silicium polycristallin, notamment de type 4H ou 3C (également appelé p-pSiC). Alternativement, et selon les applications, elle peut être constituée de carbure de silicium monocristallin de type 4H. La première couche semiconductrice 2 peut également être constituée d’un autre matériau semiconducteur à large bande, tel que le nitrure d’aluminium (AIN) ou le nitrure de gallium (GaN). The first layer formed is a first semiconductor layer 2 called “high quality”, which is configured to support a layer from which components will be formed, in particular with a view to manufacturing power electronic components. The first semiconductor layer 2 is intended to remain in the final electronic component. The first semiconductor layer 2 may be a layer of polycrystalline silicon carbide, in particular of type 4H or 3C (also called p-pSiC). Alternatively, and depending on the applications, it may be made of monocrystalline silicon carbide of type 4H. The first semiconductor layer 2 may also be made of another broadband semiconductor material, such as aluminum nitride (AIN) or gallium nitride (GaN).
Dans certains modes de réalisation, la première couche semiconductrice 2 est, en outre, configurée pour conduire un courant électrique. En particulier, la première couche semiconductrice 2 est dopée. In some embodiments, the first semiconductor layer 2 is further configured to conduct an electric current. In particular, the first semiconductor layer 2 is doped.
Lorsque la première couche semiconductrice 2 est constituée de carbure de silicium, elle peut être hautement dopée à l’azote (dopage N++). On peut également envisager un dopage de type N au phosphore ou un dopage de type P au gallium ou à l’aluminium. Ce dopage permet de conférer à la première couche semiconductrice 2 une résistivité électrique très faible, ainsi qu’une haute conductivité thermique, proche de celle du carbure de silicium massif. Lorsque la première couche semiconductrice 2 est en revanche formée d’autres matériaux, d’autres formes de dopages sont envisageables : par exemple, pour une première couche semiconductrice 2 constituée de nitrure de gallium (GaN), on peut utiliser un dopage au silicium ou au magnésium. Afin de minimiser la résistance électrique de cette première couche semiconductrice 2, il est souhaitable qu’elle présente une épaisseur comprise entre 10 et 300 pm, de préférence inférieure à 100pm. Cependant, il est nécessaire que le substrat semiconducteur intermédiaire présente une tenue mécanique suffisante pour supporter les processus frontaux qui lui seront appliqués. À cet effet, le substrat intermédiaire 10 comprend un support 13 dont l’épaisseur est configurée pour conférer au substrat 10 une résistance mécanique donnée, par exemple comprise entre environ 100 et 400 pm. When the first semiconductor layer 2 is made of silicon carbide, it can be highly doped with nitrogen (N++ doping). It is also possible to envisage N-type doping with phosphorus or P-type doping with gallium or aluminium. This doping makes it possible to give the first semiconductor layer 2 a very low electrical resistivity, as well as a high thermal conductivity, close to that of bulk silicon carbide. When the first semiconductor layer 2 is, on the other hand, formed of other materials, other forms of doping are conceivable: for example, for a first semiconductor layer 2 made of gallium nitride (GaN), silicon or magnesium doping can be used. In order to minimise the electrical resistance of this first semiconductor layer 2, it is desirable for it to have a thickness of between 10 and 300 pm, preferably less than 100 pm. However, it is necessary for the intermediate semiconductor substrate to have sufficient mechanical strength to support the front-end processes that will be applied to it. For this purpose, the intermediate substrate 10 comprises a support 13 whose thickness is configured to give the substrate 10 a given mechanical strength, for example between approximately 100 and 400 pm.
Selon des variantes envisageables, la première couche semiconductrice 2 est également susceptible d’être non-dopée, voire d’être électriquement isolante (par exemple, dans le cas d’une couche de carbure de silicium, par un dopage au vanadium). According to possible variants, the first semiconductor layer 2 is also likely to be undoped, or even to be electrically insulating (for example, in the case of a silicon carbide layer, by vanadium doping).
Le support 13 comprend une couche d’absorption 3 ainsi qu’une zone de séparation 8 qui lui est adjacente. La couche d’absorption 3 est configurée pour absorber un rayonnement laser dans une gamme de longueur d’onde déterminée, pour que sa température augmente. The support 13 comprises an absorption layer 3 and a separation zone 8 adjacent thereto. The absorption layer 3 is configured to absorb laser radiation in a determined wavelength range, so that its temperature increases.
La gamme de longueur d’ondes pour le rayonnement laser est choisie de sorte que la couche germe 1 et la première couche formant barrière thermique 5 (décrite plus bas) soient sensiblement transparentes à ce rayonnement, afin d’assurer qu’une partie suffisante du rayonnement atteigne la couche d’absorption 3, et afin d’éviter l’endommagement de ces couches par le rayonnement. The wavelength range for the laser radiation is chosen so that the seed layer 1 and the first thermal barrier layer 5 (described below) are substantially transparent to this radiation, in order to ensure that a sufficient portion of the radiation reaches the absorption layer 3, and in order to avoid damage to these layers by the radiation.
Sous l’effet de l’augmentation de température causée par l’absorption du rayonnement laser par la couche d’absorption 3, la zone de séparation 8 se dégrade, permettant ainsi la séparation du substrat intermédiaire 10 en deux parties. On peut ainsi fabriquer le substrat intermédiaire puis réaliser les processus frontaux à partir de la couche semiconductrice 2, l’épaisseur totale du substrat intermédiaire 10 lui conférant une résistance mécanique suffisante pour ne pas être endommagé par ces processus, et enfin appliquer un laser dans la gamme de longueur d’onde déterminée de façon à séparer une partie fine du substrat qui comprend la première couche semiconductrice 2 du reste du substrat 10, sans avoir recours à un polissage ou meulage mécanique qui pourrait endommager la première couche semiconductrice 2 et qui serait plus long et plus coûteux à mettre en œuvre. Under the effect of the temperature increase caused by the absorption of the laser radiation by the absorption layer 3, the separation zone 8 degrades, thus allowing the separation of the intermediate substrate 10 into two parts. It is thus possible to manufacture the intermediate substrate and then carry out the front processes from the semiconductor layer 2, the total thickness of the intermediate substrate 10 giving it sufficient mechanical strength to not be damaged by these processes, and finally apply a laser in the determined wavelength range so as to separate a thin part of the substrate which comprises the first semiconductor layer 2 from the rest of the substrate 10, without resorting to mechanical polishing or grinding which could damage the first semiconductor layer 2 and which would be longer and more expensive to implement.
La couche d’absorption 3 peut être constituée d’un matériau choisi parmi le carbure de silicium polycristallin de type p-SiC, le nitrure de titane (TiN) ou le zirconium (Zr). Lorsqu’elle est constituée de p-SiC, la couche d’absorption 3 peut être configurée pour absorber un rayonnement laser dont la longueur d’onde est comprise entre 380 et 410 nanomètres. Le nitrure de titane présente l’avantage de pouvoir absorber une gamme plus large de longueur d’ondes de rayonnement, de sorte que lorsque la couche d’absorption est constituée de ce matériau, elle peut être configurée pour absorber un rayonnement laser dont la longueur d’onde est comprise entre 380 nanomètres et 1 .7 micromètres. Le carbure de silicium présente quant à lui l’avantage d’être un matériau qui peut être utilisé pour la fabrication de la première couche semiconductrice 2, et donc de n’introduire aucun nouvel élément chimique lors de la fabrication du substrat intermédiaire 10. The absorption layer 3 may be made of a material selected from polycrystalline silicon carbide of the p-SiC type, titanium nitride (TiN) or zirconium (Zr). When it is made of p-SiC, the absorption layer 3 may be configured to absorb laser radiation whose wavelength is between 380 and 410 nanometers. Titanium nitride has the advantage of being able to absorb a wider range of radiation wavelengths, such that when the absorption layer is made of this material, it can be configured to absorb laser radiation whose wavelength is between 380 nanometers and 1.7 micrometers. Silicon carbide has the advantage of being a material that can be used for the manufacture of the first semiconductor layer 2, and therefore not to introduce any new chemical element during the manufacture of the intermediate substrate 10.
Le substrat intermédiaire comprend en outre, intercalée entre la première couche semiconductrice 2 et le support 13, une première couche formant barrière thermique 5. Cette couche est configurée pour former barrière à la conduction thermique entre la couche d’absorption 3 et la première couche semiconductrice 2, de sorte à limiter autant que possible une augmentation de température de la première couche semiconductrice. En effet, la première couche formant barrière thermique 5 est configurée pour présenter une conductivité thermique plus faible que celle de la première couche semiconductrice 2, et la première couche semiconductrice 2 subirait donc une augmentation de sa température en l’absence de la première couche formant barrière thermique 5. Malgré ceci, la première couche semiconductrice 2 doit présenter un coefficient d’absorption faible sur la gamme de longueur d’onde prévue pour le rayonnement laser, par exemple de longueur d’onde comprise entre 380 et 410 nanomètres, de façon à ce qu’elle n’absorbe pas le rayonnement prévu pour chauffer la couche d’absorption 3. The intermediate substrate further comprises, interposed between the first semiconductor layer 2 and the support 13, a first thermal barrier layer 5. This layer is configured to form a barrier to thermal conduction between the absorption layer 3 and the first semiconductor layer 2, so as to limit as much as possible an increase in temperature of the first semiconductor layer. Indeed, the first thermal barrier layer 5 is configured to have a lower thermal conductivity than that of the first semiconductor layer 2, and the first semiconductor layer 2 would therefore undergo an increase in its temperature in the absence of the first thermal barrier layer 5. Despite this, the first semiconductor layer 2 must have a low absorption coefficient over the wavelength range intended for the laser radiation, for example of a wavelength between 380 and 410 nanometers, so that it does not absorb the radiation intended to heat the absorption layer 3.
Selon un mode de réalisation, illustré à la figure 2, le support 13 comprend un ensemble de séparation 12 comprenant, d’une part, la couche d’absorption 3, et d’autre part une couche de séparation dite sacrificielle 4 adjacente à la couche d’absorption et comprenant la zone de séparation 8. La couche de séparation 4 est configurée pour que la dégradation de la zone de séparation 8 ait lieu lorsque la couche d’absorption 3 atteint une température seuil, de façon à pouvoir contrôler précisément la séparation du substrat intermédiaire 10. L’ensemble de séparation 12 est disposé entre la première couche 5 formant barrière thermique et une deuxième couche 6 formant barrière thermique. Enfin, la deuxième couche formant barrière thermique 6 est adjacente, sur son côté opposé à l’ensemble de séparation, à une couche support 7. Les deux barrières thermiques 5, 6 permettent de confiner l’élévation de température à l’ensemble de séparation de sorte que seul l’ensemble de séparation subisse une augmentation de température significative, permettant la séparation du substrat en deux parties le long de la zone de séparation 8 sans dégradation du reste du substrat 10. According to one embodiment, illustrated in FIG. 2, the support 13 comprises a separation assembly 12 comprising, on the one hand, the absorption layer 3, and on the other hand a so-called sacrificial separation layer 4 adjacent to the absorption layer and comprising the separation zone 8. The separation layer 4 is configured so that the degradation of the separation zone 8 takes place when the absorption layer 3 reaches a threshold temperature, so as to be able to precisely control the separation of the intermediate substrate 10. The separation assembly 12 is arranged between the first layer 5 forming a thermal barrier and a second layer 6 forming a thermal barrier. Finally, the second thermal barrier layer 6 is adjacent, on its side opposite the separation assembly, to a support layer 7. The two thermal barriers 5, 6 make it possible to confine the temperature rise to the separation assembly so that only the separation assembly undergoes a significant temperature increase, allowing the separation of the substrate into two parts along the separation zone 8 without degradation of the rest of the substrate 10.
Lorsque le coefficient d’absorption de la couche d’absorption 3 et de la couche de séparation 4 aux longueurs d’onde prévues pour le rayonnement laser le permettent, la couche d’absorption 3 peut être disposée, au sein de l’ensemble de séparation 12, plus proche de la première couche formant barrière thermique 5 - tel que représenté sur la figure 2 - ou, alternativement, la couche de séparation 4 peut être disposée plus proche de la première couche formant barrière thermique 5. En d’autres termes, les coefficients d’absorption de la couche d’absorption 3 et de la couche de séparation 4 doivent permettre réchauffement de la couche d’absorption 3 et la dégradation de la zone de séparation 8 de la couche de séparationWhen the absorption coefficient of the absorption layer 3 and the separation layer 4 at the wavelengths intended for the laser radiation permit it, the absorption layer 3 may be arranged, within the separation assembly 12, closer to the first thermal barrier layer 5 - as shown in FIG. 2 - or, alternatively, the separation layer 4 may be arranged closer to the first thermal barrier layer 5. In other words, the absorption coefficients of the absorption layer 3 and the separation layer 4 must allow heating of the absorption layer 3 and degradation of separation zone 8 of the separation layer
4 selon la disposition choisie pour ces deux couches 3, 4 dans l’ensemble de séparation 12. 4 according to the arrangement chosen for these two layers 3, 4 in the separation assembly 12.
La gamme de longueur d’ondes pour le rayonnement laser est choisie de sorte que la deuxième couche formant barrière thermique 6 et la couche support 7 soient sensiblement transparentes à ce rayonnement, afin d’éviter l’endommagement de ces couches par le rayonnement. The wavelength range for the laser radiation is chosen so that the second thermal barrier layer 6 and the support layer 7 are substantially transparent to this radiation, in order to avoid damage to these layers by the radiation.
La couche de séparation 4 est avantageusement très fine, par exemple de moins de 100 micromètres d’épaisseur, de sorte à ne pas fragiliser le substrat intermédiaire avant séparation. Le fait de prévoir une couche de séparation 4 mince permet également de limiter le coût de fabrication de cette couche. Il n’est pas nécessaire de prévoir une couche de séparation 4 épaisse car celle-ci n’a pas pour fonction de contribuer à la tenue mécanique du substrat. Elle peut être constituée de nitrure de silicium (de formule SisN^. The separation layer 4 is advantageously very thin, for example less than 100 micrometers thick, so as not to weaken the intermediate substrate before separation. Providing a thin separation layer 4 also makes it possible to limit the manufacturing cost of this layer. It is not necessary to provide a thick separation layer 4 because the latter does not have the function of contributing to the mechanical strength of the substrate. It can be made of silicon nitride (of formula SisN^.
Les couches formant barrière thermique 5, 6 peuvent présenter une conductivité thermique inférieure à 25 W/mK, de préférence inférieure à 10 W/mK. Elles peuvent notamment être constituées de dioxyde de titane (TiCh), ou de nitrure de silicium (SisN^. The thermal barrier layers 5, 6 may have a thermal conductivity of less than 25 W/mK, preferably less than 10 W/mK. They may in particular be made of titanium dioxide (TiCh), or silicon nitride (SisN^.
La couche support 7 a pour principale fonction d’augmenter l’épaisseur du substrat intermédiaire 10 de façon à lui conférer une résistance mécanique adéquate pour la réalisation des processus frontaux. Notamment, les propriétés semiconductrices de cette couche n’importent pas. Il est donc avantageux de minimiser le coût de cette couche autant que possible. La couche support 7 est donc de préférence de qualité inférieure à celle de la première couche semiconductrice 2 : la résistivité thermique et la résistivité électrique de la couche support 7 sont, notamment, supérieures à celles de la première couche semiconductrice 2. Par exemple, la première couche semiconductrice 2 présente une résistivité électrique inférieure à 5 mû/cm tandis que la couche support 7 présente une résistivité électrique supérieure à 5 mQ/cm. The main function of the support layer 7 is to increase the thickness of the intermediate substrate 10 so as to give it adequate mechanical strength for carrying out the front-end processes. In particular, the semiconductor properties of this layer are not important. It is therefore advantageous to minimize the cost of this layer as much as possible. The support layer 7 is therefore preferably of lower quality than that of the first semiconductor layer 2: the thermal resistivity and the electrical resistivity of the support layer 7 are, in particular, higher than those of the first semiconductor layer 2. For example, the first semiconductor layer 2 has an electrical resistivity of less than 5 mΩ/cm while the support layer 7 has an electrical resistivity of greater than 5 mΩ/cm.
La couche support 7 peut être constituée de carbure de silicium polycristallin de type 4H- SiC, ou de nitrure de silicium (SisN^. Elle peut présenter une épaisseur comprise entre 100 et 200 nanomètres. En outre, et comme la première couche semiconductrice 2, il est avantageux que la couche support 7 présente un coefficient d’absorption faible sur la gamme de longueur d’onde prévue pour le rayonnement laser, de façon à ce qu’elle n’absorbe pas le rayonnement prévu pour chauffer la couche d’absorption 3. The support layer 7 may be made of polycrystalline silicon carbide of the 4H-SiC type, or of silicon nitride (SisN^. It may have a thickness of between 100 and 200 nanometers. Furthermore, and like the first semiconductor layer 2, it is advantageous for the support layer 7 to have a low absorption coefficient over the wavelength range intended for the laser radiation, so that it does not absorb the radiation intended to heat the absorption layer 3.
Un autre mode de réalisation est illustré à la figure 3. Le substrat intermédiaire 10 selon ce mode de réalisation ne comprend pas de deuxième barrière thermique 6. Dans ce cas, la couche support 7 est constituée d’un matériau présentant un faible coefficient d’absorption aux longueurs d’ondes prévues pour le rayonnement laser (ie transparent à la longueur d’onde laser utilisée), ainsi qu’une faible conductivité thermique. Il peut par exemple s’agir de nitrure de silicium (Sisl^ ). La présence d’une deuxième couche formant barrière thermique 6 n’est alors pas nécessaire, car la couche support 7 ne risque pas d’être endommagée par le rayonnement. En outre, le nitrure de silicium présente un coefficient d’expansion thermique sensiblement proche de celui du carbure de silicium polycristallin, de sorte qu’on n’introduit pas de contraintes mécaniques additionnelles, par rapport aux modes de réalisation précédemment décrits,. Ce mode de réalisation présente l’avantage d’être compatible avec le procédé de fabrication de la couche 2 (silicium et azote dans le réacteur de dépôt) et de simplifier l’empilement de couches par rapport aux modes de réalisation précédemment décrits. Another embodiment is illustrated in Figure 3. The intermediate substrate 10 according to this embodiment does not comprise a second thermal barrier 6. In this case, the support layer 7 is made of a material having a low absorption coefficient. at the wavelengths intended for the laser radiation (i.e. transparent to the laser wavelength used), as well as low thermal conductivity. It may for example be silicon nitride (Sisl^ ). The presence of a second layer forming a thermal barrier 6 is then not necessary, since the support layer 7 is not at risk of being damaged by the radiation. In addition, silicon nitride has a coefficient of thermal expansion substantially close to that of polycrystalline silicon carbide, so that no additional mechanical stresses are introduced, compared with the embodiments previously described. This embodiment has the advantage of being compatible with the manufacturing process of layer 2 (silicon and nitrogen in the deposition reactor) and of simplifying the stacking of layers compared with the embodiments previously described.
Selon un mode de réalisation, illustré à la figure 4, le substrat intermédiaire 10 comprend une couche semiconductrice monocristalline 14 dont une première face est adjacente à la première couche semiconductrice 2 sur son côté opposé à la première couche formant barrière thermique 5. La couche semiconductrice monocristalline peut comprendre du carbure de silicium ou du nitrure de gallium (GaN). According to one embodiment, illustrated in FIG. 4, the intermediate substrate 10 comprises a monocrystalline semiconductor layer 14, a first face of which is adjacent to the first semiconductor layer 2 on its side opposite the first thermal barrier layer 5. The monocrystalline semiconductor layer may comprise silicon carbide or gallium nitride (GaN).
Un deuxième aspect porte sur un procédé de fabrication d’un substrat intermédiaire semiconducteur 10 tel que décrit précédemment. Le procédé comprend plusieurs phases de croissance de couches, mises en œuvre préférentiellement par dépôts gazeux successifs sur les couches formées précédemment. D’autres méthodes de dépôt connues de l’homme du métier rentrent cependant dans le cadre de la présente divulgation : par exemple, l’épitaxie en phase liquide, l’épitaxie par jets moléculaires ou la pulvérisation cathodique. Avantageusement, toutes les couches successives peuvent être déposées dans une même enceinte et en utilisant la même méthode de dépôt. A second aspect relates to a method for manufacturing a semiconductor intermediate substrate 10 as described above. The method comprises several layer growth phases, preferably implemented by successive gas depositions on the previously formed layers. Other deposition methods known to those skilled in the art, however, fall within the scope of the present disclosure: for example, liquid phase epitaxy, molecular beam epitaxy or cathode sputtering. Advantageously, all the successive layers can be deposited in the same enclosure and using the same deposition method.
En référence à la figure 5, la première étape 101 consiste à faire croître, sur un support germe 1 , une première couche semiconductrice 2 de haute qualité. Le procédé comprend ensuite la croissance 102 sur cette première couche semiconductrice 2 d’une première couche formant barrière thermique 5, puis la croissance 103 d’un support 13 sur la première couche formant barrière thermique 5. Enfin, une fois ces trois étapes de croissance achevées, le procédé comprend le retrait 104 de la couche germe, notamment par meulage ou polissage mécanique. Le support 13 comprend une couche d’absorption 3 et une zone de séparation 8 qui lui est adjacente. Comme décrit pour le substrat intermédiaire 10 selon le premier aspect, la couche d’absorption 3 est configurée pour absorber un rayonnement lumineux sur une plage de longueur d’ondes données, la température de la couche d’absorption 3 augmentant alors par rayonnement, et la zone de séparation 8 est configurée pour se fragiliser et se dissocier sous l’effet de réchauffement, et ainsi permettre la séparation d’au moins une partie du supportWith reference to FIG. 5, the first step 101 consists in growing, on a seed support 1, a first high-quality semiconductor layer 2. The method then comprises the growth 102 on this first semiconductor layer 2 of a first thermal barrier layer 5, then the growth 103 of a support 13 on the first thermal barrier layer 5. Finally, once these three growth steps have been completed, the method comprises the removal 104 of the seed layer, in particular by mechanical grinding or polishing. The support 13 comprises an absorption layer 3 and a separation zone 8 adjacent thereto. As described for the intermediate substrate 10 according to the first aspect, the absorption layer 3 is configured to absorb light radiation over a given wavelength range, the temperature of the absorption layer 3 then increasing by radiation, and the separation zone 8 is configured to become fragile and dissociate. under the effect of heating, and thus allow the separation of at least part of the support
13 du reste du substrat intermédiaire 10. 13 of the remainder of the intermediate substrate 10.
Selon une mise en œuvre du procédé, représentée à la figure 6, la croissance 103 du support 13 est divisée en une pluralité de sous-étapes successives. Une première sous étape consiste à faire croître un ensemble de séparation 12 comprenant la couche d’absorption 3 ainsi qu’une couche distincte de séparation 4 adjacente, la couche de séparation 4 comprenant la zone de séparation 8, la couche de séparation 4 étant configurée pour que la zone de séparation 8 se dégrade lorsque la couche d’absorption 3 atteint une température seuil. Cette première sous étape comprend la croissance 1031 de la couche d’absorption 3, puis la croissance 1032 de la couche de séparation 4. Une deuxième sous étape 1033 comprend la croissance 1033, sur l’ensemble de séparation 12 ainsi formé, d’une deuxième couche formant barrière thermique 6, permettant ainsi de contenir l’augmentation de température par irradiation entre les deux couches formant barrière thermique 5, 6, c’est-à- dire au niveau de l’ensemble de séparation 12, et donc sans compromettre la qualité de la première couche semiconductrice 2. Enfin, l’étape de croissance 103 du support 13 comprend une troisième sous-étape 1034 de croissance d’une couche support 7 configurée pour conférer au substrat intermédiaire 10 une épaisseur et une résistance mécanique adaptées à la réalisation de processus frontaux. According to an implementation of the method, shown in FIG. 6, the growth 103 of the support 13 is divided into a plurality of successive sub-steps. A first sub-step consists in growing a separation assembly 12 comprising the absorption layer 3 as well as a separate adjacent separation layer 4, the separation layer 4 comprising the separation zone 8, the separation layer 4 being configured so that the separation zone 8 degrades when the absorption layer 3 reaches a threshold temperature. This first sub-step comprises the growth 1031 of the absorption layer 3, then the growth 1032 of the separation layer 4. A second sub-step 1033 comprises the growth 1033, on the separation assembly 12 thus formed, of a second thermal barrier layer 6, thus making it possible to contain the increase in temperature by irradiation between the two thermal barrier layers 5, 6, i.e. at the level of the separation assembly 12, and therefore without compromising the quality of the first semiconductor layer 2. Finally, the growth step 103 of the support 13 comprises a third sub-step 1034 of growing a support layer 7 configured to give the intermediate substrate 10 a thickness and mechanical strength suitable for carrying out front-end processes.
Selon une mise en œuvre alternative à celle décrite au paragraphe précédent, et illustrée par la figure 7, la croissance 103 du support 13 comprend une première étape de croissance 1031 de la couche d’absorption 3 sur la première couche formant barrière thermique 5, puis une deuxième étape de croissance 1035 d’une couche support 7 qui comprend la zone de séparation 8. Dans ce cas, la couche support 7 est constituée d’un matériau présentant une faible conductivité thermique, et qui est transparent aux longueurs d’ondes prévues pour le rayonnement lumineux appliqué au substrat intermédiaire 10 afin de séparer le substrat 10 le long de la zone de séparation 8. La couche support 7 est de qualité inférieure à la première couche semiconductrice 2. Par exemple, la couche support 7 a été déposée avec une vitesse de croissance supérieure à celle de la première couche semiconductrice 2. According to an alternative implementation to that described in the preceding paragraph, and illustrated by FIG. 7, the growth 103 of the support 13 comprises a first growth step 1031 of the absorption layer 3 on the first thermal barrier layer 5, then a second growth step 1035 of a support layer 7 which comprises the separation zone 8. In this case, the support layer 7 is made of a material having a low thermal conductivity, and which is transparent to the wavelengths intended for the light radiation applied to the intermediate substrate 10 in order to separate the substrate 10 along the separation zone 8. The support layer 7 is of lower quality than the first semiconductor layer 2. For example, the support layer 7 was deposited with a growth speed greater than that of the first semiconductor layer 2.
Un troisième aspect porte sur un procédé de fabrication d’un substrat à haute performance. Ce procédé, illustré à la figure 8, comprend une première étape de mise en œuvre du procédé de fabrication d’un substrat intermédiaire 10 selon le deuxième aspect. Puis, le procédé comprend la formation 109 d’une zone de fragilisation dans un substrat donneur semiconducteur 9 par implantation d’espèces à travers une face du substrat donneur 9 de façon à séparer le substrat donneur en deux parties, une partie définissant une couche semiconductrice monocristalline 14. S’ensuit une étape de collage 110 du substrat donneur 9, au niveau de la couche semiconductrice monocristalline 14, sur une région superficielle de la première couche semiconductrice 2 et une étape de détachement 111 du substrat donneur le long de la zone de fragilisation. On obtient alors un substrat semiconducteur, comprenant une couche semiconductrice monocristalline 14 disposée sur une couche semiconductrice 2, qui peut quant à elle être monocristalline ou polycristalline selon les applications. A third aspect relates to a method for manufacturing a high-performance substrate. This method, illustrated in FIG. 8 , comprises a first step of implementing the method for manufacturing an intermediate substrate 10 according to the second aspect. Then, the method comprises the formation 109 of a weakening zone in a semiconductor donor substrate 9 by implantation of species through a face of the donor substrate 9 so as to separate the donor substrate into two parts, one part defining a monocrystalline semiconductor layer 14. This is followed by a step 110 of bonding the donor substrate 9, at the level of the monocrystalline semiconductor layer 14, on a surface region of the first semiconductor layer 2 and a detachment step 111 of the donor substrate along the weakening zone. A semiconductor substrate is then obtained, comprising a monocrystalline semiconductor layer 14 arranged on a semiconductor layer 2, which can itself be monocrystalline or polycrystalline depending on the applications.
Un quatrième aspect porte sur un procédé de fabrication d’un composant électronique, comme représenté à la figure 9. Ce procédé comprend une première étape de mise en œuvre du procédé de fabrication d’un substrat de type semiconducteur selon le troisième aspect, tel que décrit au paragraphe précédent. Puis, le procédé comprend une étape 112 de réalisation de processus frontaux dans la première couche afin de former le composant électronique. Par processus frontaux, aussi désignés par le terme anglais de processus « front-end », on entend la réalisation de composants individuels - tels que des transistors, résistances, condensateurs ou autres - intégrés dans la couche semiconductrice monocristalline 14 du substrat. A fourth aspect relates to a method for manufacturing an electronic component, as shown in FIG. 9. This method comprises a first step of implementing the method for manufacturing a semiconductor substrate according to the third aspect, as described in the preceding paragraph. Then, the method comprises a step 112 of performing front-end processes in the first layer in order to form the electronic component. Front-end processes, also referred to by the English term “front-end” processes, mean the production of individual components - such as transistors, resistors, capacitors or others - integrated into the monocrystalline semiconductor layer 14 of the substrate.
Selon une mise en œuvre, le procédé peut en outre comprendre, postérieurement à la réalisation 112 des processus frontaux, l’application 113 d’un rayonnement laser dans une gamme de longueur d’onde déterminée au substrat intermédiaire 10, augmentant ainsi la température de la couche d’absorption 4 et permettant la dégradation de la zone de séparation 8 une fois que la température de la couche d’absorption 4 atteint un seuil, et permettant ainsi la séparation d’au moins une partie du support 13 du reste du substrat intermédiaire 10. L’application 113 d’un rayonnement laser peut notamment se faire sur la couche support 7. According to one implementation, the method may further comprise, after the performance 112 of the front-end processes, the application 113 of laser radiation in a determined wavelength range to the intermediate substrate 10, thereby increasing the temperature of the absorption layer 4 and allowing the degradation of the separation zone 8 once the temperature of the absorption layer 4 reaches a threshold, and thus allowing the separation of at least part of the support 13 from the remainder of the intermediate substrate 10. The application 113 of laser radiation may in particular be done on the support layer 7.
Selon une mise en œuvre, et postérieurement à l’application 113 d’un rayonnement laser, le procédé peut en outre comprendre une étape 114 de retrait de couches résiduelles 15 situées sur une face de la première couche semiconductrice 2 opposée à la couche semiconductrice monocristalline. Les couches résiduelles 15 sont issues de l’étape d’application 113 du rayonnement laser, et comprennent notamment la première couche formant barrière thermique 5, et éventuellement la couche d’absorption 3 ainsi qu’une partie de la couche de séparation 4. According to one implementation, and after the application 113 of laser radiation, the method may further comprise a step 114 of removing residual layers 15 located on a face of the first semiconductor layer 2 opposite the monocrystalline semiconductor layer. The residual layers 15 come from the step 113 of applying the laser radiation, and comprise in particular the first thermal barrier layer 5, and possibly the absorption layer 3 as well as a portion of the separation layer 4.
La figure 10 illustre l’évolution de température dans le substrat intermédiaire 10 lors de simulations d’une irradiation du substrat par un rayonnement laser de 50 Watts et de 125 micromètres de diamètre, présentant une longueur d’ondes de 404 nanomètres. Trois courbes I, Il et III sont représentées, correspondant respectivement à une durée d’irradiation de 47,2 millisecondes, 47,9 millisecondes et 50 millisecondes. Le substrat intermédiaire 10 utilisé pour la simulation comprend deux couches formant barrière thermiques 5, 6 distinctes ainsi qu’une couche de séparation 4, et le rayonnement laser est appliqué sur une face libre de la couche support 7 opposée aux autres couches du substrat intermédiaire 10. On voit que la température de la couche d’absorption dépasse les 2000 °C tandis que les températures de la première couche semiconductrice 2 et la couche support 7 s’élèvent à un maximum d’environ 800 °C. Figure 10 illustrates the temperature evolution in the intermediate substrate 10 during simulations of irradiation of the substrate by a laser radiation of 50 Watts and 125 micrometers in diameter, having a wavelength of 404 nanometers. Three curves I, II and III are shown, corresponding respectively to an irradiation duration of 47.2 milliseconds, 47.9 milliseconds and 50 milliseconds. The intermediate substrate 10 used for the simulation comprises two separate thermal barrier layers 5, 6 as well as a separation layer 4, and the laser radiation is applied to a free face of the support layer 7 opposite the other layers of the intermediate substrate 10. It can be seen that the temperature of the absorption layer exceeds 2000 °C while the temperatures of the first semiconductor layer 2 and the support layer 7 rise to a maximum of approximately 800 °C.
La figure 11 représente une évolution de la température maximum dans la couche de séparation 4 en fonction du diamètre du laser utilisé, dans les mêmes conditions de simulation que pour la figure 10. Les trois courbes I, Il et III correspondent respectivement à des durées d’exposition du substrat intermédiaire 10 de 50, 100 et 200 microsecondes. On voit qu’il est nécessaire de prévoir un faible diamètre de rayonnement laser afin d’obtenir une montée de la température dans la couche de séparation 4 qui soit suffisamment élevée. Pour une augmentation de la température dans la couche de séparation 4 au-delà de 2000 °C, un rayonnement laser de moins de 150 micromètres de diamètre est nécessaire dans ces conditions de simulation. Figure 11 shows a change in the maximum temperature in the separation layer 4 as a function of the diameter of the laser used, under the same simulation conditions as for Figure 10. The three curves I, II and III correspond respectively to exposure times of the intermediate substrate 10 of 50, 100 and 200 microseconds. It can be seen that it is necessary to provide a small laser radiation diameter in order to obtain a sufficiently high temperature rise in the separation layer 4. For an increase in the temperature in the separation layer 4 beyond 2000 °C, laser radiation of less than 150 micrometers in diameter is necessary under these simulation conditions.
La figure 12 représente, pour les mêmes conditions de simulation : l’évolution de la température maximale dans la couche de séparation 4, cette dernière étant représentée par les courbes notées I à VI, l’évolution de la température de surface du substrat, représentée par la courbe notée VII pour un rayonnement laser de 125 micromètres de diamètre et pour une durée d’exposition de 200 microsecondes. Figure 12 shows, for the same simulation conditions: the evolution of the maximum temperature in the separation layer 4, the latter being represented by the curves marked I to VI, the evolution of the surface temperature of the substrate, represented by the curve marked VII for laser radiation of 125 micrometers in diameter and for an exposure time of 200 microseconds.
Le diamètre du rayonnement laser peut varier selon plusieurs facteurs, par exemple selon la puissance du laser ou les matériaux présents dans le substrat. Pour les valeurs de température maximale dans la couche de séparation 4, les paramètres du laser utilisé sont répertoriés, pour chaque courbe, dans le tableau 1 ci-dessous. The diameter of the laser beam can vary depending on several factors, for example the laser power or the materials present in the substrate. For the maximum temperature values in the separation layer 4, the parameters of the laser used are listed, for each curve, in Table 1 below.
En ce qui concerne la température de surface du substrat, on voit qu’elle atteint un maximum d’environ 200 °C, bien inférieur aux températures obtenues dans la couche de séparation, ce qui démontre l’efficacité des couches formant barrière thermique 5, 6.As for the surface temperature of the substrate, it is seen that it reaches a maximum of about 200 °C, much lower than the temperatures obtained in the separation layer, which demonstrates the effectiveness of the thermal barrier layers 5, 6.
Les évolutions de la température de surface du substrat observées durant ces simulations pour les autres paramètres (c’est-à-dire les paramètres de simulation correspondant aux courbes I à V), qui ne sont pas représentées sur la figure 12, sont similaires. The evolutions of the substrate surface temperature observed during these simulations for the other parameters (i.e. the simulation parameters corresponding to curves I to V), which are not shown in Figure 12, are similar.
[Tableau 1] [Table 1]
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US20110193124A1 (en) * | 2008-04-14 | 2011-08-11 | Semiconductor Energy Laboratory Co., Ltd. | Deposition Substrate and Method for Manufacturing Light-Emitting Device |
US20120012048A1 (en) * | 2000-11-27 | 2012-01-19 | S.O.I.Tec Silicon On Insulator Technologies | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
US20190244853A1 (en) * | 2018-02-02 | 2019-08-08 | Infineon Technologies Ag | Wafer Composite and Method for Producing a Semiconductor Component |
US20210028348A1 (en) * | 2018-03-29 | 2021-01-28 | Soitec | Method for separating a removable composite structure by means of a light flux |
WO2022074317A1 (en) * | 2020-10-06 | 2022-04-14 | Soitec | Method for producing a substrate for the epitaxial growth of a layer of a gallium-based iii-n alloy |
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US20120012048A1 (en) * | 2000-11-27 | 2012-01-19 | S.O.I.Tec Silicon On Insulator Technologies | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
US20110193124A1 (en) * | 2008-04-14 | 2011-08-11 | Semiconductor Energy Laboratory Co., Ltd. | Deposition Substrate and Method for Manufacturing Light-Emitting Device |
US20190244853A1 (en) * | 2018-02-02 | 2019-08-08 | Infineon Technologies Ag | Wafer Composite and Method for Producing a Semiconductor Component |
US20210028348A1 (en) * | 2018-03-29 | 2021-01-28 | Soitec | Method for separating a removable composite structure by means of a light flux |
WO2022074317A1 (en) * | 2020-10-06 | 2022-04-14 | Soitec | Method for producing a substrate for the epitaxial growth of a layer of a gallium-based iii-n alloy |
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