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WO2025020762A1 - 显示面板及其驱动方法、显示装置 - Google Patents

显示面板及其驱动方法、显示装置 Download PDF

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Publication number
WO2025020762A1
WO2025020762A1 PCT/CN2024/099577 CN2024099577W WO2025020762A1 WO 2025020762 A1 WO2025020762 A1 WO 2025020762A1 CN 2024099577 W CN2024099577 W CN 2024099577W WO 2025020762 A1 WO2025020762 A1 WO 2025020762A1
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WO
WIPO (PCT)
Prior art keywords
transistor
gate
group
control signal
signals
Prior art date
Application number
PCT/CN2024/099577
Other languages
English (en)
French (fr)
Inventor
徐元杰
谢涛峰
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2025020762A1 publication Critical patent/WO2025020762A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/03—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays
    • G09G3/035—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays for flexible display surfaces
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2380/00—Specific applications
    • G09G2380/02—Flexible displays

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display panel and a driving method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the embodiment of the present disclosure provides a display panel, including: multiple gate driving circuits, and multiple sub-pixels arranged in an array, wherein the sub-pixels include a pixel driving circuit and a light-emitting element, and the pixel driving circuit includes multiple transistors, wherein:
  • the multiple gate driving circuits are configured to output multiple gate driving signals to multiple transistors in the pixel driving circuit, wherein each of the gate driving circuits outputs a gate driving signal, and the multiple gate driving signals are divided into at least two groups, the high level voltages of the gate driving signals in the same group are the same, and the low level voltages of the gate driving signals in the same group are the same; the high level voltages of the gate driving signals in different groups are different, and/or the low level voltages of the gate driving signals in different groups are different;
  • the pixel driving circuit is configured to receive the plurality of gate driving signals and The gate driving signal drives the light emitting element to emit light.
  • An embodiment of the present disclosure further provides a display device, comprising a display panel as described in any embodiment of the present disclosure.
  • the present disclosure also provides a method for driving a display panel, including:
  • Control multiple groups of gate driving circuits to output multiple gate driving signals to multiple transistors in a pixel driving circuit wherein the multiple gate driving signals are divided into at least two groups, the high level voltages of the gate driving signals in the same group are the same, and the low level voltages of the gate driving signals in the same group are the same; the high level voltages of the gate driving signals in different groups are different, and/or the low level voltages of the gate driving signals in different groups are different.
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic plan view of a display panel
  • FIG3A is a schematic structural diagram of a pixel driving circuit
  • FIG3B is a schematic diagram of a working process of the pixel driving circuit provided in FIG3A ;
  • FIG4A is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • FIG4B is a schematic diagram of the structure of a display panel in some technologies.
  • FIG5A is a schematic structural diagram of another pixel driving circuit
  • FIG. 5B is a schematic diagram of a working process of the pixel driving circuit provided in FIG. 5A .
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, a drain region, or a drain electrode) and a source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source.
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged.
  • the gate can also be called the control electrode.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.
  • a extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.
  • a extends along direction B means "the main part of A extends along direction B".
  • FIG1 is a schematic diagram of the structure of a display device.
  • the display device may include: a timing controller 21, a data driver 22, a scan drive circuit 23, a light-emitting drive circuit 24, and a sub-pixel array 25.
  • the sub-pixel array 25 may include a plurality of sub-pixels PX arranged regularly.
  • the scan drive circuit 23 may be configured to provide a scan signal to the sub-pixel PX along a scan signal line; the data driver 22 may be configured to provide a data voltage to the sub-pixel PX along a data line; the light-emitting drive circuit 24 may be configured to provide a light-emitting control signal to the sub-pixel PX along a light-emitting control line; the timing controller 21 may be configured to control the scan drive circuit 23, the light-emitting drive circuit 24, and the data driver 22.
  • the timing controller 21 may provide the data driver 22 with a grayscale value and a control signal suitable for the specifications of the data driver 22; the timing controller 21 may provide the scan clock signal, the scan start signal, etc. suitable for the specifications of the scan drive circuit 23 to the scan drive circuit 23; the timing controller 21 may provide the light-emitting clock signal, the light-emitting start signal, etc. suitable for the specifications of the light-emitting drive circuit 24 to the light-emitting drive circuit 24.
  • the data driver 22 may generate a data voltage to be provided to the data lines D1 to Di using the grayscale value and the control signal received from the timing controller 21.
  • the data driver 22 may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data lines D1 to Di in units of sub-pixel rows.
  • the scan drive circuit 23 may generate a scan signal to be provided to the scan lines S1 to Sj using the scan clock signal, the scan start signal, etc. received from the timing controller 21.
  • the scan drive circuit 23 may sequentially provide a scan signal having an on-level pulse.
  • the scan drive circuit 23 may include a shift register, which may generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to a next-level circuit under the control of a scan clock signal.
  • the light-emitting drive circuit 24 may generate a light-emitting control signal to be provided to the light-emitting control lines EM1 to Eo by receiving a light-emitting clock signal, a light-emitting start signal, etc. from the timing controller 21. For example, the light-emitting drive circuit 24 may sequentially provide a light-emitting control signal with an off-level pulse to the light-emitting control line.
  • the light-emitting drive circuit 24 may include a shift register, which generates a light-emitting control signal by sequentially transmitting a light-emitting start signal provided in the form of an off-level pulse to a next-level circuit under the control of a clock signal. Wherein, i, j, and o are all natural numbers.
  • the display device may include a display panel.
  • the sub-pixel array, the scanning drive circuit, and the light-emitting drive circuit may be directly disposed on the display panel.
  • the scanning drive circuit may be disposed on the left frame of the display panel, and the light-emitting drive circuit may be disposed on the right frame of the display panel; or, the scanning drive circuit and the light-emitting drive circuit may be disposed on both the left frame and the right frame of the display panel.
  • the scanning drive circuit and the light-emitting drive circuit may be formed together with the sub-pixels in the process of forming the sub-pixels.
  • the data driver may be disposed on a separate chip or printed circuit board.
  • the data driver may be formed by using a chip on glass, a chip on plastic, a chip on a film, etc., disposed on the lower frame of the display panel to be connected to the driver chip pins.
  • the timing controller may be disposed separately from the data driver or integrally with the data driver. However, this embodiment is not limited to this.
  • FIG2 is a plan view of a display panel.
  • the display panel may include: a display area AA, a binding area B1 located on one side of the display area AA, and a border area B2 located on the other side of the display area AA.
  • the binding area B1 may be, for example, a lower border of the display panel, and the border area B2 may include an upper border, a left border, and a right border of the display panel.
  • the display area AA may be a flat area including a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX are configured to display dynamic pictures or still images.
  • the display area may be referred to as an effective area.
  • the display panel may be a flexible substrate, so that the display panel may be deformable, such as curling, bending, folding, or rolling up.
  • the border area B2 may include a circuit area, a power line area, a crack dam area, and a cutting area arranged in sequence along the direction of the display area AA.
  • the circuit area may be connected to the display area AA, and may include at least a plurality of cascaded gate drive circuits, and the gate drive circuits are electrically connected to a plurality of gate lines in the display area AA.
  • the power line area is connected to the circuit area, and may include at least a low-level power line, and the low-level power line may extend in a direction parallel to the edge of the display area and be connected to the cathode of the display area.
  • the crack dam area may be connected to the power line area, and may include at least a plurality of cracks arranged on the composite insulating layer.
  • the cutting area may be connected to the crack dam area, and may include at least a cutting groove arranged on the composite insulating layer, and the cutting groove It can be configured that after all the film layers of the display panel are prepared, the cutting device can perform cutting along the cutting grooves respectively.
  • a first isolation dam and a second isolation dam may be provided in the binding area B1 and the border area B2.
  • the first isolation dam and the second isolation dam may extend in a direction parallel to an edge of the display area to form an annular structure surrounding the display area AA.
  • the edge of the display area is the edge of the display area close to the binding area B1 or the border area B2.
  • the display area AA may include at least a plurality of sub-pixels PX, a plurality of gate lines Gate, and a plurality of data lines Data.
  • the plurality of gate lines Gate may extend along a first direction X
  • the plurality of data lines Data may extend along a second direction Y.
  • the orthographic projections of the plurality of gate lines Gate and the plurality of data lines Data on the substrate substrate intersect to form a plurality of sub-pixel areas, and a sub-pixel PX is arranged in each sub-pixel area.
  • the plurality of data lines Data are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines Data may be configured to provide data signals to the plurality of sub-pixels PX.
  • the plurality of data lines Data may extend to the binding area B1.
  • the plurality of gate lines Gate are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines Gate may be configured to provide gate control signals to the plurality of sub-pixels PX.
  • the gate control signal may include a scan signal and a light emitting control signal.
  • the first direction X may be an extension direction (row direction) of the gate line Gate in the display area AA
  • the second direction Y may be an extension direction (column direction) of the data line Data in the display area AA.
  • the first direction X and the second direction Y may intersect, and illustratively, the first direction X and the second direction Y may be perpendicular to each other.
  • a pixel unit of display area AA may include three sub-pixels, and the three sub-pixels are respectively a red sub-pixel, a green sub-pixel, and a blue sub-pixel.
  • this embodiment is not limited to this.
  • a pixel unit may include four sub-pixels, and the four sub-pixels are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.
  • the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in parallel horizontally, vertically, or in a square pattern.
  • this embodiment is not limited to this.
  • a sub-pixel may include: a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit.
  • the pixel driving circuit may include multiple transistors and at least one capacitor.
  • the pixel driving circuit may be a 3T1C (i.e., 3 transistors and 1 capacitor) structure, a 7T1C (i.e., 7 transistors and 1 capacitor) structure, a 5T1C (i.e., 5 transistors and 1 capacitor) structure, an 8T1C (i.e., 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., 8 transistors and 2 capacitors) structure, etc.
  • the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc.
  • the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel driving circuit. The color of the light emitted by the light-emitting element may be determined as required.
  • the light-emitting element may include: a first electrode, a second electrode, and an organic light-emitting layer located between the first electrode and the second electrode.
  • the first electrode of the light-emitting element may be electrically connected to the corresponding pixel driving circuit.
  • this embodiment is not limited to this.
  • FIG3A is a schematic diagram of the structure of a pixel driving circuit.
  • FIG3A is illustrated by taking 8T1C as an example.
  • the pixel driving circuit can be connected to 11 signal lines (data line Data, first scan line Gate-P, second scan line Gate-N, first reset line Reset-P, second reset line Reset-H, light emitting control line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, first power line VDD and second power line VSS).
  • the gate line includes: first scan line Gate-P, second scan line Gate-N, first reset line Reset-P, second reset line Reset-H, light emitting control line EM.
  • a control electrode of the first transistor M1 is connected to a first reset line Reset-P, a first electrode of the first transistor M1 is connected to a first initial signal line INIT1, and a second electrode of the first transistor is connected to a third node N3.
  • a control electrode of the second transistor M2 is connected to a second scan line Gate-N, a first electrode of the second transistor M2 is connected to a first node N1, and a second electrode of the second transistor M2 is connected to a third node N3.
  • a control electrode of the third transistor M3 is connected to a first node N1, a first electrode of the third transistor M3 is connected to a second node N2, and a second electrode of the third transistor M3 is connected to a third node N3.
  • a control electrode of the fourth transistor M4 is connected to a first scan line Gate-P, a first electrode of the fourth transistor M4 is connected to a data line Data, and a second electrode of the fourth transistor M4 is connected to a second node N2.
  • a control electrode of the fifth transistor M5 is connected to a light emission control line EM, a first electrode of the fifth transistor M5 is connected to a first power line VDD, and a second electrode of the fifth transistor M5 is connected to a second node N2.
  • the control electrode of the sixth transistor M6 is connected to the light emitting control line EM, the first electrode of the sixth transistor M6 is connected to the third node N3, and the second electrode of the sixth transistor M6 is connected to the fourth node N4.
  • the control electrode of the seventh transistor M7 is connected to the second reset line Reset-H, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor M7 is connected to the fourth node N4.
  • the control electrode of the eighth transistor M8 is connected to the second reset line Reset-H, the first electrode of the eighth transistor M8 is connected to the third initial signal line INIT3, the second electrode of the eighth transistor M8 is connected to the second node N2, the first end of the capacitor C is connected to the first power line VDD, and the second end of the capacitor C is connected to the first node N1.
  • the first electrode of the light emitting device is electrically connected to the fourth node N4, and the second electrode of the light emitting device is electrically connected to the fourth node N4.
  • the electrode is connected to the second power line VSS,
  • the signal of the second power line VSS is a low level signal
  • the signal of the first power line VDD is a continuously provided high level signal
  • the transistor can be divided into an N-type transistor and a P-type transistor.
  • the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages).
  • the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).
  • the first transistor M1 to the eighth transistor M8 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor M1 to the eighth transistor M8 may include a P-type transistor and an N-type transistor.
  • the first transistor M1 to the eighth transistor M8 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide oxide semiconductor
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display panel to form a low-temperature polycrystalline oxide (LTPO) display panel can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • the second transistor M2 may be an N-type transistor
  • the first transistor M1 and the third transistor M3 to the eighth transistor M8 may be P-type transistors.
  • the first transistor M1, the seventh transistor M7 and the eighth transistor M8 can all be called reset transistors
  • the second transistor M2 can be called a compensation transistor
  • the second transistor M3 can be called a driving transistor
  • the fourth transistor M4 can be called a data writing transistor
  • the fifth transistor M5 and the sixth transistor M6 can be called light emitting control transistors.
  • FIG3B is a working process of the pixel driving circuit provided in FIG3A.
  • the working process of the pixel driving circuit may include:
  • the first stage P1 is called the first reset stage.
  • the signal of the second reset line Reset-H is a low-level signal, and the signals of the first reset line Reset-P, the first scan line Gate-P, the second scan line Gate-N and the light-emitting control line EM are high-level signals.
  • the signal of the second reset line Reset-H is a low-level signal, which turns on the seventh transistor M7 and the eighth transistor M8.
  • the signal of the second initial signal line INIT2 is provided to the fourth node N4, and the first electrode of the light-emitting device L is initialized (reset), and the original charge in the first electrode of the light-emitting device L is cleared.
  • the signal of the third initial signal line INIT3 is provided to the second node N2, and the second node N2 is initialized (reset), and the original charge in the second node N2 is cleared.
  • the third transistor M3 is turned on.
  • the signal of the second scan line Gate-N is a high-level signal, and the second transistor M2 is turned on.
  • the signal of the second node N2 is provided to the first node N1 and the third node N3, the first node N1 and the third node N3 are initialized, the signals of the first reset line Reset-P, the first scan line Gate-P and the light emitting control line EM are high level signals, and the first transistor M1, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are turned off.
  • the light emitting device L does not emit light.
  • the second stage P2 is called the second reset stage.
  • the signal of the first reset line Reset-P is a low-level signal, and the signals of the second reset line Reset-H, the first scan line Gate-P, the second scan line Gate-N and the light-emitting control line EM are high-level signals.
  • the signal of the first reset line Reset-P is a low-level signal, so that the first transistor M1 and the signal of the first initial signal line INIT1 are provided to the third node N3, and the third node N3 is initialized (reset) again, and the original charge in the third node N3 is cleared. In this stage, the third transistor M3 is continuously turned on.
  • the signal of the second scan line Gate-N is a high-level signal, and the second transistor M2 is turned on.
  • the third node N3 is provided to the first node N1, and the first node N1 is continuously initialized.
  • the signals of the second reset line Reset-H, the first scan line Gate-P and the light-emitting control line EM are high-level signals, and the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are turned off. In this stage, the light-emitting device L does not emit light.
  • the third stage P3 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scan line Gate-P is a low-level signal, and the signals of the first reset line Reset-P, the second reset line Reset-H, the second scan line Gate-N and the light-emitting control line EM are high-level signals.
  • the data line Data outputs a data voltage.
  • the third transistor M3 is continuously turned on.
  • the signal of the first scan line Gate-P is a low-level signal, which turns on the fourth transistor M4.
  • the signal of the second scan line Gate-N is a high-level signal, and the second transistor M2 is turned on.
  • the data voltage output by the data line Data is provided to the first node N1 through the turned-on fourth transistor M4, the second node N2, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2, and the difference between the data voltage output by the data line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C.
  • the voltage at the second end (first node N1) of the capacitor C is Vd-
  • the signals of Reset-H and the light emitting control line EM are high level signals, and the first transistor M1, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are turned off. In this stage, the light emitting device L does not emit light.
  • the fourth stage P4 is called the continuous compensation stage.
  • the signals of the first reset line Reset-P, the second reset line Reset-H, the first scan line Gate-P, the second scan line Gate-N and the light-emitting control line EM are high-level signals.
  • the signal of the second scan line Gate-N is a high-level signal
  • the second transistor M2 is continuously turned on
  • the signals of the first scan line Gate-P, the first reset line Reset-P, the second reset line Reset-H and the light-emitting control line EM are high-level signals
  • the first transistor M1, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are turned off.
  • the second node N2 is still provided to the first node N1 through the turned-on third transistor M3, the third node N3 and the turned-on second transistor M2, and the threshold voltage of the third transistor M3 is continuously compensated.
  • the fifth stage P5 is called the bias stage.
  • the signals of the second scan line Gate-N and the second reset line Reset-H are low-level signals, and the signals of the first reset line Reset-P, the first scan line Gate-P and the light-emitting control line EM are high-level signals.
  • the signal of the second scan line Gate-N is a low-level signal, and the signals of the first scan line Gate-P, the first reset line Reset-P and the light-emitting control line EM are high-level signals.
  • the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are all turned off.
  • the signal of the second reset line Reset-H is a low-level signal
  • the seventh transistor M7 and the eighth transistor M8 are turned on
  • the signal of the third initial signal line INIT3 is written into the second node N2 and the third node N3
  • the signal of the second initial signal line INIT2 is written into the fourth node N3.
  • the third transistor M3 is in a biased state, and the light-emitting device L does not emit light.
  • the sixth stage P6 is called the light-emitting stage, the signals of the light-emitting control line EM and the second scanning line Gate-N are low-level signals, and the signals of the first reset line Reset-P, the second reset line Reset-H and the first scanning line Gate-P are high-level signals.
  • the signal of the light-emitting control line EM is a low-level signal, so that the fifth transistor M5 and the sixth transistor M6 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, driving the light-emitting device L to emit light.
  • the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between its control electrode and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K*(Vdd-Vd) 2 ;
  • I is the driving current flowing through the third transistor M3, that is, the driving current driving the light emitting device L
  • K is a constant
  • Vgs is a voltage difference between a control electrode and a first electrode of the third transistor M3
  • Vth is a threshold voltage of the third transistor M3
  • Vd is a data voltage output by the data line D
  • Vdd is a power voltage output by the first power line VDD.
  • the driving current of the third transistor M3 is no longer affected by the threshold voltage of the third transistor M3, thereby eliminating the influence of the threshold voltage of the third transistor M3 on the driving current, which can ensure the uniform display brightness of the display product and improve the display effect of the entire display product.
  • the mainstream image resolution (Pixels Per Inch, PPI) of OLED display panels is between 400 and 450, but with the maturity of display technology, the market demand for higher PPI products is becoming more and more urgent.
  • the PPI of some display panels has been increased to between 500 and 550.
  • Higher PPI reduces the charging time of each row of sub-pixels (for example, the sub-pixel charging time of some high-PPI products is about 1.6us, and the sub-pixel charging time of some mainstream PPI products is about 2.5us), which will cause related problems caused by insufficient charging, such as poor low grayscale image quality, poor picture uniformity, color cast and other image quality problems.
  • Some high PPI products improve the charging rate by reducing the resistance and capacitance load (RC loading) of signal lines such as data lines and scan lines.
  • RC loading resistance and capacitance load
  • the method of reducing the RC loading of signal lines is mainly to thicken the thickness of the insulating layer and the flat layer in the process, and try to avoid the overlapping capacitance generated by the signal lines between different layers. This method will increase the size of the display panel, which is not conducive to the thinness of the display panel.
  • an embodiment of the present disclosure provides a display panel, including multiple gate driving circuits, and multiple sub-pixels arranged in an array, wherein the sub-pixels include a pixel driving circuit and a light-emitting element, and the pixel driving circuit includes multiple transistors, wherein:
  • a plurality of gate driving circuits are configured to output a plurality of gate driving signals to a plurality of transistors in a pixel driving circuit, wherein each gate driving circuit outputs a gate driving signal, and the plurality of gate driving signals are divided into at least two groups, and the high level voltages of the gate driving signals in different groups are different, and/or the low level voltages of the gate driving signals in different groups are different;
  • the pixel driving circuit is configured to receive a plurality of gate driving signals and drive the light emitting element to emit light according to the received plurality of gate driving signals.
  • the display panel of the embodiment of the present disclosure divides multiple gate drive signals into at least two groups, and different groups of gate drive signals have different high-level voltages and/or different groups of gate drive signals have different low-level voltages.
  • the high and low levels of the gate drive signals can be adjusted according to the influence of each group of gate drive signals on the charging rate, thereby achieving an optimal charging rate and power consumption combination.
  • the gate driving circuit may be a Gate Driver On Array (GOA) circuit, and accordingly, the gate driving signal may be a GOA driving signal.
  • GOA Gate Driver On Array
  • the high-level voltage VGH_Gate-P of the first scan line Gate-P should be set higher, such as 9V ⁇ 10V.
  • the high-level voltages of the first reset line Reset-P, the first reset line Reset-H, and the light-emitting control line EM have little effect on the charging rate of the first node N1 and can be designed according to conventional values, such as 7.5 ⁇ 8.5V.
  • the high and low level signals of multiple GOA drive signals are set to the same signal and can only be changed uniformly, such as the high level voltage VGH_Gate-P of the first scan line Gate-P, the high level voltage VGH_Gate-N of the second scan line Gate-N, and the high level voltage VGH_EM of the light emitting control line EM, which are the same high level signal, that is, the high level voltages of multiple GOA drive signals can only be set to the same high level voltage value and the low level voltages of multiple GOA drive signals can only be set to the same low level voltage value.
  • the disclosed embodiment divides the multiple GOA drive signals into multiple groups according to their different effects on the charging rate of the first node N1.
  • the multiple groups of GOA drive signals can be set differently and combined as needed to achieve the best high and low level voltage configuration; compared with the unified
  • the high and low level signals of the same GOA can avoid the negative impact of a certain GOA driving signal. For example, by increasing the high level voltage, the charging rate of the first node N1 is improved from the perspective of the first scan line Gate-P, but the charging rate of the first node N1 is reduced from the perspective of the second scan line Gate-N.
  • the best charging rate and power consumption combination can be achieved.
  • the plurality of GOA drive signals may be divided into three groups, wherein a first group of GOA drive signals includes a first gate control signal provided by a first scan line Gate-P, a second group of GOA drive signals includes a second gate control signal provided by a second scan line Gate-N, and a third group of GOA drive signals includes a first reset control signal provided by a first reset line Reset-P, a second reset control signal provided by a second reset line Reset-N, and a light emitting control signal provided by a light emitting control line EM.
  • the high level voltage of the first group of GOA drive signals is greater than the high level voltage of the third group of GOA drive signals, and/or the low level voltage of the first group of GOA drive signals is greater than the low level voltage of the third group of GOA drive signals;
  • the high level voltage of the second group of GOA drive signals is lower than the high level voltage of the third group of GOA drive signals, and/or the low level voltage of the second group of GOA drive signals is lower than the low level voltage of the third group of GOA drive signals.
  • the high level voltage of the first group of GOA drive signals is between 9V and 10V; the high level voltage of the second group of GOA drive signals is between 6V and 7V; and the high level voltage of the third group of GOA drive signals is between 7.5V and 8.5V.
  • the high level voltage of the first group of GOA driving signals may be 9.5V; the high level voltage of the second group of GOA driving signals may be 6.5V; and the high level voltage of the third group of GOA driving signals may be 8V.
  • the low level voltage of the first group of GOA drive signals is between -6V and -7V; the low level voltage of the second group of GOA drive signals is between -8V and -9V; and the low level voltage of the third group of GOA drive signals is between -7V and -8V.
  • the low level voltage of the first group of GOA driving signals may be -6.5V; the low level voltage of the second group of GOA driving signals may be -8.5V; and the low level voltage of the third group of GOA driving signals may be -7.5V.
  • the plurality of GOA driving signals may be divided into five groups, wherein the first group of GOA driving signals includes a first gate control signal provided by the first scan line Gate-P, the second group of GOA driving signals includes a second gate control signal provided by the second scan line Gate-N, the third group of GOA driving signals includes a first reset control signal provided by the first reset line Reset-P, and the fourth group of GOA driving signals includes a second reset control signal provided by the second reset line Reset-N.
  • the fifth group of GOA driving signals includes the light emitting control signal provided by the light emitting control line EM.
  • the high level voltage of the first group of GOA drive signals is greater than the high level voltage of the third group of GOA drive signals, and/or the low level voltage of the first group of GOA drive signals is greater than the low level voltage of the third group of GOA drive signals;
  • the high level voltage of the second group of GOA drive signals is lower than the high level voltage of the third group of GOA drive signals, and/or the low level voltage of the second group of GOA drive signals is lower than the low level voltage of the third group of GOA drive signals.
  • the high level voltage of the fourth group of GOA drive signals is equal to or approximately equal to the high level voltage of the third group of GOA drive signals
  • the low level voltage of the fourth group of GOA drive signals is equal to or approximately equal to the low level voltage of the third group of GOA drive signals.
  • the high level voltage of the fifth group of GOA drive signals is equal to or approximately equal to the high level voltage of the third group of GOA drive signals, and/or the low level voltage of the fifth group of GOA drive signals is equal to or approximately equal to the low level voltage of the third group of GOA drive signals.
  • a and B are approximately equal means that the difference between A and B is within a preset difference threshold range.
  • the preset difference threshold may be 1.
  • the high level voltage of the first group of GOA drive signals is between 9V and 10V; the high level voltage of the second group of GOA drive signals is between 6V and 7V; the high level voltage of the third group of GOA drive signals is between 7.5V and 8.5V; the high level voltage of the fourth group of GOA drive signals is between 7.5V and 8.5V; and the high level voltage of the fifth group of GOA drive signals is between 7.5V and 8.5V.
  • the high level voltage of the first group of GOA drive signals can be 9.5V; the high level voltage of the second group of GOA drive signals can be 6.5V; the high level voltage of the third group of GOA drive signals can be 8V; the high level voltage of the fourth group of GOA drive signals can be 8V; and the high level voltage of the fifth group of GOA drive signals can be 8V.
  • the low level voltage of the first group of GOA drive signals is between -6V and -7V; the low level voltage of the second group of GOA drive signals is between -8V and -9V; the low level voltage of the third group of GOA drive signals is between -7V and -8V; the low level voltage of the fourth group of GOA drive signals is between -7V and -8V; and the low level voltage of the fifth group of GOA drive signals is between -7V and -8V.
  • the low level voltage of the first group of GOA drive signals may be -6.5V; the low level voltage of the second group of GOA drive signals may be -8.5V; the low level voltage of the third group of GOA drive signals may be -7.5V; the low level voltage of the fourth group of GOA drive signals may be -7.5V; and the low level voltage of the fifth group of GOA drive signals may be -7.5V.
  • FIG5A is a schematic diagram of an equivalent circuit of another pixel driving circuit of an exemplary embodiment of the present disclosure.
  • the pixel driving circuit may include 7 transistors (a first transistor T1 to a seventh transistor T7), 1 storage capacitor C, and a plurality of signal lines (a data line Data, a scan line Gate, a reset line Reset, an initial signal line INIT, a first power line VDD, a second power line VSS, and a light emitting control line EM).
  • a control electrode of the first transistor T1 is connected to a reset line Reset, a first electrode of the first transistor T1 is connected to an initial signal line INIT, and a second electrode of the first transistor T1 is connected to a first node N1.
  • a control electrode of the second transistor T2 is connected to a scan line Gate, a first electrode of the second transistor T2 is connected to a third node N3, and a second electrode of the second transistor T2 is connected to the first node N1.
  • a control electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to a second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.
  • a control electrode of the fourth transistor T4 is connected to a scan line Gate, a first electrode of the fourth transistor T4 is connected to a data line Data, and a second electrode of the fourth transistor T4 is connected to a second node N2.
  • a control electrode of the fifth transistor T5 is connected to an emission control line EM, a first electrode of the fifth transistor T5 is connected to a first power line VDD, and a second electrode of the fifth transistor T5 is connected to a second node N2.
  • the control electrode of the sixth transistor T6 is connected to the light emitting control line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4 (i.e., the first electrode of the light emitting element).
  • the control electrode of the seventh transistor T7 is connected to the scanning line Gate or the reset line Reset, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.
  • the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the first node N1.
  • the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.
  • the second electrode of the light emitting element is connected to the second power line VSS, the signal of the second power line VSS is to continuously provide a low level signal, and the signal of the first power line VDD is to continuously provide a high level signal.
  • the scanning line Gate is a scanning signal line in the pixel driving circuit of the current display row
  • the reset line Reset is a scanning signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the scanning line Gate is Gate (n), and the reset line Reset is Gate (n-1), and the reset line Reset of the current display row and the scanning line Gate in the pixel driving circuit of the previous display row can be the same signal line, so as to reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the scan line Gate, the reset line Reset, the light emitting control line EM and the initial signal The lines INIT each extend in a horizontal direction, and the second power line VSS, the first power line VDD, and the data line Data extend in a vertical direction.
  • the light emitting element may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked together.
  • OLED organic light emitting diode
  • the first transistor T1 and the seventh transistor T7 can both be called reset transistors
  • the second transistor T2 can be called a compensation transistor
  • the third transistor T3 can be called a driving transistor
  • the fourth transistor T4 can be called a data writing transistor
  • the fifth transistor T5 and the sixth transistor T6 can be called light emitting control transistors.
  • FIG5B is a working timing diagram of the pixel driving circuit shown in FIG5A.
  • the following illustrates an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit shown in FIG5B, assuming that all the seven transistors in FIG5A are P-type transistors.
  • the working process of the pixel driving circuit may include:
  • the first stage A1 is called the reset stage.
  • the signal of the reset line Reset is a low-level signal, and the signals of the scan line Gate and the light-emitting control line EM are high-level signals.
  • the signal of the reset line Reset is a low-level signal, which turns on the first transistor T1.
  • the signal of the initial signal line INIT is provided to the first node N1 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the scan line Gate and the light-emitting control line EM are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the OLED does not emit light.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the scan line Gate is a low level signal
  • the signals of the reset line Reset and the light emitting control line EM are high level signals
  • the data line Data outputs the data voltage.
  • the third transistor T3 is turned on.
  • the signal of the scan line Gate is a low level signal to turn on the second transistor T2, the fourth transistor T4 and the seventh transistor T7.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data line Data is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the sum of the data voltage output by the data line Data and the threshold voltage of the third transistor T3 is charged into the storage capacitor C.
  • the voltage of the second end (the second node N2) of the storage capacitor C is Vdata+Vth
  • Vdata is the data voltage output by the data line Data
  • Vth is the threshold voltage of the third transistor T3.
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light.
  • the signal of the reset line Reset is a high-level signal, which turns off the first transistor T1.
  • the signal of the light-emitting control line EM is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting control line EM is a low-level signal, and the signals of the scanning line Gate and the reset line Reset are high-level signals.
  • the signal of the light-emitting control line EM is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode and the first electrode. Since the voltage of the second node N2 is Vdata+Vth, the driving current of the third transistor T3 is:
  • I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3
  • Vth is the threshold voltage of the third transistor T3
  • Vdata is the data voltage output by the data line Data
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the current I flowing through the light emitting element is independent of the threshold voltage Vth of the third transistor T3, thereby eliminating the influence of the threshold voltage Vth of the third transistor T3 on the current I and ensuring the uniformity of brightness.
  • the pixel circuit eliminates the residual positive charge of the light-emitting element after the last light emission, realizes compensation for the gate voltage of the third transistor, avoids the influence of the threshold voltage drift of the third transistor on the driving current of the light-emitting element, and improves the uniformity of the displayed image and the display quality of the display panel.
  • the plurality of GOA driving signals include a gate control signal for controlling the opening and closing of a data writing transistor, a reset control signal for controlling the opening and closing of a reset transistor, and a light emission control signal for controlling the opening and closing of a light emission control transistor;
  • the various GOA driving signals are divided into two groups, wherein the first group includes gate control signals and the second group includes light emitting control signals.
  • the first group of GOA driving signals includes the reset control signal
  • the second group of GOA driving signals includes the reset control signal.
  • a high level voltage of the first group of GOA drive signals is greater than a high level voltage of the second group of GOA drive signals, and/or a low level voltage of the first group of GOA drive signals is greater than a low level voltage of the second group of GOA drive signals.
  • the pixel driving circuit includes a driving transistor, a data writing transistor, a reset transistor, a light emission control transistor, and a compensation transistor;
  • the multiple GOA driving signals include a first gate control signal for controlling the opening and closing of a data writing transistor, a second gate control signal for controlling the opening and closing of a compensation transistor, a reset control signal for controlling the opening and closing of a reset transistor, and a light emission control signal for controlling the opening and closing of a light emission control transistor;
  • the various GOA driving signals are divided into three groups, wherein the first group includes a first gate control signal, the second group includes a second gate control signal, and the third group includes a reset control signal and a light emitting control signal.
  • the high level voltage of the first group of GOA drive signals is greater than the high level voltage of the third group of GOA drive signals, and/or the low level voltage of the first group of GOA drive signals is greater than the low level voltage of the third group of GOA drive signals;
  • the high level voltage of the second group of GOA drive signals is lower than the high level voltage of the third group of GOA drive signals, and/or the low level voltage of the second group of GOA drive signals is lower than the low level voltage of the third group of GOA drive signals.
  • the high level voltage of the first group of GOA drive signals is between 9V and 10V; the high level voltage of the second group of GOA drive signals is between 6V and 7V; and the high level voltage of the third group of GOA drive signals is between 7.5V and 8.5V.
  • the high level voltage of the first group of GOA driving signals may be 9.5V; the high level voltage of the second group of GOA driving signals may be 6.5V; and the high level voltage of the third group of GOA driving signals may be 8V.
  • the low level voltage of the first group of GOA drive signals is between -6V and -7V; the low level voltage of the second group of GOA drive signals is between -8V and -9V; and the low level voltage of the third group of GOA drive signals is between -7V and -8V.
  • the low level voltage of the first group of GOA driving signals may be -6.5V; the low level voltage of the second group of GOA driving signals may be -8.5V; and the low level voltage of the third group of GOA driving signals may be -7.5V.
  • the embodiment of the present disclosure further provides a display device, including: a display panel.
  • the display panel is the display panel provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.
  • Other essential components of the display device are well understood by those skilled in the art and will not be described in detail herein and should not be used as a reference. Limitations on this Application.
  • the present disclosure also provides a method for driving a display panel, including:
  • Control multiple groups of gate driving circuits to output multiple gate driving signals to multiple transistors in a pixel driving circuit wherein the multiple gate driving signals are divided into at least two groups, the high level voltages of the gate driving signals in the same group are the same, and the low level voltages of the gate driving signals in the same group are the same; the high level voltages of the gate driving signals in different groups are different, and/or the low level voltages of the gate driving signals in different groups are different.
  • the pixel driving circuit includes a data writing transistor, a driving transistor and a light emission control transistor, wherein the data writing transistor is configured to write a data voltage provided by a data line into the driving transistor when a gate control signal provided by a scanning line is valid; the driving transistor is configured to generate a driving current according to the data voltage; the light emission control transistor is configured to control the driving current generated by the driving transistor to flow through the light emitting element to drive the light emitting element to emit light when a light emission control signal provided by a light emission line is valid;
  • the plurality of gate driving signals include a gate control signal for controlling the opening and closing of the data writing transistor and a light emission control signal for controlling the opening and closing of the light emission control transistor;
  • the plurality of gate driving signals are divided into two groups, wherein a first group of gate driving signals includes the gate control signals, and a second group of gate driving signals includes the light emitting control signals.
  • a high level voltage of the first group of gate drive signals is greater than a high level voltage of the second group of gate drive signals, and/or a low level voltage of the first group of gate drive signals is greater than a low level voltage of the second group of gate drive signals.
  • the pixel driving circuit further includes a reset transistor, and the reset transistor is configured to reset at least one of the following when a reset control signal is valid: an anode of the light emitting element, a first electrode of the driving transistor, and a second electrode of the driving transistor; the plurality of gate driving signals include a reset control signal for controlling the opening and closing of the reset transistor;
  • the first group of gate drive signals includes the reset control signal
  • the second group of gate driving signals includes the reset control signal.
  • the pixel driving circuit includes a driving transistor, a data writing transistor, a reset transistor, a light emitting control transistor, and a compensation transistor, wherein the data writing transistor is configured to When the first gate control signal provided by the scan line is valid, the data voltage provided by the data line is written into the driving transistor; the driving transistor is configured to generate a driving current according to the data voltage; the light-emitting control transistor is configured to control the driving current generated by the driving transistor to flow through the light-emitting element when the light-emitting control signal provided by the light-emitting line is valid, so as to drive the light-emitting element to emit light; the reset transistor is configured to reset at least one of the following when the reset control signal is valid: the anode of the light-emitting element, the first electrode of the driving transistor, and the second electrode of the driving transistor; the compensation transistor is configured to perform threshold compensation on the driving transistor when the second gate control signal provided by the second scan line is valid;
  • the plurality of gate driving signals include a first gate control signal for controlling the opening and closing of the data writing transistor, a second gate control signal for controlling the opening and closing of the compensation transistor, a reset control signal for controlling the opening and closing of the reset transistor, and a light emission control signal for controlling the opening and closing of the light emission control transistor;
  • the high level voltage of the first group of gate driving signals is greater than the high level voltage of the third group of gate driving signals, and/or the low level voltage of the first group of gate driving signals is greater than the low level voltage of the third group of gate driving signals;
  • the high level voltage of the second group of gate driving signals is lower than the high level voltage of the third group of gate driving signals, and/or the low level voltage of the second group of gate driving signals is lower than the low level voltage of the third group of gate driving signals.
  • the low level voltage of the first group of gate driving signals is between -6V and -7V; the low level voltage of the second group of gate driving signals is between -8V and -9V; and the low level voltage of the third group of gate driving signals is between -7V and -8V.
  • the pixel driving circuit includes a driving transistor, a data writing transistor, a first reset transistor, a second reset transistor, a light emitting control transistor, and a compensation transistor, wherein the data writing transistor is configured to convert the data voltage provided by the data line into a voltage when the first gate control signal provided by the first scan line is valid.
  • the driving transistor is configured to generate a driving current according to the data voltage
  • the light emitting control transistor is configured to control the driving current generated by the driving transistor to flow through the light emitting element when the light emitting control signal provided by the light emitting line is valid, so as to drive the light emitting element to emit light
  • the first reset transistor is configured to reset the second electrode of the driving transistor when the first reset control signal is valid
  • the second reset transistor is configured to reset the anode of the light emitting element and the first electrode of the driving transistor when the second reset control signal is valid
  • the compensation transistor is configured to perform threshold compensation on the driving transistor when the second gate control signal provided by the second scanning line is valid
  • the plurality of gate driving signals include a first gate control signal for controlling the opening and closing of the data writing transistor, a second gate control signal for controlling the opening and closing of the compensation transistor, a first reset control signal for controlling the opening and closing of the first reset transistor, a second reset control signal for controlling the opening and closing of the second reset transistor, and a light emission control signal for controlling the opening and closing of the light emission control transistor;
  • the multiple gate driving signals are divided into five groups, wherein the first group includes the first gate control signal, the second group includes the second gate control signal, the third group includes the first reset control signal, the fourth group includes the second reset control signal, and the fifth group includes the light emitting control signal.
  • the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” the other element, or there may be intermediate elements.

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Abstract

一种显示面板及其驱动方法、显示装置，该显示面板包括：多种栅极驱动电路，还包括阵列排布的多个子像素，子像素包括像素驱动电路和发光元件，像素驱动电路包括多个晶体管，其中：多种栅极驱动电路，被配置为输出多种栅极驱动信号至像素驱动电路中的多个晶体管，其中，每种栅极驱动电路输出一种栅极驱动信号，多种栅极驱动信号至少分为两组，相同组栅极驱动信号的高电平电压相同，且相同组栅极驱动信号的低电平电压相同；不同组栅极驱动信号的高电平电压不同，和/或，不同组栅极驱动信号的低电平电压不同；像素驱动电路，被配置为接收多种栅极驱动信号，并根据接收到的多种栅极驱动信号驱动发光元件发光。

Description

显示面板及其驱动方法、显示装置
本申请要求于2023年7月26日提交中国专利局、申请号为202310926864.5、发明名称为“显示面板及其驱动方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，尤其涉及一种显示面板及其驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示面板，包括：多种栅极驱动电路，还包括阵列排布的多个子像素，所述子像素包括像素驱动电路和发光元件，所述像素驱动电路包括多个晶体管，其中：
所述多种栅极驱动电路，被配置为输出多种栅极驱动信号至所述像素驱动电路中的多个晶体管，其中，每种所述栅极驱动电路输出一种栅极驱动信号，所述多种栅极驱动信号至少分为两组，相同组所述栅极驱动信号的高电平电压相同，且相同组所述栅极驱动信号的低电平电压相同；不同组所述栅极驱动信号的高电平电压不同，和/或，不同组所述栅极驱动信号的低电平电压不同；
所述像素驱动电路，被配置为接收所述多种栅极驱动信号，并根据接收到的所述多种 栅极驱动信号驱动所述发光元件发光。
本公开实施例还提供了一种显示装置，包括如本公开任一实施例所述的显示面板。
本公开实施例还提供了一种显示面板的驱动方法，包括：
控制多组栅极驱动电路输出多种栅极驱动信号至像素驱动电路中的多个晶体管，其中，所述多种栅极驱动信号至少分为两组，相同组所述栅极驱动信号的高电平电压相同，且相同组所述栅极驱动信号的低电平电压相同；不同组所述栅极驱动信号的高电平电压不同，和/或，不同组所述栅极驱动信号的低电平电压不同。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的结构示意图；
图2为一种显示面板的平面示意图；
图3A为一种像素驱动电路的结构示意图；
图3B为图3A提供的像素驱动电路的一种工作过程示意图；
图4A为本公开实施例一种显示面板的结构示意图；
图4B为一些技术中的显示面板的结构示意图；
图5A为另一种像素驱动电路的结构示意图；
图5B为图5A提供的像素驱动电路的一种工作过程示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例 中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区或漏电极)与源极(源电极端子、源区或源电极)之间具有沟道区，并且电流能够流过漏极、沟道区以及源极。在本说明书中，沟道区是指电流主要流过的区。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互 相调换。另外，栅极还可以称为控制极。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，圆形、椭圆形、三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似圆形、近似椭圆形、近似三角形、近似矩形、近似梯形、近似五边形或近似六边形等，可以存在公差导致的一些小变形，例如可以存在导角、弧边以及变形等。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。
在本公开中，A沿着B方向延伸是指，A可以包括主体部分和与主体部分连接的次要部分，主体部分是线、线段或条形状体，主体部分沿着B方向伸展，且主体部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。本公开中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
图1为一种显示装置的结构示意图。在一些示例中，如图1所示，显示装置可以包括：时序控制器21、数据驱动器22、扫描驱动电路23、发光驱动电路24以及子像素阵列25。在一些示例中，子像素阵列25可以包括规则排布的多个子像素PX。扫描驱动电路23可以配置为沿扫描信号线将扫描信号提供到子像素PX；数据驱动器22可以配置为沿数据线将数据电压提供到子像素PX；发光驱动电路24可以配置为沿发光控制线将发光控制信号提供到子像素PX；时序控制器21可以配置为控制扫描驱动电路23、发光驱动电路24和数据驱动器22。
在一些示例中，如图1所示，时序控制器21可以将适于数据驱动器22的规格的灰度值和控制信号提供到数据驱动器22；时序控制器21可以将适于扫描驱动电路23的规格的扫描时钟信号、扫描起始信号等提供到扫描驱动电路23；时序控制器21可以将适于发光驱动电路24的规格的发光时钟信号、发光起始信号等提供到发光驱动电路24。数据驱动器22可以利用从时序控制器21接收的灰度值和控制信号来产生将提供到数据线D1至Di的数据电压。例如，数据驱动器22可以利用时钟信号对灰度值进行采样，并且以子像素行为单位将与灰度值对应的数据电压施加到数据线D1至Di。扫描驱动电路23可以通过从时序控制器21接收的扫描时钟信号、扫描起始信号等来产生将提供到扫描线S1至Sj的扫描信号。例如，扫描驱动电路23可以将具有导通电平脉冲的扫描信号顺序地提供 到扫描线。在一些示例中，扫描驱动电路23可以包括移位寄存器，可以在扫描时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。发光驱动电路24可以通过从时序控制器21接收的发光时钟信号、发光起始信号等来产生将提供到发光控制线EM1至Eo的发光控制信号。例如，发光驱动电路24可以将具有截止电平脉冲的发光控制信号顺序地提供到发光控制线。发光驱动电路24可以包括移位寄存器，以在时钟信号的控制下顺序地将截止电平脉冲形式提供的发光起始信号传输到下一级电路的方式产生发光控制信号。其中，i、j和o均为自然数。
在一些示例中，显示装置可以包括显示面板。子像素阵列、扫描驱动电路和发光驱动电路可以直接设置在显示面板上。例如，扫描驱动电路可以设置在显示面板的左边框，发光驱动电路可以设置在显示面板的右边框；或者，显示面板的左边框和右边框均可以设置扫描驱动电路和发光驱动电路。在一些示例中，扫描驱动电路和发光驱动电路可以在形成子像素的工艺中与子像素一起形成。
在一些示例中，数据驱动器可以设置在单独的芯片或印刷电路板上。例如，数据驱动器可以采用玻璃上芯片、塑料上芯片、膜上芯片等形成设置在显示面板的下边框，以连接到驱动芯片引脚。时序控制器可以与数据驱动器分开设置或者与数据驱动器一体设置。然而，本实施例对此并不限定。
图2为一种显示面板的平面示意图。在一些示例中，如图2所示，显示面板可以包括：显示区AA、位于显示区AA一侧的绑定区B1以及位于显示区AA其它侧的边框区B2。绑定区B1例如可以为显示面板的下边框，边框区B2可以包括显示面板的上边框、左边框和右边框。在一些示例中，显示区AA可以是平坦的区域，包括组成像素阵列的多个子像素PX，多个子像素PX被配置为显示动态图片或静止图像。显示区可以称为有效区。在一些示例中，显示面板可以为柔性基板，因而显示面板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在一些示例中，边框区B2可以包括沿着显示区AA的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区可以连接到显示区AA，可以至少包括多个级联的栅极驱动电路，栅极驱动电路与显示区AA中的多条栅线电连接。电源线区连接到电路区，可以至少包括低电平电源线，低电平电源线可以沿着平行于显示区边缘的方向延伸，与显示区的阴极连接。裂缝坝区可以连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区可以连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽 可以被配置为在显示面板的所有膜层制备完成后，切割设置可以分别沿着切割槽进行切割。
在一些示例中，绑定区B1和边框区B2可以设置第一隔离坝和第二隔离坝，第一隔离坝和第二隔离坝可以沿着平行于显示区边缘的方向延伸，形成环绕显示区AA的环形结构，显示区边缘是显示区靠近绑定区B1或边框区B2一侧的边缘。
在一些示例中，如图2所示，显示区AA可以至少包括多个子像素PX、多条栅线Gate以及多条数据线Data。多条栅线Gate可以沿第一方向X延伸，多条数据线Data可以沿第二方向Y延伸。多条栅线Gate和多条数据线Data在衬底基板上的正投影交叉形成多个子像素区，每个子像素区内设置一个子像素PX。多条数据线Data与多个子像素PX电连接，多条数据线Data可以被配置为向多个子像素PX提供数据信号。多条数据线Data可以延伸至绑定区B1。多条栅线Gate与多个子像素PX电连接，多条栅线Gate可以被配置为向多个子像素PX提供栅极控制信号。在一些示例中，栅极控制信号可以包括扫描信号和发光控制信号。
在一些示例中，如图2所示，第一方向X可以是显示区AA中栅线Gate的延伸方向(行方向)，第二方向Y可以是显示区AA中数据线Data的延伸方向(列方向)。第一方向X和第二方向Y可以相交，示例性地，第一方向X和第二方向Y可以相互垂直。
在一些示例中，显示区AA的一个像素单元可以包括三个子像素，三个子像素分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例中，子像素的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在一些示例中，一个子像素可以包括：像素驱动电路以及与像素驱动电路电连接的发光元件。像素驱动电路可以包括多个晶体管和至少一个电容，例如，像素驱动电路可以为3T1C(即3个晶体管和1个电容)结构、7T1C(即7个晶体管和1个电容)结构、5T1C(即5个晶体管和1个电容)结构、8T1C(即8个晶体管和1个电容)结构或者8T2C(即8个晶体管和2个电容)结构等。
在一些示例中，发光元件可以是发光二极管(LED，Light Emitting Diode)、有机发光二极管(OLED，Organic Light Emitting Diode)、量子点发光二极管(QLED，Quantum Dot Light Emitting Diodes)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光元件可以为OLED，发光元件在其对应的像素驱动电路的驱动下可以发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：第一电极、第二电极以及位于第一电极和第二电极之间的有机发光层。发光元件的第一电极可以与对应的像素驱动电路电连接。然而，本实施例对此并不限定。
图3A为一种像素驱动电路的结构示意图。图3A是以8T1C为例进行说明的。如图3A所示，像素驱动电路可以与11个信号线(数据线Data、第一扫描线Gate-P、第二扫描线Gate-N、第一复位线Reset-P、第二复位线Reset-H、发光控制线EM、第一初始信号线INIT1、第二初始信号线INIT2、第三初始信号线INIT3、第一电源线VDD和第二电源线VSS)连接。其中，栅线包括：第一扫描线Gate-P、第二扫描线Gate-N、第一复位线Reset-P、第二复位线Reset-H、发光控制线EM。
在示例性实施方式中，如图3A所示，第一晶体管M1的控制极与第一复位线Reset-P连接，第一晶体管M1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第三节点N3连接。第二晶体管M2的控制极与第二扫描线Gate-N连接，第二晶体管M2的第一极与第一节点N1连接，第二晶体管M2的第二极与第三节点N3连接。第三晶体管M3的控制极与第一节点N1连接，第三晶体管M3的第一极与第二节点N2连接，第三晶体管M3的第二极与第三节点N3连接。第四晶体管M4的控制极与第一扫描线Gate-P连接，第四晶体管M4的第一极与数据线Data连接，第四晶体管M4的第二极与第二节点N2连接。第五晶体管M5的控制极与发光控制线EM连接，第五晶体管M5的第一极与第一电源线VDD连接，第五晶体管M5的第二极与第二节点N2连接。第六晶体管M6的控制极与发光控制线EM连接，第六晶体管M6的第一极与第三节点N3连接，第六晶体管M6的第二极与第四节点N4连接。第七晶体管M7的控制极与第二复位线Reset-H连接，第七晶体管M7的第一极与第二初始信号线INIT2连接，第七晶体管M7的第二极与第四节点N4连接。第八晶体管M8的控制极与第二复位线Reset-H连接，第八晶体管M8的第一极与第三初始信号线INIT3连接，第八晶体管M8的第二极与第二节点N2连接，电容C的第一端与第一电源线VDD连接，电容C的第二端与第一节点N1连接。
在示例性实施方式中，发光器件的第一电极与第四节点N4电连接，发光器件的第二 电极与第二电源线VSS连接，
在示例性实施方式中，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。
按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，第一晶体管M1到第八晶体管M8可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管M1到第八晶体管M8可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管M1到第八晶体管M8可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示面板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示面板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，如图3A所示，第二晶体管M2可以为N型晶体管，第一晶体管M1、第三晶体管M3至第八晶体管M8可以为P型晶体管。
本示例性实施方式中，第一晶体管M1、第七晶体管M7和第八晶体管M8均可以称为复位晶体管，第二晶体管M2可以称为补偿晶体管，第二晶体管M3可以称为驱动晶体管，第四晶体管M4可以称为数据写入晶体管，第五晶体管M5和第六晶体管M6可以称为发光控制晶体管。
图3B为一种图3A提供的像素驱动电路的工作过程。在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段P1，称为第一复位阶段，第二复位线Reset-H的信号为低电平信号，第一复位线Reset-P、第一扫描线Gate-P、第二扫描线Gate-N和发光控制线EM的信号为高电平信号。第二复位线Reset-H的信号为低电平信号，使第七晶体管M7和第八晶体管M8导通，第二初始信号线INIT2的信号提供至第四节点N4，对发光器件L的第一电极进行初始化(复位)，清除发光器件L的第一电极中原有电荷。第三初始信号线INIT3的信号提供至第二节点N2，对第二节点N2进行初始化(复位)，清除第二节点N2中原有电荷，此阶段，第三晶体管M3导通。第二扫描线Gate-N的信号为高电平信号，第二晶体管M2导通。第二节点N2的信号提供至第一节点N1和第三节点N3中，第一节点N1和第三节点N3进行了初始化，第一复位线Reset-P、第一扫描线Gate-P和发光控制线EM的信号为高电平信号，第一晶体管M1、第四晶体管M4、第五晶体管M5、第六晶体管M6断开。此阶段，发光器件L不发光。
第二阶段P2、称为第二复位阶段，第一复位线Reset-P的信号为低电平信号，第二复位线Reset-H、第一扫描线Gate-P、第二扫描线Gate-N和发光控制线EM的信号为高电平信号。第一复位线Reset-P的信号为低电平信号，使第一晶体管M1，第一初始信号线INIT1的信号提供至第三节点N3，对第三节点N3再次进行初始化(复位)，清除第三节点N3中原有电荷。此阶段，第三晶体管M3持续导通。第二扫描线Gate-N的信号为高电平信号，第二晶体管M2导通。第三节点N3提供至第一节点N1中，持续对第一节点N1进行初始化，第二复位线Reset-H、第一扫描线Gate-P和发光控制线EM的信号为高电平信号，第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和第八晶体管M8断开。此阶段，发光器件L不发光。
第三阶段P3、称为数据写入阶段或者阈值补偿阶段，第一扫描线Gate-P的信号为低电平信号，第一复位线Reset-P、第二复位线Reset-H、第二扫描线Gate-N和发光控制线EM的信号为高电平信号。数据线Data输出数据电压。此阶段，第三晶体管M3持续导通。第一扫描线Gate-P的信号为低电平信号使第四晶体管M4导通。第二扫描线Gate-N的信号为高电平信号，第二晶体管M2导通。数据线Data输出的数据电压经过导通的第四晶体管M4、第二节点N2、导通的第三晶体管M3、第三节点N3、导通的第二晶体管M2提供至第一节点N1，并将数据线Data输出的数据电压与第三晶体管M3的阈值电压之差充入电容C，电容C的第二端(第一节点N1)的电压为Vd-|Vth|，Vd为数据线Data输出的数据电压，Vth为第三晶体管M3的阈值电压。第一复位线Reset-P、第二复位线 Reset-H和发光控制线EM的信号为高电平信号，第一晶体管M1、第五晶体管M5、第六晶体管M6、第七晶体管M7和第八晶体管M8断开。此阶段，发光器件L不发光。
第四阶段P4、称为持续补偿阶段，第一复位线Reset-P、第二复位线Reset-H、第一扫描线Gate-P、第二扫描线Gate-N和发光控制线EM的信号为高电平信号。第二扫描线Gate-N的信号为高电平信号，第二晶体管M2持续导通，第一扫描线Gate-P、第一复位线Reset-P、第二复位线Reset-H和发光控制线EM的信号为高电平信号，第一晶体管M1、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7和第八晶体管M8断开。虽然数据线Data的信号停止写入，但是第二节点N2仍通过导通的第三晶体管M3、第三节点N3、导通的第二晶体管M2提供至第一节点N1，对第三晶体管M3的阈值电压持续地进行补偿。
第五阶段P5、称为偏置阶段，第二扫描线Gate-N和第二复位线Reset-H的信号为低电平信号，第一复位线Reset-P、第一扫描线Gate-P和发光控制线EM的信号为高电平信号。第二扫描线Gate-N的信号为低电平信号，第一扫描线Gate-P、第一复位线Reset-P和发光控制线EM的信号为高电平信号，第一晶体管M1、第二晶体管M2、第四晶体管M4、第五晶体管M5、第六晶体管M6均断开。第二复位线Reset-H的信号为低电平信号，第七晶体管M7和第八晶体管M8导通，第三初始信号线INIT3的信号写入第二节点N2和第三节点N3、第二初始信号线INIT2的信号写入第四节点N3，此阶段，第三晶体管M3处于偏置状态，发光器件L不发光。
第六阶段P6、称为发光阶段，发光控制线EM和第二扫描线Gate-N的信号为低电平信号，第一复位线Reset-P、第二复位线Reset-H和第一扫描线Gate-P的信号为高电平信号。发光控制线EM的信号为低电平信号，使第五晶体管M5和第六晶体管M6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管M5、第三晶体管M3和第六晶体管M6向发光器件L的第一电极提供驱动电压，驱动发光器件L发光。
在像素驱动电路驱动过程中，流过第三晶体管M3(驱动晶体管)的驱动电流由其控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而第三晶体管M3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*(Vdd-Vd)2；
其中，I为流过第三晶体管M3的驱动电流，也就是驱动发光器件L的驱动电流，K 为常数，Vgs为第三晶体管M3的控制极和第一极之间的电压差，Vth为第三晶体管M3的阈值电压，Vd为数据线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
由上述电流公式的推导结果可以看出，在发光阶段，第三晶体管M3的驱动电流已经不受第三晶体管M3的阈值电压的影响，从而消除了第三晶体管M3的阈值电压对驱动电流的影响，可以保证显示产品的显示亮度均匀，提升了整个显示产品的显示效果。
目前，OLED显示面板的主流图像分辨率(Pixels Per Inch，PPI)在400到450之间，但是随着显示技术的成熟，市场对于更高PPI产品的需求越来越迫切，目前部分显示面板的PPI已经提高到500到550之间。更高的PPI使得每行子像素的充电时间更少(示例性的，部分高PPI产品的子像素充电时间约为1.6us左右，部分主流PPI产品的子像素充电时间约为2.5us左右)，这会引起充电不足导致的相关问题，如低灰阶画质较差、画面均一性较差、色偏等画质问题。
如何提升高PPI产品的充电时间，提高其充电率是当前急需解决的问题。一些高PPI产品通过降低数据线和扫描线等信号线的电阻电容负载(RC loading)来提高充电率。但是，降低信号线的RC loading的方法主要是通过在工艺上加厚绝缘层和平坦层的厚度，尽量规避不同层之间的信号线产生的交叠电容来实现，这种方法会加大显示面板的尺寸，不利于显示面板的轻薄性。
如图4A所示，本公开实施例提供了一种显示面板，包括多种栅极驱动电路，还包括阵列排布的多个子像素，子像素包括像素驱动电路和发光元件，像素驱动电路包括多个晶体管，其中：
多种栅极驱动电路，被配置为输出多种栅极驱动信号至像素驱动电路中的多个晶体管，其中，每种栅极驱动电路输出一种栅极驱动信号，多种栅极驱动信号至少分为两组，不同组栅极驱动信号的高电平电压不同，和/或，不同组栅极驱动信号的低电平电压不同；
像素驱动电路，被配置为接收多种栅极驱动信号，并根据接收到的多种栅极驱动信号驱动发光元件发光。
本公开实施例的显示面板，通过将多种栅极驱动信号至少分为两组，不同组栅极驱动信号的高电平电压不同，和/或，不同组栅极驱动信号的低电平电压不同，可以分别针对每组栅极驱动信号对充电率的影响调节栅极驱动信号的高低电平，从而可以达到最佳的充电率以及功耗组合。
在一些示例性实施方式中，栅极驱动电路可以为阵列基板行驱动(Gate Driver On Array，GOA)电路，相应的，栅极驱动信号可以为GOA驱动信号。
示例性的，表1为针对一种类型的显示面板，当灰度值为10以及当灰度值为128时，分别设置第一扫描线Gate-P、第二扫描线Gate-N、第一复位线Reset-P、第二复位线Reset-H和发光控制线EM的高电平电压从6.0V到10.5V变化，得到的数据电压Vdata、第一复位线Reset-P电压跳变点对应的第一节点N1的电压值VN1@RP、发光控制线EM低电平阶段对应的第一节点N1的电压值VN1@EM、发光控制线EM低电平阶段对应的第一节点N1的电压值与数据电压的比值VN1@EM/Data以及电流变化率I表格，其中，I＝(max-min)/(max+min)，max表示最大电流，min表示最小电流。
表1


综合表1的数据，得到每种GOA驱动信号的VGH电压对第一节点N1的充电率影响如表2所示。
表2

从表2可以看出，第一扫描线Gate-P信号电压越高，第一节点N1的充电率越高，因此，第一扫描线Gate-P的高电平电压VGH_Gate-P应该设置较高，如9V～10V，第二扫描线Gate-N的高电平电压VGH_Gate-N越低，第一节点N1的充电率越高，因此第二扫描线Gate-N的高电平电压VGH_Gate-N应该设置较低，如6V～7V，而第一复位线Reset-P、第一复位线Reset-H、发光控制线EM的高电平电压对第一节点N1的充电率影响较小，可以按照常规值进行设计，如7.5～8.5V。
如图4B所示，在一些技术中，多种GOA驱动信号的高低电平信号设置为同一信号，只能统一进行变动，如第一扫描线Gate-P的高电平电压VGH_Gate-P、第二扫描线Gate-N的高电平电压VGH_Gate-N、发光控制线EM的高电平电压VGH_EM，为同一高电平信号，即多种GOA驱动信号的高电平电压只能设置为同一个高电平电压值且多种GOA驱动信号的低电平电压也只能设置为同一个低电平电压值。本公开实施例将多种GOA驱动信号按照对第一节点N1的充电率的影响不同，分为多组进行设置，多组GOA驱动信号可以进行区别设置，根据需要进行组合搭配，以达到最佳的高低电平电压配置；相比于统 一的高低电平信号，单独设置的高低电平信号可以避免某一GOA驱动信号带来的负面影响，如提高高电平电压，从第一扫描线Gate-P角度提升了第一节点N1的充电率，但从第二扫描线Gate-N角度降低了第一节点N1的充电率；通过对多种GOA驱动信号分别进行控制，可以达到最佳的充电率以及功耗组合。
在一些示例性实施方式中，多种GOA驱动信号可以分为三组，其中，第一组GOA驱动信号包括第一扫描线Gate-P提供的第一栅极控制信号，第二组GOA驱动信号包括第二扫描线Gate-N提供的第二栅极控制信号，第三组GOA驱动信号包括第一复位线Reset-P提供的第一复位控制信号、第二复位线Reset-N提供的第二复位控制信号和发光控制线EM提供的发光控制信号。
在一些示例性实施方式中，第一组GOA驱动信号的高电平电压大于第三组GOA驱动信号的高电平电压，和/或，第一组GOA驱动信号的低电平电压大于第三组GOA驱动信号的低电平电压；
第二组GOA驱动信号的高电平电压小于第三组GOA驱动信号的高电平电压，和/或，第二组GOA驱动信号的低电平电压小于第三组GOA驱动信号的低电平电压。
在一些示例性实施方式中，第一组GOA驱动信号的高电平电压在9V至10V之间；第二组GOA驱动信号的高电平电压在6V至7V之间；第三组GOA驱动信号的高电平电压在7.5V至8.5V之间。
示例性的，第一组GOA驱动信号的高电平电压可以为9.5V；第二组GOA驱动信号的高电平电压可以为6.5V；第三组GOA驱动信号的高电平电压可以为8V。
在一些示例性实施方式中，第一组GOA驱动信号的低电平电压在-6V至-7V之间；第二组GOA驱动信号的低电平电压在-8V至-9V之间；第三组GOA驱动信号的低电平电压在-7V至-8V之间。
示例性的，第一组GOA驱动信号的低电平电压可以为-6.5V；第二组GOA驱动信号的低电平电压可以为-8.5V；第三组GOA驱动信号的低电平电压可以为-7.5V。
在另一些示例性实施方式中，多种GOA驱动信号可以分为五组，其中，第一组GOA驱动信号包括第一扫描线Gate-P提供的第一栅极控制信号，第二组GOA驱动信号包括第二扫描线Gate-N提供的第二栅极控制信号，第三组GOA驱动信号包括第一复位线Reset-P提供的第一复位控制信号，第四组GOA驱动信号包括第二复位线Reset-N提供的第二复 位控制信号，第五组GOA驱动信号包括发光控制线EM提供的发光控制信号。
在另一些示例性实施方式中，第一组GOA驱动信号的高电平电压大于第三组GOA驱动信号的高电平电压，和/或，第一组GOA驱动信号的低电平电压大于第三组GOA驱动信号的低电平电压；
第二组GOA驱动信号的高电平电压小于第三组GOA驱动信号的高电平电压，和/或，第二组GOA驱动信号的低电平电压小于第三组GOA驱动信号的低电平电压。
在另一些示例性实施方式中，第四组GOA驱动信号的高电平电压与第三组GOA驱动信号的高电平电压相等或近似相等，和/或，第四组GOA驱动信号的低电平电压与第三组GOA驱动信号的低电平电压相等或近似相等。
在另一些示例性实施方式中，第五组GOA驱动信号的高电平电压与第三组GOA驱动信号的高电平电压相等或近似相等，和/或，第五组GOA驱动信号的低电平电压与第三组GOA驱动信号的低电平电压相等或近似相等。
本公开实施例中，A和B近似相等指的是A和B的差值的大小在预设的差值阈值范围内。示例性的，预设的差值阈值可以为1。
在另一些示例性实施方式中，第一组GOA驱动信号的高电平电压在9V至10V之间；第二组GOA驱动信号的高电平电压在6V至7V之间；第三组GOA驱动信号的高电平电压在7.5V至8.5V之间；第四组GOA驱动信号的高电平电压在7.5V至8.5V之间；第五组GOA驱动信号的高电平电压在7.5V至8.5V之间。
示例性的，第一组GOA驱动信号的高电平电压可以为9.5V；第二组GOA驱动信号的高电平电压可以为6.5V；第三组GOA驱动信号的高电平电压可以为8V；第四组GOA驱动信号的高电平电压可以为8V；第五组GOA驱动信号的高电平电压可以为8V。
在另一些示例性实施方式中，第一组GOA驱动信号的低电平电压在-6V至-7V之间；第二组GOA驱动信号的低电平电压在-8V至-9V之间；第三组GOA驱动信号的低电平电压在-7V至-8V之间；第四组GOA驱动信号的低电平电压在-7V至-8V之间；第五组GOA驱动信号的低电平电压在-7V至-8V之间。
示例性的，第一组GOA驱动信号的低电平电压可以为-6.5V；第二组GOA驱动信号的低电平电压可以为-8.5V；第三组GOA驱动信号的低电平电压可以为-7.5V；第四组GOA驱动信号的低电平电压可以为-7.5V；第五组GOA驱动信号的低电平电压可以为-7.5V。
图5A为本公开示例性实施例另一种像素驱动电路的等效电路示意图。在另一些示例性实施方式中，如图5A所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C和多个信号线(数据线Data、扫描线Gate、复位线Reset、初始信号线INIT、第一电源线VDD、第二电源线VSS和发光控制线EM)。
在一些示例性实施方式中，第一晶体管T1的控制极与复位线Reset连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管T1的第二极与第一节点N1连接。第二晶体管T2的控制极与扫描线Gate连接，第二晶体管T2的第一极与第三节点N3连接，第二晶体管T2的第二极与第一节点N1连接。第三晶体管T3的控制极与第一节点N1连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。第四晶体管T4的控制极与扫描线Gate连接，第四晶体管T4的第一极与数据线Data连接，第四晶体管T4的第二极与第二节点N2连接。第五晶体管T5的控制极与发光控制线EM连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。第六晶体管T6的控制极与发光控制线EM连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4(即发光元件的第一极)连接。第七晶体管T7的控制极与扫描线Gate或者复位线Reset连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与第四节点N4连接。存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第一节点N1连接。
在一些示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在一些示例性实施方式中，发光元件的第二极与第二电源线VSS连接，第二电源线VSS的信号为持续提供低电平信号，第一电源线VDD的信号为持续提供高电平信号。扫描线Gate为本显示行像素驱动电路中的扫描信号线，复位线Reset为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，扫描线Gate为Gate(n)，复位线Reset为Gate(n-1)，本显示行的复位线Reset与上一显示行像素驱动电路中的扫描线Gate可以为同一信号线，以减少显示面板的信号线，实现显示面板的窄边框。
在一些示例性实施方式中，扫描线Gate、复位线Reset、发光控制线EM和初始信号 线INIT均沿水平方向延伸，第二电源线VSS、第一电源线VDD和数据线Data沿竖直方向延伸。
在一些示例性实施方式中，发光元件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
本示例性实施方式中，第一晶体管T1和第七晶体管T7均可以称为复位晶体管，第二晶体管T2可以称为补偿晶体管，第三晶体管T3可以称为驱动晶体管，第四晶体管T4可以称为数据写入晶体管，第五晶体管T5和第六晶体管T6可以称为发光控制晶体管。
图5B为图5A所示的像素驱动电路的一种工作时序图。下面以图5A中的7个晶体管均为P型晶体管，通过图5B示例的像素驱动电路的工作过程说明本公开示例性实施例。示例性的，该像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，复位线Reset的信号为低电平信号，扫描线Gate和发光控制线EM的信号为高电平信号。复位线Reset的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第一节点N1，对存储电容C进行初始化，清除存储电容中原有数据电压。扫描线Gate和发光控制线EM的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，扫描线Gate的信号为低电平信号，复位线Reset和发光控制线EM的信号为高电平信号，数据线Data输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。扫描线Gate的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据线Data输出的数据电压经过第二节点N2、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第一节点N1，并将数据线Data输出的数据电压与第三晶体管T3的阈值电压之和充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vdata+Vth，Vdata为数据线Data输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。复位线Reset的信号为高电平信号，使第一晶体管T1断开。发光控制线EM的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光控制线EM的信号为低电平信号，扫描线Gate和复位线Reset的信号为高电平信号。发光控制线EM的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其控制极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata+Vth，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdata+Vth-Vdd)-Vth]2＝K*[(Vdata-Vdd)]2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的控制极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vdata为数据线Data输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
由上述公式可以看出，流经发光元件的电流I与第三晶体管T3的阈值电压Vth无关，消除了第三晶体管T3的阈值电压Vth对电流I的影响，保证了亮度的均一性。
基于上述工作时序，该像素电路消除了发光元件在上次发光后残余的正电荷，实现了对第三晶体管栅极电压的补偿，避免了第三晶体管的阈值电压漂移对发光元件驱动电流的影响，提高了显示图像的均匀性和显示面板的显示品质。
在一些示例性实施方式中，多种GOA驱动信号包括用于控制数据写入晶体管开闭的栅极控制信号、用于控制复位晶体管开闭的复位控制信号和用于控制发光控制晶体管开闭的发光控制信号；
多种GOA驱动信号分为两组，其中，第一组包括栅极控制信号，第二组包括发光控制信号。
在一些示例性实施方式中，当复位控制信号与栅极控制信号为相关信号时，第一组GOA驱动信号包括复位控制信号；
当复位控制信号与栅极控制信号为非相关信号时，第二组GOA驱动信号包括所述复位控制信号。
在一些示例性实施方式中，第一组GOA驱动信号的高电平电压大于第二组GOA驱动信号的高电平电压，和/或，第一组GOA驱动信号的低电平电压大于第二组GOA驱动信号的低电平电压。
在又一些示例性实施方式中，像素驱动电路包括驱动晶体管、数据写入晶体管、复位晶体管、发光控制晶体管和补偿晶体管；
多种GOA驱动信号包括用于控制数据写入晶体管开闭的第一栅极控制信号、用于控制补偿晶体管开闭的第二栅极控制信号、用于控制复位晶体管开闭的复位控制信号和用于控制发光控制晶体管开闭的发光控制信号；
多种GOA驱动信号分为三组，其中，第一组包括第一栅极控制信号，第二组包括第二栅极控制信号，第三组包括复位控制信号和发光控制信号。
在一些示例性实施方式中，第一组GOA驱动信号的高电平电压大于第三组GOA驱动信号的高电平电压，和/或，第一组GOA驱动信号的低电平电压大于第三组GOA驱动信号的低电平电压；
第二组GOA驱动信号的高电平电压小于第三组GOA驱动信号的高电平电压，和/或，第二组GOA驱动信号的低电平电压小于第三组GOA驱动信号的低电平电压。
在一些示例性实施方式中，第一组GOA驱动信号的高电平电压在9V至10V之间；第二组GOA驱动信号的高电平电压在6V至7V之间；第三组GOA驱动信号的高电平电压在7.5V至8.5V之间。
示例性的，第一组GOA驱动信号的高电平电压可以为9.5V；第二组GOA驱动信号的高电平电压可以为6.5V；第三组GOA驱动信号的高电平电压可以为8V。
在一些示例性实施方式中，第一组GOA驱动信号的低电平电压在-6V至-7V之间；第二组GOA驱动信号的低电平电压在-8V至-9V之间；第三组GOA驱动信号的低电平电压在-7V至-8V之间。
示例性的，第一组GOA驱动信号的低电平电压可以为-6.5V；第二组GOA驱动信号的低电平电压可以为-8.5V；第三组GOA驱动信号的低电平电压可以为-7.5V。
本公开实施例还提供了一种显示装置，包括：显示面板。
显示面板为前述任一个实施例提供的显示面板，实现原理和实现效果类似，在此不再赘述。
在示例性实施方式中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为 对本申请的限制。
本公开实施例还提供了一种显示面板的驱动方法，包括：
控制多组栅极驱动电路输出多种栅极驱动信号至像素驱动电路中的多个晶体管，其中，所述多种栅极驱动信号至少分为两组，相同组所述栅极驱动信号的高电平电压相同，且相同组所述栅极驱动信号的低电平电压相同；不同组所述栅极驱动信号的高电平电压不同，和/或，不同组所述栅极驱动信号的低电平电压不同。
在一些示例性实施方式中，所述像素驱动电路包括数据写入晶体管、驱动晶体管和发光控制晶体管，其中，所述数据写入晶体管被配置为在扫描线提供的栅极控制信号为有效时，将数据线提供的数据电压写入所述驱动晶体管；所述驱动晶体管被配置为根据所述数据电压产生驱动电流；所述发光控制晶体管被配置为在发光线提供的发光控制信号为有效时，控制所述驱动晶体管产生的驱动电流流过所述发光元件，以驱动所述发光元件发光；
所述多种栅极驱动信号包括用于控制所述数据写入晶体管开闭的栅极控制信号和用于控制所述发光控制晶体管开闭的发光控制信号；
所述多种栅极驱动信号分为两组，其中，第一组栅极驱动信号包括所述栅极控制信号，第二组栅极驱动信号包括所述发光控制信号。
在一些示例性实施方式中，所述第一组栅极驱动信号的高电平电压大于所述第二组栅极驱动信号的高电平电压，和/或，所述第一组栅极驱动信号的低电平电压大于所述第二组栅极驱动信号的低电平电压。
在一些示例性实施方式中，所述像素驱动电路还包括复位晶体管，所述复位晶体管被配置为在复位控制信号为有效时，对以下至少之一进行复位：所述发光元件的阳极、所述驱动晶体管的第一极、所述驱动晶体管的第二极；所述多种栅极驱动信号包括用于控制所述复位晶体管开闭的复位控制信号；
当所述复位控制信号与所述栅极控制信号为相关信号时，所述第一组栅极驱动信号包括所述复位控制信号；
当所述复位控制信号与所述栅极控制信号为非相关信号时，所述第二组栅极驱动信号包括所述复位控制信号。
在一些示例性实施方式中，所述像素驱动电路包括驱动晶体管、数据写入晶体管、复位晶体管、发光控制晶体管和补偿晶体管，其中，所述数据写入晶体管被配置为在第一扫 描线提供的第一栅极控制信号为有效时，将数据线提供的数据电压写入所述驱动晶体管；所述驱动晶体管被配置为根据所述数据电压产生驱动电流；所述发光控制晶体管被配置为在发光线提供的发光控制信号为有效时，控制所述驱动晶体管产生的驱动电流流过所述发光元件，以驱动所述发光元件发光；所述复位晶体管被配置为在复位控制信号为有效时，对以下至少之一进行复位：所述发光元件的阳极、所述驱动晶体管的第一极、所述驱动晶体管的第二极；所述补偿晶体管被配置为在第二扫描线提供的第二栅极控制信号为有效时，对所述驱动晶体管进行阈值补偿；
所述多种栅极驱动信号包括用于控制所述数据写入晶体管开闭的第一栅极控制信号、用于控制所述补偿晶体管开闭的第二栅极控制信号、用于控制所述复位晶体管开闭的复位控制信号和用于控制所述发光控制晶体管开闭的发光控制信号；
所述多种栅极驱动信号分为三组，其中，第一组栅极驱动信号包括所述第一栅极控制信号，第二组栅极驱动信号包括所述第二栅极控制信号，第三组栅极驱动信号包括所述复位控制信号和所述发光控制信号。
在一些示例性实施方式中，所述第一组栅极驱动信号的高电平电压大于所述第三组栅极驱动信号的高电平电压，和/或，所述第一组栅极驱动信号的低电平电压大于所述第三组栅极驱动信号的低电平电压；
所述第二组栅极驱动信号的高电平电压小于所述第三组栅极驱动信号的高电平电压，和/或，所述第二组栅极驱动信号的低电平电压小于所述第三组栅极驱动信号的低电平电压。
在一些示例性实施方式中，所述第一组栅极驱动信号的高电平电压在9V至10V之间；所述第二组栅极驱动信号的高电平电压在6V至7V之间；所述第三组栅极驱动信号的高电平电压在7.5V至8.5V之间。
在一些示例性实施方式中，所述第一组栅极驱动信号的低电平电压在-6V至-7V之间；所述第二组栅极驱动信号的低电平电压在-8V至-9V之间；所述第三组栅极驱动信号的低电平电压在-7V至-8V之间。
在一些示例性实施方式中，所述像素驱动电路包括驱动晶体管、数据写入晶体管、第一复位晶体管、第二复位晶体管、发光控制晶体管和补偿晶体管，其中，所述数据写入晶体管被配置为在第一扫描线提供的第一栅极控制信号为有效时，将数据线提供的数据电压 写入所述驱动晶体管；所述驱动晶体管被配置为根据所述数据电压产生驱动电流；所述发光控制晶体管被配置为在发光线提供的发光控制信号为有效时，控制所述驱动晶体管产生的驱动电流流过所述发光元件，以驱动所述发光元件发光；所述第一复位晶体管被配置为在第一复位控制信号为有效时，对所述驱动晶体管的第二极进行复位；所述第二复位晶体管被配置为在第二复位控制信号为有效时，对所述发光元件的阳极和所述驱动晶体管的第一极进行复位；所述补偿晶体管被配置为在第二扫描线提供的第二栅极控制信号为有效时，对所述驱动晶体管进行阈值补偿；
所述多种栅极驱动信号包括用于控制所述数据写入晶体管开闭的第一栅极控制信号、用于控制所述补偿晶体管开闭的第二栅极控制信号、用于控制所述第一复位晶体管开闭的第一复位控制信号、用于控制所述第二复位晶体管开闭的第二复位控制信号和用于控制所述发光控制晶体管开闭的发光控制信号；
所述多种栅极驱动信号分为五组，其中，第一组包括所述第一栅极控制信号，第二组包括所述第二栅极控制信号，第三组包括所述第一复位控制信号，第四组包括所述第二复位控制信号，第五组包括所述发光控制信号。
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (11)

  1. 一种显示面板，包括：多种栅极驱动电路，还包括阵列排布的多个子像素，所述子像素包括像素驱动电路和发光元件，所述像素驱动电路包括多个晶体管，其中：
    所述多种栅极驱动电路，被配置为输出多种栅极驱动信号至所述像素驱动电路中的多个晶体管，其中，每种所述栅极驱动电路输出一种栅极驱动信号，所述多种栅极驱动信号至少分为两组，相同组所述栅极驱动信号的高电平电压相同，且相同组所述栅极驱动信号的低电平电压相同；不同组所述栅极驱动信号的高电平电压不同，和/或，不同组所述栅极驱动信号的低电平电压不同；
    所述像素驱动电路，被配置为接收所述多种栅极驱动信号，并根据接收到的所述多种栅极驱动信号驱动所述发光元件发光。
  2. 根据权利要求1所述的显示面板，其中，所述像素驱动电路包括数据写入晶体管、驱动晶体管和发光控制晶体管，其中，所述数据写入晶体管被配置为在扫描线提供的栅极控制信号为有效时，将数据线提供的数据电压写入所述驱动晶体管；所述驱动晶体管被配置为根据所述数据电压产生驱动电流；所述发光控制晶体管被配置为在发光线提供的发光控制信号为有效时，控制所述驱动晶体管产生的驱动电流流过所述发光元件，以驱动所述发光元件发光；
    所述多种栅极驱动信号包括用于控制所述数据写入晶体管开闭的栅极控制信号和用于控制所述发光控制晶体管开闭的发光控制信号；
    所述多种栅极驱动信号分为两组，其中，第一组栅极驱动信号包括所述栅极控制信号，第二组栅极驱动信号包括所述发光控制信号。
  3. 根据权利要求2所述的显示面板，其中，所述第一组栅极驱动信号的高电平电压大于所述第二组栅极驱动信号的高电平电压，和/或，所述第一组栅极驱动信号的低电平电压大于所述第二组栅极驱动信号的低电平电压。
  4. 根据权利要求2所述的显示面板，其中，所述像素驱动电路还包括复位晶体管，所述复位晶体管被配置为在复位控制信号为有效时，对以下至少之一进行复位：所述发光元件的阳极、所述驱动晶体管的第一极、所述驱动晶体管的第二极；所述多种栅极驱动信号包括用于控制所述复位晶体管开闭的复位控制信号；
    当所述复位控制信号与所述栅极控制信号为相关信号时，所述第一组栅极驱动信号包括所述复位控制信号；
    当所述复位控制信号与所述栅极控制信号为非相关信号时，所述第二组栅极驱动信号包括所述复位控制信号。
  5. 根据权利要求1所述的显示面板，其中，所述像素驱动电路包括驱动晶体管、数据写入晶体管、复位晶体管、发光控制晶体管和补偿晶体管，其中，所述数据写入晶体管被配置为在第一扫描线提供的第一栅极控制信号为有效时，将数据线提供的数据电压写入所述驱动晶体管；所述驱动晶体管被配置为根据所述数据电压产生驱动电流；所述发光控制晶体管被配置为在发光线提供的发光控制信号为有效时，控制所述驱动晶体管产生的驱动电流流过所述发光元件，以驱动所述发光元件发光；所述复位晶体管被配置为在复位控制信号为有效时，对以下至少之一进行复位：所述发光元件的阳极、所述驱动晶体管的第一极、所述驱动晶体管的第二极；所述补偿晶体管被配置为在第二扫描线提供的第二栅极控制信号为有效时，对所述驱动晶体管进行阈值补偿；
    所述多种栅极驱动信号包括用于控制所述数据写入晶体管开闭的第一栅极控制信号、用于控制所述补偿晶体管开闭的第二栅极控制信号、用于控制所述复位晶体管开闭的复位控制信号和用于控制所述发光控制晶体管开闭的发光控制信号；
    所述多种栅极驱动信号分为三组，其中，第一组栅极驱动信号包括所述第一栅极控制信号，第二组栅极驱动信号包括所述第二栅极控制信号，第三组栅极驱动信号包括所述复位控制信号和所述发光控制信号。
  6. 根据权利要求5所述的显示面板，其中，所述第一组栅极驱动信号的高电平电压大于所述第三组栅极驱动信号的高电平电压，和/或，所述第一组栅极驱动信号的低电平电压大于所述第三组栅极驱动信号的低电平电压；
    所述第二组栅极驱动信号的高电平电压小于所述第三组栅极驱动信号的高电平电压，和/或，所述第二组栅极驱动信号的低电平电压小于所述第三组栅极驱动信号的低电平电压。
  7. 根据权利要求6所述的显示面板，其中，所述第一组栅极驱动信号的高电平电压在9V至10V之间；所述第二组栅极驱动信号的高电平电压在6V至7V之间；所述第三 组栅极驱动信号的高电平电压在7.5V至8.5V之间。
  8. 根据权利要求6所述的显示面板，其中，所述第一组栅极驱动信号的低电平电压在-6V至-7V之间；所述第二组栅极驱动信号的低电平电压在-8V至-9V之间；所述第三组栅极驱动信号的低电平电压在-7V至-8V之间。
  9. 根据权利要求1所述的显示面板，其中，所述像素驱动电路包括驱动晶体管、数据写入晶体管、第一复位晶体管、第二复位晶体管、发光控制晶体管和补偿晶体管，其中，所述数据写入晶体管被配置为在第一扫描线提供的第一栅极控制信号为有效时，将数据线提供的数据电压写入所述驱动晶体管；所述驱动晶体管被配置为根据所述数据电压产生驱动电流；所述发光控制晶体管被配置为在发光线提供的发光控制信号为有效时，控制所述驱动晶体管产生的驱动电流流过所述发光元件，以驱动所述发光元件发光；所述第一复位晶体管被配置为在第一复位控制信号为有效时，对所述驱动晶体管的第二极进行复位；所述第二复位晶体管被配置为在第二复位控制信号为有效时，对所述发光元件的阳极和所述驱动晶体管的第一极进行复位；所述补偿晶体管被配置为在第二扫描线提供的第二栅极控制信号为有效时，对所述驱动晶体管进行阈值补偿；
    所述多种栅极驱动信号包括用于控制所述数据写入晶体管开闭的第一栅极控制信号、用于控制所述补偿晶体管开闭的第二栅极控制信号、用于控制所述第一复位晶体管开闭的第一复位控制信号、用于控制所述第二复位晶体管开闭的第二复位控制信号和用于控制所述发光控制晶体管开闭的发光控制信号；
    所述多种栅极驱动信号分为五组，其中，第一组包括所述第一栅极控制信号，第二组包括所述第二栅极控制信号，第三组包括所述第一复位控制信号，第四组包括所述第二复位控制信号，第五组包括所述发光控制信号。
  10. 一种显示装置，包括如权利要求1至9任一所述的显示面板。
  11. 一种显示面板的驱动方法，包括：
    控制多组栅极驱动电路输出多种栅极驱动信号至像素驱动电路中的多个晶体管，其中，所述多种栅极驱动信号至少分为两组，相同组所述栅极驱动信号的高电平电压相同，且相同组所述栅极驱动信号的低电平电压相同；不同组所述栅极驱动信号的高电平电压不同，和/或，不同组所述栅极驱动信号的低电平电压不同。
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KR20200075488A (ko) * 2018-12-18 2020-06-26 엘지디스플레이 주식회사 픽셀 회로와 이를 이용한 전계 발광 표시장치
CN109584784A (zh) * 2019-01-21 2019-04-05 惠科股份有限公司 一种显示面板的驱动电路、驱动方法及显示装置
CN110808012A (zh) * 2019-11-28 2020-02-18 京东方科技集团股份有限公司 像素电路、移位寄存器单元、栅极驱动电路和显示装置
CN115909962A (zh) * 2021-09-30 2023-04-04 乐金显示有限公司 栅极驱动电路和包括该栅极驱动电路的显示装置
CN116844486A (zh) * 2023-07-26 2023-10-03 京东方科技集团股份有限公司 显示面板及其驱动方法、显示装置

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