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WO2024255060A1 - 信息处理装置 - Google Patents

信息处理装置 Download PDF

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Publication number
WO2024255060A1
WO2024255060A1 PCT/CN2023/126685 CN2023126685W WO2024255060A1 WO 2024255060 A1 WO2024255060 A1 WO 2024255060A1 CN 2023126685 W CN2023126685 W CN 2023126685W WO 2024255060 A1 WO2024255060 A1 WO 2024255060A1
Authority
WO
WIPO (PCT)
Prior art keywords
additional memory
memory module
mainboard
processing unit
connection structure
Prior art date
Application number
PCT/CN2023/126685
Other languages
English (en)
French (fr)
Inventor
方媛
王彦武
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Publication of WO2024255060A1 publication Critical patent/WO2024255060A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • G06F1/184—Mounting of motherboards

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to an information processing device.
  • CAMM Compression Attached Memory Module
  • CAMM connects multiple chips, fixes multiple chips on the motherboard, and electrically connects the motherboard and the chips.
  • the central processing unit electrically connected to the motherboard can write data to the chip or read data from the chip. Compared with traditional memory modules, it is thinner and has better heat dissipation.
  • Signal transmission between the chip and the central processing unit is usually achieved through signal lines located in the motherboard.
  • the number of chips connected to the CAMM increases, which not only increases the thickness of the motherboard and slows down the heat dissipation of the motherboard, but also increases the routing density of the signal lines in the motherboard, resulting in serious crosstalk between signal lines and causing signal distortion.
  • An embodiment of the present disclosure provides an information processing device.
  • An embodiment of the present disclosure provides a signal processing device, comprising: a mainboard having a first surface, the first surface having a central processing unit electrically connected to the mainboard; a compressed additional memory module located on one side of the first surface, at least one surface of the compressed additional memory module having a plurality of chips; an external connection structure located on one side of the first surface, configured to electrically connect the compressed additional memory module and the central processing unit, the central processing unit being configured to read and write data to each of the chips at least via the external connection structure.
  • a mainboard has a plurality of signal lines, each of which electrically connects the central processing unit and the compressed additional memory module, and the central processing unit is configured to read and write data to each of the chips via the signal lines and the external connection structure.
  • the external connection structure is located on a side of the compressed additional memory module facing the central processing unit.
  • a height of the CCAM module relative to the motherboard is greater than a height of the CPU relative to the motherboard.
  • the system further includes: a central processing unit connector, the central processing unit connector is located on the first surface, and a height of the central processing unit connector compared to the mainboard is greater than a height of the central processing unit compared to the mainboard.
  • the height of the CPU connector relative to the motherboard is the same as the height of the CCAM module relative to the motherboard.
  • a bottom surface of a CPU connector facing the first surface is electrically connected to the CPU, and a top surface of the CPU connector away from the first surface is electrically connected to the external connection structure.
  • the motherboard is configured to: electrically connect the central processing unit connector and the central processing unit, the central processing unit and the motherboard are electrically connected via a gold finger or a ball grid array; the central processing unit connector and the external connection structure are electrically connected via any one of a ball grid array, a press-type connector or a silicon interposer.
  • it also includes: a first adapter, located between the mainboard and the compressed additional memory module, for electrically connecting the mainboard and the compressed additional memory module, and the first adapter is also used to electrically connect the external connection structure and the compressed additional memory module.
  • the external connection structure is in electrical contact with a surface of the first adapter facing the CAM module.
  • it also includes: a first adapter, located between the mainboard and the compressed additional memory module, used to electrically connect the mainboard and the compressed additional memory module; a second adapter, located on a side of the compressed additional memory module away from the mainboard, the second adapter electrically connecting the external connection structure and the compressed additional memory module.
  • the number of the compressed additional memory modules is two, the two compressed additional memory modules are stacked in a direction perpendicular to the first surface, and the two compressed additional memory modules are electrically connected to the central processing unit through the same external connection structure.
  • the first adapter is a silicon interposer or a z-axis compression connector; and the external connection structure is a flexible circuit board.
  • the compressed additional memory module has the multiple chips on one of its surfaces along a direction perpendicular to the first surface; or, the compressed additional memory module has the multiple chips on two opposite surfaces along a direction perpendicular to the first surface.
  • it also includes: a top pad, located on the surface of the compressed additional memory module away from the mainboard, the top pad having at least one mounting hole; a bottom pad, fixed to the first surface, the bottom pad is located on the surface of the compressed additional memory module facing the mainboard, the bottom pad having at least one pin corresponding to the mounting hole; a fastener, matching the pin, the fastener is used to fix the pin after the pin passes through the mounting hole, so that the top pad and the bottom pad clamp and fix the compressed additional memory module.
  • FIG1 is a schematic cross-sectional view of a first information processing device provided by an embodiment of the present disclosure
  • FIG2 is a schematic cross-sectional view of a second information processing device provided by an embodiment of the present disclosure
  • FIG3 is a schematic diagram of a three-dimensional structure of an information processing device provided by an embodiment of the present disclosure.
  • FIG4 is a schematic cross-sectional view of a third information processing device provided by an embodiment of the present disclosure.
  • FIG5 is a schematic cross-sectional view of a fourth information processing device provided by an embodiment of the present disclosure.
  • FIG6 is a schematic cross-sectional view of a fifth information processing device provided by an embodiment of the present disclosure.
  • FIG7 is a schematic cross-sectional view of a sixth information processing device provided by an embodiment of the present disclosure.
  • FIG8 is a schematic cross-sectional view of a seventh information processing device provided by an embodiment of the present disclosure.
  • FIG9 is a schematic cross-sectional view of an eighth information processing device provided by an embodiment of the present disclosure.
  • FIG10 is a schematic cross-sectional view of a ninth information processing device provided by an embodiment of the present disclosure.
  • FIG11 is a schematic cross-sectional view of a tenth information processing device provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of the three-dimensional structure of another information processing device provided in an embodiment of the present disclosure.
  • the heat dissipation capacity of the mainboard in the current signal processing device is relatively poor.
  • the number of chips connected to the compressed additional memory module increases, the number of signal lines in the mainboard increases, which in turn leads to an increasing thickness of the mainboard, resulting in a significant reduction in the heat dissipation capacity of the mainboard.
  • the disclosed embodiment provides a signal processing device, in which an external connection structure is arranged on one side of the first surface of a mainboard, and is used to electrically connect a compressed additional memory module and a central processing unit. That is, the external connection structure is routed from the outside of the mainboard to connect the compressed additional memory module and the central processing unit.
  • the number of signal lines in the mainboard for electrically connecting the central processing unit and the compressed additional memory module can be reduced, and even the arrangement of signal lines in the mainboard can be omitted, thereby greatly reducing the thickness of the mainboard and greatly increasing the heat dissipation capacity of the mainboard.
  • FIG1 is a schematic cross-sectional structure diagram of a first information processing device provided by an embodiment of the present disclosure.
  • the signal processing device includes: a mainboard 101 having a first surface, the first surface having a central processing unit 102 electrically connected to the mainboard 101.
  • the signal processing device also includes: a compressed additional memory module 103 located on one side of the first surface, at least one surface of the compressed additional memory module 103 having a plurality of chips 104.
  • the signal processing device also includes: an external connection structure 105 located on one side of the first surface, configured to: electrically connect the compressed additional memory module 103 and the central processing unit 102, and the central processing unit 102 is configured to: read and write data to each chip 104 at least via the external connection structure 105.
  • the central processing unit 102 is the computing and control core of the computer system and is the final execution unit for information processing and program running.
  • the mainboard 101 is also called a motherboard, and can be used as a carrier for the central processing unit 102 and the compressed additional memory module 103, and realizes the electrical connection between the central processing unit 102 and the compressed additional memory module 103.
  • the mainboard 101 can be a system board, a logic board or any other printed circuit board.
  • the compression attached memory module 103 namely “Compression Attached Memory Module”, referred to as CAMM, is a new form of notebook memory different from the traditional SO-DIMM. Its structure includes: a PCB circuit board, and a chip 104 that can be installed on both sides.
  • the central processing unit 102 When the central processing unit 102 writes data to the chip 104, it can send the address information through the address line, then send a memory write command through the control line, select the chip 104, and write data to the selected chip 104 through the external connection structure 105.
  • the central processing unit 102 reads data from the chip 104, it sends the address information through the address line, then sends a memory read command through the control line, selects the chip 104, and the selected chip 104 sends the data in the chip 104 to the central processing unit 102 through the external connection structure 105.
  • chip 104 may include any one of DRAM (Dynamic Random Access Memory), SRAM (Static Random-Access Memory) or SDRAM (Synchronous Dynamic Random-Access Memory).
  • DRAM Dynamic Random Access Memory
  • SRAM Static Random-Access Memory
  • SDRAM Synchronous Dynamic Random-Access Memory
  • the chip 104 may be a DRAM, specifically some variant of synchronous DRAM, such as DDR3 (DDR version 3), DDR4 (DDR version 4), DDR5 (DDR version 5), LPDDR3 (low power DDR version 3), LPDDR4 (LPDDR version 4), LPDDR5 (LPDDR version 5), or other or a combination of memory technologies.
  • DDR3 DDR version 3
  • DDR4 DDR version 4
  • DDR5 DDR version 5
  • LPDDR3 low power DDR version 3
  • LPDDR4 LPDDR version 4
  • LPDDR5 LPDDR version 5
  • the external connection structure 105 is located on one side of the first surface of the mainboard 101. It is placed outside the motherboard 101 to realize the electrical connection between the central processing unit 102 and the compressed additional memory module 103. Since the chip 104 is electrically connected to the compressed additional memory module 103, the central processing unit 102 can read and write data to the chip 104 through the external connection structure 105 and the compressed additional memory module 103.
  • FIG2 is a schematic cross-sectional structural diagram of a second signal processing device provided in an embodiment of the present disclosure
  • FIG3 is a schematic three-dimensional structural diagram of an information processing device provided in an embodiment of the present disclosure.
  • a plurality of signal lines 10 are provided in the mainboard 101 , each signal line 10 electrically connects the central processing unit 102 and the compressed additional memory module 103 , and the central processing unit 102 is configured to read and write data to each chip 104 via the signal line 10 and the external connection structure 105 . That is, the external connection structure 105 and the signal line 10 can both realize the signal transmission between the central processing unit 102 and the chip 104 , the signal line 10 is located inside the mainboard 101 , and the external connection structure 105 is located outside the mainboard 101 , so that the number of signal lines 10 in the mainboard 101 can be greatly reduced.
  • the volume occupied by the signal line 10 in the mainboard 101 can be reduced, the thickness of the mainboard 101 can be reduced, and the heat dissipation of the mainboard 101 can be enhanced.
  • the routing density of the signal line 10 in the mainboard 101 is greatly reduced, thereby avoiding the crosstalk problem between the signals transmitted in different signal lines 10 caused by the excessive routing density of the signal line 10 , and avoiding the distortion of the transmitted signals in the signal line 10 .
  • the flexibility of the wiring of the external connection structure 105 and the signal line 10 can be enhanced, which can avoid the problem of too dense routing of the external connection structure 105 and the problem of too dense routing of the signal line 10, and greatly reduce the risk of signal distortion caused by excessive routing density.
  • the mainboard 101 further has a plurality of signal lines 10
  • the signal processing device further includes: a first pin 21, located on the first surface, and the central processing unit 102 is electrically connected to the first pin 21 to achieve electrical connection with the mainboard 101.
  • the signal line 10 is electrically connected to a portion of the first pin 21, and further electrically connected to the central processing unit 102 and the compressed additional memory module 103.
  • the signal processing device further includes: a second pin 22, located on the first surface, the second pin 22 is electrically connected to the remaining first pin 21, and the second pin 22 is electrically connected to the external connection structure 105, so as to realize the electrical connection between the central processing unit 102 and the external connection structure 105.
  • the mainboard 101 further includes a first lead 20, the first lead 20 is used to electrically connect the first pin 21 and the second pin 22, so that the second pin 22 can be electrically connected to the central processing unit 102, and then the external connection structure 105 electrically connected to the second pin 22 can be electrically connected to the central processing unit 102.
  • the second pin 22 is located on the first surface between the central processing unit 102 and the compressed additional memory module 103, and is disposed adjacent to the first pin 21, so that the length of the first lead 20 in the mainboard 101 is shorter, reducing the transmission loss of the signal transmitted in the first lead 20. And because the length of the first lead 20 is shorter, the loss of the signal transmitted in the first lead 20 is smaller, therefore, the diameter of the first lead 20 can be set smaller, reducing the volume occupied by the first lead 20 in the mainboard 101, and avoiding the increase in the thickness of the mainboard 101 due to the setting of the first lead 20.
  • the diameter of the first lead 20 may be smaller than the diameter of the signal line 10. In this way, it can be ensured that the provision of the first lead 20 will not cause a further increase in the thickness of the mainboard 101.
  • the signal line 10 may not be provided in the mainboard 101, so that the chip 104 and the central processor 102 transmit signals only through the external connection structure 105. In this way, the thickness of the mainboard 101 can be greatly reduced, and the heat dissipation of the mainboard 101 can be further enhanced.
  • the chip 104 and the central processing unit 102 transmit signals only through the external connection structure 105, and the signal processing device further includes: a first pin located on the first surface, and the central processing unit 102 is electrically connected to the first pin to achieve electrical connection with the mainboard 101.
  • the signal processing device further includes: a second pin, located on the first surface, the second pin being electrically connected to the first pin, and the second pin being electrically connected to the external connection structure 105, so as to realize the electrical connection between the central processing unit 102 and the external connection structure 105.
  • the mainboard 101 further includes a first lead, and the first lead is used to electrically connect the first pin and the second pin.
  • the first pin may be a gold finger or a ball grid array
  • the second pin may be a gold finger or a ball grid array
  • the gold finger is a structure composed of multiple golden conductive contacts. It is called a gold finger because its surface is gold-plated and the conductive contacts are arranged like fingers.
  • the ball grid array is a spherical contact made in an array on the first surface of the mainboard 101.
  • the spherical contact can be an array of solder balls.
  • Both the gold fingers and the ball grid array can be formed on the first surface in a manner well known to those skilled in the art, and are in electrical contact with the CPU 102 .
  • the first lead 20 may be formed in the mainboard 101 by electroplating.
  • the embodiment of the present disclosure does not limit the specific routing method and shape of the first lead 20 in the mainboard 101, and only needs to satisfy that the first lead 20 can electrically connect the first pin 21 and the second pin 22.
  • the material of the first lead 20 may be a metal material, for example, may be at least one of copper, tungsten, nickel, silver, copper, or other conductive materials known to those skilled in the art.
  • the external connection structure 105 is located on the side of the compressed additional memory module 103 facing the central processing unit 102.
  • the central processing unit 102 and the compressed additional memory module 103 are both located on the first surface, and the central processing unit 102 and the compressed additional memory module 103 are arranged opposite to each other.
  • the external connection structure 105 can be located between the central processing unit 102 and the compressed additional memory module 103.
  • the external connection structure 105 is located on the side of the compressed additional memory module 103 facing the central processing unit 102, that is, the external connection structure 105 is directly opposite to the compressed additional memory module 103, and the height of the external connection structure 105 compared to the first surface is not higher than the height of the compressed additional memory module 103 compared to the first surface.
  • the external connection structure 105 can be set by using the empty space between the compressed additional memory module 103 and the central processing unit 102, and because the height of the external connection structure 105 is not higher than the height of the compressed additional memory module 103, the external connection structure 105 It does not occupy too much extra volume, thus preventing the problem that the thickness of the information processing device cannot be further reduced due to the excessive thickness of the external connection structure 105.
  • the height of the CAM module relative to the motherboard 101 is greater than the height of the CPU 102 relative to the motherboard 101.
  • the height of the surface of the CAM module 103 away from the motherboard 101 relative to the first surface is greater than the height of the surface of the CPU 102 away from the motherboard 101 relative to the first surface.
  • the signal processing device further includes: a central processing unit connector 106, the central processing unit connector 106 is located on the first surface, and the central processing unit connector 106 is used to electrically connect the external connection structure 105 and the central processing unit 102.
  • the central processing unit connector 106 is located between the central processing unit 102 and the compressed additional memory module 103, and is disposed adjacent to the central processing unit 102, so that the distance between the central processing unit connector 106 and the central processing unit 102 is short, which is conducive to enhancing the electrical transmission performance between the central processing unit 102 and the external connection structure 105.
  • the bottom surface of the CPU connector 106 facing the first surface is electrically connected to the CPU 102, and the top surface of the CPU connector 106 away from the first surface is electrically connected to the external connection structure 105. Then the bottom surface of the CPU connector 106 is in electrical contact with the gold finger or ball grid array located on the first surface, the top surface of the CPU connector 106 has a ball grid array or a press-type connector, and the CPU connector 106 is in electrical contact with the external connection structure 105 through any one of the ball grid array, press-type connector or silicon interposer located on the top surface.
  • One end of the external connection structure 105 is electrically connected to the central processing unit 102, and the other end is electrically connected to the compressed additional memory module 103. That is, the external connection structure 105 extends in the direction from the central processing unit 102 to the compressed additional memory module 103. Since the height of the compressed additional memory module 103 relative to the first surface is higher than the height of the central processing unit 102 relative to the first surface, there is a large height difference between the compressed additional memory module 103 and the central processing unit 102. This may cause the heights of the two ends of the external connection structure 105 to be inconsistent, resulting in the problem that the external connection structure 105 is tilted relative to the first surface, and further resulting in a larger space occupied by the external connection structure 105.
  • the height of the CPU connector 106 relative to the motherboard 101 is greater than the height of the CPU 102 relative to the motherboard 101.
  • the height of the surface of the CPU connector 106 away from the motherboard 101 relative to the motherboard 101 is greater than the height of the surface of the CPU 102 away from the motherboard 101 relative to the motherboard 101.
  • the height difference between the CPU connector 106 and the compression additional memory module 103 is smaller than the height difference between the CPU 102 and the compression additional memory module 103.
  • the external connection structure 105 is electrically connected to the CPU connector 106, compared with being directly connected to the CPU 102, the height difference between the external connection structure 105 and the compression additional memory module 103 is smaller, so that the inclination of the external connection structure 105 relative to the first surface is not too large, thereby improving the problem of the large space occupied by the external connection structure 105.
  • the bottom surface of the CPU connector 106 facing the first surface is electrically connected to the CPU 102, and the top surface of the CPU connector 106 away from the first surface is electrically connected to the external connection structure 105.
  • the height of the external connection structure 105 is higher than the height of the CPU connector 106, which can minimize the The height difference between the external connection structure 105 and the compressed additional memory module 103.
  • the two ends of the external connection structure 105 are electrically connected to the central processing unit connector 106 and the compressed additional memory module 103 respectively, reducing the height difference between the external connection structure 105 and the compressed additional memory module 103 can make the height difference between the two ends of the external connection structure 105 smaller, or even 0, so that the external connection structure 105 can be placed horizontally or nearly horizontally, and the horizontal placement referred to here is placed parallel to the first surface.
  • the external connection structure 105 Compared with the external connection structure 105 being placed obliquely relative to the first surface, the external connection structure 105 is placed horizontally, which is conducive to maintaining the stability of the external connection structure 105 on the one hand, and on the other hand, the space occupied by the external connection structure 105 is smaller, which can provide more space for the arrangement of other components on the surface of the mainboard 101, which is conducive to the arrangement of wiring.
  • the height of the central processing connector relative to the mainboard 101 is the same as the height of the compressed additional memory module 103 relative to the mainboard 101.
  • the height of the surface of the central processing connector 106 away from the mainboard 101 relative to the first surface is the same as the height of the surface of the compressed additional memory module 103 relative to the mainboard 101 relative to the first surface.
  • the two ends of the external connection structure 105 electrically connecting the central processing connector 106 and the compressed additional memory module 103 are close to each other in height relative to the first surface, so that the height difference between the two ends of the external connection structure 105 is small, or even zero.
  • the external connection structure 105 can be arranged roughly parallel to the first surface, so that the space occupied by the external connection structure 105 on one side of the first surface is small.
  • the height of the CPU connector 106 relative to the motherboard 101 is the same as the height of the compressed additional memory module 103 relative to the motherboard 101. It may also be that the height of the surface of the CPU connector 106 away from the motherboard 101 relative to the first surface is the same as the height of the surface of the compressed additional memory module 103 facing the motherboard 101 relative to the first surface.
  • the height of the surface of the CPU connector 106 away from the motherboard 101 compared to the first surface may be different from the height of the surface of the compression additional memory module 103 away from the motherboard 101 compared to the first surface.
  • the height of the surface of the CPU connector 106 away from the motherboard 101 compared to the first surface may be slightly higher than the height of the surface of the compression additional memory module 103 away from the motherboard 101 compared to the first surface.
  • the height of the surface of the CPU connector 106 away from the motherboard 101 compared to the first surface may be slightly lower than the height of the surface of the compression additional memory module 103 away from the motherboard 101 compared to the first surface.
  • the motherboard 101 is configured as follows: the central processing unit connector 106 is electrically connected to the central processing unit 102, and the central processing unit 102 is electrically connected to the motherboard 101 through a gold finger or a ball grid array; the central processing unit connector 106 and the external connection structure 105 are electrically connected through any one of a ball grid array, a press-type connector or a silicon interposer.
  • the first surface is provided with a gold finger or a ball grid array, and the first surface is also provided with a first pin 21, and the first pin 21 is used to electrically connect the CPU 102 and the motherboard 101.
  • the motherboard 101 is also provided with a first lead 20, and the first lead 20 is used to lead the signal of the first pin 21 to the gold finger or the ball grid array on the first surface, and further lead it to the CPU connector 106 through the gold finger or the ball grid array.
  • the first lead 20 The material may be a metal material, for example, may be at least one of copper, tungsten, nickel, silver, copper or other conductive materials known to those skilled in the art.
  • the surface of the CPU connector 106 is provided with a ball grid array, a press-type connector or a silicon interposer, and the CPU 102 is provided with a connection structure inside, which is used to transmit the signal of the CPU 102 to the ball grid array or the press-type connector located on the surface of the CPU connector 106, and then transmit it to the external connection structure 105 via the ball grid array or the press-type connector.
  • a silicon interposer is disposed on the surface of the CPU connector 106, and the silicon interposer includes a through silicon via, which penetrates the silicon interposer along the thickness direction of the silicon interposer.
  • the bottom end of the through silicon via is electrically contacted with the connection structure in the CPU connector 106, and the top end of the through silicon via is electrically connected to the external connection structure 105.
  • connection structure may be a second lead.
  • the embodiment of the present disclosure does not limit the specific routing method and shape of the second lead in the CPU connector 106. It is only necessary that the second lead can lead the signal from the CPU 102 to any one of the ball grid array, the press-type connector or the silicon interposer located on the surface of the CPU connector 106.
  • the material of the second lead may be at least one of copper, tungsten, nickel, silver, copper or other conductive materials known to those skilled in the art.
  • the signal processing device further includes: a first adapter 107, located between the mainboard 101 and the compressed additional memory module 103, for electrically connecting the mainboard 101 and the compressed additional memory module 103, and the first adapter 107 is also used to electrically connect the external connection structure 105 and the compressed additional memory module 103.
  • the external connection structure 105 and the mainboard 101 share the same first adapter 107, so that space can be saved.
  • the external connection structure 105 and the mainboard 101 share the same first adapter 107, and the mainboard 101 has a plurality of signal lines 10, each of which is electrically connected to the central processing unit 102 and the compressed additional memory module 103.
  • the signal lines 10 in the mainboard 101 are electrically connected to the first adapter 107, and the external connection structure 105 is electrically connected to the first adapter 107, and both the signal lines 10 and the external connection structure 105 can realize signal transmission between the central processing unit 102 and the chip 104.
  • the external connection structure is in electrical contact with the surface of the first adapter 107 facing the compression additional memory module 103.
  • the signal line 10 is electrically connected to the surface of the first adapter 107 facing the motherboard 101
  • the external connection structure 105 is electrically connected to the surface of the first adapter 107 facing the compression additional memory module 103.
  • the external connection structure 105 and the signal line 10 are respectively located on two opposite surfaces of the first adapter 107, avoiding the signal crosstalk problem between the external connection structure 105 and the signal line 10 due to the external connection structure 105 and the signal line 10 being located on the same surface of the first adapter 107.
  • the side of the first adapter 107 facing the compression additional memory module 103 is also electrically connected to the compression additional memory module 103 , so that the signals transmitted in the external connection structure 105 and the signal line 10 can be transmitted to the compression additional memory module 103 .
  • the compressed additional memory module 103 has: a first routing line 41, the first routing line 41 is used to electrically connect the first connecting line and the chip 104, and the first routing line 41 is also used to electrically connect the first adapter 107, that is, the first adapter 107 is electrically connected to the first routing line 41 on the side facing the compressed additional memory module 103, and the first routing line 41 is used to transmit the transmission signal from the first adapter 107 and transmit it to the chip 104, or the signal in the chip 104 can be transmitted to the first adapter 107 through the first routing line 41.
  • the first adapter 107 may be a silicon interposer or a z-axis compression connector.
  • the external connection structure 105 may be a flexible circuit board.
  • the first adapter 107 is a first silicon interposer
  • the first silicon interposer includes a first through silicon via 111
  • the first through silicon via 111 penetrates the first silicon interposer along the thickness direction of the first silicon interposer
  • the first silicon interposer exposes the top and bottom ends of the first through silicon via 111
  • the signal line 10 is electrically connected to the first through silicon via 111 toward the bottom end of the mainboard 101
  • the first through silicon via 111 is electrically connected to the first trace 41 away from the top end of the mainboard 101.
  • the surface of the first silicon interposer away from the mainboard may further include: a third pin 31, the third pin 31 is electrically in contact with the top of the first through silicon via 111, and the side of the external connection structure 105 facing the first silicon interposer is electrically connected to the third pin 31. Since the third pin 31 is electrically in contact with the top of the first through silicon via 111, and the bottom of the first through silicon via 111 is electrically connected to the signal line 10, the external connection structure 105 and the signal line can also be electrically connected. In this way, the signal transmitted in the signal line can also be transmitted to the compressed additional memory module 103 via the external connection structure 105. The remaining third pin 31 is in electrical contact with the compressed additional memory module 103, and is used to input the signal transmitted in the signal line in the mainboard into the compressed additional memory module 103.
  • the third pin 31 can be any one of a gold finger or a ball grid array
  • the electrical connection structure can be a conductive metal wire
  • the material of the electrical connection structure can be at least one of copper, tungsten, nickel, silver, copper or other conductive materials known to those skilled in the art.
  • the flexible circuit board is a highly reliable and highly flexible printed circuit board made of polyimide or polyester film as a substrate, and has the characteristics of high wiring density, light weight, thin thickness, and good bendability.
  • Using a flexible circuit board as the external connection structure 105 can prevent the problem of failure of the external connection structure 105 caused by bending the external connection structure 105 during the packaging step.
  • the thickness of the flexible circuit board is relatively thin, which prevents the external connection structure 105 from occupying too much space, making the overall thickness of the signal processing device relatively small. It is conducive to miniaturization of the device and to enhancing the overall heat dissipation capacity of the signal processing device.
  • the mainboard 101 and the external connection structure 105 may not share the same first adapter 107
  • the signal processing device includes: a first adapter 107, located between the mainboard 101 and the compressed additional memory module 103, and used to electrically connect the mainboard 101 and the compressed additional memory module 103; a second adapter 108, located on a side of the compressed additional memory module 103 away from the mainboard 101, and the second adapter 108 electrically connects the external connection structure 105 and the compressed additional memory module 103.
  • the first adapter 107 and the second adapter 108 are respectively located on opposite sides of the compressed additional memory module 103, the first adapter 107 is only electrically connected to the signal line 10, and the second adapter 108 is only electrically connected to the external connection structure 105, so that the wiring density of the wiring used for signal transmission in the first adapter 107 and the second adapter 108 is relatively small, which can avoid the problem of signal crosstalk caused by excessive wiring density in the first adapter 107 and the second adapter 108.
  • the signal line 10 in the mainboard 101 is electrically connected to a side of the first adapter 107 facing the mainboard 101, and a side of the first adapter 107 away from the mainboard 101 is electrically connected to the compression additional memory module 103.
  • the external connection structure 105 is electrically connected to a side of the second adapter 108 away from the compression additional memory module 103, and a side of the second adapter 108 facing the compression additional memory module 103 is electrically connected to the compression additional memory module 103.
  • the side that is closer to the compressed additional memory module 103 is electrically connected to the compressed additional memory module 103
  • the side that is closer to the compressed additional memory module 103 is electrically connected to the compressed additional memory module 103.
  • the wiring distance between the first adapter 107 and the compressed additional memory module 103 can be reduced, as well as the wiring distance between the second adapter 108 and the compressed additional memory module 103, which is beneficial to saving wiring length.
  • the first adapter 107 is a first silicon interposer
  • the first silicon interposer includes a first through silicon via 111
  • the first through silicon via 111 penetrates the first silicon interposer along the thickness direction of the first silicon interposer
  • the first silicon interposer exposes the top and bottom of the first through silicon via 111
  • the signal line 10 is electrically connected to the bottom of the first through silicon via 111 facing the mainboard 101
  • the top of the first through silicon via 111 away from the mainboard 101 is electrically connected to the compression additional memory module 103.
  • the second adapter 108 is a second silicon interposer, the second silicon interposer includes a second through silicon via 112, the second through silicon via 112 penetrates the second silicon interposer along the thickness direction of the second silicon interposer, and the second silicon interposer exposes the top and bottom of the second through silicon via 112.
  • the bottom of the second through silicon via 112 is directly opposite to the surface of the compression additional memory module 103 away from the mainboard 101, and is electrically connected to the side of the compression additional memory module 103 away from the mainboard 101.
  • the external connection structure 105 is electrically connected to the top of the second through silicon via 112.
  • the information processing device includes a first adapter 107 and a second adapter 108
  • the compressed additional memory module 103 has: a first routing line 41, the first routing line 41 is used to electrically connect the first connecting line and the chip 104, and the first routing line 41 is also used to electrically connect the first adapter 107; a second routing line 42, the second routing line 42 is used to electrically connect the external connection structure 105 and the chip 104, and the second routing line 42 is also used to electrically connect the second adapter 108.
  • the compressed additional memory module 103 includes a third surface and a fourth surface opposite to each other, the fourth surface is directly opposite to the first surface, and the first trace 41 and the second trace 42 are arranged at intervals in a direction parallel to the third surface.
  • the second trace 42 and the first trace 41 are arranged horizontally, so that the second trace 42 and the first trace 41 do not occupy the space in the thickness direction of the compressed additional memory module 103.
  • the second trace 42 and the first trace 41 are arranged at intervals in a direction parallel to the third surface, which greatly reduces the thickness of the compressed additional memory module 103.
  • the top of the first TSV 111 is electrically connected to the first trace 41
  • the top of the second TSV 112 is electrically connected to the first trace 41
  • the bottom end is electrically connected to the second trace 42 , wherein the top end of the first through silicon via 111 faces the third surface, and the bottom end of the second through silicon via 112 faces the fourth surface.
  • the compressed additional memory module has a plurality of chips 104 on one of the surfaces along a direction perpendicular to the first surface.
  • the compressed additional memory module 103 includes a third surface and a fourth surface opposite to each other, and the third surface is directly opposite to the first surface.
  • the plurality of chips 104 may be located only on the third surface or only on the fourth surface.
  • Each chip 104 may be electrically connected to either the external connection structure 105 or the signal line 10, that is, the central processing unit 102 may read and write data to a chip 104 through either the external connection structure 105 or the signal line 10.
  • the CAM 103 has multiple chips 104 on two opposite surfaces along a direction perpendicular to the first surface. That is, the third surface and the fourth surface both have multiple chips 104, so that the integration of the chips 104 can be improved.
  • the signal processing device includes: a first adapter 107 and a second adapter 108, the first adapter 107 is located on one side of the third surface, the second adapter 108 is located on one side of the fourth surface, the external connection structure 105 is electrically connected to the second adapter 108, and the signal line 10 is electrically connected to the first adapter 107. Then the second adapter 108 can be electrically connected to the chip 104 on the fourth surface, that is, the central processing unit 102 reads and writes data to the chip 104 on the fourth surface through the external connection structure 105.
  • the first adapter 107 can be electrically connected to the chip 104 on the third surface, and the central processing unit 102 can read and write data to the chip 104 on the third surface through the signal line 10 in the motherboard 101. In this way, the wiring length can be saved and the wiring can be simplified.
  • each of the plurality of chips 104 located on the third surface may also be electrically connected to either the external connection structure 105 or the signal line 10.
  • Each of the plurality of chips 104 located on the fourth surface may also be electrically connected to either the external connection structure 105 or the signal line 10.
  • the number of the compressed additional memory modules is two, the two compressed additional memory modules 103 are stacked in a direction perpendicular to the first surface, and the two compressed additional memory modules 103 are electrically connected to the central processing unit 102 through the same external connection structure 105.
  • At least one surface of each of the two compressed additional memory modules 103 has a plurality of chips 104, and through the same external connection structure 105, the central processing unit 102 can read and write data to the chip 104 located on the surface of any compressed additional memory module 103, and the number of chips 104 electrically connected to the central processing unit 102 is increased while ensuring that the number of external connection structures 105 does not increase, thereby improving the integration of the chips 104.
  • the external connection structure 105 is arranged outside the mainboard 101, the number of signal lines 10 in the mainboard 101 can be reduced, or even the arrangement of the signal lines 10 in the mainboard 101 can be omitted.
  • the heat dissipation capacity of the mainboard 101 can be enhanced, which is beneficial to ensuring the excellent performance of the mainboard 101 and ensuring that the information processing device has a higher operating speed.
  • the two compressed additional memory modules 103 are respectively recorded as: a first compressed additional memory module 121 and a second compressed additional memory module 122, the first compressed additional memory module 121 is adjacent to the first surface, and the second compressed additional memory module 122 is adjacent to the first surface.
  • the additional memory module 122 is located at a side of the first compressed additional memory module 121 away from the mainboard 101 .
  • the information processing device may include: a first adapter 107 and a second adapter 108.
  • the first adapter 107 is located between the first compressed additional memory module 121 and the first surface, and is used to electrically connect the mainboard 101 and the first compressed additional memory module 121.
  • the second adapter 108 is located between the first compressed additional memory module 121 and the second compressed additional memory module 122, and is used to electrically connect the external connection structure 105.
  • the second adapter 108 is electrically connected to the first compressed additional memory module 121 and the second compressed additional memory module 122, and is used to transmit the signal in the external connection structure 105 to the first compressed additional memory module 121 and the second compressed additional memory module 122, respectively.
  • the first adapter 107 may be a first silicon interposer
  • the second adapter 108 may be a second silicon interposer
  • the first silicon interposer includes a first through silicon via 111
  • the first through silicon via 111 runs through the first silicon interposer
  • the top of the first through silicon via 111 is electrically connected to the first compressed additional memory module 121
  • the bottom of the first through silicon via 111 is electrically connected to the mainboard 101.
  • the mainboard 101 may have a signal line 10
  • the signal line 10 is electrically connected to the central processing unit 102
  • the bottom of the first through silicon via 111 may be electrically connected to the signal line 10.
  • the second silicon interposer includes a second through silicon via 112 , which penetrates the second silicon interposer, a top end of the second through silicon via 112 is electrically connected to the second compression additional memory module 122 , and a bottom end of the second through silicon via 112 is electrically connected to the first compression additional memory module 121 .
  • the surface of the second silicon interposer may include: a fourth pin 32, the fourth pin 32 is located on either a surface of the second silicon interposer away from the mainboard 101 or a surface of the second silicon interposer facing the mainboard 101.
  • the surface of the external connection structure 105 facing the second silicon interposer is in electrical contact with the third pin 31, so that the signal transmitted in the external connection structure 105 can be transmitted to the second silicon through via 112 through the third pin 31, and finally transmitted to the first compressed additional memory module 121 through the second silicon through via 112.
  • the second compressed additional memory module 122 may include a fifth pin 33 facing the surface of the second silicon interposer, and the fifth pin 33 is electrically contacted with the surface of the external connection structure facing the second compressed additional memory module 122, so that the signal transmitted in the external connection structure 105 can be transmitted to the second compressed additional memory module 122 through the fifth pin 33.
  • the fourth pin 32 may be any one of a gold finger or a ball grid array
  • the electrical connection structure may be a conductive metal wire
  • the material of the electrical connection structure may be at least one of copper, tungsten, nickel, silver, copper, or other conductive materials known to those skilled in the art.
  • the fifth pin 33 may be any one of a gold finger or a ball grid array
  • the electrical connection structure may be a conductive metal wire
  • the material of the electrical connection structure may be at least one of copper, tungsten, nickel, silver, copper, or other conductive materials known to those skilled in the art.
  • the signal processing device further includes: a top pad 11, located on the surface of the compressed additional memory module 103 away from the mainboard 101, and having at least one mounting hole 13; a bottom pad 12, fixed to the first surface, located on the surface of the compressed additional memory module 103 facing the mainboard 101, and having at least one latch 14 corresponding to the mounting hole 13; a fastener 15, matching with the latch 14, and used to fasten the latch 14 to the bottom surface of the first surface; and a fastener 15, matching with the latch 14, and used to fasten the latch 14 to the bottom surface of the first surface.
  • the top pad 11 may have two mounting holes 13, and the bottom pad 12 may also have two latches 14, each latch 14 corresponding to a mounting hole 13.
  • the two mounting holes 13 are respectively located on opposite sides of the top pad 11, so that the mounting stability of the top pad and the bottom pad 12 can be improved.
  • the top pad 11 may have more than two mounting holes 13, and the bottom pad 12 may have more than two latches 14; or the top pad 11 may have only one mounting hole 13, and the bottom pad 12 may have only one latch 14. It is only necessary to match the number of mounting holes 13 with the number of latches 14. The number of mounting holes 13 and latches 14 can be flexibly set according to different requirements.
  • the latch 14 may be a wire screw sleeve, which is an internal thread fastener 15 having an internal thread on the inside.
  • the fastener 15 may be any screw, which can be locked with the wire screw sleeve by being screwed into the inside of the wire screw sleeve, and then after the wire screw sleeve is inserted into the mounting hole 13, the wire screw sleeve is fixed in the mounting hole 13 to prevent the wire screw sleeve from slipping out of the mounting hole 13.
  • the pin 14 may also be a bolt
  • the fastener 15 may also be a nut.
  • the side of the bolt has an external thread
  • the inside of the nut has an internal thread that matches the external thread on the outside of the bolt.
  • an external connection structure 105 is arranged on one side of the first surface of the mainboard 101, and is used to electrically connect the compressed additional memory module 103 and the central processing unit 102. That is, the external connection structure 105 is routed from the outside of the mainboard 101, and is connected to the compressed additional memory module 103 and the central processing unit 102.
  • the number of signal lines 10 in the mainboard 101 for electrically connecting the central processing unit 102 and the compressed additional memory module 103 can be reduced, and even the arrangement of the signal lines 10 in the mainboard 101 can be omitted, thereby greatly reducing the thickness of the mainboard 101, so that the heat dissipation path of the mainboard 101 is greatly reduced, which is conducive to enhancing the heat dissipation of the mainboard 101.

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Abstract

一种信息处理装置，包括：主板（101），具有第一表面，第一表面具有与主板（101）电连接的中央处理器（102）；压缩附加内存模块（103），位于第一表面的一侧，压缩附加内存模块（103）的至少一个表面具有多个芯片（104）；外部连接结构（105），位于第一表面的一侧，被配置为：电连接压缩附加内存模块（103）以及中央处理器（102），中央处理器（102）被配置为：至少经由外部连接结构（105）向每一芯片（104）中读写数据。

Description

信息处理装置
交叉引用
本申请要求于2023年06月16日递交的名称为“信息处理装置”、申请号为202310728159.4的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本公开实施例涉及半导体技术领域，特别涉及一种信息处理装置。
背景技术
CAMM(Compression Attached Memory Module，压缩内存附加模块)是一种新型的内存模块，CAMM连接多个芯片，将多个芯片固定在主板上，并电连接主板与芯片。与主板电连接的中央处理器能够向芯片写入数据或者从芯片中读出数据。相较于传统的内存模块而言，具有更薄、散热型更优的特点。
芯片与中央处理器之间的信号传输通常是通过位于主板内的信号线实现，然而，随着CAMM连接的芯片的数量越来越多，主板内的信号线的数量越来越多，这不仅使得主板的厚度增加，使得主板的散热较慢，还使得主板内的信号线的走线密度较大，导致信号线之间的串扰严重，引发信号畸变。
发明内容
本公开实施例提供一种信息处理装置。
本公开实施例提供一种信号处理装置，包括：主板，具有第一表面，所述第一表面具有与所述主板电连接的中央处理器；压缩附加内存模块，位于所述第一表面的一侧，所述压缩附加内存模块的至少一个表面具有多个芯片；外部连接结构，位于所述第一表面的一侧，被配置为：电连接所述压缩附加内存模块以及所述中央处理器，所述中央处理器被配置为：至少经由所述外部连接结构向每一所述芯片中读写数据。
在一些实施例中，主板内具有多根信号线，每一所述信号线电连接所述中央处理器与所述压缩附加内存模块，所述中央处理器被配置为：经由所述信号线和所述外部连接结构向每一所述芯片中读写数据。
在一些实施例中，外部连接结构位于所述压缩附加内存模块朝向所述中央处理器的一侧。
在一些实施例中，压缩附加内存模块相较于主板的高度大于所述中央处理器相较于所述主板的高度。
在一些实施例中，还包括：中央处理器连接器，所述中央处理器连接器位于所述第一表面，且所述中央处理器连接器相较于所述主板的高度大于所述中央处理器相较于所述主板的高度。
在一些实施例中，中央处理连接器相较于所述主板的高度与所述压缩附加内存模块相较于所述主板的高度相同。
在一些实施例中，中央处理器连接器朝向所述第一表面的底面与所述中央处理器电连接，所述中央处理器连接器远离所述第一表面的顶面与所述外部连接结构电连接。
在一些实施例中，主板被配置为：电连接所述中央处理器连接器与所述中央处理器，所述中央处理器与所述主板之间通过金手指或者球栅阵列电连接；所述中央处理器连接器与所述外部连接结构之间通过球栅阵列、按压式连接器或者硅中介层中的任一者电连接。
在一些实施例中，还包括：第一转接件，位于所述主板与所述压缩附加内存模块之间，用于电连接所述主板和所述压缩附加内存模块，且所述第一转接件还用于电连接所述外部连接结构与所述压缩附加内存模块。
在一些实施例中，外部连接结构与所述第一转接件朝向所述压缩附加内存模块一侧表面电接触。
在一些实施例中，还包括：第一转接件，位于所述主板与所述压缩附加内存模块之间，用于电连接所述主板和所述压缩附加内存模块；第二转接件，位于所述压缩附加内存模块远离所述主板的一侧，所述第二转接件电连接所述外部连接结构与所述压缩附加内存模块。
在一些实施例中，压缩附加内存模块的数量为两个，两个所述压缩附加内存模块在垂直于所述第一表面的方向上堆叠，且两个所述压缩附加内存模块通过同一个所述外部连接结构与所述中央处理器电连接。
在一些实施例中，第一转接件为硅中介层或者是z轴压缩连接器中的任一者；所述外部连接结构为柔性电路板。
在一些实施例中，压缩附加内存模块在沿垂直于所述第一表面方向上的其中一个表面具有所述多个芯片；或者，所述压缩附加内存模块在沿垂直于所述第一表面方向上的相对的两个表面均具有所述多个芯片。
在一些实施例中，还包括：顶部垫板，位于所述压缩附加内存模块远离所述主板的表面，所述顶部垫板具有至少一个安装孔；底部垫板，固定于所述第一表面，所述底部垫板位于所述压缩附加内存模块朝向所述主板的表面，所述底部垫板具有至少一个与安装孔对应的插销；紧固件，与所述插销匹配，所述紧固件用于在所述插销穿过所述安装孔后，固定所述插销，以使所述顶部垫板和底部垫板对所述压缩附加内存模块进行夹持固定。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的第一种信息处理装置的剖面结构示意图；
图2为本公开一实施例提供的第二种信息处理装置的剖面结构示意图；
图3为本公开一实施例提供的一种信息处理装置的立体结构示意图；
图4为本公开一实施例提供的第三种信息处理装置的剖面结构示意图；
图5为本公开一实施例提供的第四种信息处理装置的剖面结构示意图；
图6为本公开一实施例提供的第五种信息处理装置的剖面结构示意图；
图7为本公开一实施例提供的第六种信息处理装置的剖面结构示意图；
图8为本公开一实施例提供的第七种信息处理装置的剖面结构示意图；
图9为本公开一实施例提供的第八种信息处理装置的剖面结构示意图；
图10为本公开一实施例提供的第九种信息处理装置的剖面结构示意图；
图11为本公开一实施例提供的第十种信息处理装置的剖面结构示意图；
图12为本公开一实施例提供的另一种信息处理装置的立体结构示意图。
具体实施方式
由背景技术可知，目前的信号处理装置中的主板的散热能力较差。分析发现，目前，导致主板的散热能力较差的原因之一在于，主板内具有较多信号线，用于电连接中央处理器和压缩附加内存模块，随着压缩附加内存模块连接的芯片的数量越来越多，使得主板内的信号线的数量越来越多，进而导致主板的厚度越来越大，导致主板的散热能力大大减小。
本公开实施例提供一种信号处理装置，设置外部连接结构位于主板的第一表面的一侧，用于电连接压缩附加内存的模块以及中央处理器，也就是说，外部连接结构从主板外部走线，连接压缩附加存内存模块以及中央处理器，如此，可以减小主板中用于电连接中央处理器和压缩附加内存模块中的信号线的数量，甚至能够省去主板中的信号线的设置，进而能够大大减小主板的厚度，使得主板的散热能力大大增加。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员 可以理解，在本公开各实施例中，为了使读者更好地理解本公开而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开所要求保护的技术方案。
图1为本公开一实施例提供的第一种信息处理装置的剖面结构示意图。
参考图1至图3，信号处理装置包括：主板101，具有第一表面，第一表面具有与主板101电连接的中央处理器102。信号处理装置还包括：压缩附加内存模块103，位于第一表面的一侧，压缩附加内存模块103的至少一个表面具有多个芯片104。信号处理装置还包括：外部连接结构105，位于第一表面的一侧，被配置为：电连接压缩附加内存模块103以及中央处理器102，中央处理器102被配置为：至少经由外部连接结构105向每一芯片104中读写数据。
中央处理器102，简称为CPU，中央处理器102作为计算机系统的运算和控制核心，是信息处理、程序运行的最终执行单元。
主板101也称作母板，主板101可以作为中央处理器102以及压缩附加内存模块103的承载体，并实现中央处理器102与压缩附加内存模块103的电连接。在一些实施例中，主板101可以是系统板，逻辑板或任何其它印刷电路板。
压缩附加内存模块103，即“Compression Attached Memory Module”，简称CAMM，是一种有别于传统SO-DIMM笔记本内存的新形态，其结构包括：PCB电路板，以及双面都可安装的芯片104。
中央处理器102在向芯片104写入数据时，可以通过地址线将地址信息发出，接着通过控制线发出内存写命令，选中芯片104，并通过外部连接结构105向选中的芯片104写入数据。中央处理器102在从芯片104中读出数据时，通过地址线将地址信息发出，接着通过控制线发出内存读命令，选中芯片104，选中的芯片104将芯片104中的数据通过外部连接结构105送入中央处理器102。
在一些实施例中，芯片104可以包括DRAM(动态随机存储器，Dynamic Random Access Memory)、SRAM(静态随机存储器，Static Random-Access Memory)或者SDRAM(同步动态随机存储器，Synchronous Dynamic Random-Access Memory)中的任一者。
在一个具体的例子中，芯片104可以为DRAM，具体可以为同步DRAM的一些变体。例如DDR3(DDR版本3)、DDR4(DDR版本4)，DDR5(DDR版本5，)，LPDDR3(低功率DDR版本3)，LPDDR4(LPDDR版本4)，LPDDR5(LPDDR版本5)或其它或存储器技术的组合。
外部连接结构105位于主板101的第一表面的一侧，也就是说，外部连接结构105设 置于主板101外部，实现中央处理器102与压缩附加内存模块103之间的电连接，由于芯片104与压缩附加内存模块103电连接，因此，中央处理器102能够通过外部连接结构105以及压缩附加内存模块103向芯片104中读写数据。
图2为本公开一实施例提供的第二种信号处理装置的剖面结构示意图，图3为本公开一实施例提供的一种信息处理装置的立体结构示意图。
参考图2以及图3，在一些实施例中，主板101内具有多根信号线10，每一信号线10电连接中央处理器102与压缩附加内存模块103，中央处理器102被配置为：经由信号线10和外部连接结构105向每一芯片104中读写数据。也就是说，外部连接结构105与信号线10均能够实现中央处理器102与芯片104之间的信号传输，信号线10位于主板101内部，外部连接结构105位于主板101外部，使得主板101内的信号线10的数量能够大大减小。一方面能够减小信号线10在主板101内部占用体积，减小主板101的厚度，有利于增强主板101的散热。另一方面，使得主板101内的信号线10的走线密度大大减小，进而能够避免由于信号线10的走线密度过大而造成的不同信号线10中传输的信号之间的串扰问题，避免信号线10中的传输的信号的畸变。
通过外部连接结构105与信号线10共同实现中央处理器102与芯片104之间的信号传输，能够增强外部连接结构105与信号线10的布线的灵活性，既能够避免外部连接结构105的走线过密问题，也能够避免信号线10的走线过密问题，大大减小由于走线密度过大而导致的信号畸变的风险。
参考图4，在一些实施例中，主板101内还具有多根信号线10，则信号处理装置还包括：第一引脚21，位于第一表面，中央处理器102与第一引脚21电连接，实现与主板101的电连接。信号线10与部分第一引脚21电连接，进而电连接中央处理器102和压缩附加内存模块103。
信号处理装置还包括：第二引脚22，位于第一表面，第二引脚22与剩余部分第一引脚21电连接，且第二引脚22与外部连接结构105电连接，以实现中央处理器102与外部连接结构105的电连接。在一些实施例中，主板101内还包括第一引线20，第一引线20用于电连接第一引脚21和第二引脚22，使得第二引脚22可以与中央处理器102电连接，进而使得与第二引脚22电连接的外部连接结构105能够与中央处理器102电连接。
在一些实施例中，第二引脚22位于中央处理器102与压缩附加内存模块103之间第一表面，且邻近第一引脚21设置，如此，使得主板101中的第一引线20长度较短，减小第一引线20中传输的信号的传输损耗。且由于第一引线20长度较短，使得第一引线20中传输的信号的损耗较小，因此，可以设置第一引线20的直径较小，减小第一引线20在主板101中所占用的体积，避免由于第一引线20的设置而导致主板101厚度的增加。
在一些实施例中，第一引线20的直径可以小于信号线10的直径。如此，可以保证第一引线20的设置不会导致主板101厚度的进一步增加。
可以理解的是，在一些实施例中，主板101内也可以不设置信号线10，使得芯片104与中央处理器102之间仅通过外部连接结构105进行信号的传输。如此，可以大大减小主板101的厚度，进一步增强主板101的散热。
在一些实施例中，芯片104与中央处理器102之间仅通过外部连接结构105进行信号的传输，则信号处理装置还包括：第一引脚，位于第一表面，中央处理器102与第一引脚电连接，实现与主板101的电连接。
信号处理装置还包括：第二引脚，位于第一表面，第二引脚与第一引脚电连接，且第二引脚与外部连接结构105电连接，以实现中央处理器102与外部连接结构105的电连接。在一些实施例中，主板101内还包括第一引线，第一引线用于电连接第一引脚和第二引脚。
在一些实施例中，第一引脚可以是金手指或者球栅阵列中的任一者，第二引脚可以是金手指或者球栅阵列中的任一者。
金手指是由多个金黄色导电触片组成的结构，因其表面镀金且导电触片排列如手指状而称作金手指。
球栅阵列为在主板101第一表面按阵列方式制出的球形触点。在一些实施例中，球形触点可以为阵列排布锡球。
金手指和球栅阵列均可以以本领域技术人员所熟知的方式形成于第一表面，并与中央处理器102电接触。
在一些实施例中，可以采用电镀的方式在主板101内形成第一引线20，本公开实施例不对第一引线20在主板101内的具体走线方式以及形状进行限定，仅需满足第一引线20能够电连接第一引脚21和第二引脚22即可。第一引线20的材料可以是金属材料，例如可以是铜、钨、镍、银、铜或者本领域技术人员所熟知的其它导电材料中至少一者。
参考图1至图3，在一些实施例中，外部连接结构105位于压缩附加内存模块103朝向中央处理器102的一侧。中央处理器102与压缩附加内存模块103均位于第一表面，且中央处理器102与压缩附加内存模块103相对设置。外部连接结构105可以位于中央处理器102于压缩附加内存模块103之间。外部连接结构105位于压缩附加内存模块103朝向中央处理器102的一侧，即外部连接结构105与压缩附加内存模块103正对，且外部连接结构105相较于第一表面的高度不高于压缩附加内存模块103相较于第一表面的高度。也就是说，可以利用压缩附加内存模块103与中央处理器102之间的空余空间来设置外部连接结构105，且由于外部连接结构105的高度不高于压缩附加内存模块103的高度，使得外部连接结构105 不会额外占用过多的体积，防止发生由于外部连接结构105的厚度过大而导致信息处理装置的厚度无法进一步减小的问题。
在一些实施例中，压缩附加内存模块相较于主板101的高度大于中央处理器102相较于主板101的高度。换句话说，压缩附加内存模块103远离主板101的表面相较于第一表面的高度大于中央处理器102远离主板101的表面相较于第一表面的高度。
参考图5，在一些实施例中，信号处理装置还包括：中央处理器连接器106，中央处理器连接器106位于第一表面，中央处理器连接器106用于当电连接外部连接结构105与中央处理器102。中央处理器连接器106位于中央处理器102与压缩附加内存模块103之间，且邻近中央处理器102设置，如此，使得中央处理器连接器106与中央处理器102之间的距离较短，有利于增强中央处理器102与外部连接结构105之间的电传输性能。
在一些实施例中，中央处理器连接器106朝向第一表面的底面与中央处理器102电连接，中央处理器连接器106远离第一表面的顶面与外部连接结构105电连接。则中央处理器连接器106的底面与位于第一表面的金手指或者球栅阵列电接触，中央处理器连接器106的顶面具有球栅阵列或者按压式连接器，中央处理器连接器106通过位于顶面的球栅阵列、按压式连接器或者硅中介层中的任一者与外部连接结构105电接触。
外部连接结构105一端电连接中央处理器102，另一端电连接压缩附加内存模块103。即外部连接结构105在中央处理器102指向压缩附加内存模块103的方向上延伸。由于压缩附加内存模块103相较于第一表面的高度高于中央处理器102相较于第一表面的高度，使得压缩附加内存模块103与中央处理器102之间具有较大的高度差。这可能会使外部连接结构105的两端高度不一致，而导致外部连接结构105相较于第一表面倾斜的问题，进而导致外部连接结构105所占用空间较大。
基于上述考虑，在一些实施例中，中央处理器连接器106相较于主板101的高度大于中央处理器102相较于主板101的高度。换句话说，中央处理器连接器106远离主板101的表面相较于主板101的高度大于中央处理器102远离主板101的表面相较于主板101的高度。如此，使得中央处理器连接器106与压缩附加内存模块103之间的高度差小于中央处理器102与压缩附加内存模块103之间的高度差。由于外部连接结构105与中央处理器连接器106电连接，相较于与中央处理器102直接连接而言，使得外部连接结构105与压缩附加内存模块103之间的高度差较小，使得外部连接结构105相较于第一表面的倾斜度不至于过大，进而改善外部连接结构105所占用空间较大的问题。
参考图6，在一些实施例中，中央处理器连接器106朝向第一表面的底面与中央处理器102电连接，中央处理器连接器106远离第一表面的顶面与外部连接结构105电连接。如此，使得外部连接结构105的高度高于中央处理器连接器106的高度，能够最大限度地减小 外部连接结构105与压缩附加内存模块103之间的高度差。由于外部连接结构105的两端分别与中央处理器连接器106以及压缩附加内存模块103电连接，因此，减小外部连接结构105与压缩附加内存模块103之间的高度差，可以使外部连接结构105的两端的高度差较小，甚至为0，进而使得外部连接结构105可以水平放置或者接近水平放置，这里指的水平放置为平行于第一表面放置。相较于外部连接结构105相对于第一表面倾斜放置而言，外部连接结构105水平放置，一方面有利于保持外部连接结构105的平稳，另一方面，使得外部连接结构105所占用的空间较小，能够为主板101表面的其它元器件的布置提供较多的空间，有利于走线的布置。
在一些实施例中，中央处理连接器相较于主板101的高度与压缩附加内存模块103相较于主板101的高度相同。换句话说，中央处理器连接器106远离主板101的表面相较于第一表面的高度与压缩附加内存模块103相对主板101的表面相较于第一表面的高度相同。如此，使得电连接中央处理器连接器106与压缩附加内存模块103的外部连接结构105的两端相较于第一表面的高度接近，进而使得当外部连接结构105的两端的高度差较小，甚至为0。如此，能够实现外部连接结构105能够大致平行于第一表面设置，使得外部连接结构105在第一表面一侧所占用的空间较小。
在一些实施例中，中央处理器连接器106相较于主板101的高度与压缩附加内存模块103相较于主板101的高度相同也可以为：中央处理器连接器106远离主板101的表面相较于第一表面的高度与压缩附加内存模块103朝向主板101的表面相较于第一表面的高度相同。
在一些实施例中，中央处理器连接器106远离主板101的表面相较于第一表面的高度与压缩附加内存模块103远离主板101的表面相较于第一表面的高度也可以不相同。例如，中央处理器连接器106远离主板101的表面相较于第一表面的高度可以略高于压缩附加内存模块103远离主板101的表面相较于第一表面的高度。或者，中央处理器连接器106远离主板101的表面相较于第一表面的高度可以略低于压缩附加内存模块103远离主板101的表面相较于第一表面的高度。
参考图7，在一些实施例中，主板101被配置为：电连接中央处理器连接器106与中央处理器102，中央处理器102与主板101之间通过金手指或者球栅阵列电连接；中央处理器连接器106与外部连接结构105之间通过球栅阵列、按压式连接器或者硅中介层中的任一者电连接。
在一些实施例中，第一表面设置有金手指或者球栅阵列，且第一表面还设置有第一引脚21，第一引脚21用于电连接中央处理器102与主板101。主板101内还设置有第一引线20，第一引线20用于将第一引脚21的信号引出至第一表面的金手指或者球栅阵列，进一步通过金手指或者球栅阵列引出至中央处理器连接器106。在一个具体的例子中，第一引线20 的材料可以是金属材料，例如可以是铜、钨、镍、银、铜或者本领域技术人员所熟知的其它导电材料中至少一者。
在一些实施例中，中央处理器连接器106表面设置有球栅阵列、按压式连接器或者硅中介层中的任一者，中央处理器102内部设置有连接结构，连接结构用于将中央处理器102的信号传输至位于中央处理器连接器106表面的球栅阵列或者按压式连接器，再经由球栅阵列或者按压式连接器传输至外部连接结构105中。
在一些实施例中，中央处理器连接器106表面设置有硅中介层，硅中介层包括硅通孔，硅通孔沿硅中介层的厚度方向贯穿硅中介层，硅通孔的底端与中央处理器连接器106中的连接结构电接触，硅通孔的顶端与外部连接结构105电连接。
在一些实施例中，连接结构可以是第二引线，本公开实施例不对第二引线在中央处理器连接器106中的具体走线方式以及形状进行限定，仅需满足第二引线能够将来自中央处理器102的信号引出至位于中央处理器连接器106表面的球栅阵列、按压式连接器或者硅中介层中的任一者即可。第二引线的材料可以是铜、钨、镍、银、铜或者本领域技术人员所熟知的其它导电材料中至少一者。
参考图6以及图7，在一些实施例中，信号处理装置还包括：第一转接件107，位于主板101与压缩附加内存模块103之间，用于电连接主板101和压缩附加内存模块103，且第一转接件107还用于电连接外部连接结构105与压缩附加内存模块103。也就是说，外部连接结构105与主板101共用同一第一转接件107，如此，可以节省空间。
在一些实施例中，外部连接结构105与主板101共用同一第一转接件107，主板101内具有多根信号线10，每一信号线10电连接中央处理器102与压缩附加内存模块103。主板101中的信号线10与第一转接件107电连接，外部连接结构105与第一转接件107电连接，信号线10与外部连接结构105均能够实现中央处理器102与芯片104的信号传输。
继续参考图6以及图7，在一些实施例中，外部连接结构与第一转接件107朝向压缩附加内存模块103一侧表面电接触。在一个具体的例子中，信号线10与第一转接件107朝向主板101的表面电连接，外部连接结构105与第一转接件107朝向压缩附加内存模块103的一侧表面电连接。也就是说，外部连接结构105与信号线10分别位于第一转接件107的相对的两个表面，避免外部连接结构105与信号线10由于位于第一转接件107的同一表面而导致外部连接结构105与信号线10的信号串扰问题。
第一转接件107朝向压缩附加内存模块103的一侧还与压缩附加内存模块103电连接，进而能够将外部连接结构105以及信号线10中传输的信号均传输至压缩附加内存模块103中。
在一些实施例中，压缩附加内存模块103内具有：第一走线41，第一走线41用于电连接第一连接线与芯片104，且第一走线41还用于电连接第一转接件107，即第一转接件107朝向压缩附加内存模块103的一侧与第一走线41电连接，第一走线41用于传输来自第一转接件107的传输信号，并将其传输至芯片104中，或者，芯片104中的信号可以通过第一走线41传输至第一转接件107中。
在一些实施例中，第一转接件107可以为硅中介层或者是z轴压缩连接器中的任一者。在一些实施例中，外部连接结构105可以为柔性电路板。
在一些实施例中，第一转接件107为第一硅中介层，则第一硅中介层包括第一硅通孔111，第一硅通孔111沿第一硅中介层的厚度方向贯穿第一硅中介层，第一硅中介层露出第一硅通孔111的顶端以及底端，信号线10与第一硅通孔111朝向主板101的底端电连接，第一硅通孔111远离主板101的顶端与第一走线41电连接。
在一些实施例中，第一硅中介层远离主板的表面还可以包括：第三引脚31，第三引脚31与第一硅通孔111顶端电接触，且外部连接结构105朝向第一硅中介层的一侧电连接第三引脚31，由于第三引脚31与第一硅通孔111顶端电接触，而第一硅通孔111底端与信号线10电连接，从而使得外部连接结构105与信号线也能够电连接。如此，信号线中传输的信号也能经由外部连接结构105传输至压缩附加内存模块103中。剩余部分第三引脚31与压缩附加内存模块103电接触，用于将主板内的信号线中传输的信号输入至压缩附加内存模块103中。
在一些实施例中，第三引脚31可以为金手指或者球栅阵列中的任一者，电连接结构可以为导电金属线，电连接结构的材料可以为铜、钨、镍、银、铜或者本领域技术人员所熟知的其它导电材料中至少一者。
柔性电路板是以聚酰亚胺或聚酯薄膜为基材制成的一种具有高度可靠性，绝佳的可挠性印刷电路板，具有配线密度高、重量轻、厚度薄、弯折性好的特点。使用柔性电路板作为外部连接结构105，可以防止发生由于封装步骤对外部连接结构105造成弯折而导致外部连接结构105失效的问题。此外，柔性电路板的厚度较薄，避免外部连接结构105占用过多的空间，使得信号处理装置整体的厚度较小。有利于实现器件的小型化，且有利于增强信号处理装置的整体散热能力。
参考图8至图10，在一些实施例中，主板101与外部连接结构105也可以不共用同一第一转接件107，则信号处理装置包括：第一转接件107，位于主板101与压缩附加内存模块103之间，用于电连接主板101和压缩附加内存模块103；第二转接件108，位于压缩附加内存模块103远离主板101的一侧，第二转接件108电连接外部连接结构105与压缩附加内存模块103。
也就是说，第一转接件107与第二转接件108分别位于压缩附加内存模块103的相对两侧，第一转接件107仅与信号线10电连接，第二转接件108仅与外部连接结构105电连接，使得第一转接件107与第二转接件108中用于信号传输的走线的走线密度均较小，能够避免第一转接件107与第二转接件108中由于走线密度过大而导致信号串扰的问题。
在一些实施例中，主板101内的信号线10与第一转接件107朝向主板101的一侧电连接，第一转接件107远离主板101的一侧与压缩附加内存模块103电连接。外部连接结构105与第二转接件108远离压缩附加内存模块103的一侧电连接，第二转接件108朝向压缩附加内存模块103的一侧与压缩附加内存模块103电连接。
也就是说，第一转接件107中，与压缩附加内存模块103距离较小的一侧与压缩附加内存模块103电连接，第二转接件108中，与压缩附加内存模块103距离较小的一侧与压缩附加内存模块103电连接，如此，能够减小第一转接件107与压缩附加内存模块103之间的走线距离，以及减小第二转接件108与压缩附加内存模块103之间的走线距离，有利于节省走线长度。
在一些实施例中，第一转接件107为第一硅中介层，第一硅中介层包括第一硅通孔111，第一硅通孔111沿第一硅中介层的厚度方向贯穿第一硅中介层，第一硅中介层露出第一硅通孔111的顶端以及底端，信号线10与第一硅通孔111朝向主板101的底端电连接，第一硅通孔111远离主板101的顶端与压缩附加内存模块103电连接。第二转接件108为第二硅中介层，第二硅中介层包括第二硅通孔112，第二硅通孔112沿第二硅中介层的厚度方向贯穿第二硅中介层，第二硅中介层露出第二硅通孔112的顶端以及底端。第二硅通孔112的底端与压缩附加内存模块103远离主板101表面正对，且与压缩附加内存模块103远离主板101的一侧电连接。外部连接结构105与第二硅通孔112顶端电连接。
在一些实施例中，信息处理装置包括第一转接件107和第二转接件108，则压缩附加内存模块103内具有：第一走线41，第一走线41用于电连接第一连接线与芯片104，且第一走线41还用于电连接第一转接件107；第二走线42，第二走线42用于电连接外部连接结构105与芯片104，且第二走线42还用于电连接第二转接件108。
在一些实施例中，压缩附加内存模块103包括相对的第三面与第四面，第四面与第一表面正对，第一走线41与第二走线42沿平行于第三面的方向间隔排布。也就是说，第二走线42与第一走线41水平排布，如此，使得第二走线42与第一走线41不会占用压缩附加内存模块103中的厚度方向上的空间，相较于第二走线42与第一走线41沿压缩附加内存模块103的厚度方向间隔排列而言，设置第二走线42与第一走线41但沿平行于第三面的方向间隔排布，大大减小了压缩附加内存模块103厚度。
在一些实施例中，第一硅通孔111的顶端与第一走线41电连接，第二硅通孔112的 底端与第二走线42电连接，其中，第一硅通孔111的顶端与第三面正对，第二硅通孔112的底端与第四面正对。
参考图8，在一些实施例中，压缩附加内存模块在沿垂直于第一表面方向上的其中一个表面具有多个芯片104。在一些实施例中，压缩附加内存模块103包括相对的第三面以及第四面，第三面与第一表面正对。多个芯片104可以仅位于第三面或者仅位于第四面。其中，每一芯片104可以与外部连接结构105或者信号线10中的任一者电连接，也就是说，中央处理器102可以通过外部连接结构105或者信号线10中的任一者向一芯片104读写数据。
参考图9，在一些实施例中，压缩附加内存模块103在沿垂直于第一表面方向上的相对的两个表面均具有多个芯片104。也就是说，第三面以及第四面均具有多个芯片104，如此，可以提高芯片104的集成度。
参考图9，在一些实施例中，信号处理装置包括：第一转接件107与第二转接件108，第一转接件107位于第三面一侧，第二转接件108位于第四面一侧，外部连接结构105与第二转接件108电连接，信号线10与第一转接件107电连接。则第二转接件108可以与第四面的芯片104电连接，即中央处理器102通过外部连接结构105向位于第四面的芯片104读写数据。第一转接件107可以与第三面的芯片104电连接，中央处理器102可以通过主板101内的信号线10向位于第三面的芯片104读写数据。如此，可以节省走线长度，简化走线。
参考图8，在一些实施例中，位于第三面的多个芯片104中的每一个芯片104也可以与外部连接结构105或者信号线10中的任一者电连接。位于第四面的多个芯片104中的每一个芯片104也可以与外部连接结构105或者信号线10中的任一者电连接。
参考图11，在一些实施例中，压缩附加内存模块的数量为两个，两个压缩附加内存模块103在垂直于第一表面的方向上堆叠，且两个压缩附加内存模块103通过同一个外部连接结构105与中央处理器102电连接。两个压缩附加内存模块103中的每一压缩附加内存模块103的至少一个表面均具有多个芯片104，通过同一外部连接结构105，使得中央处理器102可以向位于任一压缩附加内存模块103表面的芯片104读写数据，在保证外部连接结构105数量不增加的情况下，提升了与中央处理器102电连接的芯片104的数量，进而能够提升芯片104的集成度。
由于外部连接结构105设置于主板101外部，能够减少主板101内的信号线10的数量，甚至省去主板101内的信号线10的设置，如此，在提高芯片104的集成度的同时，能够增强主板101的散热能力，有利于保证主板101的优异性能，保证信息处理装置具有较高的运行速度。
在一些实施例中，将两个压缩附加内存模块103分别记为：第一压缩附加内存模块121以及第二压缩附加内存模块122，第一压缩附加内存模块121邻近第一表面，第二压缩附 加内存模块122位于第一压缩附加内存模块121远离主板101的一侧。
信息处理装置可以包括：第一转接件107和第二转接件108。第一转接件107位于第一压缩附加内存模块121与第一表面之间，用于电连接主板101与第一压缩附加内存模块121。第二转接件108位于第一压缩附加内存模块121与第二压缩附加内存模块122之间，用于电连接外部连接结构105，且第二转接件108与第一压缩附加内存模块121以及第二压缩附加内存模块122电连接，用于将外部连接结构105中的信号分别传输至第一压缩附加内存模块121以及第二压缩附加内存模块122中。
在一个具体的例子中，第一转接件107可以为第一硅中介层，第二转接件108可以为第二硅中介层，第一硅中介层包括第一硅通孔111，第一硅通孔111贯穿第一硅中介层，第一硅通孔111的顶端与第一压缩附加内存模块121电连接，第一硅通孔111的底端与主板101电连接。具体地，主板101内可以具有信号线10，信号线10电连接中央处理器102，第一硅通孔111的底端可以与信号线10电连接。
第二硅中介层包括第二硅通孔112，第二硅通孔112贯穿第二硅中介层，第二硅通孔112的顶端与第二压缩附加内存模块122电连接，第二硅通孔112的底端与第一压缩附加内存模块121电连接。
在一些实施例中，第二硅中介层表面可以包括：第四引脚32，第四引脚32位于第二硅中介层远离主板101的表面或者第二硅中介层朝向主板101的表面中的任一者。外部连接结构105朝向第二硅中介层的表面与第三引脚31电接触，使得外部连接结构105中传输的信号能够通过第三引脚31传输至第二硅通孔112中，最后通过第二硅通孔112传输至第一压缩附加内存模块121。
第二压缩附加内存模块122朝向第二硅中介层表面可以包括：第五引脚33，第五引脚33与外部连接结构朝向第二压缩附加内存模块122的表面电接触，使得外部连接结构105中传输的信号能够通过第五引脚33传输至第二压缩附加内存模块122中。
在一些实施例中，第四引脚32可以为金手指或者球栅阵列中的任一者，电连接结构可以为导电金属线，电连接结构的材料可以为铜、钨、镍、银、铜或者本领域技术人员所熟知的其它导电材料中至少一者。在一些实施例中，第五引脚33可以为金手指或者球栅阵列中的任一者，电连接结构可以为导电金属线，电连接结构的材料可以为铜、钨、镍、银、铜或者本领域技术人员所熟知的其它导电材料中至少一者。
参考图12，在一些实施例中，信号处理装置还包括：顶部垫板11，位于压缩附加内存模块103远离主板101的表面，顶部垫板11具有至少一个安装孔13；底部垫板12，固定于第一表面，底部垫板12位于压缩附加内存模块103朝向主板101的表面，底部垫板12具有至少一个与安装孔13对应的插销14；紧固件15，与插销14匹配，紧固件15用于在插销 14穿过安装孔13后，固定插销14，以使顶部垫板11和底部垫板12对压缩附加内存模块103进行夹持固定。
在一些实施例中，顶部垫板11可以具有两个安装孔13，底部垫板12也可以具有两个插销14，每一插销14与一安装孔13对应。两个安装孔13分别位于顶部垫板11的相对两侧，如此，可以提高部垫板与底部垫板12的安装稳定性。
在一些实施例中，顶部垫板11也可以具有两个以上的安装孔13，底部垫板12也可以具有两个以上的插销14；或者顶部垫板11也可以仅具有一个安装孔13，底部垫板12也可以仅具有一个插销14。仅需满足安装孔13的数量与插销14的数量匹配即可。安装孔13与插销14的数量可以根据不同的需求灵活设置。
在一些实施例中，插销14可以是钢丝螺套，钢丝螺套是一种内螺纹紧固件15，钢丝螺套内侧具有内螺纹。紧固件15可以是螺钉中的任一者，螺钉通过拧入钢丝螺套内部，可以与钢丝螺套锁紧，进而在钢丝螺套插入安装孔13之后，将钢丝螺套固定于安装孔13内，防止钢丝螺套从安装孔13中滑脱。
在一些实施例中，插销14也可以为螺栓，紧固件15也可以为螺母，螺栓侧面具有外螺纹螺母内部具有与螺栓外侧的外螺纹相匹配的内螺纹，当螺栓插入安装孔13之后，螺母拧入螺栓外侧面，与螺栓锁紧，进而将螺栓固定于安装孔13中，防止螺栓从安装孔13中滑脱，进而使得顶部与底部垫板12可以将压缩附加内存模块103夹紧固定，防止压缩附加内存模块103发生移动的问题。
上述实施例提供的信息处理装置中，设置外部连接结构105位于主板101的第一表面的一侧，用于电连接压缩附加内存模块103以及中央处理器102，也就是说，外部连接结构105从主板101外部走线，连接压缩附加内存模块103和中央处理器102。如此，可以减小主板101中用于电连接中央处理器102和压缩附加内存模块103信号线10的数量，甚至能够省去主板101中的信号线10的设置，进而能够大大减小主板101的厚度，使得主板101的散热路径大大减小，有利于增强主板101的散热。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开的精神和范围。任何本领域技术人员，在不脱离本公开的精神和范围内，均可作各自更动与修改，因此本公开的保护范围应当以权利要求限定的范围为准。

Claims (15)

  1. 一种信息处理装置，包括：
    主板(101)，具有第一表面，所述第一表面具有与所述主板(101)电连接的中央处理器(102)；
    压缩附加内存模块(103)，位于所述第一表面的一侧，所述压缩附加内存模块(103)的至少一个表面具有多个芯片(104)；
    外部连接结构(105)，位于所述第一表面的一侧，被配置为：电连接所述压缩附加内存模块(103)以及所述中央处理器(102)，所述中央处理器(102)被配置为：至少经由所述外部连接结构(105)向每一所述芯片(104)中读写数据。
  2. 根据权利要求1所述的信息处理装置，其中，所述主板(101)内具有多根信号线(10)，每一所述信号线(10)电连接所述中央处理器(102)与所述压缩附加内存模块(103)，所述中央处理器(102)被配置为：经由所述信号线(10)和所述外部连接结构(105)向每一所述芯片(104)中读写数据。
  3. 根据权利要求1或2所述的信息处理装置，其中，所述外部连接结构(105)位于所述压缩附加内存模块(103)朝向所述中央处理器(102)的一侧。
  4. 根据权利要求3所述的信息处理装置，其中，所述压缩附加内存模块(103)相较于主板(101)的高度大于所述中央处理器(102)相较于所述主板(101)的高度。
  5. 根据权利要求1～4任一项所述的信息处理装置，其中，还包括：中央处理器连接器(106)，所述中央处理器连接器(106)位于所述第一表面，且所述中央处理器连接器(106)相较于所述主板(101)的高度大于所述中央处理器(102)相较于所述主板(101)的高度。
  6. 根据权利要求5所述的信息处理装置，其中，所述中央处理器连接器相较于所述主板(101)的高度与所述压缩附加内存模块(103)相较于所述主板(101)的高度相同。
  7. 根据权利要求5所述的信息处理装置，其中，所述中央处理器连接器(106)朝向所述第一表面的底面与所述中央处理器(102)电连接，所述中央处理器连接器(106)远离所述第一表面的顶面与所述外部连接结构(105)电连接。
  8. 根据权利要求6所述的信息处理装置，其中，所述主板(101)被配置为：电连接所述中央处理器连接器(105)与所述中央处理器(102)，所述中央处理器(102)与所述主板(101)之间通过金手指或者球栅阵列电连接；所述中央处理器连接器(106)与所述外部连接结构(105)之间通过球栅阵列、按压式连接器或者硅中介层中的任一者电连接。
  9. 根据权利要求1～5任一项所述的信息处理装置，其中，还包括：第一转接件(107)，位于 所述主板(101)与所述压缩附加内存模块(103)之间，用于电连接所述主板(101)和所述压缩附加内存模块(103)，且所述第一转接件(107)还用于电连接所述外部连接结构(105)与所述压缩附加内存模块(103)。
  10. 根据权利要求9所述的信息处理装置，其中，所述外部连接结构(105)与所述第一转接件(107)朝向所述压缩附加内存模块(103)一侧表面电接触。
  11. 根据权利要求1～5任一项所述的信息处理装置，其中，还包括：
    第一转接件(107)，位于所述主板(101)与所述压缩附加内存模块(103)之间，用于电连接所述主板(101)和所述压缩附加内存模块(103)；
    第二转接件(108)，位于所述压缩附加内存模块(103)远离所述主板(101)的一侧，所述第二转接件(108)电连接所述外部连接结构(105)与所述压缩附加内存模块(103)。
  12. 根据权利要求11所述的信息处理装置，其中，所述压缩附加内存模块(103)的数量为两个，两个所述压缩附加内存模块(103)在垂直于所述第一表面的方向上堆叠，且两个所述压缩附加内存模块(103)通过同一个所述外部连接结构(105)与所述中央处理器(102)电连接。
  13. 根据权利要求9或11所述的信息处理装置，其中，所述第一转接件(107)为硅中介层或者是z轴压缩连接器中的任一者；所述外部连接结构(105)为柔性电路板。
  14. 根据权利要求1～5、9或11任一项所述的信息处理装置，其中，所述压缩附加内存模块(103)在沿垂直于所述第一表面方向上的其中一个表面具有所述多个芯片(104)；或者，所述压缩附加内存模块(103)在沿垂直于所述第一表面方向上的相对的两个表面均具有所述多个芯片(104)。
  15. 根据权利要求1～14任一项所述的信息处理装置，其中，还包括：
    顶部垫板(11)，位于所述压缩附加内存模块(103)远离所述主板(101)的表面，所述顶部垫板(11)具有至少一个安装孔(13)；
    底部垫板(12)，固定于所述第一表面，所述底部垫板(12)位于所述压缩附加内存模块(103)朝向所述主板(101)的表面，所述底部垫板(12)具有至少一个与所述安装孔(13)对应的插销(14)；
    紧固件(15)，与所述插销(14)匹配，所述紧固件(15)用于在所述插销(14)穿过所述安装孔(13)后，固定所述插销(14)，以使所述顶部垫板(11)和底部垫板(12)对所述压缩附加内存模块(103)进行夹持固定。
PCT/CN2023/126685 2023-06-16 2023-10-26 信息处理装置 WO2024255060A1 (zh)

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