WO2024247025A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

A semiconductor device (10) according to the present application is configured to comprise a substrate (1) of a semiconductor material, a surface electrode (3) formed on one surface of the substrate (1), and a solid via (10v) including: a covering layer (42) formed from gold, which covers the inner wall of a tubular hole opening on the other surface of the substrate (1) and having the surface electrode (3) as the bottom surface thereof, and in which is formed a depression (42d) depressed from the opening side toward the bottom surface; and a filler layer (43) filling the depression (42d) and formed from any of copper, silver, nickel, tin, and gold with a larger crystal grain size than the covering layer (42).

Description

Semiconductor device and method for manufacturing the same

This application relates to a semiconductor device and a method for manufacturing the semiconductor device.

In semiconductor devices that have electrodes (vias) that penetrate the front and back surfaces of a semiconductor substrate, filling the vias with copper (Cu) plating, which is usually called Cu via filling, is expected to improve electrical connection, high frequency characteristics, and heat dissipation.

Via filling with copper plating is performed by electrolytic plating, which requires precise control of the plating solution composition, applied voltage waveform, solution agitation, etc. (see, for example, Patent Document 1). In addition, there is concern that the electrical characteristics may deteriorate due to the diffusion of copper into the semiconductor, so a diffusion barrier layer must be formed on the inner wall of the via (see, for example, Patent Document 2).

JP 2014-095104 A (paragraphs 0042 to 0050, Table 1) JP2013-532903A (paragraph 0039, FIG. 13)

However, Cu via filling by electrolytic plating requires precise control of the plating process (composition of plating solution, applied voltage waveform, agitation of solution), which poses problems of excessive equipment investment and increased costs for process management. Furthermore, the diffusion barrier layer requires materials such as conductive metal nitrides, which have a complex formation process and are difficult to handle, which again poses problems of excessive equipment investment and increased costs for process management.

This application discloses technology to solve the problems described above, and aims to provide a semiconductor device with good electrical connection and heat dissipation in the thickness direction at low cost.

The semiconductor device disclosed in this application is characterized by comprising a substrate of a semiconductor material, a solid via having an opening on the other side of the substrate, a first plating layer of gold covering the inner wall of a cylindrical hole having the wiring member as its bottom surface and having a recess recessed from the opening side toward the bottom surface, and a second plating layer of copper, silver, nickel, tin, or gold having a larger crystal grain size than the first plating layer, filling the recess.

The method of manufacturing a semiconductor device disclosed in this application is characterized by including the steps of forming a wiring member on one side of a substrate made of a semiconductor material, forming a cylindrical hole that opens on the other side of the substrate and has the wiring member as its bottom, forming a first plating layer of gold by electroless plating so as to cover the inner wall of the cylindrical hole and form a recess that is recessed from the opening side toward the bottom, and forming a second plating layer of copper, silver, nickel, tin, or gold by electrolytic plating so as to fill the recess.

The semiconductor device or semiconductor device manufacturing method disclosed in this application does not require excessively large equipment and forms a gold coating layer on the inner wall of the via in a simple process, making it possible to obtain a semiconductor device with good electrical connection and heat dissipation in the thickness direction at low cost.

4 is an end view for explaining a configuration of a via of the semiconductor device according to the first embodiment; FIG. 1 is an end view for explaining a configuration of a semiconductor device according to a first embodiment; 1 is a flowchart for explaining a method of manufacturing a semiconductor device according to a first embodiment. 1 is an end view during a via filling process for explaining the configuration of a covering layer of a via in the semiconductor device according to the first embodiment; FIG. 1A to 1C are diagrams showing cross-sectional SEM images during a via filling process in the semiconductor device according to the first embodiment; 5A to 5C are schematic end views showing stages during formation of a covering layer in via filling of the semiconductor device according to the first embodiment. 13 is an end view for explaining a configuration of a via of a semiconductor device according to a modified example of the first embodiment; FIG. 11 is an end view for explaining a configuration of a via of a semiconductor device according to a comparative example. FIG. 11A and 11B are diagrams showing cross-sectional SEM images during a via filling process in a semiconductor device according to a comparative example. 13 is an end view for explaining a configuration before a filling layer is formed in via filling of a semiconductor device according to a second embodiment. FIG. 10 is a flowchart for explaining a method of manufacturing a semiconductor device according to a second embodiment. FIG. 11 is an end view for explaining a configuration of a via of a semiconductor device according to a second embodiment. FIG. 13 is an end view for explaining a configuration of a via of a semiconductor device according to a third embodiment. FIG. 13 is an end view for explaining a configuration of a via in a semiconductor device according to a modified example of the third embodiment. FIG. 13 is an end view for explaining a configuration of a via of a semiconductor device according to a fourth embodiment. FIG. 13 is an end view for explaining a configuration of a via in a semiconductor device according to a modified example of the fourth embodiment. FIG. 13 is an end view for explaining a configuration of a via of a semiconductor device according to a fifth embodiment. FIG. 13 is an end view for explaining a configuration of a via in a semiconductor device according to a modified example of the fifth embodiment. FIG. 23 is an end view for explaining the configuration of a via of a semiconductor device according to a sixth embodiment. FIG. 23 is an end view for explaining a configuration of a via in a semiconductor device according to a modified example of the sixth embodiment. FIG. 23 is an end view for explaining a configuration of a via of a semiconductor device according to a seventh embodiment. FIG. 23 is an end view for explaining a configuration of a via in a semiconductor device according to a modified example of the seventh embodiment.

Embodiment 1.
1 to 9 are for explaining the semiconductor device according to the first embodiment and the manufacturing method of the semiconductor device, and FIG. 1 is an end view corresponding to the line A-A in FIG. 2 described later for explaining the configuration of the via of the semiconductor device, and FIG. 2 is an end view for explaining the configuration of the semiconductor device. And FIG. 3 is a flow chart for explaining the manufacturing method of the semiconductor device, and FIG. 4 is an end view corresponding to FIG. 1 before forming the filling layer and forming the coating layer during the via filling process for explaining the configuration of the coating layer of the via of the semiconductor device, and FIG. 5 is a cross-sectional SEM image at the stage of forming the coating layer similar to FIG. 4 in the via filling process. Also, FIG. 6 is an end view schematic diagram showing the state at each stage during the formation of the coating layer in the via filling of the semiconductor device according to the first embodiment.

FIG. 7 is an end view corresponding to FIG. 4 at the stage where a coating layer has been formed to explain the configuration of the via of the semiconductor device according to the modified example. Meanwhile, FIG. 8 is an end view at the stage where a coating layer has been formed to explain the configuration of the via of the semiconductor device according to the comparative example, and FIG. 9 is a cross-sectional SEM image at the stage where a coating layer similar to that of FIG. 8 has been formed in the via filling process.

The semiconductor device 10 according to the first embodiment is assumed to be, for example, a semiconductor device called a high electron mobility transistor (HEMT). As shown in Figures 1 and 2, a case will be described in which a via 10v is formed from the back surface directly below the source electrode 3s on the front surface (the upper surface in the figure). Note that the via 10v shown in Figure 1 is a detailed view of the via 10v formed directly below the source electrode 3s in Figure 2, but the via 10v does not necessarily have to be directly below the source electrode 3s, and may be located directly below a conductor layer (wiring member) formed on the front surface, including the wiring pattern.

In the semiconductor device 10, there is an epitaxial growth layer 2 on a silicon carbide (SiC) substrate 1, and there are a source electrode 3s, a drain electrode 3d, and a gate electrode 3g (collectively, surface electrodes 3) on top of that. The via 10v is formed directly below the source electrode 3s, with the source electrode 3s serving as an etching stop layer. There is a metal layer along the inner wall of the via 10v, and this metal layer serves as a seed layer 41, and a coating layer 42 and a filling layer 43 are formed in that order to form the filling body 4, thereby achieving via filling.

In the first embodiment and the following embodiments, a gallium nitride (GaN) HEMT on a silicon carbide substrate 1 is described as an example, but the present invention is not limited to this. For example, the same effect can be obtained with other semiconductor substrates, such as compound semiconductors such as indium phosphide (InP), gallium nitride, and germanium silicide (SiGe), and silicon (Si)-based semiconductors. This is because the gold (Au) that constitutes the coating layer 42 of the via 10v is formed on the seed layer 41, and is therefore not dependent on the element type of the substrate 1.

Next, the details of the configuration of the semiconductor device 10 according to the first embodiment will be described together with a manufacturing method with reference to the flow chart of FIG.
First, epitaxial growth, metal film and insulating film formation, and transfer patterning are repeatedly performed in a wafer process on the surface (upper surface in Figs. 1 and 2) of a substrate 1 made of SiC single crystal, to form an electric circuit on the surface (step S100). The wafer process is performed on a disk-shaped substrate having a diameter of 4 to 8 inches and a thickness of 0.35 mm or 0.5 mm.

First, an epitaxial growth layer 2 is formed on a substrate 1. In the case of a gallium nitride HEMT, a laminated structure is generally formed in which an aluminum gallium nitride (AlGaN) layer is laminated on a gallium nitride layer. Next, a source electrode 3s, a drain electrode 3d, and a gate electrode 3g are formed. For the source electrode 3s and the drain electrode 3d, a laminated structure such as titanium/aluminum/gold (Ti/Al/Au) or titanium/aluminum/nickel/gold (Ti/Al/Ni/Au) is used. For the gate electrode 3g, a laminated structure such as titanium/platinum/gold (Ti/Pt/Au) is used.

Then, the source electrode 3s, the drain electrode 3d, and the gate electrode 3g are protected with an insulating film 9 made of, for example, silicon nitride (SiN). After the source electrode 3s and the drain electrode 3d are formed and protected with the insulating film 9, only the gate electrode 3g portion may be opened by dry etching to form the gate electrode 3g, and the whole may be protected again with the insulating film 9. After this, electrodes for wiring may be further attached. For the electrodes for wiring, electrolytic gold plating or the like is used.

Once the wafer processing on the front side is complete, a wax material is used to attach the front side of the wafer to a support substrate for processing the back side (the lower surface in Figures 1 and 2). At this time, a tape material may be used instead of the wax material. The thickness of the wax material is, for example, 20 μm. The back side of the wafer is ground and polished while still attached to the support substrate. For example, the substrate thickness is thinned to 50 μm. By thinning the substrate, the heat dissipation and high frequency characteristics of the device are improved.

Next, the via processing process (steps S200 to S230) is performed. To form the via 10v, which is an electrode that penetrates the substrate 1, a resist material is applied using a spin coater, and then the resist is removed only from the processed area using transfer and development patterning. For example, the substrate is etched using ICP (Inductively Coupled Plasma) dry etching to form a through hole for the via 10v (step S200).

Once the through holes are formed, the applied resist material is removed by immersion in a stripping solution. A semiconductor back surface can be obtained with the inner surface of the through hole, which becomes the via 10v in the substrate 1, exposed. Smaller vias 10v are advantageous because they provide greater freedom in layout, but if they are too small, the etching process for forming the through holes will not proceed and they will not be able to penetrate the substrate 1. For example, they can be formed in a cylindrical shape with a diameter of 50 μm. Here, the aspect ratio (via depth/via diameter) of the via 10v (through hole) is 1, but this can vary depending on the substrate thickness and via shape, and can range from 1 to 5.

A seed layer 41 is formed to cover the inner wall of the formed through hole (step S210). The seed layer 41 is formed, for example, by stacking a 200 nm thick gold layer on a 50 nm thick titanium layer in contact with the substrate 1. The titanium layer is a film inserted to improve adhesion between the gold layer, which is the main component of the seed layer 41, and the substrate 1. Titanium nitride, tantalum (Ta), tungsten (W), chromium (Cr), etc. may be used instead of titanium. A platinum layer may also be inserted between the titanium layer and the gold layer. In that case, for example, the titanium layer may be 50 nm thick, the platinum layer may be 50 nm thick, and the gold layer may be 200 nm thick. An insulating film layer may also be inserted between the substrate 1 and the seed layer 41.

In order to promote the deposition reaction of electroless gold plating in the next step of forming the coating layer 42, it is necessary to cover the deposition surface of the seed layer 41 with a catalytic metal. The electroless plating reaction begins when the surface of the seed layer 41 is made into a gold layer. Other than gold, silver (Ag), copper (Cu), palladium (Pd), platinum, nickel, ruthenium (Ru), tin (Sn), etc. may also be used.

On the other hand, in the case of metal surfaces with weak catalytic power, the electroless plating reaction can be initiated by adding a step of immersing the surface in a pretreatment solution containing catalytic metal ions as a pretreatment for electroless plating, thereby adding a catalyst. Once the plating reaction has begun, the gold, which is the deposited metal, itself acts as a catalyst, so the reaction continues and a gold plating film can be obtained (autocatalytic electroless plating).

The seed layer 41 is interposed between the substrate 1 and the gold coating layer 42, and therefore does not need to function as a barrier layer to prevent copper diffusion as was feared in Patent Document 2. Therefore, there is no need to use materials that are difficult to handle and require complex formation processes, such as conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

Once the seed layer 41 is formed, as shown in FIG. 4, the seed layer 41 is covered by electroless gold plating to form a gold coating layer 42 having a recess 42d that opens to the back side (step S220). The figure shows an example of forming a conical recess 42d whose cross section passing through the axial center of the through hole is V-shaped. The formation of the conical recess 42d can be achieved by adjusting the additive in the electroless gold plating solution within an appropriate range. Note that this additive has the effect of suppressing plating deposition on the opening side (lower side in the figure) and preferentially depositing gold from the bottom surface (upper side in the figure) and inner peripheral surface of the seed layer 41.

As shown in the cross-sectional SEM (Scanning Electron Microscope) image of Figure 5, the above-mentioned method allows the formation of a coating layer 42 having a conical recess 42d. Here, it is desirable that the thickness t42 (see Figure 4) from the bottom of the via to the apex of the cone (bottom 42b of recess 42d) is at least 1/4 of the via height Hv. In other words, it is desirable that the depth Dd of recess 42d is less than 4/3 of the via height Hv. By doing so, when forming the filling layer 43 by electrolytic plating in the next step, the shape of the via filling can be achieved without the generation of voids.

In FIG. 4, the via height Hv is drawn as the dimension obtained by subtracting the thickness of the seed layer 41 from the thickness of the substrate 1 including the epitaxial growth layer 2, but the thickness of the seed layer 41 is negligibly thin compared to the thickness of the substrate 1. Thinner than the substrate 1. Therefore, the sum of the thickness of the substrate 1 and the thickness of the epitaxial growth layer 2 is defined as the above-mentioned via height Hv. On the other hand, it is desirable that the thickness t42 is 1/2 or less of the via height Hv. If the thickness t42 is made thicker than 1/2 of the via height Hv, the amount of additive in the plating solution will be reduced, increasing the risk of the via opening being blocked as shown in FIG. 9. Also, because the amount of additive is small, the thickness of the coating layer 42 on the back surface of the wafer will be too thick.

As mentioned above, the vertical growth of the plating can be suppressed by the additive. Therefore, as shown in FIG. 6, once the plating has grown through stages 1, 2, and 3 to a thickness t42 determined by the amount of additive added, the gold plating will not grow even if the wafer is subsequently immersed in an electroless plating solution for, for example, two hours (from stage 3 to stage 4). Therefore, a coating layer 42 having recesses 42d with the same uniform thickness t42 can be formed in each of the multiple through holes in the substrate surface.

Once the coating layer 42 is formed, the recesses 42d shown in FIG. 1 are filled by electrolytic plating to form a gold filling layer 43 with a larger crystal grain size than the coating layer 42 formed by electroless plating (step S230). This forms a solid via 10v whose through hole is filled completely with gold. To efficiently supply gold ions into the recesses 42d, it is advisable to apply a pulse voltage. There is a possibility that a depression will occur in the opening end of the via 10v (the lower surface in the figure), i.e., the filling layer 43, reflecting the recesses 42d in the coating layer 42, but the presence or absence of this depression and its shape are not important.

The via 10v is completely filled with the filling layer 43 formed by electrolytic plating, improving high frequency characteristics and heat dissipation. If the gold film thickness on the back surface (lower part in the figure) of the wafer becomes too thick due to the complete filling of the via 10v, etching can be carried out until the desired film thickness is reached. For example, argon (Ar) ion milling is used for dry etching, and for example, iodine (I)-based wet etching is used for wet etching.

Finally, the support substrate is peeled off from the wafer. The support substrate and wafer are heated to 100°C on a hot plate for at least one minute to melt the wax material, and then slid parallel to the wafer surface to peel them off. The wafer is then immersed in acetone heated to 50°C for 10 minutes to remove the wax material from the surface (step S300). At this time, the higher the temperature and the longer the immersion time, the better the removability.

Variant examples.
The recess 42d of the coating layer 42 does not necessarily have to have a V-shaped (conical) cross-sectional shape as shown in Fig. 4, but may have a curved recessed shape as shown in the modified example of Fig. 7. It is sufficient that the opening width Wd of the recess 42d of the coating layer 42 is formed so as to decrease toward the bottom 42b, and the bottom 42b does not have to be pointed.

Comparative example.
In contrast, as shown in the comparative example in FIG. 8, the opening width Wd of the recess 42dC of the coating layer 42C must not be an overhang shape having a portion that becomes larger toward the bottom 42bC. If electrolytic plating is performed to form the filling layer 43C in this state, the opening of the recess 42dC will be blocked, and a gap will be generated inside the via. If no additive is used, the recess 42dC will have an overhang shape as shown in FIG. 9, the via opening will be blocked first, and a void 4v will be generated. In the comparative example (FIG. 8, FIG. 9), the parts corresponding to the embodiment are distinguished by adding "C" to the end of the reference numeral.

In other words, by forming a coating layer 42 with a recess 42d that tapers toward the bottom 42b using electroless plating, the inside of the via 10v can be completely filled without any voids with a gold filling layer 43 formed by electrolytic plating and having a larger crystal grain size than the coating layer 42.

As a result, the inductor component of the via 10v is reduced, improving high frequency characteristics. Furthermore, an improvement of about 10% in heat dissipation is expected compared to hollow via structures, for example (R. Baskaran, Allen W. Hanson, CS MANTECH Conference (USA), May 18th-21st, 2015 "Simulation of the Impact of Through-Substrate Vias on the Thermal Resistance of Compound Semiconductor Devices"). Furthermore, because the coating layer 42 is made of gold, there is no concern about reduced electrical reliability due to copper contamination.

Embodiment 2.
In the above-mentioned first embodiment, an example in which a portion covered with a coating layer remains on the rear surface of the wafer has been described. In the second embodiment, an example in which the coating layer is removed from the rear surface of the wafer will be described.

FIGS. 10 to 12 are used to explain the semiconductor device and the manufacturing method of the semiconductor device according to the second embodiment, and FIG. 10 is a flow chart for explaining the manufacturing method of the semiconductor device. FIG. 11 is an end view corresponding to FIG. 3 used to explain the configuration after the formation of the covering layer and before the formation of the filling layer in via filling of the semiconductor device, and FIG. 12 is an end view corresponding to FIG. 1 used to explain the configuration of the via. Note that the same reference numerals are used for the same parts as in the first embodiment, and the description of the same parts is omitted, and FIG. 2 and FIG. 4 used in the first embodiment are used.

The configuration of the semiconductor device 10 according to the second embodiment will be described together with the manufacturing process.
As shown in the flow chart of Fig. 10, the process up to the formation of the seed layer 41 is the same as that of the first embodiment. The formation of the coating layer 42 (step S220V) is also the same as that of the first embodiment, up to the formation of the gold coating layer 42 having the recess 42d opening on the back side as described in Fig. 4 of the first embodiment, so as to cover the back surface of the wafer. However, in the process of forming the coating layer 42 (step S220V) of the second embodiment, as shown in Fig. 11, a process of adjusting the coverage by removing the layer of the coating layer 42 and the seed layer 41 precipitated on the front surface (back surface of the wafer) by etching is added.

Dry etching or wet etching is used for the etching. For dry etching, for example, argon ion milling is used. By using dry etching, titanium, gold, and platinum can be etched at the same time. For wet etching, the chemical used is changed depending on the target layer to be removed. For example, an iodine-based chemical is used for gold, and for titanium, buffered hydrofluoric acid (BHF) or a mixture of ammonia (NH ₃ ) and hydrogen peroxide (H ₂ O ₂ ) is used.

Note that the seed layer 41 does not necessarily have to be etched. For example, by etching only the gold with an iodine-based chemical, the flat area on the backside of the wafer can have the surface of the gold base of the seed layer 41 (titanium and platinum in this example). Because a thicker layer of gold is deposited inside the through-holes than on the flat area, the surface is mainly gold.

Then, in the same manner as when forming the seed layer 41, a metal film 44 is formed on the coating layer 42 and the back surface of the wafer by sputtering as shown in FIG. 12 (step S225). For example, a titanium layer with a thickness of 50 nm and a gold layer with a thickness of 200 nm are used.

Then, as in the first embodiment, a filling layer 43 is formed by electrolytic gold plating to fill the recess 42d (step S230). Again, if the thickness of the filling layer 43 becomes too thick, etching may be performed until the desired thickness is reached. For dry etching, for example, argon ion milling or the like is used, and for wet etching, for example, iodine-based wet etching or the like is used.

Here, in the electroless gold plating used to form the coating layer 42, if the film thickness on the flat part of the back surface of the wafer becomes as thick as, for example, about 5 μm, the internal stress of the plating film becomes high, causing wafer warping and chip warping. These can lead to cracks, abnormalities in thermal resistance characteristics, and deterioration of handleability.

In contrast, in the semiconductor device 10 or semiconductor device manufacturing method according to the second embodiment, the plating film on the flat portion on the back surface of the wafer is etched back to reduce the gold thickness on the flat portion, thereby improving the above-mentioned problem. However, when the etch-back is performed, the gold on the flat portion is removed, and if left as is, the electrical resistance of the flat portion increases, which interferes with the power supply in the next electrolytic plating process. Therefore, by forming the metal film 44 by sputtering or vapor deposition, it is possible to ensure the uniformity of the film and the filling characteristics in the via 10v in the electrolytic plating in the process of forming the filling layer 43 (step S230), in the same way as reconstructing the seed layer 41.

In other words, by removing the portion of the coating layer 42 that covers the flat portion on the back surface of the wafer, wafer warping is reduced and wafer cracks and chip cracks can be suppressed. Furthermore, the uniformity of the plating thickness on the flat portion across the wafer surface is improved, which contributes to uniform chip characteristics and high yields.

Embodiment 3.
In the above-mentioned first and second embodiments, the manufacturing method and the crystal grain size are different, but the filling layer is made of the same gold as the covering layer. In the present embodiment 3, an example in which the filling layer is made of copper will be described.

13 and 14 are intended to explain a semiconductor device according to the third embodiment and a method for manufacturing the semiconductor device, with FIG. 13 being an end view corresponding to FIG. 1 used to explain the configuration of the vias in the semiconductor device, and FIG. 14 being an end view corresponding to FIG. 13 to explain the configuration of the vias in the semiconductor device according to a modified example. Note that parts similar to those in the first embodiment are given the same reference numerals, and explanations of similar parts are omitted, with reference to FIGS. 2 to 4 used in the first embodiment.

In the third embodiment, the configuration of the coating layer 42 and the manufacturing method thereof (up to step S220) are the same as those in the first embodiment. However, in the first embodiment, the step of forming the filling layer 53 is performed by electrolytic plating, but the copper filling layer 53 is formed by electrolytic plating of copper (electrolytic copper plating) as shown in FIG. 13.

Variant examples.
It is also possible to perform CMP (Chemical Mechanical Polishing) from the state shown in FIG. 13 after the filling layer 53 has been formed, so as to completely flatten the flat portion of the rear surface of the wafer, as shown in FIG.

As in the first embodiment, by forming a coating layer 42 having a recess 42d that tapers toward the bottom 42b by electroless plating, the inside of the via 10v can be completely filled without gaps together with the copper filling layer 53 formed by electrolytic plating. Furthermore, in the third embodiment, since the filling layer 53 is made of copper, CMP polishing can be performed without using special chemicals, making it easier to flatten the surface. Furthermore, in electrolytic plating, additives that are more effective for filling vias have been developed for copper plating than for gold plating, making it easier to fill the recess 42d.

In other words, in the semiconductor device 10 according to the third embodiment or the method for manufacturing the semiconductor device, the inductor component of the via 10v is reduced, improving the high frequency characteristics. Compared to a case in which the entire filling body 4 is made of copper, the gold coating layer 42 acts as a copper diffusion barrier in addition to the conductive nitride film shown in Patent Document 2, improving the reliability of the device.

In addition, copper has better electrical and thermal conductivity than gold, so the device characteristics (electrical characteristics, high frequency characteristics, thermal characteristics) are improved compared to when the filler 4 is made of gold alone. In addition, the back surface of the wafer can be easily planarized, allowing three-dimensional device design in which the next layer is stacked on top of the planarized layer.

Embodiment 4.
In the above-described third embodiment, an example was described in which the filling layer in the semiconductor device of the first embodiment is made of copper. In the fourth embodiment, an example is described in which the filling layer in the semiconductor device of the second embodiment is made of copper.

15 and 16 are intended to explain the semiconductor device and the method of manufacturing the semiconductor device according to the fourth embodiment, with FIG. 15 being an end view corresponding to FIG. 12 used to explain the second embodiment and intended to explain the via configuration of the semiconductor device, and FIG. 16 being an end view corresponding to FIG. 15 and intended to explain the via configuration of the semiconductor device according to the modified example. Note that parts similar to those in the first and second embodiments are given the same reference numerals, and explanations of similar parts are omitted, with reference to FIGS. 2 and 4 used in the first embodiment and FIGS. 10 and 11 used in the second embodiment.

In this fourth embodiment, the configuration of the coating layer 42 and the manufacturing method thereof (up to step S225) are the same as those in the second embodiment. However, in this fourth embodiment, the step of forming the filling layer 53 is performed by electrolytic plating, but the copper filling layer 53 is formed by electrolytic plating of copper (electrolytic copper plating) as shown in FIG. 15.

Variant examples.
It is also possible to perform CMP polishing from the state shown in FIG. 15 after the filling layer 53 has been formed, so as to completely flatten the flat portion of the rear surface of the wafer, as shown in FIG.

As in the second embodiment, by forming a coating layer 42 having a recess 42d that tapers toward the bottom 42b by electroless plating, the inside of the via 10v can be completely filled without gaps together with the copper filling layer 53 formed by electrolytic plating. Furthermore, in the fourth embodiment, since the filling layer 53 is made of copper, CMP polishing can be performed without using special chemicals, making it easier to flatten the surface. Furthermore, in electrolytic plating, additives that are more effective for filling vias have been developed for copper plating than for gold plating, making it easier to fill the recess 42d.

In other words, in the semiconductor device 10 according to the fourth embodiment or the method for manufacturing the semiconductor device, the inductor component of the via 10v is reduced, improving the high frequency characteristics. Compared to a case in which the entire filling body 4 is made of copper, the gold coating layer 42 acts as a copper diffusion barrier in addition to the conductive nitride film, improving the reliability of the device.

In addition, copper has better electrical and thermal conductivity than gold, so the device characteristics (electrical characteristics, high frequency characteristics, thermal characteristics) are improved compared to when the filler 4 is made of gold alone. In addition, the back surface of the wafer can be easily planarized, allowing three-dimensional device design in which the next layer is stacked on top of the planarized layer.

Embodiment 5.
In the above-described third and fourth embodiments, examples were described in which the composition of the filling layer was changed from gold to copper in comparison with the first and second embodiments. In the present fifth embodiment, an example will be described in which the composition of the filling layer is changed from gold to silver.

17 and 18 are intended to explain the semiconductor device and the manufacturing method of the semiconductor device according to the fifth embodiment, with FIG. 17 being an end view corresponding to FIG. 1 used in the description of the first embodiment and illustrating the via configuration of the semiconductor device, and FIG. 18 being an end view corresponding to FIG. 12 used in the description of the second embodiment and illustrating the via configuration of the semiconductor device according to the modified example. Note that parts similar to those in the first and second embodiments are given the same reference numerals, and descriptions of similar parts are omitted, and FIG. 2 to FIG. 4 used in the first embodiment and FIG. 10 and FIG. 11 used in the second embodiment are used.

In this fifth embodiment, the configuration of the coating layer 42 and the manufacturing method thereof (up to step S220) are the same as those in the first embodiment. However, in this fifth embodiment, the step of forming the filling layer 63 involves electrolytic plating, but the filling layer 63 is formed of silver by electrolytic plating (electrolytic silver plating) as shown in FIG. 17.

Variant examples.
In the modified example, the configuration of coating layer 42 and the manufacturing method thereof (up to step S225) are the same as those in embodiment 2. However, in this modified example, the step of forming filling layer 63 is performed by electrolytic plating, but by electrolytic plating of silver (electrolytic silver plating), to form filling layer 63 of silver, as shown in FIG.

As in the first and second embodiments, a coating layer 42 having a recess 42d that tapers toward the bottom 42b is formed by electroless plating, and together with the silver filling layer 63 formed by electrolytic plating, the inside of the via 10v can be completely filled without gaps. Furthermore, in the fifth embodiment, since the filling layer 63 is made of silver, there is no need to worry about copper contamination as in the first and second embodiments, and there is no concern about a decrease in electrical reliability.

In addition, silver has better electrical and thermal conductivity than gold or copper, so the inductor component of via 10v is lower and the device characteristics (electrical characteristics, high frequency characteristics, thermal characteristics) are improved compared to when the filler 4 is made of gold alone or when the filler layer is made of copper.

Embodiment 6.
In the above-mentioned embodiment 5, an example was described in which the composition of the filling layer was changed from gold to silver in comparison with embodiments 1 and 2. In the present embodiment 6, an example will be described in which the composition of the filling layer is changed from gold to nickel.

19 and 20 are intended to explain the semiconductor device and the method of manufacturing the semiconductor device according to the sixth embodiment, with FIG. 19 being an end view corresponding to FIG. 1 used in the explanation of the first embodiment and illustrating the via configuration of the semiconductor device, and FIG. 20 being an end view corresponding to FIG. 12 used in the explanation of the second embodiment and illustrating the via configuration of the semiconductor device according to the modified example. Note that parts similar to those in the first and second embodiments are given the same reference numerals, and explanations of similar parts are omitted, and FIG. 2 to FIG. 4 used in the first embodiment and FIG. 10 and FIG. 11 used in the second embodiment are used.

In the sixth embodiment, the configuration of the coating layer 42 and the manufacturing method thereof (up to step S220) are the same as in the first embodiment. However, in the sixth embodiment, the step of forming the filling layer 73 is performed by electrolytic plating, but the nickel (Ni) filling layer 73 is formed by electrolytic plating (electrolytic nickel plating) as shown in FIG. 19.

Variant examples.
In the modified example, the configuration of coating layer 42 and its manufacturing method (up to step S225) are the same as those in the embodiment 2. However, in this modified example, the step of forming filling layer 73 is performed by electrolytic plating, but by electrolytic plating of nickel (electrolytic nickel plating), to form nickel filling layer 73 as shown in FIG.

As in the first and second embodiments, by forming a coating layer 42 having a recess 42d that tapers toward the bottom 42b by electroless plating, the inside of the via 10v can be completely filled without gaps with the silver filling layer 63 formed by electrolytic plating. Therefore, compared to the hollow case, it is expected that the high frequency characteristics will be improved by suppressing the heat dissipation and inductor components. Furthermore, in the sixth embodiment, since the filling layer 73 is made of nickel, there is no need to worry about copper contamination as in the first and second embodiments, and there is no concern about a decrease in electrical reliability.

The back surface of the high frequency device is die-bonded with gold-tin (AuSn) solder, silver-tin (SnAg) solder, etc., but when die-bonding to a gold or copper surface with solder, a thick alloy layer is formed at the interface, leading to poor conductivity, poor adhesion, and deterioration of thermal properties. However, in this embodiment 6, the nickel that constitutes the filling layer 73 at the gold and solder interface acts as a barrier layer, preventing these deteriorations in properties.

Embodiment 7.
In the above-mentioned fifth and sixth embodiments, examples were described in which the composition of the filling layer was changed from gold to silver and nickel, as compared with the first and second embodiments. In the seventh embodiment, an example will be described in which the composition of the filling layer is changed from gold to tin.

21 and 22 are intended to explain the semiconductor device and the method of manufacturing the semiconductor device according to the seventh embodiment, with FIG. 21 being an end view corresponding to FIG. 1 used in the explanation of the first embodiment and illustrating the via configuration of the semiconductor device, and FIG. 22 being an end view corresponding to FIG. 12 used in the explanation of the second embodiment and illustrating the via configuration of the semiconductor device according to the modified example. Note that parts similar to those in the first and second embodiments are given the same reference numerals, and explanations of similar parts are omitted, and FIG. 2 to FIG. 4 used in the first embodiment and FIG. 10 and FIG. 11 used in the second embodiment are used.

In the seventh embodiment, the configuration of the coating layer 42 and the manufacturing method thereof (up to step S220) are the same as in the first embodiment. However, in the seventh embodiment, the step of forming the filling layer 83 is performed by electrolytic plating, but the tin filling layer 83 is formed by electrolytic plating of tin (electrolytic tin plating) as shown in FIG. 21.

Variant examples.
In the modified example, the configuration of coating layer 42 and the manufacturing method thereof (step S225) are the same as those in the embodiment 2. However, in this modified example, the step of forming filling layer 83 is performed by electrolytic plating, but by electrolytic plating of tin (electrolytic tin plating), to form tin filling layer 83 as shown in FIG.

As in the first and second embodiments, by forming a coating layer 42 having a recess 42d that tapers toward the bottom 42b by electroless plating, the inside of the via 10v can be completely filled without gaps with the tin filling layer 83 formed by electrolytic plating. Therefore, compared to the hollow case, it is expected that the high frequency characteristics will be improved by suppressing the heat dissipation and inductor components. Furthermore, in the seventh embodiment, since the filling layer 83 is made of tin, there is no need to worry about copper contamination as in the first and second embodiments, and there is no concern about a decrease in electrical reliability.

The backside of the high frequency device is die-bonded using gold-tin (AuSn) solder, silver-tin (SnAg) solder, etc., but this eliminates the need to apply solder. In addition, since the tin on the backside of the wafer is a component of the solder, the solder is essentially formed directly on the device, resulting in good adhesion.

Furthermore, although various exemplary embodiments and examples are described in this application, the various features, aspects, and functions described in one or more embodiments are not limited to application in a particular embodiment, but may be applied to the embodiments alone or in various combinations. Thus, countless variations not illustrated are anticipated within the scope of the technology disclosed in this specification. For example, this includes cases in which at least one component is modified, added, or omitted, and even cases in which at least one component is extracted and combined with components of another embodiment.

As described above, the semiconductor device 10 of the present application includes a substrate 1 made of a semiconductor material, a wiring member formed on one surface (the upper surface in the figure) of the substrate 1, a first plating layer (coating layer 42) made of gold that opens on the other surface of the substrate 1 and covers the inner wall of a cylindrical hole with the wiring member (surface electrode 3) as its bottom surface, and has a recess 42d recessed from the opening side toward the bottom surface, and a solid via 10v that has a second plating layer (filling layer 43, 53, 63, 73, 83) made of copper, silver, nickel, tin, or gold with a crystal grain size larger than that of the first plating layer (coating layer 42) that fills the recess 42d. This makes it possible to obtain a semiconductor device that has good electrical connection and heat dissipation in the thickness direction through the via 10v at low cost without worrying about copper contamination.

In particular, if the recess 42d is configured to widen from the bottom surface toward the opening, it is possible to reliably obtain a semiconductor device with excellent electrical conductivity and heat dissipation without the generation of voids.

Furthermore, if the thickness t42 of the first plating layer (coating layer 42) to the bottom surface of the recess is set to 1/4 or more of the thickness of the substrate (via height Hv), the occurrence of voids can be more reliably prevented.

If a metal film 44 containing titanium, tantalum, tungsten, chromium, or platinum is provided between the first plating layer (coating layer 42) and the second plating layer (filling layer 43, 53, 63, 73, 83), the plating film of the filling layer 43 becomes uniform, and the embeddability in the via 10v is further improved.

If the substrate 1 is made of silicon carbide, indium phosphide, gallium nitride, germanium silicide, germanium, or silicon, a semiconductor device with higher performance can be obtained.

As described above, the manufacturing method of the semiconductor device 10 of the present application includes the steps of forming a wiring member on one side of the substrate 1 of the semiconductor material, opening on the other side of the substrate 1 and forming a cylindrical hole with the wiring member (surface electrode 3) as the bottom (steps S100 to S200), forming a first gold plating layer (coating layer 42) by electroless plating so as to cover the inner wall of the cylindrical hole and form a recess 42d recessed from the opening side toward the bottom (steps S220, S220V), and forming a second plating layer (filling layer 43) of copper, silver, nickel, tin, or gold by electrolytic plating so as to fill the recess 42d (step S230). This makes it possible to obtain a semiconductor device at low cost that has good electrical connection and heat dissipation in the thickness direction through the vias 10v without worrying about copper contamination.

If the process includes a step (step S225) of forming a metal film 44 that covers the inner surface of the recess 42d by sputtering or vapor deposition, the plating film will be uniform when the filling layer 43 is formed by electrolytic plating, and the embeddability of the via 10v will be improved.

1: Substrate, 10: Semiconductor device, 10v: Via, 2: Epitaxial growth layer, 3: Surface electrode (wiring member), 4: Filler, 41: Seed layer, 42: Cover layer (first plating layer), 42d: Recess, 43: Filler layer (second plating layer), 44: Metal film, 53: Filler layer (second plating layer), 63: Filler layer (second plating layer), 73: Filler layer (second plating layer), 83: Filler layer (second plating layer), Dd: Depth, Hv: Via height, t42: Thickness, Wd: Opening width.

Claims (7)

a substrate of semiconductor material;
a wiring member formed on one surface of the substrate; a first plating layer of gold that opens on the other surface of the substrate, covers an inner wall of a cylindrical hole having the wiring member as a bottom surface, and has a recess recessed from the opening side toward the bottom surface; and a second plating layer of copper, silver, nickel, tin, or gold that fills the recess and has a crystal grain size larger than that of the first plating layer;
A semiconductor device comprising: The semiconductor device according to claim 1, characterized in that the recess widens from the bottom surface toward the opening. The semiconductor device according to claim 1 or 2, characterized in that the thickness of the first plating layer to the bottom surface of the recess is at least 1/4 of the thickness of the substrate. The semiconductor device according to any one of claims 1 to 3, characterized in that it has a metal film containing any one of titanium, tantalum, tungsten, chromium, and platinum and interposed between the first plating layer and the second plating layer. The semiconductor device according to any one of claims 1 to 4, characterized in that the substrate is made of any one of silicon carbide, indium phosphide, gallium nitride, germanium silicide, germanium, and silicon. A step of forming a wiring member on one surface of a substrate made of a semiconductor material, and forming a cylindrical hole on the other surface of the substrate, the hole being open and having the wiring member as a bottom surface;
forming a first plating layer of gold by electroless plating so as to cover the inner wall of the cylindrical hole and form a recess recessed from the opening side toward the bottom surface; and forming a second plating layer of any of copper, silver, nickel, tin, and gold by electrolytic plating so as to fill the recess.
2. A method for manufacturing a semiconductor device comprising the steps of: The method for manufacturing a semiconductor device according to claim 6, further comprising the step of forming a metal film that covers the inner surface of the recess by a sputtering method or a vapor deposition method.

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