JP7378693B1 - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

A semiconductor device (10) of the present application includes a substrate (1) made of a semiconductor material, a surface electrode (3) formed on one surface of the substrate (1), and an opening on the other surface of the substrate (1). The inner wall of the cylindrical hole with (3) as the bottom is covered with a gold coating layer (42) in which a recess (42d) is formed that is concave from the opening side toward the bottom, and the recess (42d) is filled. , a filling layer (43) made of any of copper, silver, nickel, tin, and gold having a crystal grain size larger than that of the coating layer (42), and a solid via (10V). .

Description

The present application relates to a semiconductor device and a method for manufacturing the semiconductor device.

In semiconductor devices that have electrodes (vias) that penetrate the front and back surfaces of a semiconductor substrate, electrical connections and high-frequency characteristics are improved by filling the vias with copper (Cu) plating, which is usually referred to as Cu via filling. This is expected to improve heat dissipation and heat dissipation.

Via filling by copper plating is performed by electrolytic plating, which requires precise control of the composition of the plating solution, the applied voltage waveform, and the stirring of the solution (see, for example, Patent Document 1). Furthermore, since there is a concern that electrical characteristics may deteriorate due to diffusion of copper into the inside of the semiconductor, it is necessary to form a diffusion barrier layer on the inner wall of the via (see, for example, Patent Document 2).

JP 2014-095104 (Paragraphs 0042 to 0050, Table 1) Special Publication No. 2013-532903 (Paragraph 0039, Figure 13)

However, Cu via filling by electrolytic plating requires precise control of the plating process (composition of the plating solution, applied voltage waveform, and stirring of the solution), resulting in problems such as excessive equipment investment and increased cost for process control. there were. Furthermore, the diffusion barrier layer requires a material such as conductive metal nitride that has a complicated formation process and is difficult to handle, which again poses problems such as excessive investment in equipment and increased costs such as process control.

The present application discloses a technique for solving the above problems, and aims to obtain a semiconductor device having good electrical connection and heat dissipation in the thickness direction at a low cost.

The semiconductor device disclosed in the present application includes a substrate made of a semiconductor material, an inner wall of a cylindrical hole that is opened on the other side of the substrate, and has the wiring member as the bottom surface, and is provided with a substrate formed of a semiconductor material. a first plating layer made of gold in which a concave portion is formed; and a second plating layer that fills the concave portion and is made of copper, silver, nickel, tin, or gold having a crystal grain size larger than that of the first plating layer. and a metal film containing any one of titanium, tantalum, tungsten, chromium, and platinum and interposed between the first plating layer and the second plating layer. It is characterized by

A method for manufacturing a semiconductor device disclosed in the present application includes forming a wiring member on one surface of a substrate made of a semiconductor material, and forming a cylindrical hole that opens on the other surface of the substrate and has the wiring member as a bottom surface. a step of forming a first plating layer of gold by electroless plating so as to cover the inner wall of the cylindrical hole and form a recess that is concave from the opening side toward the bottom surface; , a step of forming a metal film covering the inner surface of the recess by a sputtering method or a vapor deposition method, and a step of forming a second metal film of copper, silver, nickel, tin, or gold by electrolytic plating to fill the recess. The method is characterized by including a step of forming a plating layer.

According to the semiconductor device or the method for manufacturing a semiconductor device disclosed in the present application, a gold coating layer is formed on the inner wall of the via in a simple process without requiring an excessively large device, so that good electrical connection is achieved in the thickness direction. A semiconductor device having heat dissipation properties can be obtained at low cost.

FIG. 2 is an end view for explaining the configuration of a via of the semiconductor device according to the first embodiment. 1 is an end view for explaining the configuration of a semiconductor device according to a first embodiment; FIG. 3 is a flowchart for explaining a method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is an end view during a via filling process for explaining the structure of a via coating layer of the semiconductor device according to the first embodiment. FIG. 3 is a diagram showing a cross-sectional SEM image during a via filling process in the semiconductor device according to the first embodiment. FIG. 3 is a schematic end view showing states at each stage during formation of a covering layer in via filling of the semiconductor device according to the first embodiment. 7 is an end view for explaining the configuration of a via of a semiconductor device according to a modification of the first embodiment. FIG. FIG. 3 is an end view for explaining the configuration of a via of a semiconductor device according to a comparative example. FIG. 7 is a diagram showing a cross-sectional SEM image during a via filling process in a semiconductor device according to a comparative example. FIG. 7 is an end view for explaining the configuration before forming a filling layer in via filling of a semiconductor device according to a second embodiment. 7 is a flowchart for explaining a method for manufacturing a semiconductor device according to a second embodiment. 7 is an end view for explaining the configuration of a via of a semiconductor device according to a second embodiment. FIG. FIG. 7 is an end view for explaining the configuration of a via of a semiconductor device according to a third embodiment. FIG. 7 is an end view for explaining the configuration of a via of a semiconductor device according to a modification of the third embodiment. FIG. 7 is an end view for explaining the configuration of a via of a semiconductor device according to a fourth embodiment. FIG. 7 is an end view for explaining the configuration of a via of a semiconductor device according to a modification of the fourth embodiment. FIG. 7 is an end view for explaining the configuration of a via of a semiconductor device according to a fifth embodiment. FIG. 7 is an end view for explaining the configuration of a via of a semiconductor device according to a modification of the fifth embodiment. FIG. 7 is an end view for explaining the configuration of a via of a semiconductor device according to a sixth embodiment. FIG. 7 is an end view for explaining the configuration of a via of a semiconductor device according to a modification of the sixth embodiment. FIG. 7 is an end view for explaining the configuration of a via of a semiconductor device according to a seventh embodiment. FIG. 12 is an end view for explaining the configuration of a via of a semiconductor device according to a modification of the seventh embodiment.

Embodiment 1.
1 to 9 are for explaining the semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment, and FIG. 1 is for explaining the structure of the via of the semiconductor device in FIG. FIG. 2 is an end view taken along line AA. FIG. 2 is an end view for explaining the configuration of the semiconductor device. FIG. 3 is a flowchart for explaining a method for manufacturing a semiconductor device, and FIG. 4 is a flowchart for explaining the structure of a coating layer for a via in a semiconductor device. An end view corresponding to FIG. 1 before formation, and FIG. 5 is a cross-sectional SEM image at a stage where a coating layer similar to that shown in FIG. 4 is formed in the via filling process. Further, FIG. 6 is a schematic end view showing the state at each stage during formation of a covering layer in via filling of the semiconductor device according to the first embodiment.

Further, FIG. 7 is an end view corresponding to FIG. 4 at a stage where a covering layer is formed to explain the structure of a via of a semiconductor device according to a modification. On the other hand, FIG. 8 is an end view at a stage where a covering layer is formed to explain the structure of a via of a semiconductor device according to a comparative example, and FIG. 9 is a cross-sectional view at a stage where a covering layer similar to that shown in FIG. 8 is formed in a via filling process. This is an SEM image.

The semiconductor device 10 according to the first embodiment is assumed to be, for example, a semiconductor device called a high electron mobility transistor (HEMT). As shown in FIGS. 1 and 2, a case will be described as an example in which a via 10v is formed from the back surface directly under the source electrode 3s on the front surface (the upper surface in the figure). Note that the via 10v shown in FIG. 1 is a detailed diagram of the via 10v formed directly under the source electrode 3s in FIG. 2, but the via 10v does not necessarily need to be directly under the source electrode 3s, It may be located directly under the conductor layer (wiring member) formed on the surface.

In a semiconductor device 10, an epitaxial growth layer 2 is provided on a silicon carbide (SiC) substrate 1, and a source electrode 3s, a drain electrode 3d, and a gate electrode 3g (collectively, a surface electrode 3) are provided thereon. The via 10v is formed directly under the source electrode 3s using the source electrode 3s as an etching stop layer. There is a metal layer along the inner wall of the via 10v, and using this metal layer as a seed layer 41, a covering layer 42 and a filling layer 43 are formed in this order to form the filling body 4, thereby achieving via filling.

In the first embodiment and subsequent embodiments, a gallium nitride (GaN) HEMT on a silicon carbide substrate 1 will be described as an example, but the present invention is not limited to this. For example, similar effects can be obtained with other semiconductor substrates such as compound semiconductors such as indium phosphide (InP), gallium nitride, germanium silicide (SiGe), and silicon (Si)-based semiconductors. This is because gold (Au) constituting the coating layer 42 of the via 10v is formed on the seed layer 41, so it does not depend on the element type of the substrate 1.

Next, details of the configuration of the semiconductor device 10 according to the first embodiment will be explained together with a manufacturing method with reference to the flowchart of FIG.
First, epitaxial growth, metal film, insulating film formation, and transfer patterning are repeatedly performed in a wafer process on the surface (upper surface in FIGS. 1 and 2) of a substrate 1 made of SiC single crystal, and an electric circuit is formed on the surface. form (step S100). Note that the wafer process is performed on a disk-shaped wafer having a diameter of 4 to 8 inches and a thickness of 0.35 mm or 0.5 mm.

First, an epitaxial growth layer 2 is formed on a substrate 1. In the case of a gallium nitride HEMT, it is common to have a stacked structure in which an aluminum gallium nitride (AlGaN) layer is stacked on a gallium nitride layer. Next, a source electrode 3s, a drain electrode 3d, and a gate electrode 3g are formed. The source electrode 3s and drain electrode 3d are made of, for example, titanium/aluminum/gold (Ti/Al/Au). A laminated structure of titanium/aluminum/nickel/gold (Ti/Al/Ni/Au) is used. A laminated structure of titanium/platinum/gold (Ti/Pt/Au) or the like is used for the gate electrode 3g.

Thereafter, the source electrode 3s, drain electrode 3d, and gate electrode 3g are protected with an insulating film 9 made of silicon nitride (SiN), for example. Note that after forming the source electrode 3s and the drain electrode 3d and protecting them with the insulating film 9, only the gate electrode 3g portion is opened by dry etching to form the gate electrode 3g, and the whole is protected again with the insulating film 9. You can do it like this. After this, electrodes for wiring may be further attached. Electrolytic gold plating or the like is used for the wiring electrodes.

When the front wafer process is completed, the front side of the wafer is attached to a support substrate using a wax material for back side (lower side in FIGS. 1 and 2) processing. At this time, a tape material may be used instead of the wax material. The thickness of the wax material is, for example, 20 μm. The back surface of the wafer is ground and polished while it is attached to the support substrate. For example, the substrate thickness is reduced to 50 μm. By making it thinner, the heat dissipation and high frequency characteristics of the device are improved.

Next, a via processing process (steps S200 to S230) is performed. In order to form vias 10v, which are electrodes penetrating the substrate 1, a resist material is applied using a spin coater, and then the resist is removed only from the processed portion by transfer/development patterning. For example, the substrate is etched by ICP (Inductively Coupled Plasma) dry etching to form a through hole for the via 10v (step S200).

Once the through holes are formed, the applied resist material is removed by immersion in a stripping solution. It is possible to obtain the back surface of the semiconductor in which the inner surface of the through hole that becomes the via 10v of the substrate 1 is exposed. The smaller the via 10v is, the more flexible the layout is, which is advantageous. However, if the via 10v is too small, etching will not proceed when forming the through hole, and the substrate 1 will not be able to be penetrated. For example, it is formed in a cylindrical shape with a diameter of 50 μm. Here, the aspect ratio (via depth/via diameter) of the via 10v (through hole) is 1, but it varies depending on the substrate thickness and via shape, and can be implemented from 1 to 5.

A seed layer 41 is formed to cover the inner wall of the formed through hole (step S210). The seed layer 41 is formed by laminating, for example, a 200 nm thick gold layer on a 50 nm thick titanium layer in contact with the substrate 1 . The titanium layer is a film inserted to improve the adhesion between the gold layer, which is the main component of the seed layer 41, and the substrate 1. Instead of titanium, titanium nitride, tantalum (Ta), tungsten (W), and chromium (Cr) are used. ) etc. may be used. Further, a platinum layer may be inserted between the titanium layer and the gold layer, and in that case, the titanium layer thickness is, for example, 50 nm, the platinum layer thickness is 50 nm, and the gold layer is 200 nm thick. Further, an insulating film layer may be inserted between the substrate 1 and the seed layer 41.

Note that in order to advance the precipitation reaction of electroless gold plating in the next step of forming the coating layer 42, it is necessary to cover the deposition surface of the seed layer 41 with a catalytic metal. By forming the gold layer on the surface of the seed layer 41, an electroless plating reaction is started. In addition to gold, silver (Ag), copper (Cu), palladium (Pd), platinum, nickel, ruthenium (Ru), tin (Sn), etc. may be used.

On the other hand, in the case of metal surfaces with weak catalytic power, the electroless plating reaction can be started by adding a step of applying a catalyst by immersing the surface in a pretreatment solution containing catalytic metal ions as a pretreatment for electroless plating. can be done. Once the plating reaction starts, the gold itself, which is the deposited metal, acts as a catalyst, so the reaction continues and a gold plated film can be obtained (autocatalytic electroless plating).

Since the seed layer 41 is interposed between the substrate 1 and the gold coating layer 42, it does not need to act as a barrier layer to prevent copper diffusion, as was feared in Patent Document 2. Therefore, there is no need to use materials that have complicated formation processes and are difficult to handle, such as conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN). .

Once the seed layer 41 is formed, as shown in FIG. 4, a gold coating layer 42 is formed by electroless gold plating to cover the seed layer 41 and have a recess 42d opening on the back side (step S220). ). The figure shows an example in which a conical recess 42d whose cross section passing through the axial center of the through hole is V-shaped is formed. Formation of the conical recess 42d can be achieved by adjusting additives in the electroless gold plating solution within an appropriate range. Note that this additive has the function of suppressing plating precipitation on the opening side (lower side in the figure) and preferentially depositing gold from the bottom surface (upper side in the figure) and inner peripheral surface of the seed layer 41.

As shown in the cross-sectional SEM (Scanning Electron Microscope) image of FIG. 5, the coating layer 42 could be formed to have a conical recess 42d by the above-described method. Here, the thickness t42 (see FIG. 4) from the bottom of the via to the apex of the cone (bottom 42b of the recess 42d) is desirably 1/4 or more of the via height Hv. In other words, the depth Dd of the recess 42d is desirably less than 4/3 of the via height Hv. By doing so, when forming the filling layer 43 by the next electrolytic plating, it is possible to realize a via-embedded shape without generating voids.

In FIG. 4, the dimension obtained by subtracting the thickness of the seed layer 41 from the thickness of the substrate 1 including the epitaxial growth layer 2 is drawn as the via height Hv, but the thickness of the seed layer 41 is smaller than the thickness of the substrate 1. It is so thin that it can be ignored. It is thinner than substrate 1. Therefore, the sum of the thickness of the substrate 1 and the thickness of the epitaxial growth layer 2 is defined as the above-mentioned via height Hv. On the other hand, the thickness t42 is preferably 1/2 or less of the via height Hv. If the thickness t42 is made thicker than 1/2 of the via height Hv, the amount of additive in the plating solution decreases, increasing the risk of the via opening being blocked as shown in FIG. Further, since the amount of additives is small, the thickness of the coating layer 42 on the back surface of the wafer becomes too thick.

As mentioned above, the vertical growth of plating can be suppressed by additives. Therefore, as shown in FIG. 6, when the plating grows in stages 1, 2, and 3 to a thickness t42 determined by the amount of additive added, the wafer is placed in the electroless plating solution for, for example, 2 hours. Gold plating does not grow upon immersion (stage 3 to stage 4). Therefore, the covering layer 42 having the recesses 42d having the uniform thickness t42 can be formed in each of the plurality of through holes in the substrate surface.

When the coating layer 42 is formed, the inside of the recess 42d shown in FIG. 1 is filled by electrolytic plating to form a gold filling layer 43 having a larger crystal grain size than the coating layer 42 formed by electroless plating (step S230). . As a result, a solid via 10v whose through hole is filled with gold is formed. In order to efficiently supply gold ions into the recess 42d, it is preferable to apply a pulse voltage. There is a possibility that a depression will be formed in the opening end of the via 10v (lower surface in the figure), that is, in the filling layer 43, reflecting the depression 42d of the covering layer 42, but the presence or absence and shape of this depression are not important.

Since the via 10v is completely filled with the filling layer 43 formed by electrolytic plating, high frequency characteristics and heat dissipation are improved. If the gold film on the back side of the wafer (lower side in the figure) becomes too thick by completely filling the via 10v, etching may be performed until the desired film thickness is achieved. The dry etching uses, for example, argon (Ar) ion milling, and the wet etching uses, for example, iodine (I)-based wet etching.

Finally, the support substrate is peeled off from the wafer. The support substrate and wafer are heated to 100° C. for 1 minute or more on a hot plate to melt the wax material, and the wax material is peeled off by sliding each other parallel to the wafer surface. Then, it is finished by immersing it in acetone heated to 50° C. for 10 minutes to remove the wax material on the surface (step S300). At this time, the higher the temperature and the longer the immersion time, the better the removability.

Variation example.
Note that the recessed portion 42d of the coating layer 42 does not necessarily have to have a V-shaped (conical) cross-sectional shape as shown in FIG. It may be a shape. It is sufficient that the opening width Wd of the recess 42d of the covering layer 42 is formed so as to decrease toward the bottom 42b, and the bottom 42b does not need to be sharp.

Comparative example.
On the other hand, as in the comparative example shown in FIG. 8, the opening width Wd of the recess 42dC of the covering layer 42C should not have an overhang shape with a portion that increases toward the bottom 42bC. This is because if electrolytic plating for forming the filling layer 43C is performed in this state, the opening of the recess 42dC will be closed and a void will be created inside the via. If no additive is used, the recess 42dC will have an overhanging shape as shown in FIG. 9, and the via opening will be closed first, creating a void 4v. Note that in the comparative example (FIGS. 8 and 9), parts corresponding to the embodiment are distinguished by adding "C" to the end of the reference numeral.

That is, by forming the coating layer 42 having the concave portion 42d that becomes thinner toward the bottom portion 42b by electroless plating, the gold filling layer 43 formed by electrolytic plating and having a larger crystal grain size than the coating layer 42 is formed. The inside of the via 10v can be completely filled without any gaps.

As a result, the inductor component of the via 10v is reduced and the high frequency characteristics are improved. For example, it is expected that heat dissipation will be improved by about 10% compared to a hollow via structure (R. Baskaran, Allen W. Hanson, CS MANTECH Conference (USA), May 18th-21st, 2015 “Simulation of the Impact of Through-Substrate Vias on the Thermal Resistance of Compound Semiconductor Devices”). Furthermore, since the covering layer 42 is made of gold, there is no concern that electrical reliability will deteriorate due to copper contamination.

Embodiment 2.
In the first embodiment described above, an example was described in which a portion covered with the coating layer was left on the back surface of the wafer. In the second embodiment, an example in which the coating layer is removed from the back surface of the wafer will be described.

10 to 12 are for explaining the semiconductor device and the method for manufacturing the semiconductor device according to the second embodiment, and FIG. 10 is a flowchart for explaining the method for manufacturing the semiconductor device. FIG. 11 is an end view corresponding to FIG. 3 used in the description of the first embodiment, for explaining the configuration after the formation of the covering layer and before the formation of the filling layer in via filling of a semiconductor device, and FIG. 12 is an end view of the via filling. FIG. 2 is an end view corresponding to FIG. 1 used to explain the first embodiment for explaining the configuration. Note that the same parts as in the first embodiment are given the same reference numerals, explanations of the same parts are omitted, and FIGS. 2 and 4 used in the first embodiment are referred to.

The configuration of the semiconductor device 10 according to the second embodiment will be explained together with the manufacturing process.
As shown in the flowchart of FIG. 10, the process up to the formation of the seed layer 41 is the same as in the first embodiment. Then, in the formation of the coating layer 42 (step S220V), the gold coating layer 42 is formed so as to have the concave portion 42d opening on the back surface side as described in FIG. 4 of the first embodiment, and to cover the back surface of the wafer. are the same. However, in the step of forming the covering layer 42 (step S220V) in the second embodiment, as shown in FIG. A step is added to adjust the coverage range.

Dry etching or wet etching is used for etching. For example, argon ion milling is used for the dry etching. Dry etching allows titanium, gold, and platinum to be etched all at once. In wet etching, the chemical solution used is changed depending on the layer to be removed. For gold, for example, an iodine-based chemical is used, and for titanium, buffered hydrofluoric acid (BHF) or a mixture of ammonia (NH ₃ ) and hydrogen peroxide (H ₂ O ₂ ) is used. use

Note that the seed layer 41 does not necessarily need to be etched. For example, by etching only gold with an iodine-based chemical solution, the flat portion of the back surface of the wafer can obtain the surface of the gold underlying surface (titanium or platinum in this example) of the seed layer 41. Since gold is deposited thicker inside the through hole than in the flat part, the gold surface is mainly formed.

Thereafter, as in the case of forming the seed layer 41, a metal film 44 is formed on the covering layer 42 and the back surface of the wafer by sputtering as shown in FIG. 12 (step S225). For example, a titanium layer with a thickness of 50 nm and a gold layer with a thickness of 200 nm are used.

Thereafter, similarly to Embodiment 1, the filling layer 43 that fills the recess 42d is formed by electrolytic gold plating (step S230). Here too, if the thickness of the filling layer 43 becomes too thick, etching may be performed until the desired thickness is achieved. The dry etching uses, for example, argon ion milling, and the wet etching uses, for example, iodine-based wet etching.

In electroless gold plating for forming the coating layer 42, if the film thickness on the flat part of the back surface of the wafer is as thick as, for example, 5 μm, the internal stress of the plating film is high, causing wafer warping and chip warping. cause. These become causes of cracks, abnormal thermal resistance characteristics, and deterioration of handling properties.

On the other hand, in the semiconductor device 10 or the semiconductor device manufacturing method according to the second embodiment, the plating film on the flat part of the back surface of the wafer is etched back to reduce the gold thickness on the flat part and improve the above-mentioned problems. . On the other hand, when etchback is performed, the gold in the flat areas is lost, so if left as is, the electrical resistance of the flat areas will increase, which will interfere with power supply in the next step, electrolytic plating. Therefore, by forming the metal film 44 by sputtering or vapor deposition, in the same way as the seed layer 41 is reconfigured, the uniformity of the film and the via 10V are improved by electrolytic plating in the filling layer 43 forming step (step S230). It is possible to ensure the embedding properties within.

That is, by removing the portion of the coating layer 42 that covers the flat portion of the back surface of the wafer, wafer warpage is reduced and wafer cracks and chip cracks can be suppressed. Furthermore, since the uniformity of the plating thickness on the flat part within the wafer surface is improved, it also contributes to uniformity of chip characteristics and higher yield.

Embodiment 3.
In the first and second embodiments described above, although the manufacturing method is different and the crystal grain size is different, an example in which the filling layer is made of the same gold as the coating layer has been described. In the third embodiment, an example in which the filling layer is made of copper will be described.

13 and 14 are for explaining a semiconductor device and a method for manufacturing the semiconductor device according to the third embodiment, and FIG. 13 is a diagram for explaining the structure of the via of the semiconductor device according to the first embodiment. FIG. 14 is an end view corresponding to FIG. 13 used to explain the structure of a via of a semiconductor device according to a modified example. Note that the same parts as in Embodiment 1 are given the same reference numerals, explanations of the same parts are omitted, and FIGS. 2 to 4 used in Embodiment 1 are referred to.

Also in the third embodiment, the structure of the coating layer 42 and the manufacturing method thereof (up to step S220) are the same as those in the first embodiment. However, in the first embodiment, in the step of forming the filling layer 53, the copper filling layer 53 is formed by electrolytic plating of copper (electrolytic copper plating), as shown in FIG. do.

Variation example.
Note that CMP polishing (Chemical Mechanical Polishing) may be performed from the state shown in FIG. 13 in which the filling layer 53 is formed to completely flatten the flat portion of the back surface of the wafer, as shown in FIG.

By forming the covering layer 42 having the concave portion 42d that becomes narrower toward the bottom portion 42b by electroless plating as in the first embodiment, the inside of the via 10v is freed from voids with the copper filling layer 53 formed by electrolytic plating. Can be fully embedded. Furthermore, in Embodiment 3, since the filling layer 53 is made of copper, CMP polishing can be performed without using special chemicals, making it easy to flatten the surface. Furthermore, in electrolytic plating, the development of additives that are more effective for filling vias in copper plating than in gold plating is progressing, making it easier to fill in the recess 42d.

That is, in the semiconductor device 10 or the method for manufacturing a semiconductor device according to the third embodiment, the inductor component of the via 10v is small and the high frequency characteristics are improved. Compared to the case where the filler 4 is entirely made of copper, the gold coating layer 42 acts as a copper diffusion barrier in addition to the conductive nitride film shown in Patent Document 2, improving the reliability of the device. do.

Further, since copper has better electrical conductivity and thermal conductivity than gold, the device characteristics (electrical characteristics, high frequency characteristics, thermal characteristics) are improved compared to the case where the filler 4 is made of only gold. Furthermore, since the back surface of the wafer can be easily flattened, three-dimensional device design can be performed in which the next layer is laminated on top of the flattened layer.

Embodiment 4.
In the third embodiment, an example was described in which the filling layer in the semiconductor device of the first embodiment was made of copper. Embodiment 4 will describe an example in which the filling layer in the semiconductor device of Embodiment 2 is made of copper.

15 and 16 are for explaining a semiconductor device and a method for manufacturing the semiconductor device according to a fourth embodiment, and FIG. 15 is a diagram for explaining a structure of a via of a semiconductor device according to a second embodiment. FIG. 16 is an end view corresponding to FIG. 15 for explaining the structure of a via of a semiconductor device according to a modified example. 2 and 4 used in Embodiment 1, and the drawings used in Embodiment 2. 10 and FIG. 11 are used.

In the fourth embodiment, the structure of the coating layer 42 and the manufacturing method thereof (up to step S225) are the same as in the second embodiment. However, in the fourth embodiment, in the step of forming the filling layer 53, the copper filling layer 53 is formed by electrolytic plating of copper (electrolytic copper plating), as shown in FIG. do.

Variation example.
Note that CMP polishing may be performed from the state shown in FIG. 15 in which the filling layer 53 is formed to completely flatten the flat portion of the back surface of the wafer as shown in FIG.

By forming the covering layer 42 having the concave portion 42d that becomes narrower toward the bottom portion 42b by electroless plating as in the second embodiment, the inside of the via 10v is made void-free with the copper filling layer 53 formed by electrolytic plating. Can be fully embedded. Furthermore, in the fourth embodiment, since the filling layer 53 is made of copper, CMP polishing can be performed without using any special chemicals, and the surface can be easily flattened. Furthermore, in electrolytic plating, the development of additives that are more effective for filling vias in copper plating than in gold plating is progressing, making it easier to fill in the recess 42d.

That is, in the semiconductor device 10 or the method for manufacturing a semiconductor device according to the fourth embodiment, the inductor component of the via 10v is small and the high frequency characteristics are improved. Compared to the case where the filler 4 is entirely made of copper, the gold coating layer 42 acts as a copper diffusion barrier in addition to the conductive nitride film, thereby improving the reliability of the device.

Further, since copper has better electrical conductivity and thermal conductivity than gold, the device characteristics (electrical characteristics, high frequency characteristics, thermal characteristics) are improved compared to the case where the filler 4 is made of only gold. Furthermore, since the back surface of the wafer can be easily flattened, three-dimensional device design can be performed in which the next layer is laminated on top of the flattened layer.

Embodiment 5.
In Embodiments 3 and 4 above, an example was explained in which the structure of the filling layer was changed from gold to copper compared to Embodiments 1 and 2. In the fifth embodiment, an example in which the structure of the filling layer is changed from gold to silver will be described.

17 and 18 are for explaining a semiconductor device and a method for manufacturing a semiconductor device according to a fifth embodiment, and FIG. 17 is a diagram for explaining a structure of a via of a semiconductor device according to a first embodiment. FIG. 18 is an end view corresponding to FIG. 12 used to explain the second embodiment, and FIG. 18 is an end view corresponding to FIG. 12 used to explain the second embodiment, and FIG. 18 is an end view corresponding to FIG. . Note that the same parts as in Embodiments 1 and 2 are given the same reference numerals, and explanations of the same parts are omitted. 10 and FIG. 11 are used.

In the fifth embodiment, the structure of the coating layer 42 and the manufacturing method thereof (up to step S220) are the same as in the first embodiment. However, in the fifth embodiment, in the step of forming the filling layer 63, the silver filling layer 63 is formed by electrolytic plating of silver (electrolytic silver plating), as shown in FIG. do.

Variation example.
In the modified example as well, the structure of the coating layer 42 and the manufacturing method thereof (up to step S225) are the same as in the second embodiment. However, in this modification, in the step of forming the filling layer 63, the silver filling layer 63 is formed by electrolytic plating of silver (electrolytic silver plating), as shown in FIG. 18.

As in Embodiments 1 and 2, the coating layer 42 having the concave portion 42d that becomes narrower toward the bottom portion 42b is formed by electroless plating, so that the inside of the via 10v is filled with the silver filling layer 63 formed by electrolytic plating. It can be completely embedded without any gaps. Furthermore, in the fifth embodiment, since the filling layer 63 is made of silver, there is no need to worry about copper contamination as in the first and second embodiments, and there is no concern that electrical reliability will deteriorate.

Also, since silver has better electrical and thermal conductivity than gold and copper, the inductor component of the via 10V is The device characteristics (electrical characteristics, high frequency characteristics, thermal characteristics) are improved.

Embodiment 6.
In Embodiment 5 above, an example has been described in which the structure of the filling layer is changed from gold to silver compared to Embodiments 1 and 2. In the sixth embodiment, an example in which the composition of the filling layer is changed from gold to nickel will be described.

19 and 20 are for explaining a semiconductor device and a method for manufacturing the semiconductor device according to a sixth embodiment, and FIG. 19 is a diagram for explaining a structure of a via of a semiconductor device according to a first embodiment. 20 is an end view corresponding to FIG. 12 used in the description of Embodiment 2, and FIG. 20 is an end view corresponding to FIG. 12 used in the description of Embodiment 2, and FIG. . Note that the same parts as in Embodiments 1 and 2 are given the same reference numerals, and explanations of the same parts are omitted. 10 and FIG. 11 are used.

In the sixth embodiment, the structure of the coating layer 42 and the manufacturing method thereof (up to step S220) are the same as in the first embodiment. However, in the sixth embodiment, although electrolytic plating is used in the step of forming the filling layer 73, nickel (Ni) electrolytic plating (electrolytic nickel plating) is used to form the nickel filling layer 73, as shown in FIG. Form 73.

Variation example.
In the modified example as well, the structure of the coating layer 42 and the manufacturing method thereof (up to step S225) are the same as in the second embodiment. However, in this modification, in the step of forming the filling layer 73, the nickel filling layer 73 is formed by electrolytic plating of nickel (electrolytic nickel plating), as shown in FIG. 20.

As in Embodiments 1 and 2, the coating layer 42 having the concave portion 42d that becomes narrower toward the bottom portion 42b is formed by electroless plating, so that the inside of the via 10v is filled with the silver filling layer 63 formed by electrolytic plating. It can be completely embedded without any gaps. Therefore, compared to a hollow case, it is expected that heat dissipation and high frequency characteristics will be improved by suppressing the inductor component. Furthermore, in the sixth embodiment, since the filling layer 73 is made of nickel, there is no need to worry about copper contamination, as in the first and second embodiments, and there is no concern that electrical reliability will deteriorate.

Furthermore, the back side of a high-frequency device is die-bonded using gold-tin (AuSn) solder, silver-tin (SnAg) solder, etc., but when die-bonding is done with solder on the gold or copper side, a thick alloy layer is formed at the interface, resulting in poor conductivity and This results in poor adhesion and deterioration of thermal properties. However, in the sixth embodiment, the nickel forming the filling layer 73 at the interface between gold and solder acts as a barrier layer and can prevent these characteristics from deteriorating.

Embodiment 7.
In the fifth and sixth embodiments described above, an example has been described in which the structure of the filling layer is changed from gold to silver and nickel in contrast to the first and second embodiments. In the seventh embodiment, an example in which the structure of the filling layer is changed from gold to tin will be described.

21 and 22 are for explaining a semiconductor device and a method for manufacturing the semiconductor device according to a seventh embodiment, and FIG. 21 is a diagram for explaining a structure of a via of a semiconductor device according to a first embodiment. FIG. 22 is an end view corresponding to FIG. 12 used to explain Embodiment 2, and FIG. 22 is an end view corresponding to FIG. 12 used to explain Embodiment 2, and FIG. . Note that the same parts as in Embodiments 1 and 2 are given the same reference numerals, and explanations of the same parts are omitted. 10 and FIG. 11 are used.

In the seventh embodiment as well, the structure of the coating layer 42 and the manufacturing method thereof (up to step S220) are the same as in the first embodiment. However, in the seventh embodiment, in the step of forming the filling layer 83, the tin filling layer 83 is formed by electroplating of tin (electrolytic tin plating), as shown in FIG. do.

Variation example.
In the modified example as well, the structure of the coating layer 42 and the manufacturing method thereof (step S225) are the same as in the second embodiment. However, in this modification, in the step of forming the filling layer 83, the tin filling layer 83 is formed by electrolytic plating of tin (electrolytic tin plating), as shown in FIG. 22.

As in Embodiments 1 and 2, by forming the coating layer 42 having the concave portion 42d that becomes narrower toward the bottom portion 42b by electroless plating, the inside of the via 10v is covered with the tin filling layer 83 formed by electrolytic plating. It can be completely embedded without any gaps. Therefore, compared to a hollow case, it is expected that heat dissipation and high frequency characteristics will be improved by suppressing the inductor component. Furthermore, in the seventh embodiment, since the filling layer 83 is made of tin, there is no need to worry about copper contamination, as in the first and second embodiments, and there is no concern that electrical reliability will deteriorate.

Further, the back side of the high frequency device is die-bonded with gold-tin (AuSn) solder, silver-tin (SnAg) solder, etc., but at that time, application of solder is not necessary. Further, since tin on the back surface of the wafer is a constituent material of the solder, good adhesion can be obtained since the solder is essentially formed directly on the device.

Additionally, while this application describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments may be specific to the specific embodiments. The present invention is not limited to application, but can be applied to the embodiments alone or in various combinations. Accordingly, countless variations not illustrated are envisioned within the scope of the technology disclosed herein. For example, this includes cases where at least one component is modified, added, or omitted, and cases where at least one component is extracted and combined with components of other embodiments.

As described above, according to the semiconductor device 10 of the present application, the substrate 1 is made of a semiconductor material, the wiring member formed on one surface of the substrate 1 (the upper surface in the figure), and the opening formed on the other surface of the substrate 1. , a first plating layer (covering layer 42) made of gold that covers the inner wall of a cylindrical hole whose bottom is the wiring member (surface electrode 3), and has a recess 42d that is depressed from the opening side toward the bottom. , a second plating layer (filling layer 43, 53, 63, 73) made of copper, silver, nickel, tin, or gold having a larger grain size than the first plating layer (covering layer 42) fills the recess 42d. , 83) and a solid via 10v. As a result, a semiconductor device having good electrical connection and heat dissipation in the thickness direction via the via 10v without fear of copper contamination can be obtained at low cost.

In particular, if the recess 42d is configured to widen from the bottom toward the opening, a semiconductor device with excellent electrical conductivity and heat dissipation can be reliably obtained without generating voids.

Also, if the thickness t42 to the bottom of the recess in the first plating layer (coating layer 42) is 1/4 or more of the thickness of the board (via height Hv), the generation of voids can be more reliably prevented. can.

A metal film containing any one of titanium, tantalum, tungsten, chromium, and platinum and interposed between the first plating layer (covering layer 42) and the second plating layer (filling layer 43, 53, 63, 73, 83) 44, the plating film of the filling layer 43 becomes uniform, and the embeddability in the via 10v is further improved.

If the substrate 1 is made of silicon carbide, indium phosphide, gallium nitride, germanium silicide, germanium, or silicon, a higher performance semiconductor device can be obtained.

As described above, according to the method of manufacturing the semiconductor device 10 of the present application, a wiring member is formed on one surface of the substrate 1 made of a semiconductor material, an opening is formed on the other surface of the substrate 1, and the wiring member (surface electrode 3) is formed on the other surface of the substrate 1. In the step of forming a cylindrical hole having a bottom surface of Steps of forming a first gold plating layer (coating layer 42) by electrolytic plating (steps S220, S220V), and forming one of copper, silver, nickel, tin, and gold by electrolytic plating so as to fill the recess 42d. The method is configured to include a step (step S230) of forming a second plating layer (filling layer 43). As a result, a semiconductor device having good electrical connection and heat dissipation in the thickness direction via the via 10v without fear of copper contamination can be obtained at low cost.

By including the step (step S225) of forming the metal film 44 covering the inner surface of the recess 42d by sputtering or vapor deposition, the plating film when forming the filling layer 43 by electrolytic plating can be made uniform; The embeddability within the via 10v is further improved.

1: Substrate, 10: Semiconductor device, 10v: Via, 2: Epitaxial growth layer, 3: Surface electrode (wiring member), 4: Filler, 41: Seed layer, 42: Covering layer (first plating layer), 42d: Recess, 43: Filling layer (second plating layer), 44: Metal film, 53: Filling layer (second plating layer), 63: Filling layer (second plating layer), 73: Filling layer (second plating layer) , 83: Filling layer (second plating layer), Dd: Depth, Hv: Via height, t42: Thickness, Wd: Opening width.

Claims (6)

substrate of semiconductor material,
a wiring member formed on one surface of the substrate; and a cylindrical hole that is open on the other surface of the substrate and has the wiring member as the bottom surface, and covers an inner wall of the cylindrical hole, and extends from the opening side toward the bottom surface. a first plating layer made of gold in which a concave portion is formed; and a second plating layer that fills the concave portion and is made of copper, silver, nickel, tin, or gold having a crystal grain size larger than that of the first plating layer. and a metal film containing any one of titanium, tantalum, tungsten, chromium, and platinum and interposed between the first plating layer and the second plating layer,
A semiconductor device characterized by comprising: 2. The semiconductor device according to claim 1, wherein the recessed portion widens from the bottom surface toward the opening. 3. The semiconductor device according to claim 1, wherein the thickness of the recess in the first plating layer up to the bottom surface is 1/4 or more of the thickness of the substrate. 3. The semiconductor device according to claim 1, wherein the substrate is made of silicon carbide, indium phosphide, gallium nitride, germanium silicide, germanium, or silicon. 4. The semiconductor device according to claim 3, wherein the substrate is made of silicon carbide, indium phosphide, gallium nitride, germanium silicide, germanium, or silicon. forming a wiring member on one side of a substrate made of a semiconductor material, and forming a cylindrical hole that opens on the other side of the substrate and has the wiring member as a bottom surface;
forming a first plating layer of gold by electroless plating so as to cover the inner wall of the cylindrical hole and form a recess that is concave from the opening side toward the bottom surface ;
A step of forming a metal film to cover the inner surface of the recess by sputtering or vapor deposition, and a second plating of copper, silver, nickel, tin, or gold by electrolytic plating to fill the recess. a step of forming a layer;
A method for manufacturing a semiconductor device, comprising:

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