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WO2024244858A1 - 阵列基板以及显示装置 - Google Patents

阵列基板以及显示装置 Download PDF

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Publication number
WO2024244858A1
WO2024244858A1 PCT/CN2024/090260 CN2024090260W WO2024244858A1 WO 2024244858 A1 WO2024244858 A1 WO 2024244858A1 CN 2024090260 W CN2024090260 W CN 2024090260W WO 2024244858 A1 WO2024244858 A1 WO 2024244858A1
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WO
WIPO (PCT)
Prior art keywords
line
signal transmission
transmission line
display area
common signal
Prior art date
Application number
PCT/CN2024/090260
Other languages
English (en)
French (fr)
Inventor
周焱
朱宁
王超
李云
陈晓晓
张毅
Original Assignee
京东方科技集团股份有限公司
武汉京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 武汉京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024244858A1 publication Critical patent/WO2024244858A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • Embodiments of the present disclosure relate to an array substrate and a display device.
  • ADS Advanced Super Dimension Switching
  • Embodiments of the present disclosure provide an array substrate and a display device.
  • the orthographic projection of the first signal line on the base substrate comprises a first orthographic projection
  • the orthographic projection of the connecting portion on the base substrate comprises a second orthographic projection
  • the second orthographic projection is located within the orthographic projection of the light shielding layer on the base substrate
  • the orthographic projection of the opening on the base substrate comprises a third orthographic projection
  • the distance between the first orthographic projection and the edges of the third orthographic projection close to each other is a first distance
  • the first orthographic projection comprises an overlapping edge overlapping with the second orthographic projection
  • the distance between the overlapping edge and the edge of the third orthographic projection closest to the overlapping edge is a second distance
  • the second distance is greater than the first distance.
  • the array substrate also comprises common signal transmission lines located in the first non-display area, and the common signal transmission lines comprise a first common signal transmission line and a second common signal transmission line, and the first common signal transmission line comprises a first common signal transmission line and a second common signal transmission line.
  • Two common signal transmission lines are arranged on a side of the first common signal transmission line away from the display area, the common signal transmission lines extend along the first direction, the first common signal transmission line is electrically connected to a part of the multiple common electrode lines, the second common signal transmission line is electrically connected to another part of the multiple common electrode lines, and the first non-display area also includes a pad area, and the pad area is configured to be electrically connected to a circuit board.
  • two gate lines are arranged between two adjacent sub-pixels arranged along the second direction
  • two sub-pixels arranged along the first direction are arranged between two adjacent data lines
  • the first electrodes of the two sub-pixels are an integrated structure.
  • the array substrate further includes: a transition portion, through which at least one common electrode line is electrically connected to the common signal transmission line.
  • the at least one common electrode line includes a first conductive layer and a second conductive layer that are stacked, wherein the first conductive layer is arranged in the same layer as the data line, the second conductive layer is arranged in the same layer as the first electrode, and at least part of the common signal transmission line is arranged in the same layer as the gate line;
  • the transition portion includes a first transition layer and a second transition layer that are stacked, wherein the first transition layer is arranged in the same layer as the first conductive layer, and the second transition layer is arranged in the same layer as the second conductive layer.
  • the array substrate further includes: a third non-display area and a fourth non-display area, wherein the third non-display area, the display area, and the fourth non-display area are sequentially arranged along the first direction.
  • the third non-display area is provided with a first connecting line connecting the second common signal transmission line and the third common signal transmission line
  • the fourth non-display area is provided with a second connecting line connecting the first common signal transmission line and the fourth common signal transmission line, and at least a portion of the first connecting line, at least a portion of the second connecting line, and at least a portion of the common signal transmission line are provided in the same layer.
  • the third non-display area is provided with a fifth common signal transmission line, a first gate driving circuit and a first common signal feedback line, the fifth common signal transmission line and the first common signal feedback line are both electrically connected to the third common signal transmission line, the first gate driving circuit is The circuit is electrically connected to the multiple gate lines, the fifth common signal transmission line and the first common signal feedback line are both located on a side of the first gate driving circuit away from the display area, and the first connecting line is located between the first gate driving circuit and the display area.
  • the fourth non-display area is provided with a sixth common signal transmission line, a second gate driving circuit and a second common signal feedback line, the sixth common signal transmission line and the second common signal feedback line are both electrically connected to the fourth common signal transmission line, the second gate driving circuit is electrically connected to the multiple gate lines, the sixth common signal transmission line and the second common signal feedback line are both located on a side of the second gate driving circuit away from the display area, and the second connecting line is located between the second gate driving circuit and the display area.
  • the first electrodes of two columns of sub-pixels located between adjacent data lines are electrically connected to the same common electrode line, and the first electrodes of two columns of sub-pixels located on both sides of the same data line and closest to the same data line are spaced apart and electrically connected to the first common signal transmission line and the second common signal transmission line, respectively.
  • the first common signal transmission line and the second common signal transmission line are configured to transmit different electrical signals.
  • FIG. 1 is a schematic diagram of a partial planar structure of a display device.
  • FIG. 2 is a schematic diagram of a common electrode layer in the display device shown in FIG. 1 .
  • FIG. 3 is a schematic diagram of a black matrix in the display device shown in FIG. 1 .
  • FIG. 4 is a schematic diagram of a partial planar structure of an array substrate provided according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a second electrode layer in the array substrate shown in FIG. 4 .
  • FIG. 6 is a schematic diagram of a layer where the second signal line in the array substrate shown in FIG. 4 is located.
  • FIG. 7 is a schematic diagram of an active layer in the array substrate shown in FIG. 4 .
  • FIG. 8 is a schematic diagram of a layer where the first signal line in the array substrate shown in FIG. 4 is located.
  • FIG. 9 is a schematic diagram of via holes in the array substrate shown in FIG. 4 .
  • FIG. 10A is a schematic diagram of a layer where the first electrode layer is located in the array substrate shown in FIG. 4 .
  • FIG. 10B is a schematic diagram of a layer where a first electrode is provided according to another example of an embodiment of the present disclosure.
  • FIG. 11 is a partial structural diagram of a display device including the above-mentioned array substrate.
  • FIG. 12 is a plan view showing the relationship between the black matrix and the array substrate in the display device shown in FIG. 11 .
  • FIG. 13 is a plan view of a black matrix in the display device shown in FIG. 11 .
  • FIG. 14 is an enlarged view of a portion of FIG. 12 .
  • FIG. 15 is a schematic diagram of a partial planar structure of an array substrate provided according to another example of an embodiment of the present disclosure.
  • FIG. 16 is a partial enlarged view of the array substrate shown in FIG. 15 .
  • FIG. 17 is a schematic diagram of a layer where the first signal line is located in the array substrate shown in FIG. 15 .
  • FIG. 18 is a schematic diagram of a planar structure of an array substrate provided according to an embodiment of the present disclosure.
  • Fig. 1 is a schematic diagram of a partial planar structure of a display device.
  • Fig. 2 is a schematic diagram of a common electrode layer in the display device shown in Fig. 1.
  • Fig. 3 is a schematic diagram of a black matrix in the display device shown in Fig. 1.
  • the display device may be a display device using a dual gate structure, such as two columns of sub-pixels are arranged between two adjacent data lines 13 arranged along the X direction, and two gate lines 16 are arranged between two adjacent rows of sub-pixels arranged along the Y direction.
  • the use of dual gate technology is conducive to reducing the number of data lines, thereby reducing the number of source driver chips to reduce costs.
  • the display device also includes a black matrix 14, which includes a plurality of openings 15 to define the light emitting area of the sub-pixels.
  • the large load problem can be solved by increasing the distance between the pixel electrode and the data line, or increasing the distance between the common electrode and the data line.
  • the common electrodes on both sides of the data line are electrically connected through the connecting part. Due to the distance between the pixel electrode or the common electrode and the data line, the load problem is solved.
  • the electric field effect on the liquid crystal near the connection becomes weaker; the width of the black matrix used to shield the data line is limited by the aperture ratio, and a larger width cannot be set at the connection position.
  • the alignment of the data line and the black matrix deviates, the risk of light leakage at the connection position will be greatly increased.
  • An array substrate provided by an embodiment of the present disclosure includes a base substrate and a first electrode layer, a plurality of first signal lines and a plurality of second signal lines located on the base substrate.
  • the plurality of first signal lines are arranged along a first direction
  • the plurality of second signal lines are arranged along a second direction, and the first direction intersects with the second direction.
  • the first electrode layer includes a plurality of first electrodes arranged in an array along the first direction and the second direction, and a connecting portion is provided between two adjacent first electrodes located on both sides of the same first signal line, and the connecting portion is configured to connect the two first electrodes; relative to a straight line passing through a central area of the first electrode and extending along the first direction, the connecting portion is closer to the second signal line.
  • the array substrate provided by the present disclosure by arranging the connecting portion closer to the second signal line, can reduce the load of the display device without affecting the aperture ratio and reducing the risk of light leakage.
  • Another array substrate includes a substrate and a plurality of sub-pixels, a plurality of data lines and a plurality of common electrode lines located on the substrate.
  • the substrate includes a display area and a first non-display area located at least on one side of the display area; a plurality of sub-pixels are located in the display area, each sub-pixel includes a first electrode and a second electrode arranged in a stacked manner; a plurality of data lines are located in the display area and are configured to be electrically connected to the second electrode, and the plurality of data lines are arranged along a first direction; a plurality of gate lines are located in the display area and are arranged along a second direction, and the second direction intersects the first direction; a plurality of common electrode lines are located in the display area and are electrically connected to the first electrode, and the plurality of common electrode lines and the plurality of data lines are alternately arranged along the first direction.
  • the array substrate further includes a common signal transmission line located in the first non-display area, the common signal transmission line includes a first common signal transmission line and a second common signal transmission line, the second common signal transmission line is arranged on a side of the first common signal transmission line away from the display area, the common signal transmission line extends along a first direction, the first common signal transmission line is electrically connected to a portion of the plurality of common electrode lines, the second common signal transmission line is electrically connected to another portion of the plurality of common electrode lines, the first non-display area further includes a pad area, and the pad area is configured to be electrically connected to the circuit board.
  • the array substrate provided by the present disclosure is conducive to improving problems such as uneven display brightness and linear mura by providing two first common signal transmission lines and a second common signal transmission line that transmit different electrical signals.
  • FIG4 is a schematic diagram of a partial planar structure of an array substrate provided according to an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of a second electrode layer in the array substrate shown in FIG4.
  • FIG6 is a schematic diagram of a layer where a second signal line is located in the array substrate shown in FIG4.
  • FIG7 is a schematic diagram of an active layer in the array substrate shown in FIG4.
  • Figure 8 is a schematic diagram of a layer where the first signal line is located in the array substrate shown in Figure 4.
  • Figure 9 is a schematic diagram of a via hole in the array substrate shown in Figure 4.
  • Figure 10A is a schematic diagram of a layer where the first electrode layer is located in the array substrate shown in Figure 4.
  • the first electrode layer 100 includes a plurality of first electrodes 110 arranged in an array along a first direction and a second direction.
  • the array substrate includes a plurality of sub-pixels 400.
  • the plurality of sub-pixels 400 are arranged in an array along a first direction and a second direction.
  • the array substrate further includes a second electrode layer 200 stacked with the first electrode layer 100, the second electrode layer 200 includes a plurality of second electrodes 210, and each sub-pixel 400 includes a second electrode 210.
  • the second electrode 210 may be a pixel electrode.
  • the second electrode 210 may be made of a transparent conductive material, such as indium tin oxide (ITO).
  • two sub-pixels 400 arranged along the first direction are arranged between two adjacent first signal lines 310, and two second signal lines 320 are arranged between two adjacent sub-pixels 400 arranged along the second direction, the first signal line 310 is a data line, and the second signal line 320 is a gate line.
  • the array substrate provided by the present disclosure adopts a dual gate technology, such as a driving technology that reduces the number of data lines by half and doubles the number of gate lines, that is, reduces the number of source driver integrated circuits (ICs) connected to the data lines by half, and doubles the number of gate driver integrated circuits connected to the gate lines, thereby reducing costs.
  • the first electrodes 110 of adjacent sub-pixels 400 located between two adjacent first signal lines 310 and arranged along the first direction are an integrated structure, a gap is provided between the first electrodes 110 of adjacent sub-pixels 400 located on both sides of the first signal line 310 and arranged along the first direction, and the first signal line 310 is located in the gap.
  • each sub-pixel 400 includes a transistor, and the transistor includes a first electrode 330, a second electrode 340, an active layer 350 and a gate 360.
  • the gate 360 overlaps with the active layer 350, and the gate 360 can be a part of the second signal line 320.
  • the first signal line 310 is connected to the first electrode 330 of the transistor of two adjacent sub-pixels 400 located on the same side and in the same row of the first signal line 310, and the second electrode 210 of the above two adjacent sub-pixels 400 is connected to the second electrode 340 of the transistor.
  • the second electrode extends along the first direction and overlaps with the gate line in a direction perpendicular to the substrate.
  • the gates 360 of the transistors of the above two adjacent sub-pixels 400 are electrically connected to different second signal lines 320, and the above different second signal lines 320 are respectively located on both sides of the above two adjacent sub-pixels 400 in the Y direction.
  • two second electrodes 210 arranged along the first direction are disposed between two adjacent first signal lines 310, and one first electrode 110 corresponds to two second electrodes 210.
  • the distance between two second electrodes 210 located between two adjacent first signal lines 310 and arranged along the first direction is smaller than the distance between two second electrodes 210 located on both sides of the first signal line 310 and adjacently disposed.
  • the second electrode 210 and the second signal line 320 may be structures arranged in the same layer.
  • the second electrode 210 and the second signal line 320 may be formed using the same mask.
  • the second electrode 210 and the second signal line 320 are made of different materials.
  • no insulating layer is arranged between the layer where the second electrode 210 is located and the layer where the second signal line 320 is located.
  • the shapes of the second electrode connecting portions 211 for electrically connecting to the second electrode 340 of the transistor in the two adjacent second electrodes 210 arranged along the first direction between the two adjacent first signal lines 310 are different, and the second electrode connecting portion 211 is electrically connected to the second electrode 240 of the transistor through a via 361 penetrating through the insulating layer between the second electrode 210 and the second electrode 240 of the transistor.
  • the orthographic projection of the second electrode connecting portion 211 on the base substrate 01 is located in the light shielding layer (described later), such as the orthographic projection of the black matrix on the base substrate 01.
  • the connecting portion 510 is closer to the second signal line 320.
  • the "central area" of the first electrode mentioned above may refer to an area including the geometric center of the first electrode, which may be a circular area or a square area around the geometric center, etc., and the area of the area does not exceed 10% of the area of the first electrode, such as not more than 5%, such as not more than 2%, etc.
  • the array substrate provided by the present disclosure arranges the connection portion closer to the second signal line, thereby reducing the load of the display device without affecting the aperture ratio and reducing the risk of light leakage.
  • the ratio of the distance between the connecting portion 510 and a straight line passing through the central area of the first electrode 110, such as located at the center of the central area and extending along the first direction, to the size of the first electrode 110 in the second direction is not less than 0.1, such as not less than 0.2, such as not less than 0.3, such as not less than 0.4, and not greater than 0.5.
  • connection portion 510 and the two first electrodes 110 are integrally arranged.
  • the connection portion 510 overlaps with the first signal line 310 .
  • the first electrode layer 100 is a common electrode layer, and the number of the connection portion 510 is multiple, so as to connect multiple first electrodes 110 arranged along the first direction.
  • the common electrode layer material can be a transparent conductive material, such as indium tin oxide (ITO).
  • ITO indium tin oxide
  • the size of the connection portion 510 in the first direction is greater than its size in the second direction.
  • the connection portion 510 can be a strip extending in the first direction.
  • the edge of the connection portion 510 extending in the second direction is a part of the edge of the first electrode 110 extending in the second direction.
  • the portion of the film layer where the first electrode layer is located that overlaps with the first signal line can also be used as a connection portion, and the portions on both sides of the connection portion can be used as first electrodes.
  • connection portion 510 there is at least one connection portion 510 disposed between two adjacent first electrodes 110 along the first direction.
  • the connection portion 510 may be located at least one side of the sub-pixel 500 close to the second signal lines 320 on the upper and lower sides.
  • FIG10A schematically shows that a connection portion is provided between two adjacent first electrodes, but is not limited thereto.
  • FIG10B is a schematic diagram of a layer where a first electrode is provided according to another example of an embodiment of the present disclosure.
  • two connection portions 511 and 512 may also be provided between at least two adjacent first electrodes, such as the two connection portions 511 and 512 are symmetrically distributed relative to a straight line passing through the center of the first electrode and extending along the first direction; such as the two connection portions 511 and 512 are respectively close to two second signal lines 320 located on both sides of the first electrode 110, and the ratio of the minimum distance between the two connection portions 511 and 512 and the two second signal lines 320 is 0.9 to 1.1.
  • the orthographic projections of the two connection portions 511 and 512 on the substrate substrate Both fall within the orthographic projection of the black matrix (described later) on the base substrate.
  • the two connecting portions 511 and 512 can also be two structures that are asymmetrically distributed relative to a straight line passing through the center of the first electrode and extending along the first direction, and the orthographic projections of the two connecting portions 511 and 512 on the base substrate both fall within the orthographic projection of the black matrix on the base substrate.
  • the distance between the first electrode 110 and the second signal line 320 is not greater than the distance between the connection portion 510 and the second signal line 320.
  • the ratio of the shortest distance between the first electrode 110 and the second signal line 320 to the shortest distance between the connection portion 510 and the same second signal line 320 may be 0.1 to 1, such as 0.3 to 0.8, such as 0.2 to 0.7, such as 0.4 to 0.9, such as 0.5 to 0.6, etc., and the distance between the connection portion and the second signal line may be set as required.
  • the edge of the connection portion 510 extending along the first direction and closest to the second signal line 320 may be flush with at least a portion of the edge of the first electrode 110 closest to the same second signal line 320.
  • the first electrode includes a plurality of strip electrodes 111, such as a plurality of strip electrodes 111 arranged at intervals.
  • the sub-pixels 400 include multiple domains, and by arranging multiple domains in the same sub-pixel, the diversity of the liquid crystal rotation direction in the display device using the array substrate is increased to alleviate the color shift problem of the display device at a large viewing angle.
  • the extension directions of the strip electrodes 111 in two adjacent domains intersect.
  • at least some of the sub-pixels 400 include two domains, and the extension direction of the strip electrodes in each domain intersects both the first direction and the second direction.
  • the embodiments of the present disclosure are not limited thereto, for example, at least some of the sub-pixels may also include four domains, eight domains, etc.; for example, at least some of the strip electrodes in at least some of the sub-pixels may be parallel to at least one of the first direction and the second direction.
  • At least one strip electrode 111 in the first electrode 110 of one sub-pixel is located on the same straight line as at least one strip electrode 111 in the first electrode 110 of another sub-pixel, and a partition extending along the second direction is provided in the middle of the first electrodes 110 of the two sub-pixels, and the partition is a part of the first common electrode line layer 121.
  • the width of the connection portion 510 is greater than the width of the strip electrode 111, and the width of the connection portion 510 is not greater than 10 microns.
  • the width of the connection portion 510 is not greater than 9 microns.
  • the width of the connection portion 510 is not greater than 8 microns.
  • the width of the connection portion 510 may be 5 microns.
  • the width of the strip electrode 111 may be 2 microns.
  • the width of the connection portion 510 is not less than the width of the strip electrode 111, and the width of the connection portion 510 is not greater than the minimum line width of the first signal line 310.
  • the shapes of two second signal lines 320 disposed between two adjacent rows of sub-pixels are different, such as the shapes of the two at some positions are complementary to each other to improve the compactness of the pixel arrangement in the array substrate.
  • the array substrate further includes a plurality of common electrode lines 120, and the plurality of common electrode lines 120 and the plurality of first signal lines 310 are alternately arranged along the first direction.
  • the common electrode line 120 includes a first common electrode line layer 121 arranged in the same layer as the first electrode 110, and the first common electrode line layer 121 and the first electrode 110 are an integrated structure, and are located between adjacent sub-pixels 400.
  • the common electrode line 120 also includes a second common electrode line layer 122 arranged in the same layer as the first signal line 310, and the first common electrode line layer 121 is electrically connected to the second common electrode line layer 122 through a via 362 in an insulating layer between the first common electrode line layer 121 and the second common electrode line layer 122.
  • the area defined by one common electrode line 120, one first signal line 310, and two second signal lines 320 arranged adjacent to each other is a pixel area where the sub-pixel 400 is located, and the area where the sub-pixel 400 is located is an area for displaying an image.
  • FIG11 is a partial structural diagram of a display device including the above array substrate.
  • FIG12 is a plan view of the black matrix in the display device shown in FIG11 and the array substrate.
  • FIG13 is a plan view of the black matrix in the display device shown in FIG11.
  • FIG14 is an enlarged view of a part of FIG12.
  • the array substrate shown in FIG11 may include the structure of the first electrode layer shown in FIG10A or FIG10B.
  • the display device includes an array substrate 001 in any of the above examples and an opposing substrate 002 disposed opposite to the array substrate 001, wherein the opposing substrate 002 includes a light shielding layer 600, and the light shielding layer 600 includes a plurality of openings 610 to define the light exit area of the sub-pixel 400.
  • the light shielding layer 600 may be a black matrix.
  • the opposing substrate 002 further includes a color filter layer (not shown) located at the position of the opening 610, an alignment film (not shown) on the side of the black matrix facing the array substrate, and other structures.
  • the display device may be a liquid crystal display device, and a liquid crystal layer 003 is disposed between the array substrate 001 and the counter substrate 002 .
  • the orthographic projection of the first signal line 310 on the base substrate 01 includes a first orthographic projection
  • the orthographic projection of the connecting portion 510 on the base substrate 01 includes a second orthographic projection.
  • the shadow is located within the orthographic projection of the light shielding layer 600 on the base substrate 01.
  • the connecting portion 510 is completely covered by the light shielding layer 600.
  • the orthographic projection of the opening 610 on the substrate 01 includes a third orthographic projection, the distance between the edges of the first orthographic projection and the third orthographic projection that are close to each other is a first distance D1
  • the first orthographic projection includes an overlapping edge 311 that overlaps with the second orthographic projection
  • the distance between the overlapping edge 311 and the edge closest to the overlapping edge in the third orthographic projection is a second distance D2
  • the second distance D2 is greater than the first distance D1.
  • the minimum distance between the edges of the first signal line 310 and the opening 610 that are close to each other in the first direction is D1.
  • the distance between the position where the connection portion 510 overlaps with the first signal line 310 and the opening 610 that is closest to it on a plane parallel to the XY plane is the second distance D2.
  • the distance between the first electrode 110 and the first signal line 310 is greater than 5 micrometers, such as 5.5-6 micrometers.
  • the distance between the second electrode 210 and the first signal line 310 is greater than 5 micrometers, such as 5.5-6 micrometers.
  • the display device provided by the present invention Compared with a general array substrate in which the distance between the first electrode or the second electrode and the first signal line is 5 microns, the display device provided by the present invention increases the distance between the first electrode or the second electrode and the first signal line, and sets the position of the connecting part to be at a larger distance from the opening of the light-shielding layer, so as to reduce the load of the display device without affecting the aperture ratio. Even if the black matrix has an alignment deviation, the risk of light leakage is still very low.
  • one of the first color sub-pixel 410 and the second color sub-pixel 420 is a red sub-pixel and the other is a blue sub-pixel.
  • the sub-pixel with the protrusion 520 in the light emitting area can be a red sub-pixel or a blue sub-pixel.
  • Figures 15 and 16 schematically show that the number of protrusions set in the same light exit area is one, but is not limited to this.
  • the number of protrusions set in the same light exit area can be multiple, such as two, three or more, and the two ends of the multiple protrusions located at the edge do not exceed the edge of the light exit area.
  • the protrusion 520 is disposed on the same layer as one of the first signal line 310 and the second signal line 320.
  • the protrusion 520 is disposed on the same layer as the first signal line 310.
  • the protrusion 520 is not electrically connected to any signal line, such as being in a floating state.
  • the disclosed embodiment is not limited thereto, and the protrusion may also be disposed in the same layer as the second signal line.
  • the protrusion may also be a part of the insulating layer, such as forming a protrusion thicker than other positions in the insulating layer by a half-tone mask process.
  • the disclosed embodiment schematically shows that the second electrode layer and the second signal line are located in different layers, but the present invention is not limited thereto.
  • the second electrode layer and the second signal line may also be located in the same layer, and in this case, the protrusion is located in the same layer as the first signal line.
  • the second electrode is located in the same layer as one of the first signal line and the second signal line, and the protrusion is located in the same layer as the other of the first signal line and the second signal line.
  • this case can reduce the number of data lines.
  • this case can also be a single-gate structure, that is, the same row of gate lines corresponds to a row of pixels, and two adjacent columns of sub-pixels are connected to different data lines.
  • the specific display architecture is not limited in this case.
  • Fig. 18 is a schematic diagram of a planar structure of an array substrate provided according to an embodiment of the present disclosure.
  • the array substrate shown in Fig. 18 may include any of the array substrates in the above examples.
  • the array substrate includes a display area 10 and a non-display area 20 located on at least one side of the display area 10 , and a plurality of sub-pixels 400 , a plurality of first signal lines 310 , and a plurality of second signal lines 320 are all located in the display area 10 .
  • the array substrate further includes a plurality of signal transmission lines 710 located in the non-display area 20 and disposed in the same layer as the second signal line 320, and a connection line 720 electrically connected to the signal transmission line 710, the connection line 720 extending along the first direction, the signal transmission line 710 extending along the second direction, and the connection line 720 being disposed in the same layer as the first signal line 310.
  • the signal transmission line 710 is electrically connected to the second signal line 320 via the connection line 720.
  • FIG. 19 is a schematic diagram of signal transmission lines and connection lines in an array substrate.
  • the connecting line 720 realizes the electrical connection between the signal transmission line 710 and the connecting line 720 through the adapter 702. At least one connecting line 720 needs to cross the signal transmission line 710 between it and the display area to be electrically connected to the corresponding second signal line 320.
  • the position crossed by the connecting line 720 is provided with an opening 701 to reduce the overlapping area between the two, thereby reducing the signal line load.
  • the connecting line 720 is located on the side of the signal transmission line 710 away from the substrate.
  • the connecting line 720 needs to climb twice when crossing a signal transmission line 710. The more signal transmission lines 710 crossed by the connecting line 720, the more times the climbing is, which not only affects the non-display area position
  • the flatness of the wires may also lead to the risk of disconnection of the connecting wires.
  • Figure 20 is a schematic diagram of a signal transmission line, a connecting line, and a connecting structure provided according to an embodiment of the present disclosure.
  • Figure 21 is a schematic diagram of a signal transmission line shown in Figure 20.
  • Figure 22 is a schematic diagram of a connecting line shown in Figure 20.
  • Figures 23 and 24 are schematic diagrams of a via and a connecting structure shown in Figure 20.
  • At least one signal transmission line 710 overlaps with the connection line 720, and the edge of the overlapped portion of the signal transmission line 710 with the connection line 720 includes a notch 711, so that the size of the overlapped portion in the extension direction of the connection line 720 is smaller than the size of at least part of the signal transmission line 710 other than the overlapped portion in the extension direction of the connection line 720.
  • the signal transmission line 710 may include a clock signal line for providing a clock signal to a gate drive circuit disposed in a non-display area of the display panel, the gate drive circuit being used to electrically connect the gate line of the display area of the display panel, and optionally, the signal transmission line may also include a DC signal for providing the gate drive circuit, such as a VGH or VGL signal, or may also include a signal for providing the gate drive circuit with an initial signal (STV), etc., which is not limited here.
  • a clock signal line for providing a clock signal to a gate drive circuit disposed in a non-display area of the display panel
  • the gate drive circuit being used to electrically connect the gate line of the display area of the display panel
  • the signal transmission line may also include a DC signal for providing the gate drive circuit, such as a VGH or VGL signal, or may also include a signal for providing the gate drive circuit with an initial signal (STV), etc., which is not limited here.
  • STV initial signal
  • the size of the overlapped portion in the first direction is D01
  • the size of the portion outside the overlapped portion and closest to the overlapped portion in the first direction is D02
  • D02 can be the line width of the signal transmission line 710 (the size of the position where the width is the largest in the first direction).
  • D01 is smaller than D02.
  • the ratio of D01 to D02 can be 0.1 to 0.9, such as 0.3 to 0.8, such as 0.4 to 0.6 to balance the capacitance and resistance.
  • connection trace 720 is connected to the connection structure 731 through a via 733 in the insulating layer between the connection trace 720 and the connection structure 731
  • the signal transmission line 710 is connected to the connection structure 731 through a via 732 in the insulating layer between the connection trace 720 and the connection structure 731, thereby realizing the connection between the connection trace 720 and the signal transmission line 710.
  • the connection structure 731 can be disposed in the same layer as one of the first electrode layer and the second electrode layer.
  • the number of vias 733 can be multiple, and the number of vias 732 can be multiple.
  • each signal transmission line 710 includes a plurality of notches 711, and notches 711 are provided on both edges of the signal transmission line 710 extending along the second direction, and the plurality of notches 711 are symmetrically distributed relative to the center line of each signal transmission line 710 extending along the second direction.
  • the signal transmission line is electrically connected through the connection structure and the connection trace, and at the connection structure position, the connection between the connection trace and the connection structure is at least partially arranged at the notch position.
  • the portion of the signal transmission line 710 between two notches 711 arranged along the first direction is a narrowing portion 712.
  • at least one signal transmission line 710 includes a plurality of narrowing portions 712, and the plurality of narrowing portions 712 are evenly arranged in the second direction.
  • At least one narrowing portion 712 of at least one signal transmission line 710 does not overlap with the connection line 720.
  • each narrowing portion 712 of at least one signal transmission line 710 does not overlap with the connection line 720.
  • the number of the plurality of narrowing portions 712 of at least one signal transmission line 710 that overlaps with the connection line 720 may be less than, equal to, or greater than the number of the plurality of narrowing portions 712 that do not overlap with the connection line 720.
  • connection wiring 720 includes a first connection wiring portion 721 extending along a first direction and a second connection wiring portion 722 extending along a second direction
  • first connection wiring portion 721 and the second connection wiring portion 722 can be an integrated structure.
  • the corner formed by the first connection wiring portion 721 and the second connection wiring portion 722 overlaps with the notch 711, such as the corner formed by the first connection wiring portion 721 and the second connection wiring portion 722 does not overlap with the signal transmission line 710.
  • At least some of the signal transmission lines 710 that do not overlap with the signal transmission lines are provided with slots 713.
  • a plurality of slots 713 are provided between adjacent narrowing portions 712.
  • a plurality of slots 713 between adjacent narrowing portions 712 are arranged in an array along the first direction and the second direction.
  • Fig. 25 is a schematic diagram of a partial planar structure of an array substrate.
  • Fig. 26 to Fig. 28 are schematic diagrams of different film layers in the array substrate shown in Fig. 25 .
  • the array substrate may include the sub-pixels 400, the first signal lines 310, the second signal lines 320, and the common electrode lines 120 in the above-mentioned embodiment, the sub-pixels 400 share the first electrode layer 100, and the above-mentioned sub-pixels 400, the first signal lines 310, the second signal lines 320, and the common electrode lines 120 are all located in the display area.
  • the array substrate shown in FIGS. 25 to 28 also includes a common signal transmission line 80 located in the non-display area, and each common electrode line 120 is electrically connected to the same common signal transmission line 80.
  • the display device may be a liquid crystal display device.
  • the content of large polar monomers in the liquid crystal continues to increase. Due to the influence of the large polar monomer components in the liquid crystal included in the liquid crystal layer, when the display device displays a checkerboard or other similar black and white grid images for a long time, linear stains are likely to occur at the overlapping position of the black image and the white image.
  • the array substrate further includes a common signal transmission line located in the first non-display area, the common signal transmission line includes a first common signal transmission line and a second common signal transmission line, the second common signal transmission line is arranged on a side of the first common signal transmission line away from the display area, the common signal transmission line extends along a first direction, the first common signal transmission line is electrically connected to a part of the plurality of common electrode lines, the second common signal transmission line is electrically connected to another part of the plurality of common electrode lines, the first non-display area further includes a pad area, and the pad area is configured to be electrically connected to the circuit board.
  • the array substrate provided by the present disclosure is conducive to improving problems such as uneven display brightness and linear mura by arranging the first common signal transmission line and the second common signal transmission line.
  • the first common signal transmission line and the second common signal transmission line are configured to transmit different electrical signals.
  • the first common signal transmission line and the second common signal transmission line that transmit different electrical signals, it is helpful to improve problems such as uneven display brightness and linear mura.
  • Figure 29 is a schematic diagram of the planar structure of an array substrate provided according to an embodiment of the present disclosure.
  • Figure 30 is a partial enlarged view of the display area and the second non-display area in the array substrate shown in Figure 29.
  • Figure 31 is a schematic diagram of the layer where the second electrode of the sub-pixel of the array substrate shown in Figure 30 is located.
  • Figure 32 is a schematic diagram of the layer where the gate line of the array substrate shown in Figure 30 is located.
  • Figure 33 is a schematic diagram of the layer where the data line of the array substrate shown in Figure 30 is located.
  • Figure 34 is a schematic diagram of the via hole of the array substrate shown in Figure 30.
  • Figure 35 is a schematic diagram of the layer where the first electrode of the sub-pixel of the array substrate shown in Figure 30 is located.
  • the array substrate includes a base substrate 01, and the base substrate 01 includes a display area 10 and a first non-display area 21 located at least on one side of the display area 10.
  • the array substrate includes a plurality of sub-pixels 400, a plurality of data lines 310, a plurality of gate lines 320, and a plurality of common electrode lines 120 located on the base substrate 01.
  • the plurality of sub-pixels 400, the plurality of data lines 310, the plurality of gate lines 320, and the plurality of common electrode lines 120 are all located in the display area 10.
  • each sub-pixel 400 includes a first electrode 110 and a second electrode 210 that are stacked.
  • the second electrode 210 included in the sub-pixel 400 in the array substrate shown in FIGS. 29 to 34 can be the same as the second electrode 210 included in the sub-pixel 400 in the array substrate shown in FIGS. 4 to 17. They have the same features and will not be described again here.
  • multiple data lines 310 are configured to be electrically connected to the second electrode 210 of the sub-pixel 400, and the multiple data lines are arranged along the first direction; multiple gate lines 320 are arranged along the second direction, and the second direction intersects with the first direction.
  • two gate lines 320 are disposed between two adjacent sub-pixels 400 arranged along the second direction
  • two sub-pixels 400 arranged along the first direction are disposed between two adjacent data lines 310
  • the first electrodes 110 of the two sub-pixels 400 are an integrated structure.
  • the data line 310 in the array substrate shown in Figures 29 to 35 has the same features as the first signal line 310 in the array substrate shown in Figures 4 to 17, and the gate line 320 in the array substrate shown in Figures 29 to 35 has the same features as the second signal line 320 in the array substrate shown in Figures 4 to 17, which will not be repeated here.
  • the first direction and the second direction in the array substrate shown in Figures 29 to 35 can refer to the first direction and the second direction in the array substrate shown in Figures 4 to 17, which will not be repeated here.
  • the positional relationship between the sub-pixel 400, the data line 310 and the gate line 320 in the array substrate shown in Figures 29 to 35 can refer to the positional relationship between the sub-pixel 400, the data line 310 and the gate line 320 in the array substrate shown in Figures 4 to 17.
  • the array substrate shown in Figures 29 to 35 also includes the transistors in the array substrate shown in Figures 4 to 17, and the connection relationships between the transistors and the data lines, gate lines and the first electrodes of the sub-pixels can all refer to the corresponding connection relationships in the array substrate shown in Figures 4 to 17.
  • the plurality of common electrode lines 120 are electrically connected to the first electrodes 110 of the sub-pixels 400 , and the plurality of common electrode lines 120 and the plurality of data lines 310 are alternately arranged along the first direction.
  • At least one common electrode line 120 includes a first conductive layer 122 and a second conductive layer 121 that are stacked, the first conductive layer 122 is arranged in the same layer as the data line 310, and the second conductive layer 121 is arranged in the same layer as the first electrode 110.
  • the first conductive layer 122 of the common electrode line 120 shown in Figure 33 has the same characteristics as the second common electrode line layer 122 of the common electrode line 120 shown in Figure 8, and the first conductive layer 122 of the common electrode line 120 shown in Figure 33 can refer to the relevant description of the second common electrode line layer 122 of the common electrode line 120 shown in Figure 8;
  • the second conductive layer 121 of the common electrode line 120 shown in Figure 35 has the same characteristics as the first common electrode line layer 121 of the common electrode line 120 shown in Figure 10A or 10B, and the second conductive layer 121 of the common electrode line 120 shown in Figure 35 can refer to the relevant description of the first common electrode line layer 121 of the common electrode line 120 shown in Figure 10A or 10B.
  • the array substrate further includes a common signal transmission line located in the first non-display area 21. 800
  • the common signal transmission line 800 includes a first common signal transmission line 810 and a second common signal transmission line 820
  • the second common signal transmission line 820 is arranged on a side of the first common signal transmission line 810 away from the display area 10
  • the common signal transmission line 800 extends along a first direction.
  • the first common signal transmission line 810 and the second common signal transmission line 820 are arranged in parallel.
  • the first common signal transmission line 810 and the second common signal transmission line 820 are configured to transmit different electrical signals, the first common signal transmission line 810 is electrically connected to a portion of the plurality of common electrode lines 120, and the second common signal transmission line 820 is electrically connected to another portion of the plurality of common electrode lines 120.
  • the number of the plurality of common electrode lines 120 is N, wherein M common electrode lines 120 are electrically connected to the first common signal transmission line 810, and (N-M) common electrode lines 120 are electrically connected to the second common signal transmission line 820, and both M and N are positive integers, and M is less than N.
  • the number of common electrode lines 120 electrically connected to the first common signal transmission line 810 is equal to the number of common electrode lines 120 electrically connected to the second common signal transmission line 820.
  • the number of common electrode lines electrically connected to the first common signal transmission line and the number of common electrode lines electrically connected to the second common signal transmission line may be different according to display requirements.
  • the first non-display area 21 further includes a pad area 910, which is configured to be electrically connected to a circuit board.
  • the second common signal transmission line 820 is located between the first common signal transmission line 810 and the pad area 910.
  • the pad area 910 includes a plurality of pads electrically connected to the circuit board.
  • the circuit board may be a flexible printed circuit (FPC), a printed circuit board (PCB), etc.
  • the array substrate provided by the present disclosure by setting up two first common signal transmission lines and second common signal transmission lines that transmit different electrical signals, can flexibly adjust the difference in the electrical signals transmitted by the two to reduce the degree of uneven brightness when a display device including the array substrate is displayed.
  • the array substrate further includes a second non-display area 22, and the first non-display area 21, the display area 10, and the second non-display area 22 are arranged in sequence along the second direction.
  • the first non-display area 21 and the second non-display area 22 are located on both sides of the display area 10 in the second direction.
  • the common signal transmission line 800 further includes a third common signal transmission line 830 and a fourth common signal transmission line 840 located in the second non-display area 22, the fourth common signal transmission line 840 is located on a side of the third common signal transmission line 830 away from the display area 10, the third common signal transmission line 830 is electrically connected to the second common signal transmission line 820, and the fourth common signal transmission line 840 is electrically connected to the first common signal transmission line 810.
  • the common signal transmission line 800 is disposed in the same layer as the gate line 320.
  • the first common signal transmission line 810, the second common signal transmission line 820, the third common signal transmission line 830 and the fourth common signal transmission line 840 may be disposed in the same layer.
  • the third common signal transmission line 830 and the fourth common signal transmission line 840 are arranged in parallel.
  • the two ends of at least one common electrode line 120 are respectively connected to the first common signal transmission line 810 and the fourth common signal transmission line 840; the two ends of at least one common electrode line 120 are respectively connected to the second common signal transmission line 820 and the third common signal transmission line 830.
  • the array substrate further includes a third non-display area 23 and a fourth non-display area 24, and the third non-display area 23, the display area 10, and the fourth non-display area 24 are sequentially arranged along the first direction.
  • the display area 10 is located between the third non-display area 23 and the fourth non-display area 24.
  • the first non-display area 21, the second non-display area 22, the third non-display area 23, and the fourth non-display area 24 form a circle of non-display areas surrounding the display area 10.
  • the third non-display area 23 is provided with a first connection line 801 connecting the second common signal transmission line 820 and the third common signal transmission line 830
  • the fourth non-display area 24 is provided with a second connection line 802 connecting the first common signal transmission line 810 and the fourth common signal transmission line 840, and at least a portion of the first connection line 801, at least a portion of the second connection line 802, and at least a portion of the common signal transmission line 800 are structures arranged in the same layer.
  • first common signal transmission line 810, the fourth common signal transmission line 840, and the second connection line 802 can be an integrated structure
  • the second common signal transmission line 820, the third common signal transmission line 830, and the first connection line 801 can be an integrated structure
  • the embodiments of the present disclosure are not limited to this, and at least one of the first connection line and the second connection line can also be connected to the common signal transmission line through other transfer layers.
  • the first electrodes 110 of the two columns of sub-pixels 400 located between adjacent data lines 310 are electrically connected to the same common electrode line 120, and the first electrodes 110 of the two columns of sub-pixels 400 located on both sides of the same data line 310 and closest to the same data line 310 are arranged at intervals and are respectively electrically connected to the first common signal transmission line 810 and the second common signal transmission line 820.
  • the first electrodes 110 of the two sub-pixels 400 located on both sides of the data line 310 and arranged along the first direction are insulated and respectively electrically connected to the third common signal line 830 and the fourth common signal line 840.
  • the rows and columns in the present disclosure may be interchangeable.
  • the odd-numbered common electrode lines 120 among the plurality of common electrode lines 120 are electrically connected to one of the third common signal transmission line 830 and the fourth common signal transmission line 840, and the even-numbered common electrode lines 120 are electrically connected to the other of the third common signal transmission line 830 and the fourth common signal transmission line 840.
  • different voltage levels can be set according to the position of the linear stain. Levels to fine-tune pixel brightness at the black-white boundary and improve linear staining issues.
  • the embodiments of the present disclosure are not limited thereto, and the connection relationship between the common electrode lines and the common signal transmission lines can be set according to actual needs, such as grouping a plurality of common electrode lines, each group including at least two common electrode lines that are adjacently arranged, and each group of common electrode lines is connected to the same common signal transmission line, and the number of common electrode lines in different groups can be the same or different.
  • the odd-even separation of the common electrode lines is not limited to the plurality of common electrode lines arranged along the first direction mentioned above. If the common electrode lines are arranged along the second direction, the common electrode lines of the odd and even rows can also be separated.
  • the array substrate also includes a transfer portion 920, at least one common electrode line 120 is electrically connected to the common signal transmission line 800 through the transfer portion 920, and the transfer portion 920 includes a first transfer layer 921 and a second transfer layer 922 which are stacked, the first transfer layer 921 and the first conductive layer 122 are arranged on the same layer, and the second transfer layer 922 and the second conductive layer 121 are arranged on the same layer.
  • the first transfer layer 921 and the first conductive layer 122 may be an integrated structure.
  • part of the second transfer layer 922 and the second conductive layer 121 can be an integrated structure, and this part of the second transfer layer 922 is connected to the third common signal transmission line 830, and another part of the second transfer layer 922 is spaced apart from the second conductive layer 121, and this part of the second transfer layer 922 is connected to the fourth common signal transmission line 840.
  • the second transfer layer 922 is electrically connected to the first transfer layer 921 through a portion of the multiple vias 363, and the first transfer layer 921 is connected to the third common signal transmission line 830 and the fourth common signal transmission line 840 through another portion of the multiple vias 363.
  • the size of the interval between the third common signal transmission line 830 and the fourth common signal transmission line 840 is smaller than the width of at least one of the third common signal transmission line 830 and the fourth common signal transmission line 840.
  • the ratio of the width of the third common signal transmission line 830 to the fourth common signal transmission line 840 is 0.9 to 1.1, such as the width of the third common signal transmission line 830 is equal to the width of the fourth common signal transmission line 840.
  • At least one of the third common signal transmission line 830 and the fourth common signal transmission line 840 may be provided with a plurality of grooves (not shown in the figure) to improve the uniformity of the alignment of the alignment film.
  • the third non-display area 23 is provided with a fifth common signal transmission line 850, a first gate driving circuit 930, and a first common signal feedback line 940, and the fifth common signal transmission line 850 and the first common signal feedback line 940 are both electrically connected to the third common signal transmission line 830.
  • the first gate driving circuit 930 is electrically connected to the plurality of gate lines 320
  • the fifth common signal transmission line 850 and the first common signal feedback line 840 are both located on a side of the first gate driving circuit 930 away from the display area 10
  • the first connecting line 801 is located between the first gate driving circuit 930 and the display area 10 .
  • the gate line 320 may be connected to the first gate driving circuit 930 via the connection line 720 shown in Figure 22.
  • the first gate driving circuit 930 may include the signal transmission line 710 shown in Figure 20.
  • the first gate driving circuit 930 may be a GOA gate driving circuit.
  • the first common signal feedback line 940 can be used to detect the common signal at the far end.
  • the common signal at the far end can be compensated through the fifth common signal transmission line 850; when the first common signal feedback line 940 detects that the common signal at the far end is normal, the fifth common signal transmission line 850 is input with a general common signal.
  • the compensation method adopts reverse complementarity. When the compensation signal acts on the above waveform, the above upward fluctuation can be pulled back to the balance point.
  • the fourth non-display area 24 is provided with a sixth common signal transmission line 860, a second gate drive circuit 950 and a second common signal feedback line 960, the sixth common signal transmission line 860 and the second common signal feedback line 960 are both electrically connected to the fourth common signal transmission line 840, the second gate drive circuit 950 is electrically connected to a plurality of gate lines 320, the sixth common signal transmission line 860 and the second common signal feedback line 960 are both located on a side of the second gate drive circuit 950 away from the display area 10, and the second connection line 802 is located between the second gate drive circuit 950 and the display area 10.
  • the array substrate adopts a bilateral gate driving technology.
  • the second gate driving circuit 950 may have the same features as the first gate driving structure 930
  • the second common signal feedback line 960 may have the same features as the first common signal feedback line 940
  • the sixth common signal transmission line 860 may have the same features as the fifth common signal transmission line 850, which will not be described in detail here.
  • the array substrate further includes a ground line (GND) 972, a test signal line (such as an enhancement signal line, Addition Line, ADD) 971, an ESD electrostatic discharge circuit 975, and electrostatic discharge rings (inner short ring) 973 and 974.
  • the common signal transmission line in the array substrate further includes transmission lines 871 and 872, but is not limited thereto, and transmission lines 871 and 872 may also be omitted.
  • Another embodiment of the present disclosure provides a display device, including the array substrate shown in any one of Figures 29 to 35.
  • the display device may further include an opposing substrate.
  • the opposing substrate is provided with a black matrix and Color filter layer.
  • the display device further includes a liquid crystal layer located between the array substrate and the counter substrate.
  • the above-mentioned structure does not constitute a limitation on the above-mentioned display device provided in the embodiments of the present disclosure.
  • the above-mentioned display device provided in the embodiments of the present disclosure may include more or fewer of the above-mentioned components, or a combination of certain components, or different component arrangements.

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Abstract

一种阵列基板以及显示装置。阵列基板包括衬底基板(01)以及位于衬底基板(01)上的第一电极层(100)、多条第一信号线(310)以及多条第二信号线(320)。多条第一信号线(310)沿第一方向(X)排列，多条第二信号线(320)沿第二方向(Y)排列，第一方向(X)与第二方向(Y)相交。第一电极层(100)包括沿第一方向(X)和第二方向(Y)阵列排布的多个第一电极(110)，位于同一条第一信号线(310)两侧且相邻的两个第一电极(110)之间设置有连接部(510)，连接部(510)被配置为连接两个第一电极(110)；相对于经过第一电极(110)的中心区域且沿第一方向(X)延伸的直线，连接部(510)更靠近第二信号线(320)。通过将连接部(510)设置为更靠近第二信号线(320)，以在降低显示装置负载的同时，既不影响开口率，又可以降低漏光的风险。

Description

阵列基板以及显示装置
本申请要求于2023年5月29日递交的中国专利申请第202310620215.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种阵列基板以及显示装置。
背景技术
随着显示技术的发展，人们对于显示装置的尺寸以及显示效果要求越来越高，采用高级超维场(Advanced Super Dimension Switching，ADS)显示模式的大尺寸显示装置具有高开口率、高分辨率以及高透过率等特点，受到了广泛的应用。
发明内容
本公开实施例提供一种阵列基板以及显示装置。
本公开实施例提供的阵列基板，包括：衬底基板以及位于所述衬底基板上的第一电极层、多条第一信号线以及多条第二信号线，所述多条第一信号线沿第一方向排列，所述多条第二信号线沿第二方向排列，所述第一方向与所述第二方向相交；所述第一电极层包括沿所述第一方向和所述第二方向阵列排布的多个第一电极，位于同一条第一信号线两侧且相邻的两个第一电极之间设置有连接部，所述连接部被配置为连接所述两个第一电极；相对于经过所述第一电极的中心区域且沿所述第一方向延伸的直线，所述连接部更靠近所述第二信号线。
例如，根据本公开实施例，在所述第二方向上，所述第一电极与所述第二信号线之间的距离不大于所述连接部与所述第二信号线之间的距离。
例如，根据本公开实施例，所述阵列基板包括多个子像素，所述多个子像素至少包括第一颜色子像素和第二颜色子像素，且所述第一颜色子像素和所述第二颜色子像素均包括多畴，所述第一颜色子像素和所述第二颜色子像素之一 的出光区设置有突起部，所述突起部位于所述多畴中相邻两畴之间。
例如，根据本公开实施例，所述第一颜色子像素和所述第二颜色子像素中，所述第一电极包括多个条状电极，且相邻两畴中条状电极的延伸方向相交；沿垂直于所述衬底基板的方向，所述突起部与所述相邻两畴至少之一中的所述条状电极交叠，或者所述突起部与所述条状电极没有交叠。
例如，根据本公开实施例，所述突起部与所述第一信号线和所述第二信号线之一同层设置。
例如，根据本公开实施例，所述第一颜色子像素和所述第二颜色子像素之一为红色子像素，另一个为蓝色子像素。
例如，根据本公开实施例，在垂直于所述衬底基板的方向上，所述突起部的边缘与相邻子像素的出光区没有交叠，且所述突起部在所述相邻两畴的排列方向上的尺寸为1.5～6微米。
例如，根据本公开实施例，所述连接部的宽度大于所述条状电极的宽度，且所述连接部的宽度不大于10微米。
例如，根据本公开实施例，阵列基板还包括与所述第一电极层层叠设置的第二电极层，所述第二电极层包括多个第二电极，每个子像素包括一个第二电极。
例如，根据本公开实施例，在沿所述第一方向上，所述两个第一电极之间设置的所述连接部的数量至少为一个。
例如，根据本公开实施例，所述连接部与所述两个第一电极为一体化设置的结构。
例如，根据本公开实施例，相邻两条第一信号线之间设置有沿所述第一方向排列的两个子像素，且沿所述第二方向排列的相邻两个子像素之间设置有两条第二信号线，所述第一信号线为数据线，所述第二信号线为栅线。
例如，根据本公开实施例，位于相邻两条第一信号线之间且沿所述第一方向排列的相邻子像素的第一电极为一体化设置的结构，位于所述第一信号线两侧且沿所述第一方向排列的相邻子像素的第一电极之间设置有间隔，且所述第一信号线位于所述间隔中。
例如，根据本公开实施例，阵列基板包括显示区和位于所述显示区至少一侧的非显示区。所述多个子像素、所述多条第一信号线和所述多条第二信号线均位于所述显示区，所述阵列基板还包括位于所述非显示区的且与所述第二信 号线同层设置的多条信号传输线，以及与所述信号传输线电连接的连接走线，所述连接走线沿所述第一方向延伸，所述信号传输线沿所述第二方向延伸，所述连接走线与所述第一信号线同层设置；沿垂直于所述衬底基板的方向，至少一条信号传输线与所述连接走线交叠，且所述信号传输线中与所述连接走线交叠部分的边缘包括凹口以使所述交叠部分在所述连接走线的延伸方向上的尺寸小于与所述信号传输线中除所述交叠部分以外的至少部分位置在所述连接走线的延伸方向上的尺寸。
本公开另一实施例提供一种显示装置，包括上述阵列基板以及对置基板；对置基板与所述阵列基板相对设置，所述对置基板包括遮光层，所述遮光层包括多个开口以限定子像素的出光区。所述第一信号线在所述衬底基板上的正投影包括第一正投影，所述连接部在所述衬底基板上的正投影包括第二正投影，所述第二正投影位于所述遮光层在所述衬底基板上的正投影内；所述开口在所述衬底基板上的正投影包括第三正投影，所述第一正投影与所述第三正投影的彼此靠近的边缘之间的距离为第一距离，所述第一正投影包括与所述第二正投影交叠的交叠边缘，所述交叠边缘与所述第三正投影中最靠近所述交叠边缘的边缘之间的距离为第二距离，所述第二距离大于所述第一距离。
例如，根据本公开实施例，所述第一信号线沿所述第二方向延伸，所述开口包括沿所述第二方向延伸且最靠近所述第一信号线的开口边缘，所述连接部位于所述开口边缘和最靠近所述开口边缘的所述第二信号线之间。
例如，根据本公开实施例，经过所述连接部且沿所述第一方向延伸的直线不经过所述开口边缘。
本公开另一实施例提供一种阵列基板，包括：衬底基板、位于衬底基板上的多个子像素、多条数据线、多条栅线以及多条公共电极线。衬底基板包括显示区以及位于所述显示区至少一侧的第一非显示区；多个子像素位于所述衬底基板的显示区，各子像素包括层叠设置的第一电极和第二电极；多条数据线位于所述衬底基板的显示区且被配置为与所述第二电极电连接，所述多条数据线沿第一方向排列；多条栅线位于所述衬底基板的显示区且沿第二方向排列，所述第二方向与所述第一方向相交；多条公共电极线位于所述衬底基板的显示区且与所述第一电极电连接，所述多条公共电极线与所述多条数据线沿所述第一方向交替设置。所述阵列基板还包括位于所述第一非显示区的公共信号传输线，所述公共信号传输线包括第一公共信号传输线和第二公共信号传输线，所述第 二公共信号传输线设置在所述第一公共信号传输线远离所述显示区的一侧，所述公共信号传输线沿所述第一方向延伸，所述第一公共信号传输线与所述多条公共电极线的一部分电连接，所述第二公共信号传输线与所述多条公共电极线的另一部分电连接，所述第一非显示区还包括焊盘区，所述焊盘区被配置为与电路板电连接。
例如，根据本公开实施例，阵列基板还包括第二非显示区，所述第一非显示区、所述显示区和所述第二非显示区沿所述第二方向依次排布，所述公共信号传输线还包括位于所述第二非显示区的第三公共信号传输线和第四公共信号传输线，所述第四公共信号传输线位于所述第三公共信号传输线远离所述显示区的一侧，所述第三公共信号传输线和所述第二公共信号传输线电连接，所述第四公共信号传输线和所述第一公共信号传输线电连接。
例如，根据本公开实施例，沿所述第二方向排列的相邻两个子像素之间设置有两条栅线，相邻两条数据线之间设置有沿所述第一方向排列的两个子像素，所述两个子像素的第一电极为一体化设置的结构。
例如，根据本公开实施例，阵列基板还包括：转接部，至少一条公共电极线通过所述转接部与所述公共信号传输线电连接。所述至少一条公共电极线包括层叠设置的第一导电层和第二导电层，所述第一导电层与所述数据线同层设置，所述第二导电层与所述第一电极同层设置，所述公共信号传输线的至少部分与所述栅线同层设置；所述转接部包括层叠设置的第一转接层和第二转接层，所述第一转接层与所述第一导电层同层设置，所述第二转接层与所述第二导电层同层设置。
例如，根据本公开实施例，阵列基板还包括：第三非显示区和第四非显示区，所述第三非显示区、所述显示区以及所述第四非显示区沿所述第一方向依次排列。所述第三非显示区设置有连接所述第二公共信号传输线和所述第三公共信号传输线的第一连接线，所述第四非显示区设置有连接所述第一公共信号传输线和所述第四公共信号传输线的第二连接线，所述第一连接线的至少部分、所述第二连接线的至少部分以及所述公共信号传输线的至少部分为同层设置的结构。
例如，根据本公开实施例，所述第三非显示区设置有第五公共信号传输线、第一栅极驱动电路以及第一公共信号反馈线，所述第五公共信号传输线和所述第一公共信号反馈线均与所述第三公共信号传输线电连接，所述第一栅极驱动 电路与所述多条栅线电连接，所述第五公共信号传输线和所述第一公共信号反馈线均位于所述第一栅极驱动电路远离所述显示区的一侧，所述第一连接线位于所述第一栅极驱动电路与所述显示区之间。
例如，根据本公开实施例，所述第四非显示区设置有第六公共信号传输线、第二栅极驱动电路以及第二公共信号反馈线，所述第六公共信号传输线和所述第二公共信号反馈线均与所述第四公共信号传输线电连接，所述第二栅极驱动电路与所述多条栅线电连接，所述第六公共信号传输线和所述第二公共信号反馈线均位于所述第二栅极驱动电路远离所述显示区的一侧，所述第二连接线位于所述第二栅极驱动电路与所述显示区之间。
例如，根据本公开实施例，位于相邻数据线之间的两列子像素的第一电极与同一条公共电极线电连接，分别位于同一条数据线两侧且与所述同一条数据线距离最近的两列子像素的第一电极间隔设置，且分别与所述第一公共信号传输线和所述第二公共信号传输线电连接。
例如，根据本公开实施例，所述第一公共信号传输线和所述第二公共信号传输线被配置为传输不同电信号。
本公开另一实施例提供一种显示装置，包括上述任一阵列基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示装置的局部平面结构示意图。
图2为图1所示显示装置中的公共电极层的示意图。
图3为图1所示显示装置中的黑矩阵的示意图。
图4为根据本公开实施例提供的阵列基板的局部平面结构示意图。
图5为图4所示阵列基板中的第二电极层的示意图。
图6为图4所示阵列基板中的第二信号线所在层的示意图。
图7为图4所示阵列基板中的有源层的示意图。
图8为图4所示阵列基板中的第一信号线所在层的示意图。
图9为图4所示阵列基板中过孔示意图。
图10A为图4所示阵列基板中第一电极层所在层的示意图。
图10B为根据本公开实施例的另一示例提供的第一电极所在层的示意图。
图11为包括上述阵列基板的显示装置的局部结构图。
图12为图11所示显示装置中的黑矩阵以及阵列基板的平面关系图。
图13为图11所示显示装置中的黑矩阵的平面图。
图14为图12的部分位置放大图。
图15为根据本公开实施例的另一示例提供的阵列基板的局部平面结构示意图。
图16为图15所示阵列基板的局部放大图。
图17为图15所示阵列基板中第一信号线所在层的示意图。
图18为根据本公开实施例提供的阵列基板的平面结构示意图。
图19为一种阵列基板中的信号传输线和连接走线的示意图。
图20为根据本公开实施例提供的信号传输线、连接走线以及连接结构的示意图。
图21为图20所示信号传输线的示意图。
图22为图20所示连接走线的示意图。
图23和图24为图20所示过孔以及连接结构的示意图。
图25为一种阵列基板的局部平面结构示意图。
图26至图28为图25所示阵列基板中不同膜层的示意图。
图29为根据本公开实施例提供的阵列基板的平面结构示意图。
图30为图29所示阵列基板中的显示区和第二非显示区的局部放大图。
图31为图30所示阵列基板的子像素的第二电极所在层的示意图。
图32为图30所示阵列基板的栅线所在层的示意图。
图33为图30所示阵列基板的数据线所在层的示意图。
图34为图30所示阵列基板的过孔的示意图。
图35为图30所示阵列基板的子像素的第一电极所在层的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所 有其它实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。本公开实施例中使用的“平行”、“垂直”以及“相同”等特征均包括严格意义的“平行”、“垂直”、“相同”等特征，以及“大致平行”、“大致垂直”、“大致相同”等包含一定误差的情况，考虑到测量和与特定量的测量相关的误差(例如，测量系统的限制)，表示在本领域的普通技术人员所确定的对于特定值的可接受的偏差范围内。例如，“大致”能够表示在一个或多个标准偏差内，或者在所述值的10％或者5％内。在本公开实施例的下文中没有特别指出一个成分的数量时，意味着该成分可以是一个也可以是多个，或可理解为至少一个。“至少一个”指一个或多个，“多个”指至少两个。本公开中所称的“同层设置”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的结构，它们的材料可以相同或不同。
图1为一种显示装置的局部平面结构示意图。图2为图1所示显示装置中的公共电极层的示意图。图3为图1所示显示装置中的黑矩阵的示意图。
如图1至图3所示，显示装置可以为采用双栅(dual gate)结构的显示装置，如沿X方向排列的相邻两条数据线13之间设置有两列子像素，沿Y方向排列的相邻两行子像素之间设置有两条栅线16。通过采用双栅技术，有利于减少数据线数量，进而减少源极驱动芯片的数量，以降低成本。显示装置还包括黑矩阵14，黑矩阵14包括多个开口15以限定子像素的出光区。
采用双栅设计的大尺寸显示装置的显示面板中，通常采用顶层透明导电层，如氧化铟锡(ITO)为公共电极的像素结构，如图2所示的公共电极11。位于数据线13两侧的公共电极11通过连接部12电连接，如连接部12位于相邻子像素的中部之间的区域。
在研究中，本申请的发明人发现，采用双栅技术的大尺寸显示面板容易出现负载较大的问题，对此可以通过增加像素电极与数据线之间的距离，或者增加公共电极与数据线之间的距离以解决负载较大问题。然而，位于数据线两侧的公共电极通过连接部电连接，由于像素电极或者公共电极与数据线之间的距 离增大，该连接部附近的液晶受到的电场作用变弱；用于遮挡数据线的黑矩阵的宽度受开口率限制，不能在连接部位置处设置较大宽度，此时，如果数据线与黑矩阵对位出现偏差，会极大增加连接部位置处的漏光风险。
本公开提供一种阵列基板以及显示装置。
本公开实施例提供的一种阵列基板包括衬底基板以及位于衬底基板上的第一电极层、多条第一信号线以及多条第二信号线。多条第一信号线沿第一方向排列，多条第二信号线沿第二方向排列，第一方向与第二方向相交。第一电极层包括沿第一方向和第二方向阵列排布的多个第一电极，位于同一条第一信号线两侧且相邻的两个第一电极之间设置有连接部，连接部被配置为连接两个第一电极；相对于经过第一电极的中心区域且沿第一方向延伸的直线，连接部更靠近第二信号线。本公开提供的阵列基板，通过将连接部设置的更靠近第二信号线，以在降低显示装置负载的同时，既不影响开口率，又可以降低漏光的风险。
本公开实施例提供的另一种阵列基板包括衬底基板以及位于衬底基板上的多个子像素、多条数据线以及多条公共电极线。衬底基板包括显示区以及位于显示区至少一侧的第一非显示区；多个子像素位于显示区，各子像素包括层叠设置的第一电极和第二电极；多条数据线位于显示区且被配置为与第二电极电连接，多条数据线沿第一方向排列；多条栅线位于显示区且沿第二方向排列，第二方向与第一方向相交；多条公共电极线位于显示区且与第一电极电连接，多条公共电极线与多条数据线沿第一方向交替设置。阵列基板还包括位于第一非显示区的公共信号传输线，公共信号传输线包括第一公共信号传输线和第二公共信号传输线，第二公共信号传输线设置在第一公共信号传输线远离显示区的一侧，公共信号传输线沿第一方向延伸，第一公共信号传输线与多条公共电极线的一部分电连接，第二公共信号传输线与多条公共电极线的另一部分电连接，第一非显示区还包括焊盘区，焊盘区被配置为与电路板电连接。本公开提供的阵列基板，通过设置两条传输不同电信号的第一公共信号传输线和第二公共信号传输线，有利于改善显示亮度不均匀、线性mura等问题。
下面结合附图对本公开实施例提供的阵列基板以及显示装置进行描述。
图4为根据本公开实施例提供的阵列基板的局部平面结构示意图。图5为图4所示阵列基板中的第二电极层的示意图。图6为图4所示阵列基板中的第二信号线所在层的示意图。图7为图4所示阵列基板中的有源层的示意图。图 8为图4所示阵列基板中的第一信号线所在层的示意图。图9为图4所示阵列基板中过孔示意图。图10A为图4所示阵列基板中第一电极层所在层的示意图。
如图4至图10A所示，阵列基板包括衬底基板01以及位于衬底基板01上的第一电极层100、多条第一信号线310以及多条第二信号线320，多条第一信号线310沿第一方向排列，多条第二信号线320沿第二方向排列，第一方向与第二方向相交。例如，第一方向可以为图中的X方向，第二方向可以为图中的Y方向，但不限于此，第一方向与第二方向可以互换。例如，第一方向与第二方向之间的夹角可以为80～100度，如第一方向与第二方向垂直。
如图4和图10A所示，第一电极层100包括沿第一方向和第二方向阵列排布的多个第一电极110。
在一些示例中，如图4所示，阵列基板包括多个子像素400。例如，多个子像素400沿第一方向和第二方向阵列排布。
在一些示例中，如图4和图5所示，阵列基板还包括与第一电极层100层叠设置的第二电极层200，第二电极层200包括多个第二电极210，每个子像素400包括一个第二电极210。例如，第二电极210可以为像素电极。例如，第二电极210可以采用透明导电材料，如氧化铟锡(ITO)。
在一些示例中，如图4和图10A所示，相邻两条第一信号线310之间设置有沿第一方向排列的两个子像素400，且沿第二方向排列的相邻两个子像素400之间设置有两条第二信号线320，第一信号线310为数据线，第二信号线320为栅线。本公开提供的阵列基板采用了双栅(Dual Gate)技术，如将数据线的数量减少一半，栅线的数量增加一倍的驱动技术，即，将与数据线连接的源极驱动集成电路(integrated circuit，IC)的数量减半，将与栅线连接的栅极驱动集成电路的数量加倍，从而实现成本的降低。
在一些示例中，如图4、图8和图10A所示，位于相邻两条第一信号线310之间且沿第一方向排列的相邻子像素400的第一电极110为一体化设置的结构，位于第一信号线310两侧且沿第一方向排列的相邻子像素400的第一电极110之间设置有间隔，且第一信号线310位于间隔中。
例如，如图4、图8和图10A所示，各子像素400包括晶体管，晶体管包括第一极330、第二极340、有源层350以及栅极360。例如，栅极360与有源层350交叠，栅极360可以为第二信号线320的一部分。例如，同一条第一信 号线310与位于该第一信号线310同一侧且同一行的两个相邻子像素400的晶体管的第一极330连接，上述两个相邻子像素400的第二电极210与晶体管的第二极340连接，可选的，第二极沿着第一方向延伸，在垂直于衬底基板的方向上，与栅线有交叠，上述两个相邻子像素400的晶体管的栅极360与不同第二信号线320电连接，且上述不同第二信号线320分别位于上述两个相邻子像素400在Y方向上的两侧。
例如，如图4、图5和图10A所示，相邻两条第一信号线310之间设置有沿第一方向排列的两个第二电极210，一个第一电极110对应两个第二电极210。例如，位于相邻两条第一信号线310之间且沿第一方向排列的两个第二电极210之间的距离小于分别位于第一信号线310两侧且相邻设置的两个第二电极210之间的距离。
例如，如图5和图6所示，第二电极210与第二信号线320可以为同层设置的结构。例如，第二电极210与第二信号线320可以采用同一个掩模板形成。例如，第二电极210与第二信号线320的材料不同。例如，第二电极210所在层与第二信号线320所在层之间没有设置绝缘层。例如，第二信号线320所在层包括层叠部3200，该层叠部3200与第二电极210的第二电极连接部211层叠设置，两者之间没有设置绝缘层，且直接接触以实现电连接，有利于提高第二电极的电学性能。
例如，如图4、图5、图8以及图9所示，相邻两条第一信号线310之间设置的沿第一方向排列的相邻两个第二电极210中用于与晶体管的第二极340电连接的第二电极连接部211的形状不同，且第二电极连接部211通过贯穿位于第二电极210与晶体管的第二极240之间的绝缘层中的过孔361与晶体管的第二极240电连接。例如，第二电极连接部211在衬底基板01上的正投影位于遮光层(后续描述)，如黑矩阵在衬底基板01上的正投影内。
例如，如图4和图5所示，相邻两条第一信号线310之间设置的沿第一方向排列的相邻两个第二电极210还包括除第二电极连接部211以外的两个第二电极主体部212，这两个第二电极主体部212相对于公共电极线120(后续描述)基本呈对称分布，有利于提高像素开口率。
如图4和图10A所示，位于同一条第一信号线310两侧且相邻的两个第一电极110之间设置有连接部510，连接部510被配置为连接两个第一电极110。
如图4和图10A所示，相对于经过第一电极110的中心区域且沿第一方向延伸的直线，可选的，相对于经过第一电极110的中心且沿第一方向延伸的直线，连接部510更靠近第二信号线320。例如，上述第一电极的“中心区域”可以指包括第一电极的几何中心的区域，该区域可以为围绕几何中心的圆形区域或方形区域等，该区域的面积不超过第一电极的面积的10％，如不超过5％，如不超过2％等。
本公开提供的阵列基板，通过将连接部设置的更靠近第二信号线，以在降低显示装置负载的同时，既不影响开口率，又可以降低漏光的风险。
例如，如图4所示，连接部510与经过第一电极110的中心区域，如位于中心区域的中心，且沿第一方向延伸的直线之间的距离与第一电极110在第二方向上的尺寸之比不小于0.1，如不小于0.2，如不小于0.3，如不小于0.4，且不大于0.5。
在一些示例中，如图4和图10A所示，连接部510与两个第一电极110为一体化设置的结构。例如，在垂直于衬底基板01的方向，连接部510与第一信号线310交叠。例如，第一电极层100为公共电极层，连接部510的数量为多个，以用于连接沿第一方向排列的多个第一电极110。例如，公共电极层材料可以采用透明导电材料，如氧化铟锡(ITO)。例如，连接部510在第一方向上的尺寸大于其在第二方向上的尺寸。例如，连接部510可以为沿第一方向延伸的条状。例如，连接部510的沿第二方向延伸的边缘为第一电极110的沿第二方向延伸的边缘的一部分。但不限于此，还可以将第一电极层所在膜层中与第一信号线交叠的部分作为连接部，该连接部两侧的部分作为第一电极。
在一些示例中，如图4和图10A所示，在沿第一方向上，相邻两个第一电极110之间设置的连接部510的数量至少为一个。例如，连接部510可以位于子像素500靠近上下两侧第二信号线320的至少一侧的位置。
图10A示意性的示出相邻两个第一电极之间设置有一个连接部，但不限于此。图10B为根据本公开实施例的另一示例提供的第一电极所在层的示意图，如图10B所示，至少两个相邻的第一电极之间还可以设置两个连接部511和512，如两个连接部511和512相对于经过第一电极的中心且沿第一方向延伸的直线对称分布；如两个连接部511和512分别靠近位于第一电极110两侧的两条第二信号线320，且两个连接部511和512与两条第二信号线320之间的最小距离之比为0.9～1.1。例如，两个连接部511和512在衬底基板上的正投影 均落入黑矩阵(后续描述)在衬底基板上的正投影内。当然，两个连接部511和512也可以为相对于经过第一电极的中心且沿第一方向延伸的直线非对称分布的两个结构，且两个连接部511和512在衬底基板上的正投影均落入黑矩阵在衬底基板上的正投影内。通过在阵列基板中设置两个或两个以上的第一连接部，有利于在降低显示装置负载，既不影响开口率，又可以降低漏光的风险的同时，提高相邻第一电极的电连接效果。
在一些示例中，如图4所示，在第二方向上，第一电极110与第二信号线320之间的距离不大于连接部510与第二信号线320之间的距离。例如，第一电极110与第二信号线320之间的最短距离与连接部510与同一条第二信号线320之间的最短距离之比可以为0.1～1，如0.3～0.8，如0.2～0.7，如0.4～0.9，如0.5～0.6等，可以根据需求对连接部与第二信号线之间的距离进行设置。例如，连接部510的沿第一方向延伸且最靠近第二信号线320的边缘可以与第一电极110的最靠近同一条第二信号线320的边缘的至少部分齐平。
在一些示例中，如图4和图10A所示，至少部分子像素400中，第一电极包括多个条状电极111，如多个条状电极111间隔设置。例如，至少部分子像素400中包括多畴，通过在同一个子像素中设置多畴，增加了采用该阵列基板的显示装置中液晶旋转方向的多样性以缓解显示装置在大视角下的色偏问题。
在一些示例中，如图4和图10A所示，同一子像素400中，相邻两畴中条状电极111的延伸方向相交。例如，至少部分子像素400中包括两畴，每畴中的条状电极的延伸方向与第一方向和第二方向均相交。当然，本公开实施例不限于此，如至少部分子像素还可以包括四畴、八畴等；如至少部分子像素中至少部分条状电极可以与第一方向和第二方向至少之一平行。
例如，如图4所示，相邻两个子像素的一体化设置的第一电极110中，一个子像素的第一电极110中的至少一个条状电极111与另一个子像素的第一电极110中的至少一个条状电极111位于同一直线上，且两个子像素的第一电极110的中部设置有沿第二方向延伸的分隔部，该分隔部为第一公共电极线层121的一部分。
在一些示例中，如图4和图10A所示，连接部510的宽度大于条状电极111的宽度，且连接部510的宽度不大于10微米。例如，连接部510的宽度不大于9微米。例如，连接部510的宽度不大于8微米。例如，连接部510的宽度可以为5微米。例如，条状电极111的宽度可以为2微米。
在一些示例中，如图4和图10A所示，连接部510的宽度不小于条状电极111的宽度，且连接部510的宽度不大于第一信号线310的最小线宽。通过对连接部、第一信号线以及条状电极的宽度关系的设置，可以在实现相邻第一电极之间较好电连接效果的同时，尽量降低连接部位置处产生的电场对液晶偏转的影响，以防止漏光。
例如，如图4和图6所示，位于相邻两行子像素(如沿X方向排列的多个子像素可以为一行子像素)之间设置的两条第二信号线320的形状不同，如两者在部分位置处的形状互补以提升阵列基板中像素排布的紧凑性。
例如，如图4、图8至图10A所示，阵列基板还包括多条公共电极线120，多条公共电极线120和多条第一信号线310沿第一方向交替设置。例如，公共电极线120包括与第一电极110同层设置的第一公共电极线层121，该第一公共电极线层121与第一电极110为一体化设置的结构，且位于相邻子像素400之间。例如，公共电极线120还包括与第一信号线310同层设置的第二公共电极线层122，第一公共电极线层121通过位于第一公共电极线层121与第二公共电极线层122之间的绝缘层中的过孔362与第二公共电极线层122电连接。例如，相邻设置的一条公共电极线120、一条第一信号线310以及两条第二信号线320限定的区域为子像素400所在的像素区，子像素400所在的区域为用于显示图像的区域。
图11为包括上述阵列基板的显示装置的局部结构图。图12为图11所示显示装置中的黑矩阵以及阵列基板的平面关系图。图13为图11所示显示装置中的黑矩阵的平面图。图14为图12的部分位置放大图。图11所示阵列基板可以包括图10A或图10B所示的第一电极所在层的结构。
如图11至图14所示，显示装置包括上述任一示例中的阵列基板001以及与阵列基板001相对设置的对置基板002，对置基板002包括遮光层600，遮光层600包括多个开口610以限定子像素400的出光区。例如，遮光层600可以为黑矩阵。例如，对置基板002还包括位于开口610位置处的彩膜层(未示出)、黑矩阵面向阵列基板一侧的配向膜(未示出)等结构。
例如，如图11所示，显示装置可以为液晶显示装置，阵列基板001与对置基板002之间设置有液晶层003。
如图11和图13所示，第一信号线310在衬底基板01上的正投影包括第一正投影，连接部510在衬底基板01上的正投影包括第二正投影，第二正投 影位于遮光层600在衬底基板01上的正投影内。例如，连接部510完全被遮光层600覆盖。
如图12至图14所示，开口610在衬底基板01上的正投影包括第三正投影，第一正投影与第三正投影的彼此靠近的边缘之间的距离为第一距离D1，第一正投影包括与第二正投影交叠的交叠边缘311，交叠边缘311与第三正投影中最靠近交叠边缘的边缘之间的距离为第二距离D2，第二距离D2大于第一距离D1。例如，第一信号线310与开口610的彼此靠近的边缘在第一方向上的最小距离为D1。例如，连接部510与第一信号线310交叠的位置和与其距离最近的开口610之间在平行于XY面上的距离为第二距离D2。
例如，如图12所示，第一电极110与第一信号线310之间的距离大于5微米，如5.5～6微米。第二电极210与第一信号线310之间的距离为大于5微米，如5.5～6微米。
相对于一般第一电极或第二电极与第一信号线之间的距离为5微米的阵列基板，本公开提供的显示装置，通过增加第一电极或第二电极与第一信号线之间的距离的同时，将连接部的位置设置为其距离遮光层的开口的距离较大，以在降低显示装置负载且不影响开口率的同时，即使黑矩阵出现对位偏差，漏光的风险仍很低。
在一些示例中，如图12至图14所示，第一信号线310沿第二方向延伸，开口610包括沿第二方向延伸且最靠近第一信号线310的开口边缘611，连接部510位于开口边缘611和最靠近开口边缘611的第二信号线320之间。
在一些示例中，如图11所示，经过连接部510且沿第一方向延伸的直线不经过开口边缘611。例如，连接部510在沿第二方向延伸的直线上的正投影与开口边缘611在沿第二方向延伸的直线上的正投影没有交叠。例如，开口边缘611在衬底基板01上的正投影没有延伸至经过连接部510在衬底基板上的正投影且沿第一方向延伸的直线。
通过对连接部与开口边缘的位置关系的设置，有利于增加连接部与开口边缘之间的距离，降低显示装置的漏光风险。
图15为根据本公开实施例的另一示例提供的阵列基板的局部平面结构示意图。图16为图15所示阵列基板的局部放大图。图17为图15所示阵列基板中第一信号线所在层的示意图。图15所示阵列基板在一示例中，除第一信号线所在层外的其它层可以与图4至图10B所示阵列基板的各层具有相同的特 征，在此不再赘述。
在一些示例中，如图15至图17所示，多个子像素400至少包括第一颜色子像素410和第二颜色子像素420，且第一颜色子像素410和第二颜色子像素420均包括多畴。例如，第一颜色子像素410和第二颜色子像素420包括的畴的数量相同。例如，第一颜色子像素410和第二颜色子像素420均包括两畴。但不限于此，第一颜色子像素和第二颜色子像素还可以均包括四畴、八畴等。
在一些示例中，如图15至图17所示，第一颜色子像素410和第二颜色子像素420之一的出光区设置有突起部520，突起部520位于多畴中相邻两畴之间。例如，多畴的数量可以为两个，两个畴沿第二方向排列，突起部520位于两个畴之间。
在一些示例中，如图15至图17所示，第一颜色子像素410和第二颜色子像素420之一为红色子像素，另一个为蓝色子像素。例如，出光区设置有突起部520的子像素可以为红色子像素或者蓝色子像素。
采用负性液晶的显示装置偏振片(POL)对红光和蓝光的吸收率不同，容易产生大视角色偏问题，如大视角偏蓝或者大视角偏红。
以出光区设置有突起部的子像素为红色子像素为例，相对于没有设置突起部的显示装置，如显示过程中大视角下会出现偏蓝的问题的显示装置，本公开提供的阵列基板中，通过在红色子像素的出光区设置突起部，使得配向膜在配向过程中，对应突起部的位置处的配向异常，进而使得液晶在对应突起部的位置处无法被正常配向而漏出少量红光，漏出的少量红光可以中和部分蓝光，降低大视角下显示装置偏蓝的影响。
以出光区设置有突起部的子像素为蓝色子像素为例，相对于没有设置突起部的显示装置，如显示过程中大视角下会出现偏红的问题的显示装置，本公开提供的阵列基板中，通过在蓝色子像素的出光区设置突起部，使得配向膜在配向过程中，对应突起部的位置处的配向异常，进而使得液晶在对应突起部的位置处无法被正常配向而漏出少量蓝光，漏出的少量蓝光可以中和部分红光，可以降低大视角下显示装置偏红的影响。
例如，如图15至图17所示，第一颜色子像素410的出光区设置有突起部520，第二颜色子像素420的出光区不设置突起部520，第一颜色子像素410的数量为多个，至少一个第一颜色子像素410的出光区设置有突起部520，如每个第一颜色子像素410的出光区均设置突起部520，突起部520的数量为多个， 且多个突起部520均匀设置。
例如，如图15所示，多个子像素400还包括第三颜色子像素，第三颜色子像素可以为绿色子像素。例如，绿色子像素的出光区不设置突起部。
在一些示例中，如图15和图16所示，沿垂直于衬底基板01的方向，突起部520与相邻两畴至少之一中的条状电极111交叠，或者突起部520与条状电极111没有交叠。例如，突起部520可以包括多个子部，每个子部仅与相邻条状电极111之间的间隔交叠。
在一些示例中，如图15和图16所示，在垂直于衬底基板01的方向上，突起部520的边缘与相邻子像素400的出光区没有交叠，以防止对与突起部520所在子像素400相邻的子像素400的出光区产生影响。例如，突起部520的边缘位于子像素400的出光区内。但不限于此，突起部的边缘也可以与黑矩阵交叠。例如，突起部520在第一方向上的尺寸大于1微米。例如，突起部520在第一方向上的尺寸大于1.5微米。
在一些示例中，如图15和图16所示，突起部520在相邻两畴的排列方向上的尺寸为1.5～6微米。
例如，突起部520在相邻两畴的排列方向上的尺寸不大于4.8微米。例如，突起部520在相邻两畴的排列方向上的尺寸不大于4.5微米。例如，突起部520在相邻两畴的排列方向上的尺寸不大于4.2微米。例如，突起部520在相邻两畴的排列方向上的尺寸不大于4微米。例如，突起部520在相邻两畴的排列方向上的尺寸可以为2微米。例如，突起部520在相邻两畴的排列方向上的尺寸可以为2.5微米。例如，突起部520在相邻两畴的排列方向上的尺寸可以为3微米。
例如，如图15和图16所示，突起部520的延伸方向与位于其两侧的相邻两畴的排列方向相交。例如，突起部520沿第一方向延伸，相邻两畴沿第二方向排列。例如，突起部520在第一方向上的尺寸不大于其所在出光区在第一方向上的尺寸。
通过对突起部的尺寸以及位置的设置，有利于实现其所在子像素漏出一定量光，进而中和另一颜色光，以缓解大角度下色偏现象。
例如，图15和图16示意性的示出同一个出光区设置的突起部的数量为一个，但不限于此，同一个出光区设置的突起部的数量可以为多个，如两个、三个或者更多个，且多个突起部中位于最边缘的两端不超过出光区的边缘。
在一些示例中，如图15至图17所示，突起部520与第一信号线310和第二信号线320之一同层设置。例如，突起部520与第一信号线310同层设置。例如，突起部520不与任何信号线电连接，如处于浮置(floating)状态。
当然，本公开实施例不限于此，突起部还可以与第二信号线同层设置。在其他示例中，突起部也可以为绝缘层中的一部分，如通过半色调掩模工艺等在绝缘层中形成厚度较其他位置较大的突起部。
本公开实施例示意性的示出第二电极层与第二信号线位于不同层，但不限于此，第二电极层还可以与第二信号线位于同一层，此时突起部与第一信号线同层设置。例如，第二电极与第一信号线和第二信号线之一同层设置，突起部与第一信号线和第二信号线中的另一个同层设置。
需要说明的是，本案中示意了双栅结构，这样设置可以减少数据线的数量，当然本案也可以是单栅结构，即同一行栅线对应一行像素行，且相邻两列子像素列连接不同的数据线，具体显示架构本案不限定。
图18为根据本公开实施例提供的阵列基板的平面结构示意图。图18所示阵列基板可以包括上述任一示例中的阵列基板。
在一些示例中，如图18所示，阵列基板包括显示区10和位于显示区10至少一侧的非显示区20，多个子像素400、多条第一信号线310和多条第二信号线320均位于显示区10。
在一些示例中，如图18所示，阵列基板还包括位于非显示区20的且与第二信号线320同层设置的多条信号传输线710，以及与信号传输线710电连接的连接走线720，连接走线720沿第一方向延伸，信号传输线710沿第二方向延伸，连接走线720与第一信号线310同层设置。例如，信号传输线710通过连接走线720与第二信号线320电连接。
图19为一种阵列基板中的信号传输线和连接走线的示意图。
在研究中，本申请的发明人发现：如图19所示，连接走线720通过转接部702实现信号传输线710与连接走线720的电连接，至少一条连接走线720需要跨过位于其与显示区之间的信号传输线710以与相应的第二信号线320电连接，被连接走线720跨越的位置设置有开口701以减小两者交叠面积，进而降低信号线负载，但是连接走线720位于信号传输线710远离衬底基板的一侧，连接走线720跨越一条信号传输线710则需要爬坡两次，连接走线720跨越的信号传输线710的数量越多，爬坡的次数越多，不仅影响非显示区位置处 的平坦性，还容易导致连接走线出现断线风险。
图20为根据本公开实施例提供的信号传输线、连接走线以及连接结构的示意图。图21为图20所示信号传输线的示意图。图22为图20所示连接走线的示意图。图23和图24为图20所示过孔以及连接结构的示意图。
在一些示例中，如图18、图20至图24所示，沿垂直于衬底基板01的方向，至少一条信号传输线710与连接走线720交叠，且信号传输线710中与连接走线720交叠部分的边缘包括凹口711，以使交叠部分在连接走线720的延伸方向上的尺寸小于与信号传输线710中除交叠部分以外的至少部分位置在连接走线720的延伸方向上的尺寸。例如，信号传输线710可以包括时钟信号(clock)线，用于给设置在显示面板非显示区的栅极驱动电路提供时钟信号，栅极驱动电路用于给显示面板显示区域的栅线电连接，可选的，信号传输线还可以包括用于给栅极驱动电路提供的直流信号，例如VGH或这VGL信号，或者还包括用于给栅极驱动电路提供初始信号(STV)等，在此不限定。
例如，如图21所示，交叠部分在第一方向上的尺寸为D01，交叠部分以外且与交叠部分距离最近的部分在第一方向上的尺寸为D02，如D02可以为信号传输线710的线宽(其在第一方向上宽度最大的位置处的尺寸)D01小于D02。例如，D01与D02之比可以为0.1～0.9，如0.3～0.8，如0.4～0.6以平衡电容和电阻。
相对于图19所示的在信号传输线与连接走线交叠位置设置开口的方案，本公开提供的阵列基板中，通过在信号传输线中与连接走线的边缘位置设置凹口，可以在不改变电阻和电容的情况下，减少连接走线跨越信号传输线时爬坡的次数，以降低连接走线出现断线的风险。
例如，如图20至图24所示，连接走线720通过位于其与连接结构731之间的绝缘层中的过孔733与连接结构731连接，信号传输线710通过位于其与连接结构731之间的绝缘层中的过孔732与连接结构731连接，从而实现连接走线720与信号传输线710的连接。例如，连接结构731可以与第一电极层和第二电极层之一同层设置。例如，过孔733的数量可以为多个，过孔732的数量可以为多个。
例如，如图20所示，每条信号传输线710包括多个凹口711，且信号传输线710的沿第二方向延伸的两条边缘均设置凹口711，上述多个凹口711相对于每条信号传输线710的沿第二方向延伸的中心线对称分布。
例如，参考图20，信号传输线通过连接结构和连接走线实现电连接，在连接结构位置处，连接走线和连接结构连接处至少部分设置在凹口位置。
例如，如图20所示，信号传输线710的数量为多条，不同信号传输线710中的凹口711的具有相同的分布，以方便制作。
例如，如图20所示，信号传输线710中位于在沿第一方向上排列的两个凹口711之间的部分为收窄部712。例如，至少一条信号传输线710包括多个收窄部712，多个收窄部712在第二方向上均匀设置。
例如，如图20所示，至少一条信号传输线710的至少一个收窄部712与连接走线720没有交叠。例如，至少一条信号传输线710的各收窄部712均与连接走线720没有交叠。例如，至少一条信号传输线710的多个收窄部712中与连接走线720交叠的数量可以小于、等于或者大于多个收窄部712中没有与连接走线720交叠的数量。
例如，如图20和图22所示，连接走线720包括沿第一方向延伸的第一连接走线部721和沿第二方向延伸的第二连接走线部722，第一连接走线部721和第二连接走线部722可以为一体化设置的结构。例如，第一连接走线部721与第二连接走线部722形成的拐角处与凹口711交叠，如第一连接走线部721与第二连接走线部722形成的拐角处与信号传输线710没有交叠。
例如，如图20和图21所示，至少一些信号传输线710中不与信号传输线交叠的部分设置有开槽713。例如，相邻收窄部712之间设置有多个开槽713。例如，相邻收窄部712之间的多个开槽713沿第一方向和第二方向阵列排布。
图25为一种阵列基板的局部平面结构示意图。图26至图28为图25所示阵列基板中不同膜层的示意图。
如图25至图28所示，该阵列基板可以包括上述实施例中的子像素400、第一信号线310、第二信号线320以及公共电极线120，子像素400共用第一电极层100，上述子像素400、第一信号线310、第二信号线320以及公共电极线120均位于显示区。图25至图28所示阵列基板还包括位于非显示区的公共信号传输线80，各公共电极线120均与同一条公共信号传输线80电连接。
在研究中，本申请的发明人发现：显示装置可以为液晶显示装置，随着液晶光效的不断提高，液晶中大极性单体的含量不断提高，由于受到液晶层包括的液晶中大极性单体成分的影响，在显示装置长期显示棋盘格或其他类似黑白格画面时，黑色画面与白色画面交叠位置容易出现线性污渍问题。
本公开实施例提供一种阵列基板，该阵列基板包括衬底基板以及位于衬底基板上的多个子像素、多条数据线以及多条公共电极线。衬底基板包括显示区以及位于显示区至少一侧的第一非显示区；多个子像素位于显示区，各子像素包括层叠设置的第一电极和第二电极；多条数据线位于显示区且被配置为与第二电极电连接，多条数据线沿第一方向排列；多条栅线位于显示区且沿第二方向排列，第二方向与第一方向相交；多条公共电极线位于显示区且与第一电极电连接，多条公共电极线与多条数据线沿第一方向交替设置。阵列基板还包括位于第一非显示区的公共信号传输线，公共信号传输线包括第一公共信号传输线和第二公共信号传输线，第二公共信号传输线设置在第一公共信号传输线远离显示区的一侧，公共信号传输线沿第一方向延伸，第一公共信号传输线与多条公共电极线的一部分电连接，第二公共信号传输线与多条公共电极线的另一部分电连接，第一非显示区还包括焊盘区，焊盘区被配置为与电路板电连接。本公开提供的阵列基板，通过设置第一公共信号传输线和第二公共信号传输线，有利于改善显示亮度不均匀、线性mura等问题。
在一些示例中，第一公共信号传输线和第二公共信号传输线被配置为传输不同电信号，通过设置传输不同电信号的第一公共信号传输线和第二公共信号传输线，有利于改善显示亮度不均匀、线性mura等问题。
图29为根据本公开实施例提供的阵列基板的平面结构示意图。图30为图29所示阵列基板中的显示区和第二非显示区的局部放大图。图31为图30所示阵列基板的子像素的第二电极所在层的示意图。图32为图30所示阵列基板的栅线所在层的示意图。图33为图30所示阵列基板的数据线所在层的示意图。图34为图30所示阵列基板的过孔的示意图。图35为图30所示阵列基板的子像素的第一电极所在层的示意图。
如图29所示，阵列基板包括衬底基板01，衬底基板01包括显示区10以及位于显示区10至少一侧的第一非显示区21。阵列基板包括位于衬底基板01上的多个子像素400、多条数据线310、多条栅线320以及多条公共电极线120。多个子像素400、多条数据线310、多条栅线320以及多条公共电极线120均位于显示区10。
如图29至图31以及图34所示，各子像素400包括层叠设置的第一电极110和第二电极210。图29至图34所示阵列基板中子像素400包括的第二电极210可以与图4至图17所示阵列基板中的子像素400包括的第二电极210 具有相同的特征，在此不再赘述。
如图29、图30、图32和图33所示，多条数据线310被配置为与子像素400的第二电极210电连接，且多条数据线沿第一方向排列；多条栅线320沿第二方向排列，第二方向与第一方向相交。
在一些示例中，如图29至图35所示，沿第二方向排列的相邻两个子像素400之间设置有两条栅线320，相邻两条数据线310之间设置有沿第一方向排列的两个子像素400，两个子像素400的第一电极110为一体化设置的结构。
图29至图35所示阵列基板中的数据线310与图4至图17所示阵列基板中的第一信号线310具有相同的特征，图29至图35所示阵列基板中的栅线320与图4至图17所示阵列基板中的第二信号线320具有相同的特征，在此不再赘述。图29至图35所示阵列基板中的第一方向与第二方向可以参考图4至图17所示阵列基板中的第一方向与第二方向，在此不再赘述。图29至图35所示阵列基板中子像素400、数据线310以及栅线320的位置关系可以参考图4至图17所示阵列基板中子像素400、数据线310以及栅线320的位置关系。
例如，图29至图35所示阵列基板还包括图4至图17所示阵列基板中的晶体管，晶体管与数据线、栅线以及子像素的第一电极的连接关系均可参考图4至图17所示阵列基板中的相应连接关系。
如图29、图30、图33以及图35所示，多条公共电极线120与子像素400的第一电极110电连接，且多条公共电极线120与多条数据线310沿第一方向交替设置。
在一些示例中，如图29、图30、图33以及图35所示，至少一条公共电极线120包括层叠设置的第一导电层122和第二导电层121，第一导电层122与数据线310同层设置，第二导电层121与第一电极110同层设置。
图33所示公共电极线120的第一导电层122与图8所示公共电极线120的第二公共电极线层122具有相同的特征，图33所示公共电极线120的第一导电层122可参考图8所示公共电极线120的第二公共电极线层122的相关描述；图35所示公共电极线120的第二导电层121与图10A或图10B所示公共电极线120的第一公共电极线层121具有相同的特征，图35所示公共电极线120的第二导电层121可参考图10A或图10B所示公共电极线120的第一公共电极线层121的相关描述。
如图29所示，阵列基板还包括位于第一非显示区21的公共信号传输线 800，公共信号传输线800包括第一公共信号传输线810和第二公共信号传输线820，第二公共信号传输线820设置在第一公共信号传输线810远离显示区10的一侧，公共信号传输线800沿第一方向延伸。例如，第一公共信号传输线810与所述第二公共信号传输线820平行设置。
如图29所示，第一公共信号传输线810和第二公共信号传输线820被配置为传输不同电信号，第一公共信号传输线810与多条公共电极线120的一部分电连接，第二公共信号传输线820与多条公共电极线120的另一部分电连接。例如，多条公共电极线120的数量为N，其中M条公共电极线120与第一公共信号传输线810电连接，(N-M)条公共电极线120与第二公共信号传输线820电连接，M和N均为正整数，且M小于N。例如，与第一公共信号传输线810电连接的公共电极线120的数量等于与第二公共信号传输线820电连接的公共电极线120的数量。但不限于此，根据显示需求，与第一公共信号传输线和与第二公共信号传输线电连接的公共电极线的数量可以不同。
如图29所示，第一非显示区21还包括焊盘区910，焊盘区910被配置为与电路板电连接。例如，第二公共信号传输线820位于第一公共信号传输线810与焊盘区910之间。例如，焊盘区910包括与电路板电连接的多个焊盘。例如，电路板可以为柔性电路板(Flexible Printed Circuit，FPC)、印刷电路板(Printed circuit boards，PCB)等。
本公开提供的阵列基板，通过设置两条传输不同电信号的第一公共信号传输线和第二公共信号传输线，可以通过灵活调节两者传输的电信号的差异，以降低包括该阵列基板的显示装置显示时出现亮度不均匀的程度。
在一些示例中，如图29和图30所示，阵列基板还包括第二非显示区22，第一非显示区21、显示区10和第二非显示区22沿第二方向依次排布。例如，第一非显示区21和第二非显示区22位于显示区10在第二方向上的两侧。公共信号传输线800还包括位于第二非显示区22的第三公共信号传输线830和第四公共信号传输线840，第四公共信号传输线840位于第三公共信号传输线830远离显示区10的一侧，第三公共信号传输线830和第二公共信号传输线820电连接，第四公共信号传输线840和第一公共信号传输线810电连接。
在一些示例中，如图29、图30以及图32所示，公共信号传输线800的至少部分与栅线320同层设置。例如，第一公共信号传输线810、第二公共信号传输线820、第三公共信号传输线830以及第四公共信号传输线840可以为同 层设置的结构。例如，第三公共信号传输线830与第四公共信号传输线840平行设置。
例如，如图29所示，至少一条公共电极线120的两端分别与第一公共信号传输线810和第四公共信号传输线840连接；至少一条公共电极线120的两端分别与第二公共信号传输线820和第三公共信号传输线830连接。
在一些示例中，如图29所示，阵列基板还包括第三非显示区23和第四非显示区24，第三非显示区23、显示区10以及第四非显示区24沿第一方向依次排列。例如，显示区10位于第三非显示区23和第四非显示区24之间。例如，第一非显示区21、第二非显示区22、第三非显示区23以及第四非显示区24形成围绕显示区10的一圈非显示区。
在一些示例中，如图29所示，第三非显示区23设置有连接第二公共信号传输线820和第三公共信号传输线830的第一连接线801，第四非显示区24设置有连接第一公共信号传输线810和第四公共信号传输线840的第二连接线802，第一连接线801的至少部分、第二连接线802的至少部分以及公共信号传输线800的至少部分为同层设置的结构。例如，第一公共信号传输线810、第四公共信号传输线840以及第二连接线802可以为一体化设置的结构，第二公共信号传输线820、第三公共信号传输线830以及第一连接线801可以为一体化设置的结构。当然，本公开实施例不限于此，第一连接线和第二连接线至少之一还可以通过其它转接层与公共信号传输线连接。
在一些示例中，如图29、图30以及图35所示，位于相邻数据线310之间的两列子像素400的第一电极110与同一条公共电极线120电连接，且分别位于同一条数据线310两侧且与同一条数据线310距离最近的两列子像素400的第一电极110间隔设置，且分别与第一公共信号传输线810和第二公共信号传输线820电连接。例如，位于数据线310两侧且沿第一方向排列的两个子像素400的第一电极110绝缘设置，以分别与第三公共信号线830和第四公共信号线840电连接。本公开中的行与列可以互换。
例如，如图29、图30以及图35所示，多条公共电极线120中的第奇数条公共电极线120与第三公共信号传输线830和第四公共信号传输线840之一电连接，第偶数条公共电极线120与第三公共信号传输线830和第四公共信号传输线840中的另一条电连接。通过将第奇数条和第偶数条公共电极线分开引出，并从外部电路获得两个独立的公共电平电压，以根据线性污渍的位置设置不同 电平，从而微调黑白边界处的像素亮度，改善线性污渍问题。
当然，本公开实施例不限于此，可以根据现实需要，对公共电极线与公共信号传输线的连接关系进行设置，如对多条公共电极线进行分组，每组包括至少两条且相邻设置的公共电极线，每组公共电极线连接至同一条公共信号传输线，如不同组公共电极线的数量可以相同，也可以不同。公共电极线的奇偶分离不局限于上述沿第一方向排列的多条公共电极线。如果公共电极线沿第二方向排列，则同样可将奇偶行的公共电极线进行分离。
在一些示例中，如图29、图30、图33和图35所示，阵列基板还包括转接部920，至少一条公共电极线120通过转接部920与公共信号传输线800电连接，转接部920包括层叠设置的第一转接层921和第二转接层922，第一转接层921与第一导电层122同层设置，第二转接层922与第二导电层121同层设置。
例如，如图33所示，第一转接层921与第一导电层122可以为一体化设置的结构。
例如，如图35所示，部分第二转接层922与第二导电层121可以为一体化设置的结构，该部分第二转接层922与第三公共信号传输线830连接，另一部分第二转接层922与第二导电层121间隔设置，该部分第二转接层922与第四公共信号传输线840连接。
例如，如图30至图35所示，第二转接层922通过多个过孔363的一部分与第一转接层921电连接，第一转接层921通过多个过孔363的另一部分与第三公共信号传输线830以及第四公共信号传输线840连接。
例如，如图32所示，第三公共信号传输线830与第四公共信号传输线840之间的间隔的尺寸小于第三公共信号传输线830和第四公共信号传输线840至少之一的宽度。例如，第三公共信号传输线830与第四公共信号传输线840的宽度之比为0.9～1.1，如第三公共信号传输线830与第四公共信号传输线840的宽度相等。
例如，第三公共信号传输线830和第四公共信号传输线840至少之一可以设置多个开槽(图中未示出)以提高配向膜配向的均匀性。
在一些示例中，如图29所示，第三非显示区23设置有第五公共信号传输线850、第一栅极驱动电路930以及第一公共信号反馈线940，第五公共信号传输线850和第一公共信号反馈线940均与第三公共信号传输线830电连接， 第一栅极驱动电路930与多条栅线320电连接，第五公共信号传输线850和第一公共信号反馈线840均位于第一栅极驱动电路930远离显示区10的一侧，第一连接线801位于第一栅极驱动电路930与显示区10之间。
例如，栅线320可以通过图22所示的连接走线720与第一栅极驱动电路930。例如，第一栅极驱动电路930可以包括图20所示的信号传输线710。例如，第一栅极驱动电路930可以是GOA栅极驱动电路。
例如，显示区远离电路板的区域为远端，显示区靠近电路板的区域为近端，第一公共信号反馈线940可以用于检测远端的公共信号，当第一公共信号反馈线940检测到远端的公共信号的波形有较大的起伏时，可以通过第五公共信号传输线850对上述远端的公共信号进行补偿；当第一公共信号反馈线940检测到远端的公共信号正常时，第五公共信号传输线850被输入一般的公共信号。例如，当检测到远端的公共信号的波形相对于公共信号平衡点的电压向上波动时，补偿方式采用反向互补，补偿信号作用在上述波形时，可以将上述向上波动拉回到平衡点。
在一些示例中，如图29所示，第四非显示区24设置有第六公共信号传输线860、第二栅极驱动电路950以及第二公共信号反馈线960，第六公共信号传输线860和第二公共信号反馈线960均与第四公共信号传输线840电连接，第二栅极驱动电路950与多条栅线320电连接，第六公共信号传输线860和第二公共信号反馈线960均位于第二栅极驱动电路950远离显示区10的一侧，第二连接线802位于第二栅极驱动电路950与显示区10之间。
例如，如图29所示，阵列基板采用双边栅极驱动技术。例如，第二栅极驱动电路950可以与第一栅极驱动结构930具有相同的特征，第二公共信号反馈线960可以与第一公共信号反馈线940具有相同的特征，第六公共信号传输线860可以与第五公共信号传输线850具有相同的特征，在此不再赘述。
例如，如图29所示，阵列基板还包括接地线(GND)972、测试信号线(如增强信号线，Addition Line，ADD)971、ESD静电释放电路975、静电释放环(inner short ring)973和974。例如，阵列基板中的公共信号传输线还包括传输线871和872，但不限于此，传输线871和872也可以省去。
本公开另一实施例提供一种显示装置，包括图29至图35任一项所示的阵列基板。
例如，显示装置还可以包括对置基板。例如，对置基板设置有黑矩阵以及 彩膜层。例如，显示装置还包括位于阵列基板与对置基板之间的液晶层。
例如，本公开实施例提供的上述任一显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。该显示装置包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、用户输入单元、接口单元、存储器、处理器、以及电源等部件。另外，本领域技术人员可以理解的是，上述结构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述显示装置中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
有以下几点需要说明：
(1)本公开的实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (27)

  1. 一种阵列基板，包括：
    衬底基板以及位于所述衬底基板上的第一电极层、多条第一信号线以及多条第二信号线，所述多条第一信号线沿第一方向排列，所述多条第二信号线沿第二方向排列，所述第一方向与所述第二方向相交；
    其中，所述第一电极层包括沿所述第一方向和所述第二方向阵列排布的多个第一电极，位于同一条第一信号线两侧且相邻的两个第一电极之间设置有连接部，所述连接部被配置为连接所述两个第一电极；
    相对于经过所述第一电极的中心区域且沿所述第一方向延伸的直线，所述连接部更靠近所述第二信号线。
  2. 根据权利要求1所述的阵列基板，其中，在所述第二方向上，所述第一电极与所述第二信号线之间的距离不大于所述连接部与所述第二信号线之间的距离。
  3. 根据权利要求1或2所述的阵列基板，其中，所述阵列基板包括多个子像素，所述多个子像素至少包括第一颜色子像素和第二颜色子像素，且所述第一颜色子像素和所述第二颜色子像素均包括多畴，所述第一颜色子像素和所述第二颜色子像素之一的出光区设置有突起部，所述突起部位于所述多畴中相邻两畴之间。
  4. 根据权利要求3所述的阵列基板，其中，所述第一颜色子像素和所述第二颜色子像素中，所述第一电极包括多个条状电极，且相邻两畴中条状电极的延伸方向相交；
    沿垂直于所述衬底基板的方向，所述突起部与所述相邻两畴至少之一中的所述条状电极交叠，或者所述突起部与所述条状电极没有交叠。
  5. 根据权利要求3或4所述的阵列基板，其中，所述突起部与所述第一信号线和所述第二信号线之一同层设置。
  6. 根据权利要求3-5任一项所述的阵列基板，其中，所述第一颜色子像素和所述第二颜色子像素之一为红色子像素，另一个为蓝色子像素。
  7. 根据权利要求3-6任一项所述的阵列基板，其中，在垂直于所述衬底基板的方向上，所述突起部的边缘与相邻子像素的出光区没有交叠，且所述突起部在所述相邻两畴的排列方向上的尺寸为1.5～6微米。
  8. 根据权利要求4所述的阵列基板，其中，所述连接部的宽度大于所述条状电极的宽度，且所述连接部的宽度不大于10微米。
  9. 根据权利要求5所述的阵列基板，还包括与所述第一电极层层叠设置的第二电极层，所述第二电极层包括多个第二电极，每个子像素包括一个第二电极。
  10. 根据权利要求1-9任一项所述的阵列基板，其中，在沿所述第一方向上，所述两个第一电极之间设置的所述连接部的数量至少为一个。
  11. 根据权利要求1-10任一项所述的阵列基板，其中，所述连接部与所述两个第一电极为一体化设置的结构。
  12. 根据权利要求1-11任一项所述的阵列基板，其中，相邻两条第一信号线之间设置有沿所述第一方向排列的两个子像素，且沿所述第二方向排列的相邻两个子像素之间设置有两条第二信号线，所述第一信号线为数据线，所述第二信号线为栅线。
  13. 根据权利要求12所述的阵列基板，其中，位于相邻两条第一信号线之间且沿所述第一方向排列的相邻子像素的第一电极为一体化设置的结构，位于所述第一信号线两侧且沿所述第一方向排列的相邻子像素的第一电极之间设置有间隔，且所述第一信号线位于所述间隔中。
  14. 根据权利要求1-13任一项所述的阵列基板，包括：显示区和位于所述显示区至少一侧的非显示区，
    其中，所述多个子像素、所述多条第一信号线和所述多条第二信号线均位于所述显示区，所述阵列基板还包括位于所述非显示区的且与所述第二信号线同层设置的多条信号传输线，以及与所述信号传输线电连接的连接走线，所述连接走线沿所述第一方向延伸，所述信号传输线沿所述第二方向延伸，所述连接走线与所述第一信号线同层设置；
    沿垂直于所述衬底基板的方向，至少一条信号传输线与所述连接走线交叠，且所述信号传输线中与所述连接走线交叠部分的边缘包括凹口以使所述交叠部分在所述连接走线的延伸方向上的尺寸小于与所述信号传输线中除所述交叠部分以外的至少部分位置在所述连接走线的延伸方向上的尺寸。
  15. 一种显示装置，包括：
    权利要求1-14任一项所述的阵列基板；
    对置基板，与所述阵列基板相对设置，所述对置基板包括遮光层，所述遮 光层包括多个开口以限定子像素的出光区；
    其中，所述第一信号线在所述衬底基板上的正投影包括第一正投影，所述连接部在所述衬底基板上的正投影包括第二正投影，所述第二正投影位于所述遮光层在所述衬底基板上的正投影内；
    所述开口在所述衬底基板上的正投影包括第三正投影，所述第一正投影与所述第三正投影的彼此靠近的边缘之间的距离为第一距离，所述第一正投影包括与所述第二正投影交叠的交叠边缘，所述交叠边缘与所述第三正投影中最靠近所述交叠边缘的边缘之间的距离为第二距离，所述第二距离大于所述第一距离。
  16. 根据权利要求15所述的显示装置，其中，所述第一信号线沿所述第二方向延伸，所述开口包括沿所述第二方向延伸且最靠近所述第一信号线的开口边缘，所述连接部位于所述开口边缘和最靠近所述开口边缘的所述第二信号线之间。
  17. 根据权利要求16所述的显示装置，其中，经过所述连接部且沿所述第一方向延伸的直线不经过所述开口边缘。
  18. 一种阵列基板，包括：
    衬底基板，包括显示区以及位于所述显示区至少一侧的第一非显示区；
    多个子像素，位于所述衬底基板的显示区，各子像素包括层叠设置的第一电极和第二电极；
    多条数据线，位于所述衬底基板的显示区且被配置为与所述第二电极电连接，所述多条数据线沿第一方向排列；
    多条栅线，位于所述衬底基板的显示区且沿第二方向排列，所述第二方向与所述第一方向相交；
    多条公共电极线，位于所述衬底基板的显示区且与所述第一电极电连接，所述多条公共电极线与所述多条数据线沿所述第一方向交替设置；
    其中，所述阵列基板还包括位于所述第一非显示区的公共信号传输线，所述公共信号传输线包括第一公共信号传输线和第二公共信号传输线，所述第二公共信号传输线设置在所述第一公共信号传输线远离所述显示区的一侧，所述公共信号传输线沿所述第一方向延伸，所述第一公共信号传输线与所述多条公共电极线的一部分电连接，所述第二公共信号传输线与所述多条公共电极线的另一部分电连接，所述第一非显示区还包括焊盘区，所述焊盘区被配置为与电 路板电连接。
  19. 根据权利要求18所述的阵列基板，还包括第二非显示区，所述第一非显示区、所述显示区和所述第二非显示区沿所述第二方向依次排布，
    所述公共信号传输线还包括位于所述第二非显示区的第三公共信号传输线和第四公共信号传输线，所述第四公共信号传输线位于所述第三公共信号传输线远离所述显示区的一侧，所述第三公共信号传输线和所述第二公共信号传输线电连接，所述第四公共信号传输线和所述第一公共信号传输线电连接。
  20. 根据权利要求19所述的阵列基板，其中，沿所述第二方向排列的相邻两个子像素之间设置有两条栅线，相邻两条数据线之间设置有沿所述第一方向排列的两个子像素，所述两个子像素的第一电极为一体化设置的结构。
  21. 根据权利要求19或20所述的阵列基板，还包括：
    转接部，至少一条公共电极线通过所述转接部与所述公共信号传输线电连接，
    其中，所述至少一条公共电极线包括层叠设置的第一导电层和第二导电层，所述第一导电层与所述数据线同层设置，所述第二导电层与所述第一电极同层设置，所述公共信号传输线的至少部分与所述栅线同层设置；
    所述转接部包括层叠设置的第一转接层和第二转接层，所述第一转接层与所述第一导电层同层设置，所述第二转接层与所述第二导电层同层设置。
  22. 根据权利要求19-21任一项所述的阵列基板，还包括：
    第三非显示区和第四非显示区，所述第三非显示区、所述显示区以及所述第四非显示区沿所述第一方向依次排列，
    其中，所述第三非显示区设置有连接所述第二公共信号传输线和所述第三公共信号传输线的第一连接线，所述第四非显示区设置有连接所述第一公共信号传输线和所述第四公共信号传输线的第二连接线，所述第一连接线的至少部分、所述第二连接线的至少部分以及所述公共信号传输线的至少部分为同层设置的结构。
  23. 根据权利要求22所述的阵列基板，其中，所述第三非显示区设置有第五公共信号传输线、第一栅极驱动电路以及第一公共信号反馈线，所述第五公共信号传输线和所述第一公共信号反馈线均与所述第三公共信号传输线电连接，所述第一栅极驱动电路与所述多条栅线电连接，所述第五公共信号传输线和所述第一公共信号反馈线均位于所述第一栅极驱动电路远离所述显示区 的一侧，所述第一连接线位于所述第一栅极驱动电路与所述显示区之间。
  24. 根据权利要求22或23所述的阵列基板，其中，所述第四非显示区设置有第六公共信号传输线、第二栅极驱动电路以及第二公共信号反馈线，所述第六公共信号传输线和所述第二公共信号反馈线均与所述第四公共信号传输线电连接，所述第二栅极驱动电路与所述多条栅线电连接，所述第六公共信号传输线和所述第二公共信号反馈线均位于所述第二栅极驱动电路远离所述显示区的一侧，所述第二连接线位于所述第二栅极驱动电路与所述显示区之间。
  25. 根据权利要求18-24任一项所述的阵列基板，其中，位于相邻数据线之间的两列子像素的第一电极与同一条公共电极线电连接，分别位于同一条数据线两侧且与所述同一条数据线距离最近的两列子像素的第一电极间隔设置，且分别与所述第一公共信号传输线和所述第二公共信号传输线电连接。
  26. 根据权利要求18-25任一项所述的阵列基板，其中，所述第一公共信号传输线和所述第二公共信号传输线被配置为传输不同电信号。
  27. 一种显示装置，包括权利要求18-26任一项所述的阵列基板。
PCT/CN2024/090260 2023-05-29 2024-04-28 阵列基板以及显示装置 WO2024244858A1 (zh)

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