WO2024237467A1 - Memory device - Google Patents

Abstract

The present invention relates to a memory device comprising a memory cell configured to store n-bit data by operations of a word line and a bit line. The memory device comprises an op amp having a first inverting input terminal coupled to a first other-side terminal of a cell mode switch having a first one-side terminal coupled to a bit line to which a memory cell is coupled, the op amp having a first non-inverting input terminal coupled to a second other-side terminal of a precharge switch having a second one-side terminal coupled to a precharge voltage terminal, and the op amp having a feedback switch coupled between a first output terminal and the first inverting input terminal. The memory device comprises a comparator having a second inverting input terminal coupled to the second other side-terminal of the precharge switch, the comparator having a second non-inverting input terminal coupled to a third other-side terminal of a sampling capacitor having a third one-side terminal coupled to the first output terminal of the op-amp, and the comparator having a second output terminal. The memory device comprises a flip switch having a fourth one-side terminal coupled between the first output terminal of the op amp and the third one-side terminal of the sampling capacitor, and the flip switch having a fourth other-side terminal coupled to a flip voltage terminal. The memory device comprises a sampling switch having a fifth one-side terminal coupled between the third other-side terminal of the sampling capacitor and the second non-inverting input terminal of the comparator, and the sampling switch having a fifth other-side terminal coupled to a minimum level voltage terminal for providing a minimum level voltage. The minimum level voltage is the first level voltage among a first level voltage to a (2^n)th level voltage for distinguishing n-bit data, and n is an integer equal to or larger than 1. The memory device comprises (i) a first voltage generator to (ii) a nth voltage generator. The first voltage generator comprises: a first capacitor having a (1_1)th one-side terminal coupled between the second other-side terminal of the precharge switch and the second non-inverting input terminal of the comparator; a first common switch having a (1_2)th one-side terminal coupled to the (1_1)th other-side terminal of the first capacitor and having a (1_2)th other-side terminal coupled to the precharge voltage terminal; a first positive switch having a (1_3)th one-side terminal coupled to the a (1_1)th other-side terminal of the first capacitor and having a (1_3)th other-side terminal coupled to a maximum level voltage terminal for providing a maximum level voltage, the maximum level voltage being the 2^nth level voltage; and a first negative switch having a (1_4)th one-side terminal coupled to the (1_1)th other-side terminal of the first capacitor and having a (1_4)th other-side terminal coupled to the minimum level voltage terminal. The nth voltage generator comprises: a nth capacitor having a (n_1)th one-side terminal coupled between the second other-side terminal of the precharge switch and the second inverting input terminal of the comparator; a nth common switch having a (n_2)th one-side terminal coupled to the (n_1)th other-side terminal of the nth capacitor and having a (n_2)th other-side terminal coupled to the precharge voltage terminal; a nth positive switch having a (n_3)th one-side terminal coupled to the a (n_1)th other-side terminal of the nth capacitor and having a (n_3)th other-side terminal coupled to the maximum level voltage terminal; and a nth negative switch having a (n_4)th one-side terminal coupled to the (n_1)th other-side terminal of the nth capacitor and having a (n_4)th other-side terminal coupled to the minimum level voltage terminal. The memory device comprises a switch controller for controlling the first voltage generator to the nth voltage generator in response to output digital data which is output from the second output terminal of the comparator, or n-bit input digital data which is input to write the n-bit data in the memory cell, thereby generating an analog signal corresponding to the output digital data or the n-bit input digital data.

Description

Memory device

The present invention relates to a memory device, and more particularly, to a memory device capable of reducing the influence of nonlinearity of a digital-to-analog converter for storing data in a memory cell.

DRAM, a representative element in semiconductor memory devices, records data in memory cells composed of one transistor and one capacitor, and records one bit of information, for example, “0” and “1,” in the memory cell by charging or discharging the charge in the capacitor.

In addition, multi-level DRAMs have been recently proposed to increase data storage capacity by storing more than one bit of data in a single memory cell, unlike memory cells that store one bit of information, i.e., one bit of information of “0” or “1”, in a memory cell that includes one transistor and one capacitor.

And, in DRAM, the word line determines whether to access the capacitor by turning the transistor on and off, and data is stored in the capacitor or read from the capacitor through the bit line.

For example, referring to FIG. 1, in a conventional DRAM, when digital data is written or refreshed in a memory cell, i.e., a capacitor (Co) of a memory cell, a digital-to-analog converter (DAC) converts the input digital data into analog data, i.e., an analog voltage of a specific level corresponding to the digital data, and the converted analog voltage is stored in the memory cell (Co). Then, when data stored in the memory cell (Co) is read, the specific level voltage stored in the memory cell (Co) is amplified and output through an amplifier (AMP), and the output voltage of the amplified amplifier is converted into digital data and output by an analog-to-digital converter (ADC).

However, in such conventional DRAMs, due to variations in the process, the conversion function between the input and output of the digital-to-analog converter (DAC) may not be linear, and when data is written to or refreshed in a memory cell (Co), the voltage output from the digital-to-analog converter (DAC) is stored as is in the memory cell (Co), so data reflecting the nonlinearity of the digital-to-analog converter (DAC) is stored in the memory cell (Co).

Therefore, even if the same data is stored in the memory cell (Co), the linearity of the digital-to-analog converter (DAC) coupled for each bit line (BL0, BL1, BL2) may be different, and the voltage amplified through the same amplifier (AMP) may differ significantly for each bit line (BL0, BL1, BL2). In addition, since the output voltage of the amplified amplifier becomes the input voltage of the analog-to-digital converter (ADC), if the analog-to-digital converter (ADC) performs ideal operation without reflecting the nonlinearity of the digital-to-analog converter (DAC), a problem occurs in which the digital codes output for each bit line (BL0, BL1, BL2) are different.

In addition, if the linearity of the digital-to-analog converter (DAC) and the analog-to-digital converter (ADC) are different even within the same bit line, there is a problem in that the input code input to the digital-to-analog converter (DAC) and the output code read out by the analog-to-digital converter (ADC) become different.

That is, in conventional memory devices, since the nonlinearity of the digital-to-analog converter (DAC) is not reflected in the analog-to-digital converter (ADC), there is a problem in that the stored data cannot be accurately read out when writing to the memory cell.

That is, as in Fig. 2a, when the same digital code (D _IN ) is input to a digital-to-analog converter (DAC1) having a linear input-output relationship and a digital-to-analog converter (DAC2) having a nonlinear input-output relationship, the digital-to-analog converter (DAC1) outputs Y _DAC1 based on the linear input-output relationship, but the digital-to-analog converter (DAC2) outputs Y _DAC2 which is different from YD _AC1 because it has a nonlinear input-output relationship.

At this time, it can be assumed that the value of Y _DAC1 is greater than the value of Y _DAC2 , and the output values of the amplifier for Y _DAC1 and Y _DAC2 can be expressed as follows.

V _OUT1 = A(Y _DAC1 - V _REF )

V _OUT2 = A(Y _DAC2 - V _REF )

And, referring to FIG. 2b, if it is assumed that the analog-to-digital converter (ADC) operates ideally while the amplifier is connected to an ideal 2-bit analog-to-digital converter (ADC), the digital code converted by the analog-to-digital converter (ADC) of V _OUT1 amplified by passing through the linear digital-to-analog converter (DAC1) may be “10”, but the digital code converted by the analog-to-digital converter (ADC) of V _OUT2 amplified by passing through the nonlinear digital-to-analog converter (DAC2) may be “01”.

That is, even when the same digital code is input, there is a problem in which the output code of the analog-to-digital converter (ADC) changes due to the nonlinearity of the digital-to-analog converter (DAC), and accordingly, a problem occurs in which the same data is read with different output codes in the memory element.

To solve this problem, a circuit can be added to directly remove the non-ideality of the memory device due to the nonlinearity of the digital-to-analog converter, but this requires additional area within the memory device, thereby reducing the integration density of the memory device.

The present invention aims to solve all of the problems described above.

In addition, another object of the present invention is to provide a memory device capable of reducing the influence of nonlinearity of a digital-to-analog converter that causes errors when reading data recorded in a memory cell.

In addition, another object of the present invention is to provide a memory device capable of preventing non-ideality due to nonlinearity of a digital-to-analog converter without adding a separate circuit.

In addition, another object of the present invention is to provide a memory device that enables an analog-to-digital converter to read data recorded in a memory cell by reflecting the nonlinearity of the digital-to-analog converter.

In addition, another object of the present invention is to provide a memory device capable of accurately reading data of a memory cell regardless of the nonlinearity of a digital-to-analog converter.

According to one embodiment of the present invention for achieving the above object, a memory device including a memory cell storing n-bit data by operations of a word line and a bit line, comprising: an operational amplifier having a first inverting input terminal coupled to a first other end of a cell mode switch having a first end coupled to a bit line to which a memory cell is coupled, a first non-inverting input terminal coupled to a second other end of a precharge switch having a second end coupled to a precharge voltage terminal, and a feedback switch coupled between a first output terminal and the first inverting input terminal; a comparator having a second output terminal, a second inverting input terminal coupled to the second other end of the precharge switch, a second non-inverting input terminal coupled to a third other end of a sampling capacitor having a third end coupled to the first output terminal of the operational amplifier; A flip switch, the fourth side terminal of which is coupled between the first output terminal of the op amp and the third side terminal of the sampling capacitor, and the fourth side terminal of which is coupled to a flip voltage terminal; A sampling switch, the fifth side terminal of which is coupled between the third side terminal of the sampling capacitor and the second non-inverting input terminal of the comparator, and the fifth side terminal of which is coupled to a minimum level voltage terminal that provides a minimum level voltage, wherein the minimum level voltage is a first level voltage among a first level voltage to a 2^n level voltage that distinguishes n-bit data, and n is an integer greater than or equal to 1; (i) a first voltage generating unit including a first capacitor having a first one-side terminal coupled between the second other-side terminal of the precharge switch and the second inverting input terminal of the comparator, a first common switch having a first one-side terminal coupled to the first other-side terminal of the first capacitor and a first other-side terminal coupled to the precharge voltage terminal, a first positive switch having a first one-side terminal coupled to the first other-side terminal of the first capacitor and a first other-side terminal coupled to a maximum level voltage terminal providing a maximum level voltage, wherein the maximum level voltage is the 2^n level voltage, and a first negative switch having a first one-side terminal coupled to the first other-side terminal of the first capacitor and a first other-side terminal coupled to the minimum level voltage terminal; and (ii) between the second other-side terminal of the precharge switch and the second inverting input terminal of the comparator. An nth voltage generating unit including an nth capacitor having one end connected to the nth capacitor, an nth common switch having one end connected to the nth capacitor's other end and the nth common switch having the nth capacitor's other end connected to the precharge voltage terminal, an nth positive switch having one end connected to the nth capacitor's other end and the nth capacitor's other end connected to the maximum level voltage terminal, and an nth negative switch having one end connected to the nth capacitor's other end and the nth capacitor's other end connected to the minimum level voltage terminal; and a switch control unit controlling the first voltage generating unit to the nth voltage generating unit in response to output digital data output from the second output terminal of the comparator or n-bit input digital data input to write the n-bit data in the memory cell to generate an analog signal corresponding to the output digital data or the n-bit input digital data. A memory device including a is provided.

In the above embodiment, when k is an integer greater than or equal to 1 and less than or equal to n, the kth capacitance of the kth capacitor may be (the first capacitance of the first capacitor)/2^(k-1).

In the above embodiment, while the precharge switch maintains an enabled state and the first common switch to the nth common switch maintain an enabled state, the cell mode switch and the feedback switch may be enabled in conjunction with a first clock signal of a precharge clock cycle of the precharge mode so that the bit line is precharged by the precharge voltage, and the cell mode switch and the feedback switch may be disabled in conjunction with a second clock signal of the precharge clock cycle.

In the above embodiment, in a write mode for storing the n-bit data in the memory cell, in a state where the bit line is precharged, in conjunction with a first clock signal of a write mode clock cycle, the precharge switch is disabled, the cell mode switch, the feedback switch, and the memory cell are enabled, and by the switch control unit corresponding to the n-bit input data being input, when k is an integer greater than or equal to 1 and less than or equal to n, the k-th common switch of the k-th voltage generation unit is disabled, and one of the k-th positive switch and the k-th negative switch is enabled so that a specific level voltage corresponding to the n-bit input data generated by the first capacitor to the n-th capacitor is written to the memory cell, and in conjunction with a second clock signal of the write mode clock cycle, the precharge switch is enabled, the cell mode switch, the feedback switch, and the memory cell are disabled, and by the switch control unit, the k-th common switch of the k-th voltage generation unit is enabled. is enabled, and a switch among the k-th positive switch and the k-th negative switch that was enabled at the first clock signal of the light mode clock cycle can be disabled.

In the above embodiment, in a read mode for reading 1-bit data, which is the n-bit data written in the memory cell, in a state where the bit line is precharged, (i) in conjunction with a first clock signal of a first read mode clock cycle, the memory cell is enabled so that the bit line is charge-shared with the memory cell, in conjunction with a second clock signal of the first read mode clock cycle, the memory cell is disabled, the cell mode switch and the sampling switch are enabled so that the operational amplifier senses an output voltage, which is a difference between the precharge voltage applied through the first non-inverting input terminal and a specific level voltage written in the memory cell applied through the first inverting input terminal, through the first output terminal, and (ii) in conjunction with a first clock signal of a second read mode clock cycle, the cell mode switch and the sampling switch are disabled, and the flip switch is enabled so that the output voltage output through the first output terminal of the operational amplifier is the specific level voltage. (iii) in conjunction with a third read mode clock cycle, one of the first positive switch and the first negative switch of the first voltage generation unit is enabled by the switch control unit corresponding to the 1-bit data output from the second output terminal of the comparator so as to be flipped, and the comparator is enabled to output the 1-bit data obtained by comparing the first reference voltage, which is the precharge voltage applied through the second inverting input terminal, with the specific level voltage applied through the second non-inverting input terminal, and the second clock switch of the second read mode clock cycle, the comparator, and the flip switch are disabled, and (iv) in conjunction with the third read mode clock cycle, one of the first positive switch and the first negative switch of the first voltage generation unit is enabled by the switch control unit corresponding to the 1-bit data output from the second output terminal of the comparator so that the specific level voltage can be regenerated by the first capacitor.

In the above embodiment, in a read mode for reading 2-bit data, which is the n-bit data written in the memory cell, in a state where the bit line is precharged, (i) in conjunction with a first clock signal of a first read mode clock cycle, the memory cell is enabled so that the bit line is charge-shared with the memory cell, in conjunction with a second clock signal of the first read mode clock cycle, the memory cell is disabled, the cell mode switch and the sampling switch are enabled so that the operational amplifier senses the difference between the precharge voltage applied through the first non-inverting input terminal and the specific level voltage written in the memory cell applied through the first inverting input terminal, and outputs an output voltage through the first output terminal of the operational amplifier, (ii) (ii_1) in conjunction with a first clock signal of a second read mode clock cycle, the cell mode switch and the sampling switch are disabled, and the flip switch is enabled so that the output voltage output through the first output terminal of the operational amplifier is The first voltage generator is configured to output first-priority bit data obtained by comparing a first reference voltage, which is the precharge voltage, which is applied through the second inverting input terminal, with the specific level voltage applied through the second non-inverting input terminal, and, in conjunction with a second clock signal of the second read mode clock cycle, the precharge switch, the first common switch of the first voltage generator, and the comparator are disabled, and (ii_2) in conjunction with a first clock signal of a third read mode clock cycle, one of the first positive switch and the first negative switch of the first voltage generator is enabled by the switch control unit corresponding to the first-priority bit data output from the second output terminal of the comparator, so as to generate a second reference voltage by the first capacitor and the second capacitor, and the comparator is enabled to output the second reference voltage applied through the second inverting input terminal and the second non-inverting input terminal. The second priority bit data, which is obtained by comparing the applied specific level voltage, is output through the second output terminal, and in conjunction with the second clock signal of the third read mode clock cycle, the second common switch of the second voltage generation unit, the comparator, and the flip switch are disabled, and (iii) in conjunction with the fourth read mode clock cycle, one of the second positive switch and the second negative switch of the second voltage generation unit is enabled by the switch control unit corresponding to the second priority bit data output from the second output terminal of the comparator, so that the specific level voltage can be regenerated by the first capacitor and the second capacitor.

In the above embodiment, in a read mode for reading the n-bit data of 3 or more bits written in the memory cell, in a state where the bit line is precharged, (i) in conjunction with a first clock signal of a first read mode clock cycle, the memory cell is enabled so that the bit line is charge-shared with the memory cell, in conjunction with a second clock signal of the first read mode clock cycle, the memory cell is disabled, the cell mode switch and the sampling switch are enabled so that the operational amplifier senses an output voltage between the precharge voltage applied through the first non-inverting input terminal and a specific level voltage written in the memory cell applied through the first inverting input terminal, and outputs the output voltage through the first output terminal of the operational amplifier, (ii) (ii_1) in conjunction with a first clock signal of a second read mode clock cycle, the cell mode switch and the sampling switch are disabled, and the flip switch is enabled so that the output voltage output through the first output terminal of the operational amplifier is The comparator is enabled to output first priority bit data by comparing a first reference voltage, which is the precharge voltage applied through the second inverting input terminal, with the specific level voltage applied through the second non-inverting input terminal, and in conjunction with a second clock signal of the second read mode clock cycle, the precharge switch, the first common switch of the first voltage generation unit, and the comparator are disabled, and (ii_2) when j is an integer greater than or equal to 2 and less than or equal to (n-1), in conjunction with a first clock signal of the (j+1)-th read mode clock cycle, one of the (j-1)-th positive switch and the (j-1)-th negative switch of the (j-1)-th voltage generation unit is enabled by the switch control unit corresponding to the (j-1)-th priority bit data output from the second output terminal of the comparator to generate a j-th reference voltage by the first capacitor to the n-th capacitor, and the comparator The jth reference voltage applied through the second inverting input terminal is compared with the specific level voltage applied through the second non-inverting input terminal, and the jth common switch of the jth voltage generation unit and the comparator are disabled in conjunction with the second clock signal of the (j+1)th read mode clock cycle, (ii_3) in conjunction with the first clock signal of the (n+1)th read mode clock cycle, one of the (n-1)th positive switch and the (n-1)th negative switch of the (n-1)th voltage generation unit is enabled by the switch control unit corresponding to the (n-1)th rank bit data output from the second output terminal of the comparator to generate the nth reference voltage by the first capacitor to the nth capacitor, and the comparator is enabled to compare the nth reference voltage applied through the second inverting input terminal with the second non-inverting input terminal. The nth order bit data compared with the specific level voltage applied through the input terminal is output through the second output terminal, and in conjunction with the second clock signal of the (n+1)th read mode clock cycle, the nth common switch, the comparator, and the flip switch of the nth voltage generation unit are disabled, and (iii) in conjunction with the (n+2)th read mode clock cycle, one of the nth positive switch and the nth negative switch of the nth voltage generation unit is enabled by the switch control unit corresponding to the nth bit data output from the second output terminal of the comparator, so that the specific level voltage can be regenerated by the first capacitor to the nth capacitor.

In the above embodiment, in a state where the specific level voltage is regenerated by the first capacitor to the nth capacitor, in the refresh mode of the memory cell, in response to a first clock signal of the refresh mode clock cycle, the memory cell, the cell mode switch, and the feedback switch are enabled so that the specific level voltage regenerated by the first capacitor to the nth capacitor is written to the memory cell, and in response to a second clock signal of the refresh mode clock cycle, among the k-th positive switch and the k-th negative switch of the k-th voltage generation unit, a switch that maintains an enabled state at the time of the first clock signal of the refresh mode clock cycle, the memory cell, the cell mode switch, and the feedback switch are disabled, and the precharge switch and the k-th common switch of the k-th voltage generation unit can be enabled.

In the above embodiment, the memory cell can be enabled and maintained in an enabled state in conjunction with a first clock signal of the first read mode clock cycle, and can be disabled in conjunction with a second clock signal of the refresh mode clock cycle.

According to another embodiment of the present invention, a memory device including a memory cell storing n-bit data by operations of a word line and a bit line, comprising: an operational amplifier having a first inverting input terminal coupled to a first other end of a cell mode switch having a first end coupled to a bit line to which a memory cell is coupled, a first non-inverting input terminal coupled to a second other end of a precharge switch having a second end coupled to a precharge voltage terminal, and a feedback capacitor and a feedback switch coupled in parallel between a first output terminal and the first inverting input terminal; a comparator having a second inverting input terminal coupled to the second other end of the precharge switch, a second non-inverting input terminal coupled to a third other end of a sampling capacitor having a third end coupled to the first output terminal of the operational amplifier, and a second output terminal; A flip switch, the fourth side terminal of which is coupled between the first output terminal of the op amp and the third side terminal of the sampling capacitor, and the fourth side terminal is coupled to a flip voltage terminal; A sampling switch, the fifth side terminal of which is coupled between the third side terminal of the sampling capacitor and the second non-inverting input terminal of the comparator, and the fifth side terminal is coupled to a minimum level voltage terminal that provides a minimum level voltage, wherein the minimum level voltage is a first level voltage among a first level voltage to a 2^n level voltage that distinguishes n-bit data, and n is an integer greater than or equal to 1; (i) a first voltage generating unit including a first capacitor having a first one-side terminal coupled between the second other-side terminal of the precharge switch and the second inverting input terminal of the comparator, a first common switch having a first one-side terminal coupled to the first other-side terminal of the first capacitor and a first other-side terminal coupled to the precharge voltage terminal, a first positive switch having a first one-side terminal coupled to the first other-side terminal of the first capacitor and a first other-side terminal coupled to a maximum level voltage terminal providing a maximum level voltage, wherein the maximum level voltage is the 2^n level voltage, and a first negative switch having a first one-side terminal coupled to the first other-side terminal of the first capacitor and a first other-side terminal coupled to the minimum level voltage terminal; and (ii) between the second other-side terminal of the precharge switch and the second inverting input terminal of the comparator. An nth voltage generating unit including an nth capacitor having one end connected to the nth capacitor, an nth common switch having one end connected to the nth capacitor's other end and the nth common switch having the nth capacitor's other end connected to the precharge voltage terminal, an nth positive switch having one end connected to the nth capacitor's other end and the nth capacitor's other end connected to the maximum level voltage terminal, and an nth negative switch having one end connected to the nth capacitor's other end and the nth capacitor's other end connected to the minimum level voltage terminal; and a switch control unit controlling the first voltage generating unit to the nth voltage generating unit in response to output digital data output from the second output terminal of the comparator or n-bit input digital data input to write n-bit data in the memory cell to generate an analog signal corresponding to the output digital data or the n-bit input digital data. A memory device including a is provided.

In the above embodiment, when k is an integer greater than or equal to 1 and less than or equal to n, the kth capacitance of the kth capacitor may be (the first capacitance of the first capacitor)/2^(k-1).

In the above embodiment, while the precharge switch maintains an enabled state and the first common switch to the nth common switch maintain an enabled state, the cell mode switch and the feedback switch may be enabled in conjunction with a first clock signal of a precharge clock cycle of the precharge mode so that the bit line is precharged by the precharge voltage, and the cell mode switch and the feedback switch may be disabled in conjunction with a second clock signal of the precharge clock cycle.

In the above embodiment, in a write mode for storing the n-bit data in the memory cell, in a state where the bit line is precharged, in conjunction with a first clock signal of a write mode clock cycle, the precharge switch is disabled, the cell mode switch, the feedback switch, and the memory cell are enabled, and by the switch control unit corresponding to the n-bit input data being input, when k is an integer greater than or equal to 1 and less than or equal to n, the k-th common switch of the k-th voltage generation unit is disabled, and one of the k-th positive switch and the k-th negative switch is enabled so that a specific level voltage corresponding to the n-bit input data generated by the first capacitor to the n-th capacitor is written to the memory cell, and in conjunction with a second clock signal of the write mode clock cycle, the precharge switch is enabled, the cell mode switch, the feedback switch, and the memory cell are disabled, and by the switch control unit, the k-th common switch of the k-th voltage generation unit is enabled. is enabled, and a switch among the k-th positive switch and the k-th negative switch that was enabled at the first clock signal of the light mode clock cycle can be disabled.

In the above embodiment, in a read mode for reading 1-bit data, which is the n-bit data written in the memory cell, in a state where the bit line is precharged, (i) in conjunction with a first clock signal and a second clock signal of a first read mode clock cycle, the memory cell, the cell mode switch, and the sampling switch are enabled so that the operational amplifier outputs an output voltage, which senses a specific voltage level stored in the memory cell through capacitive feedback via the feedback capacitor, through the first output terminal, (ii) in conjunction with a first clock signal of a second read mode clock cycle, the memory cell, the cell mode switch, and the sampling switch are disabled, and the flip switch is enabled so that the output voltage output through the first output terminal of the operational amplifier is flipped to the specific level voltage, and the comparator is enabled so that the first reference voltage, which is the precharge voltage applied through the second inverting input terminal, and the specific level voltage applied through the second non-inverting input terminal are The compared 1-bit data is output, and in conjunction with a second clock signal of the second read mode clock cycle, the precharge switch, the first common switch of the first voltage generation unit, the comparator, and the flip switch are disabled, and (iii) in conjunction with a third read mode clock cycle, one of the first positive switch and the first negative switch of the first voltage generation unit is enabled by the switch control unit corresponding to the 1-bit data output from the second output terminal of the comparator, so that the specific level voltage can be regenerated by the first capacitor.

In the above embodiment, in a read mode for reading 2-bit data, which is the n-bit data written in the memory cell, in a state where the bit line is precharged, (i) in conjunction with a first clock signal and a second clock signal of a first read mode clock cycle, the memory cell, the cell mode switch, and the sampling switch are enabled so that the operational amplifier outputs an output voltage, which senses a specific voltage level stored in the memory cell through capacitive feedback via the feedback capacitor, through the first output terminal, (ii) in conjunction with a first clock signal of a second read mode clock cycle, the memory cell, the cell mode switch, and the sampling switch are disabled, and the flip switch is enabled so that the output voltage output through the first output terminal of the operational amplifier is flipped to the specific level voltage, and the comparator is enabled so that the first reference voltage, which is the precharge voltage applied through the second inverting input terminal, and the second reference voltage, which is the non-inverting input terminal, are applied. (ii_2) In conjunction with the first clock signal of the third read mode clock cycle, one of the first positive switch and the first negative switch of the first voltage generation unit is enabled by the switch control unit corresponding to the first priority bit data output from the second output terminal of the comparator to generate a second reference voltage by the first capacitor and the second capacitor, and the comparator is enabled to output second priority bit data obtained by comparing the second reference voltage applied through the second inverting input terminal with the specific level voltage applied through the second non-inverting input terminal, and in conjunction with the second clock signal of the third read mode clock cycle, the second common switch of the second voltage generation unit, The above comparator and the flip switch are disabled, and (iii) in conjunction with the fourth read mode clock cycle, one of the second positive switch and the second negative switch of the second voltage generation unit is enabled by the switch control unit corresponding to the second priority bit data output from the second output terminal of the comparator, so that the specific level voltage can be regenerated by the first capacitor and the second capacitor.

In the above embodiment, in a read mode for reading the n-bit data of 3 or more bits written in the memory cell, in a state where the bit line is precharged, (i) in conjunction with a first clock signal and a second clock signal of a first read mode clock cycle, the memory cell, the cell mode switch, and the sampling switch are enabled so that the operational amplifier outputs an output voltage sensed to a specific voltage level stored in the memory cell through capacitive feedback via the feedback capacitor through the first output terminal, (ii) (ii_1) in conjunction with a first clock signal of a second read mode clock cycle, the memory cell, the cell mode switch, and the sampling switch are disabled, and the flip switch is enabled so that the output voltage outputted through the first output terminal of the operational amplifier is flipped to the specific level voltage, and the comparator is enabled so that a first reference voltage, which is the precharge voltage applied through the second inverting input terminal, and the second reference voltage, which is the voltage applied through the second non-inverting input terminal, are sensed. The first priority bit data that is obtained by comparing a specific level voltage is output, and in conjunction with the second clock signal of the second read mode clock cycle, the precharge switch, the first common switch of the first voltage generation unit, and the comparator are disabled, and (ii_2) when j is an integer greater than or equal to 2 and less than or equal to (n-1), in conjunction with the first clock signal of the (j+1)-th read mode clock cycle, one of the (j-1) positive switch and the (j-1) negative switch of the (j-1) voltage generation unit is enabled by the switch control unit corresponding to the (j-1)-th priority bit data output from the second output terminal of the comparator, so that the j-th reference voltage is generated by the first capacitor to the n-th capacitor, and the j-th reference voltage applied through the second inverting input terminal and the specific level voltage applied through the second non-inverting input terminal are compared, and the comparator is enabled, and the j-th priority bit data is output through the second output terminal. (ii_3) in conjunction with the first clock signal of the (n+1)-th read mode clock cycle, one of the (n-1)-th positive switch and the (n-1)-th negative switch of the (n-1)-th voltage generation unit is enabled by the switch control unit corresponding to the (n-1)-th rank bit data output from the second output terminal of the comparator to generate an n-th reference voltage by the first capacitor to the n-th capacitor, and the comparator is enabled to compare the n-th reference voltage applied through the second inverting input terminal with the specific level voltage applied through the second non-inverting input terminal, and in conjunction with the second clock signal of the (n+1)-th read mode clock cycle, the n-th voltage The nth common switch of the generation unit, the comparator, and the flip switch are disabled, and (iii) in conjunction with the (n+2)th read mode clock cycle, one of the nth positive switch and the nth negative switch of the nth voltage generation unit is enabled by the switch control unit corresponding to the nth bit data output from the second output terminal of the comparator, so that the specific level voltage can be regenerated by the first capacitor to the nth capacitor.

In the above embodiment, in a state where the specific level voltage is regenerated by the first capacitor to the nth capacitor, in the refresh mode of the memory cell, in response to a first clock signal of the refresh mode clock cycle, the memory cell, the cell mode switch, and the feedback switch are enabled so that the specific level voltage regenerated by the first capacitor to the nth capacitor is written to the memory cell, and in response to a second clock signal of the refresh mode clock cycle, among the k-th positive switch and the k-th negative switch of the k-th voltage generation unit, a switch that maintains an enabled state at the time of the first clock signal of the refresh mode clock cycle, the memory cell, the cell mode switch, and the feedback switch are disabled, and the precharge switch and the k-th common switch of the k-th voltage generation unit can be enabled.

In the above embodiment, the memory cell can be enabled and maintained in an enabled state in conjunction with a first clock signal of the first read mode clock cycle, and can be disabled in conjunction with a second clock signal of the refresh mode clock cycle.

According to the present invention, the following effects are achieved.

The present invention can reduce the influence of nonlinearity of a digital-to-analog converter that causes errors when reading data written in a memory cell.

The present invention can prevent non-ideality due to nonlinearity of a digital-to-analog converter without adding a separate circuit.

The present invention reflects the nonlinearity of a digital-to-analog converter so that the analog-to-digital converter can read data recorded in a memory cell.

The present invention enables accurate reading of data from a memory cell regardless of the nonlinearity of a digital-to-analog converter.

Figure 1 schematically illustrates a conventional memory device.

Figure 2a schematically illustrates a case where a code applied to a digital-to-analog converter having a linear input-output relationship and a digital-to-analog converter having a nonlinear input-output relationship are amplified by the same amplifier, and Figure 2b schematically illustrates a relationship between the input and output of a 2-bit analog-to-digital converter.

FIG. 3 schematically illustrates a memory device according to one embodiment of the present invention.

FIG. 4 schematically illustrates a timing diagram of a memory device according to one embodiment of the present invention.

FIG. 5 schematically illustrates a state of generating level voltages according to 2-bit data in a memory device according to one embodiment of the present invention.

FIG. 6 schematically illustrates a state in which 2-bit data written to a memory cell is read in a memory device according to one embodiment of the present invention.

FIG. 7 schematically illustrates a memory device according to another embodiment of the present invention.

FIG. 8 schematically illustrates a timing diagram of a memory device according to another embodiment of the present invention.

The detailed description of the present invention set forth below refers to the accompanying drawings which illustrate specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention, while different from one another, are not necessarily mutually exclusive. For example, specific shapes, structures, and features described herein may be implemented in other embodiments without departing from the spirit and scope of the invention. It should also be understood that the positions or arrangements of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. Accordingly, the following detailed description is not intended to be limiting, and the scope of the invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if any. Like reference numerals in the drawings designate the same or similar functionality throughout the several aspects.

Hereinafter, in order to enable those skilled in the art to easily practice the present invention, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. A memory device according to the present invention may be any one of random access memories (RAMs) including DRAM (Dynamic Random Access Memory), SDRAM (Synchronous DRAM), SRAM (Static RAM), DDR SDRAM (Double Date Rate SDRAM), DDR2 SDRAM, DDR3 SDRAM, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), etc., and the following description will focus on DRAM. In addition, a memory cell includes a switching element that is switched by a word line signal and a cell capacitor that stores a charge, but for convenience of explanation, the cell capacitor may also be referred to as a memory cell. Also, although the memory device includes multiple bit lines, multiple word lines, and multiple memory cells, for convenience of explanation, the explanation will be based on one bit line, one word line, and one memory cell.

FIG. 3 schematically illustrates a memory device according to one embodiment of the present invention.

Referring to FIG. 3, according to a memory device (100) according to one embodiment of the present invention, a memory cell (110) including a cell switch (SW_WL) and a cell capacitor (Co) enabled by a word line (not shown) can be coupled to a bit line (BL).

And, according to a memory device (100) according to one embodiment of the present invention, an operational amplifier (120) has a first inverting input terminal coupled to a first other end of a cell mode switch (SW_MODE) having a first one end coupled to a bit line (BL) to which a memory cell (110) is coupled, a first non-inverting input terminal coupled to a second other end of a precharge switch (SW_VM) having a second one end coupled to a precharge voltage terminal (V _M ), and a feedback switch (SW_NFB) coupled between the first output terminal and the first inverting input terminal.

At this time, the precharge voltage (V _M ) may be an average voltage of the first level voltage, which is the minimum level voltage, and the second level voltage, which is the maximum level voltage, among the first level voltage to the second level voltage that distinguish n-bit data, and n may be an integer greater than or equal to 1.

And, according to a memory device (100) according to one embodiment of the present invention, a comparator (130) may have a second inverting input terminal coupled to a second other-side terminal of a precharge switch (SW_VM), a second non-inverting input terminal coupled to a third other-side terminal of a sampling capacitor (Cs) having a third one-side terminal coupled to a first output terminal of an operational amplifier (120), and a second output terminal.

In addition, according to a memory device (100) according to one embodiment of the present invention, a flip switch (SW_FLIP) may have a fourth side terminal coupled between the first output terminal of the operational amplifier (110) and the sampling capacitor (Cs), and a fourth other side terminal coupled to a flip voltage terminal (V _FLIP ).

And, according to a memory device (100) according to one embodiment of the present invention, a sampling switch (SW_SAMPLE) may have a fifth side terminal coupled between a third side terminal of a sampling capacitor (Cs) and a second non-inverting input terminal of a comparator (130), and a fifth side terminal coupled to a minimum level voltage terminal (V _SS ).

In addition, according to a memory device (100) according to one embodiment of the present invention, a first capacitor (C1) having a first one-side terminal coupled between a second other-side terminal of a precharge switch (SW_VM) and a second inverting input terminal of a comparator (130), a first common switch (S_1) having a first one-side terminal coupled to the first other-side terminal of the first capacitor (C1) and the first other-side terminal coupled to a precharge voltage terminal (V _M ), a first positive switch (SP_1) having a first one-side terminal coupled to the first other-side terminal of the first capacitor (C1) and the first other-side terminal coupled to a maximum level voltage terminal (V _DD ) that provides a maximum level voltage, and a first capacitor (C1) having a first one-side terminal coupled to the first other-side terminal of the first capacitor (C1) and the first other-side terminal coupled to a minimum level voltage terminal (V _SS ). An nth capacitor (Cn) having an n_1-th one-side terminal coupled between a first voltage generating unit (140_1) including a negative switch (SN_1) and a second other-side terminal of a precharge switch (SW_VM) and a second inverting input terminal of a comparator (130), an nth common switch (S_n) having an n_2-th one-side terminal coupled to the n_1-th other-side terminal of the nth capacitor (Cn) and the n_2-th other-side terminal coupled to a precharge voltage terminal (V _M ), an nth positive switch (SP_n) having an n_3-th one-side terminal coupled to the n_1-th other-side terminal of the nth capacitor (Cn) and the n_3-th other-side terminal coupled to a maximum level voltage terminal (V _DD ), and an nth negative having an n_4-th one-side terminal coupled to the n1-th other-side terminal of the nth capacitor (Cn) and the n_4-th other-side terminal coupled to a minimum level voltage terminal (V _SS ) An nth voltage generating unit (140_n) including a switch (SN_n) can be formed.

At this time, when k is an integer greater than or equal to 1 and less than or equal to n, the kth capacitance of the kth capacitor can be (the first capacitance of the first capacitor)/2^(k-1).

And, according to the memory device (100) according to one embodiment of the present invention, a switch control unit (150) may be formed to control the first voltage generation unit (140_1) to the n-th voltage generation unit (140_n) in response to the output digital data output from the second output terminal of the comparator (130) or the n-bit input digital data input to write n-bit data into the memory cell (110) to generate an analog signal corresponding to the output digital data or the n-bit input digital data. At this time, the switch control unit (150) may include a logic circuit (Logic) that determines a specific voltage generation unit to be controlled in response to the output digital data output from the second output terminal of the comparator (130), and a MUX that transmits a control signal to the first voltage generation unit (140_1) to the n-th voltage generation unit (140_n) in response to the input digital data.

The operation process of another memory device (100) according to one embodiment of the present invention configured as described above will be described using the timing diagram of FIG. 4 as follows. The memory device (100) operates in response to a clock (CLK) frequency, and each clock cycle has two signals. The operation states of the switches of the memory device (100) can be set in various ways according to the signals of the clock cycle. However, in the following description, it is assumed that the first clock signal corresponds to “logic high” and the second clock signal corresponds to “logic low.”

First, in the precharge mode (PCG) of the memory cell (110) for precharging the bit line (BL), while the precharge switch (SW_VM) maintains an enabled state and the first common switch (S_1) to the nth common switch (S_n) maintain an enabled state, the cell mode switch (SW_MODE) and the feedback switch (SW_NFB) are enabled in conjunction with the first clock signal of the precharge clock cycle of the precharge mode (PCG), so that the bit line (BL) can be precharged by the precharge voltage (V _M ).

Meanwhile, the generated voltage (V _T1 ) generated by the first voltage generator (140_1) to the nth voltage generator (140_n) can be expressed as follows.

At this time, the voltage applied to the first capacitor (C1) of the first voltage generating unit (140_1) to the nth capacitor (Cn) of the nth voltage generating unit (140_n) is a precharge voltage (V _M ), so the generated voltage (V _T1 ) generated by the first voltage generating unit (140_1) to the nth voltage generating unit (140_n) in the precharge mode clock cycle can be the precharge voltage (V _M ).

Accordingly, since the precharge voltage (V _M ) is applied to the first non-inverting input terminal of the op-amp (120), the output voltage (V _OUT1 ) output through the first output terminal of the op-amp (120) becomes the precharge voltage (V _M ), and accordingly, the bit line (BL) can be precharged by the precharge voltage (V _M ), which is the output voltage of the op-amp (120), according to the negative feedback of the op-amp (120) by the feedback switch (SW_NFB).

At this time, the parasitic capacitor (C _P ) of the bit line (BL) is charged with the precharge voltage (V _M ), which is the output voltage of the op-amp (120), and accordingly, the amount of charge (Q _P ) stored in the parasitic capacitor (C _P ) can be expressed as follows.

Afterwards, the cell mode switch (SW_MODE) and the feedback switch (SW_NFB) can be disabled in conjunction with the second clock signal of the precharge clock cycle.

Next, in the write mode (WRITE) of the memory cell (110) for storing n-bit data in the memory cell (110) through the bit line (BL) precharged by the precharge voltage (V _M ), in conjunction with the first clock signal of the write mode clock cycle, the precharge switch (SW_VM) is disabled, the cell mode switch (SW_MODE), the feedback switch (SW_NFB), and the memory cell (110) are enabled, and by the switch control unit (150) corresponding to the input n-bit input data (D _IN ), when k is an integer greater than or equal to 1 and less than or equal to n, the k-th common switch (S_1 to S_n) of the k-th voltage generation unit is disabled, and one of the k-th positive switch and the k-th negative switch (SX_1 to SX_n) is enabled to store n-bit input data generated by the first capacitor (C1) to the n-th capacitor (Cn). A corresponding specific level voltage can be written to the memory cell (110). At this time, the memory cell (110) can be enabled by enabling the cell switch (SW_WL) by the word line.

Meanwhile, the generated voltage (V _T2 ) generated by the first voltage generator (140_1) to the nth voltage generator (140_n) can be expressed as follows.

At this time, since the capacitance of the kth capacitor, which is one of the first capacitor (C1) to the nth capacitor (Cn), is C ₁ /2^(n-1), the generated voltage (V _T2 ) generated by the first voltage generating unit (140_1) to the nth voltage generating unit (140_n) can be expressed as follows.

And, since the switch control unit (150) enables one of the k-th positive switch and the k-th negative switch (SX_1 to SX_n) of the k-th voltage generation unit (140_1 to 140_n) in response to the k-th rank bit data in the n-bit data, each of the voltages (V ₁ to V _n ) applied to each of the first capacitor (C1) to the n-th capacitor (Cn) can be one of the minimum level voltage (V _SS ) and the maximum level voltage (V _DD ). For example, when the k-th rank bit data is “1”, the k-th positive switch can be enabled, and when the k-th rank bit data is “0”, the k-th negative switch can be enabled.

Accordingly, the first voltage generating unit (140_1) to the n-th voltage generating unit (140_n) can generate a specific level voltage (V _T2 ) corresponding to n-bit input data (D _IN ) to be written to the memory cell (110) among the first level voltage to the second^n-th level voltage that distinguishes n-bit data.

For example, referring to Fig. 5, the following explanation is given based on 2-bit data. At this time, the minimum level voltage (V _SS ) is assumed to be the ground voltage.

The generated voltage (VT) generated by the first voltage generator and the second voltage generator corresponding to 2-bit data can be expressed as follows.

가 되며, 도 5의 (c)에서와 같이 제1 전압 생성부의 제1 포지티브 스위치(SP_1)이 인에이블되고 제2 전압 생성부의 제2 네거티브 스위치(SN_2)가 인에이블될 경우에는 생성 전압(VT)은

가 되며, 도 5의 (d)에서와 같이 제1 전압 생성부의 제1 포지티브 스위치(SP_1)가 인에이블되고 제2 전압 생성부의 제2 포지티브 스위치(SP_2)가 인에이블될 경우에는 생성 전압(V_T)은 V_DD이 될 수 있다. 따라서, 제1 전압 생성부와 제2 전압 생성부를 통해, 2비트 데이터의 코드인 “00”, “01”, “10”, 및 “11”을 나타내는 4개의 레벨 전압인 V_SS,

,

, 및 V_DD를 생성할 수 있게 된다.Therefore, when the first negative switch (SN_1) of the first voltage generator is enabled and the second negative switch (SN_2) of the second voltage generator is enabled as in (a) of Fig. 5, the generated voltage (V _T ) becomes V _SS , and when the first negative switch (SN_1) of the first voltage generator is enabled and the second positive switch (SP_2) of the second voltage generator is enabled as in (b) of Fig. 5, the generated voltage (VT ) becomes

, and when the first positive switch (SP_1) of the first voltage generation unit is enabled and the second negative switch (SN_2) of the second voltage generation unit is enabled, as in (c) of Fig. 5, the generated voltage (VT) is

, and when the first positive switch (SP_1) of the first voltage generation unit is enabled and the second positive switch (SP_2) of the second voltage generation unit is enabled as in (d) of Fig. 5, the generated voltage (V _T ) can be V _DD . Accordingly, through the first voltage generation unit and the second voltage generation unit, four level voltages, V _SS , representing the codes of 2-bit data, “00”, “01”, “10”, and “11”, are generated.

,

, and V _DD can be generated.

Again, referring to FIGS. 3 and 4, a specific level voltage (V _T2 ) generated from the first voltage generating unit (140_1) to the nth voltage generating unit (140_n) is applied to the first non-inverting input terminal of the operational amplifier (120).

Accordingly, the output voltage (V _OUT2 ) output through the first output terminal of the operational amplifier (120) becomes a specific level voltage (V _T2 ), and according to the negative feedback of the operational amplifier (120), the specific level voltage (V _T2 ), which is the output voltage of the operational amplifier (120), is applied to the precharged bit line (BL), thereby charging the cell capacitor (Co) with a charge corresponding to the specific level voltage (V _T2 ).

At this time, the amount of charge (Q _O ) stored in the cell capacitor (C _O ) can be expressed as follows.

After writing data to the memory cell (C _O ) in this way, the total charge (Q ₁ ) stored in the cell capacitor (C _O ) and the parasitic capacitor (C _P ) can be expressed as follows.

Thereafter, in conjunction with the second clock signal of the light mode clock cycle, the precharge switch (SW_VM) is enabled, the cell mode switch (SW_MODE), the feedback switch (SW_NFB), and the memory cell (110) are disabled, and the kth common switch (S_1 to S_n) of the kth voltage generation unit (140_1 to 140_n) is enabled by the switch control unit (150), and among the kth positive switch and the kth negative switch, the switches (SX_1 to SX_n) that were enabled at the first clock signal of the light mode clock cycle can be disabled.

Next, the operation process in the read mode (READ) for reading n-bit data written in the memory cell (110) while the bit line (BL) is precharged is described as follows. At this time, it is assumed that a specific level voltage (V _T2 ) input in the write mode is stored in the cell capacitor (Co).

First, the memory cell (110) is enabled by enabling the cell switch (SW_WL) by the word line in conjunction with the first clock signal of the first read mode clock cycle (AMPLIFY), and accordingly, the bit line (BL) can be charge-shared with the memory cell (110).

At this time, a sharing voltage (V _sharing ) is generated in the bit line (BL) by charge sharing between the cell capacitor (Co) and the parasitic capacitor (Cp), and the sharing voltage (V _sharing ) generated in the bit line (BL) can be expressed as follows.

And, in conjunction with the second clock signal of the first read mode clock cycle (AMPLIFY), the memory cell (110) is disabled, and the cell mode switch (SW_MODE) and the sampling switch (SW_SAMPLE) are enabled so that the op amp (120) can sense the difference between the precharge voltage applied through the first non-inverting input terminal and the specific level voltage recorded in the memory cell applied through the first inverting input terminal and output the output voltage through the first output terminal.

At this time, a precharge voltage (V _M ) is applied to the first non-inverting input terminal of the operational amplifier (120), and a sharing voltage (V _sharing ) of the bit line (BL) is applied to the first inverting input terminal of the operational amplifier (120).

Therefore, the output voltage (V _OUT3 ) output from the first output terminal of the op-amp (120) can be expressed as follows.

At this time, the output voltage (V _OUT3 ) of the operational amplifier (120) can be stored in the sampling capacitor (C _S ) by the minimum level voltage (V _SS ) supplied according to the enable of the sampling switch (SW_SAMPLE).

Thereafter, in conjunction with the first clock signal of the second read mode clock cycle (MSB), the cell mode switch (SW_MODE) and the sampling switch (SW_SAMPLE) are disabled, and the flip switch (SW_FLIP) is enabled so that the output voltage (V _OUT3 ) output through the first output terminal of the operational amplifier (120) is flipped to a specific level voltage (V _T2 ), and the comparator (130) is enabled so that the first priority bit data is output by comparing the first reference voltage, which is the precharge voltage (V _M ), applied through the second inverting input terminal with the specific level voltage (V _T2 ) applied through the second non-inverting input terminal.

에 비하여 상대적으로 높은 값을 가지므로, 오피 앰프(120)의 출력 전압(V_OUT3)은

와 같이 나타낼 수 있으며, 이 출력 전압(V_OUT3)이 그대로 비교기(130)에 인가되어 디지털 코드로 변환되면, 이후에 설명되는 리제너레이션에서 출력 전압(V_OUT3)이 그대로 재생성되며, 이를 이용하여 리프레시를 수행할 경우, 최초 기록한 메모리 셀(110)의 특정 레벨 전압(V_T2)과는 다른 전압이 리프레시에 의해 메모리 셀(110)에 기록될 수 있다.At this time, the amplification factor (A) of the op-amp (120) is

Since it has a relatively high value compared to the op-amp (120), the output voltage (V _OUT3 ) of the op-amp (120)

It can be expressed as follows, and when this output voltage (V _OUT3 ) is applied as it is to the comparator (130) and converted into a digital code, the output voltage (V _OUT3 ) is regenerated as it is in the regeneration described later, and when a refresh is performed using this, a voltage different from the specific level voltage (V _T2 ) of the initially recorded memory cell (110) can be written to the memory cell (110) by the refresh.

Therefore, to prevent this, the flip switch (SW_FLIP) is enabled to supply a flip voltage (V _FLIP ) so that the output voltage of the op-amp (120) stored in the sampling capacitor (C _S ) can be flipped to a specific level voltage (V _T2 ).

이 저장된 상태에서, 샘플링 캐패시터(C_S)의 제3 일측단에 플립 전압(V_FLIP)이 인가되면, 샘플링 캐패시터(C_S)의 제3 타측단에는 전압

이 생성되므로, 플립 전압(V_FLIP)을 적정한 값으로 설정함으로써 샘플링 캐패시터(C_S)의 제3 타측단에 메모리 셀(110)에 기록한 것과 동일한 특정 레벨 전압

이 생성되도록 할 수 있다.That is, the output voltage of the op-amp (120) to the sampling capacitor (C _S ).

In this stored state, when a flip voltage (V _FLIP ) is applied to the third terminal of the sampling capacitor (C _S ), a voltage is applied to the third terminal of the sampling capacitor (C _S ).

Since this is generated, by setting the flip voltage (V _FLIP ) to an appropriate value, a specific level voltage identical to that recorded in the memory cell (110) is generated at the third terminal of the sampling capacitor (C _S ).

This can be created.

And, in conjunction with the second clock signal of the second read mode clock cycle (MSB), the precharge switch (SW_VM), the first common switch (S_1) of the first voltage generator (140_1), and the comparator (130) can be disabled.

Thereafter, when j is an integer greater than or equal to 2 and less than or equal to (n-1), in conjunction with the first clock signal of the (j+1)-th read mode clock cycle, one of the (j-1)-th positive switch and the (j-1)-th negative switch of the (j-1)-th voltage generation unit is enabled by the switch control unit (150) corresponding to the (j-1)-th rank bit data output from the second output terminal of the comparator (130) to generate the j-th reference voltage by the first capacitor (C1) to the n-th capacitor (Cn), and the comparator (130) is enabled to compare the j-th reference voltage applied through the second inverting input terminal with the specific level voltage (V _T2 ) applied through the second non-inverting input terminal, so that the j-th rank bit data is output through the second output terminal, and in conjunction with the second clock signal of the (j+1)-th read mode clock cycle, the j-th common switch of the j-th voltage generation unit and The comparator (130) can be disabled.

That is, in conjunction with the first clock signal of the third read mode clock cycle (MSB-1), the switch control unit (150) enables one of the first positive switch and the first negative switch of the first voltage generation unit (140_1) according to the first priority bit data output from the second output terminal of the comparator (130), so that the second reference voltage can be generated by the first capacitor (C1) to the n-th capacitor (Cn). And, the comparator (130) is enabled to output the second priority bit data obtained by comparing the second reference voltage applied through the second inverting input terminal with the specific level voltage (V _T2 ) applied through the second non-inverting input terminal through the second output terminal, and the second common switch and the comparator (130) of the second voltage generation unit (140_2) can be disabled in conjunction with the second clock signal of the third read mode clock cycle (MSB-1). This operation is repeated from the fourth read mode clock cycle to the n-th read mode clock cycle, and the third priority bit data to the (n-1)th priority bit data can be read from the specific voltage level (V _T2 ).

Thereafter, in conjunction with the first clock signal of the (n+1)th read mode clock period (LSB), one of the (n-1)th positive switch (SP_(n-1)) and the (n-1)th negative switch (SN_(n-1)) of the (n-1)th voltage generation unit (140_(n-1)) is enabled by the switch control unit (150) corresponding to the (n-1)th rank bit data output from the second output terminal of the comparator (130) to generate an nth reference voltage by the first capacitor (C1) to the nth capacitor (Cn), and the comparator (130) is enabled to compare the nth reference voltage applied through the second inverting input terminal with the specific level voltage (V _T2 ) applied through the second non-inverting input terminal, thereby outputting the nth rank bit data through the second output terminal.

And, in conjunction with the second clock signal of the (n+1)th lead mode clock cycle (LSB), the nth common switch (S_n), the comparator (130), and the flip switch (SW_FLIP) of the nth voltage generation unit (140_n) can be disabled.

Thereafter, in conjunction with the (n+2) read mode clock cycle (REGEN), one of the nth positive switch (SP_n) and the nth negative switch (SN_n) of the nth voltage generation unit (140_n) is enabled by the switch control unit (150) corresponding to the nth bit data output from the second output terminal of the comparator (130), so that a specific level voltage (V _T2 ) can be regenerated by the first capacitor (C1) to the nth capacitor (Cn).

Meanwhile, the above describes a general concept for reading n-bit data, and a brief explanation is given below for the case where n-bit data is 1-bit data or 2-bit data.

When the memory device according to the present invention is applied to 1-bit data using only the first voltage generator (140_1), after performing the first read mode clock cycle (AMPLIFY), the cell mode switch (SW_MODE) and the sampling switch (SW_SAMPLE) are disabled and the flip switch (SW_FLIP) is enabled in conjunction with the first clock signal of the second read mode clock cycle (MSB) so that the output voltage (V _OUT3 ) output through the first output terminal of the op-amp (120) is flipped to a specific level voltage (V _T2 ), and the comparator (130) is enabled so that the 1-bit data is output by comparing the first reference voltage, which is the precharge voltage (V _M ), applied through the second inverting input terminal with the specific level voltage (V _T2 ) applied through the second non-inverting input terminal, and in conjunction with the second clock signal of the second read mode clock cycle (MSB), the precharge The switch (SW_VM), the first common switch (S_1) of the first voltage generator (140_1), the comparator (130), and the flip switch (SW_FLIP) can be disabled. Then, in conjunction with the third read mode clock cycle (REGEN), one of the first positive switch (SP_1) and the first negative switch (SN_1) of the first voltage generator (140_1) can be enabled by the switch control unit (150) corresponding to 1-bit data output from the second output terminal of the comparator (130) so that a specific level voltage (V _T2 ) can be regenerated by the first capacitor (C1).

In addition, when the memory device according to the present invention is applied to 2-bit data using only the first voltage generation unit (140_1) and the second voltage generation unit (140_2), after performing the first read mode clock cycle (AMPLIFY) and the second read mode clock cycle (MSB), in conjunction with the first clock signal of the third read mode clock cycle (LSB), one of the first positive switch (SP_1) and the first negative switch (SN_1) of the first voltage generation unit (140_1) is enabled by the switch control unit (150) corresponding to the first priority bit data output from the second output terminal of the comparator (130) to generate a second reference voltage by the first capacitor (C1) and the second capacitor (C2), and the comparator (130) is enabled to generate the second reference voltage applied through the second inverting input terminal and the specific level voltage (V) applied through the second non-inverting input terminal. _T2 ) can be output through the second output terminal. Then, in conjunction with the second clock signal of the third read mode clock cycle (LSB), the second common switch (S_2), the comparator (130), and the flip switch (SW_FLIP) of the second voltage generation unit (140_2) can be disabled. Thereafter, in conjunction with the fourth read mode clock cycle (REGEN), the switch control unit (150) corresponding to the second priority bit data output from the second output terminal of the comparator (130) enables one of the second positive switch (SP_2) and the second negative switch (SN_2) of the second voltage generation unit (140_2), so that a specific level voltage (V _T2 ) can be regenerated by the first capacitor (C1) and the second capacitor (C2).

Meanwhile, although the precharge switch (SW_VM) is described as being disabled in conjunction with the second clock signal of the second read mode clock cycle (MSB) in the read mode above, it may be disabled in conjunction with the first clock signal of the third read mode clock cycle, differently. Also, although the flip switch (SW_FLIP) is described as being disabled in conjunction with the second clock signal of the (n+1)th read mode clock cycle (LSB) in the read mode above, it may be disabled in conjunction with the (n+2)th read mode clock cycle (REGEN). In addition, although the common switches are described as being disabled in conjunction with the second clock signal of their respective corresponding read mode clock cycles in the read mode above, it may be disabled in conjunction with the first clock signal of the read mode clock cycle immediately following the corresponding read mode clock cycle.

The operation of reading n-bit data written to a memory cell as described above is explained as follows with an example. At this time, since the operations of the switches in each clock cycle can be easily understood according to the above explanation, the following explanation focuses on the data actually read.

Figure 6 schematically illustrates a state of reading 2-bit data of “10”, assuming that the minimum level voltage V _SS = 0 V, the maximum level voltage VDD = 1.2 V, and the voltage interval are 0.4 V.

First, in a state where a specific level voltage of “0.8 V” corresponding to 2-bit data “10” is stored in the memory cell (110), a specific level voltage of “0.8 V” can be sampled through an amplifier (120) in the first read mode clock cycle (AMPLIFY).

And, in the second read mode clock cycle (MSB), the comparator (130) compares the first reference voltage, the precharge voltage (V _M ), “0.6 V” applied through the second inverting input terminal, with the specific level voltage “0.8 V” applied through the second non-inverting input terminal to output the first priority bit data, “1”.

Thereafter, in the third read mode clock cycle (LSB), the first positive switch (SP_1) of the first power supply (140_1) is enabled according to the first priority bit data “1”, and accordingly, the second reference voltage generated by the first capacitor (C1) and the second capacitor (C2) becomes “1 V”, and the comparator (130) compares the second reference voltage “1 V” applied through the second inverting input terminal with the specific level voltage “0.8 V” applied through the second non-inverting input terminal to output the second priority bit data “0”.

Through this, the memory device can output 2-bit data of “10” corresponding to “0.8 V” written in the memory cell (110).

And, in the 4th read mode clock cycle (REGEN), the second negative switch (SN_2) of the second power supply (140_1) is enabled according to the second priority bit data “0”, and accordingly, a specific level voltage of “0.8 V” generated by the first capacitor (C1) and the second capacitor (C2) can be regenerated.

Referring again to FIGS. 3 and 4, in a state where a specific level voltage (V _T2 ) is regenerated by the first capacitor (C1) to the nth capacitor (Cn), in the refresh mode of the memory cell (110), in response to a first clock signal of the refresh mode clock cycle (REFRESH), the memory cell (110), the cell mode switch (SW_MODE), and the feedback switch (SW_NFB) are enabled so that the specific level voltage (V _T2 ) regenerated by the first capacitor (C1) to the nth capacitor (Cn) can be written to the memory cell (110).

And, in conjunction with the second clock signal of the refresh mode clock cycle (REFRESH), among the k-th positive switch and the k-th negative switch of the k-th voltage generation unit (140_1 to 140_n), the switches (SX_1 to SX_n), the memory cell (110), the cell mode switch (SW_MODE), and the feedback switch (SW_NFB) that maintain an enabled state at the time of the first clock signal of the refresh mode clock cycle are disabled, and the precharge switch (SW_VM) and the k-th common switch (S_1 to S_n) of the k-th voltage generation unit (140_1 to 140_n) can be enabled.

Meanwhile, in the above, the memory cell (110) is enabled in conjunction with the first clock signal of the first read mode clock cycle (AMPLIFY), then disabled in conjunction with the second clock signal of the first read mode clock cycle (AMPLIFY), then enabled in response to the first clock signal of the refresh mode clock cycle (REFRESH), then disabled in conjunction with the second clock signal of the refresh mode clock cycle (REFRESH). However, alternatively, the memory cell (110) may be enabled in conjunction with the first clock signal of the first read mode clock cycle (AMPLIFY), then disabled in conjunction with the second clock signal of the refresh mode clock cycle (REFRESH) while maintaining an enabled state in the read mode (READ).

According to one embodiment of the present invention, the first voltage generating unit (140_1) to the nth voltage generating unit (140_n) generate a specific level voltage for writing to the memory cell (110) and generate a reference voltage of the comparator (130) for reading out the specific level voltage written to the memory cell (110). Therefore, even if the first voltage generating unit (140_1) to the nth voltage generating unit (140_n) has nonlinearity, the comparator (130) reads out the data written to the memory cell (110) using the reference voltage that reflects this, and accordingly, it is possible to solve a problem related to non-ideality due to nonlinearity of a digital-to-analog converter in a conventional memory device.

Next, a memory device according to another embodiment of the present invention will be described as follows. In the following description, the same reference numerals are used for the same parts as in the memory device according to one embodiment of the present invention described with reference to FIGS. 3 and 4, and a detailed description of parts that can be easily understood from the description using FIGS. 3 and 4 will be omitted.

FIG. 7 schematically illustrates a memory device according to another embodiment of the present invention.

Referring to FIG. 7, according to a memory device (200) according to another embodiment of the present invention, a memory cell (210) including a cell switch (SW_WL) and a cell capacitor (Co) enabled by a word line (not shown) can be coupled to a bit line (BL).

And, according to a memory device (200) according to another embodiment of the present invention, an operational amplifier (220) has a first inverting input terminal coupled to a first other-side terminal of a cell mode switch (SW_MODE) having a first one-side terminal coupled to a bit line (BL) to which a memory cell (210) is coupled, a first non-inverting input terminal coupled to a second other-side terminal of a precharge switch (SW_VM) having a second one-side terminal coupled to a precharge voltage terminal (V _M ), and a feedback capacitor (C _FB ) and a feedback switch (SW_NFB) are coupled in parallel between the first output terminal and the first inverting input terminal.

At this time, the precharge voltage (V _M ) may be an average voltage of the first level voltage, which is the minimum level voltage, and the second level voltage, which is the maximum level voltage, among the first level voltage to the second level voltage that distinguish n-bit data, and n may be an integer greater than or equal to 1.

And, according to a memory device (200) according to another embodiment of the present invention, the comparator (230) may have a second inverting input terminal coupled to the second other-side terminal of the precharge switch (SW_VM), a second non-inverting input terminal coupled to the third other-side terminal of a sampling capacitor (Cs) which has a third one-side terminal coupled to the first output terminal of the operational amplifier (220), and a second output terminal.

In addition, according to a memory device (200) according to another embodiment of the present invention, a flip switch (SW_FLIP) may have a fourth side terminal coupled between the first output terminal of the operational amplifier (210) and the sampling capacitor (Cs), and a fourth other side terminal coupled to a flip voltage terminal (V _FLIP ).

And, according to a memory device (200) according to another embodiment of the present invention, a sampling switch (SW_SAMPLE) may have a fifth side terminal coupled between a third side terminal of a sampling capacitor (Cs) and a second non-inverting input terminal of a comparator (230), and a fifth side terminal coupled to a minimum level voltage terminal (V _SS ).

In addition, according to a memory device (200) according to another embodiment of the present invention, a first capacitor (C1) having a first one-side terminal coupled between a second other-side terminal of a precharge switch (SW_VM) and a second inverting input terminal of a comparator (230), a first common switch (S_1) having a first one-side terminal coupled to the first other-side terminal of the first capacitor (C1) and the first other-side terminal coupled to a precharge voltage terminal (V _M ), a first positive switch (SP_1) having a first one-side terminal coupled to the first other-side terminal of the first capacitor (C1) and the first other-side terminal coupled to a maximum level voltage terminal (V _DD ) that provides a maximum level voltage, and a first capacitor (C1) having a first one-side terminal coupled to the first other-side terminal of the first capacitor (C1) and the first other-side terminal coupled to a minimum level voltage terminal (V _SS ). An nth capacitor (Cn) having an n_1-th one-side terminal coupled between a first voltage generating unit (240_1) including a negative switch (SN_1) and a second other-side terminal of a precharge switch (SW_VM) and a second inverting input terminal of a comparator (230), an nth common switch (S_n) having an n_2-th one-side terminal coupled to the n_1-th other-side terminal of the nth capacitor (Cn) and the n_2-th other-side terminal coupled to a precharge voltage terminal (V _M ), an nth positive switch (SP_n) having an n_3-th one-side terminal coupled to the n_1-th other-side terminal of the nth capacitor (Cn) and the n_3-th other-side terminal coupled to a maximum level voltage terminal (V _DD ), and an nth negative having an n_4-th one-side terminal coupled to the n_1-th other-side terminal of the nth capacitor (Cn) and the n_4-th other-side terminal coupled to a minimum level voltage terminal (V _SS ) An nth voltage generating unit (240_n) including a switch (SN_n) can be formed.

At this time, when k is an integer greater than or equal to 1 and less than or equal to n, the kth capacitance of the kth capacitor can be (the first capacitance of the first capacitor)/2^(k-1).

And, according to a memory device (200) according to another embodiment of the present invention, a switch control unit (250) may be formed to control the first voltage generation unit (240_1) to the n-th voltage generation unit (240_n) in response to the output digital data output from the second output terminal of the comparator (230) or the n-bit input digital data input to write n-bit data into the memory cell (210) to generate an analog signal corresponding to the output digital data or the n-bit input digital data. At this time, the switch control unit (250) may include a logic circuit (Logic) that determines a specific voltage generation unit to be controlled in response to the output digital data output from the second output terminal of the comparator (230), and a MUX that transmits a control signal to the first voltage generation unit (240_1) to the n-th voltage generation unit (240_n) in response to the input digital data.

The operation process of another memory device (200) according to another embodiment of the present invention configured as described above will be described using the timing diagram of FIG. 8 as follows. The memory device (200) operates in response to a clock (CLK) frequency, and each clock cycle has two signals. The operation states of the switches of the memory device (200) can be set in various ways according to the signals of the clock cycle. However, in the following description, it is assumed that the first clock signal corresponds to “logic high” and the second clock signal corresponds to “logic low.”

First, in the precharge mode (PCG) of the memory cell (210) for precharging the bit line (BL), while the precharge switch (SW_VM) maintains an enabled state and the first common switch (S_1) to the nth common switch (S_n) maintain an enabled state, the cell mode switch (SW_MODE) and the feedback switch (SW_NFB) are enabled in conjunction with the first clock signal of the precharge clock cycle of the precharge mode (PCG), so that the bit line (BL) can be precharged by the precharge voltage (V _M ).

Meanwhile, the generated voltage (V _T1 ) generated by the first voltage generator (240_1) to the nth voltage generator (240_n) can be expressed as follows.

At this time, the voltage applied to the first capacitor (C1) of the first voltage generating unit (240_1) to the nth capacitor (Cn) of the nth voltage generating unit (240_n) is a precharge voltage (V _M ), so the generated voltage (V _T1 ) generated by the first voltage generating unit (240_1) to the nth voltage generating unit (240_n) in the precharge mode clock cycle can be the precharge voltage (V _M ).

Accordingly, since the precharge voltage (V _M ) is applied to the first non-inverting input terminal of the op-amp (220), the output voltage (V _OUT1 ) output through the first output terminal of the op-amp (220) becomes the precharge voltage (V _M ), and accordingly, the bit line (BL) can be precharged by the precharge voltage (V _M ), which is the output voltage of the op-amp (220), according to the negative feedback of the op-amp (220) by the feedback switch (SW_NFB).

At this time, the parasitic capacitor (C _P ) of the bit line (BL) is charged with the precharge voltage (V _M ), which is the output voltage of the op-amp (220), and accordingly, the amount of charge (Q _P ) stored in the parasitic capacitor (C _P ) can be expressed as follows. Meanwhile, as the feedback switch (SW_NFB) is enabled, the amount of charge (Q _FB ) stored in the feedback capacitor (C _FB ) becomes “0”.

Afterwards, the cell mode switch (SW_MODE) and the feedback switch (SW_NFB) can be disabled in conjunction with the second clock signal of the precharge clock cycle.

Next, in the write mode (WRITE) of the memory cell (210) for storing n-bit data in the memory cell (210) through the bit line (BL) precharged by the precharge voltage (V _M ), in conjunction with the first clock signal of the write mode clock cycle, the precharge switch (SW_VM) is disabled, the cell mode switch (SW_MODE), the feedback switch (SW_NFB), and the memory cell (210) are enabled, and by the switch control unit (250) corresponding to the input n-bit input data (D _IN ), when k is an integer greater than or equal to 1 and less than or equal to n, the k-th common switch (S_1 to S_n) of the k-th voltage generation unit (240_1 to 240_n) is disabled, and one of the k-th positive switch and the k-th negative switch (SX_1 to SX_n) is enabled to generate a first capacitor (C1) to the n-th capacitor (C2). A specific level voltage corresponding to n-bit input data generated by a capacitor (Cn) can be written to a memory cell (210). At this time, the memory cell (210) can be enabled by enabling a cell switch (SW_WL) by a word line.

Meanwhile, the generated voltage (V _T2 ) generated by the first voltage generator (240_1) to the nth voltage generator (240_n) can be expressed as follows.

At this time, since the capacitance of the kth capacitor, which is one of the first capacitor (C1) to the nth capacitor (Cn), is C ₁ /2^(n-1), the generated voltage (V _T2 ) generated by the first voltage generating unit (240_1) to the nth voltage generating unit (240_n) can be expressed as follows.

And, since the switch control unit (250) enables one of the k-th positive switch and the k-th negative switch (SX_1 to SX_n) of the k-th voltage generation unit (240_1 to 240_n) in response to the k-th rank bit data in the n-bit data, each of the voltages (V ₁ to V _n ) applied to each of the first capacitor (C1) to the n-th capacitor (Cn) can be one of the minimum level voltage (V _SS ) and the maximum level voltage (V _DD ). For example, when the k-th rank bit data is “1”, the k-th positive switch can be enabled, and when the k-th rank bit data is “0”, the k-th negative switch can be enabled.

Accordingly, the first voltage generating unit (240_1) to the n-th voltage generating unit (240_n) can generate a specific level voltage (V _T2 ) corresponding to the n-bit input data (D _IN ) to be written to the memory cell (210) among the first level voltage to the second^n-th level voltage that distinguishes n-bit data.

For example, referring to Fig. 5, the following explanation is given based on 2-bit data. At this time, the minimum level voltage (V _SS ) is assumed to be the ground voltage.

The generated voltage (V _T ) generated by the first voltage generator and the second voltage generator corresponding to 2-bit data can be expressed as follows.

가 되며, 도 5의 (c)에서와 같이 제1 전압 생성부의 제1 포지티브 스위치(SP_1)이 인에이블되고 제2 전압 생성부의 제2 네거티브 스위치(SN_2)가 인에이블될 경우에는 생성 전압(VT)은

가 되며, 도 5의 (d)에서와 같이 제1 전압 생성부의 제1 포지티브 스위치(SP_1)가 인에이블되고 제2 전압 생성부의 제2 포지티브 스위치(SP_2)가 인에이블될 경우에는 생성 전압(V_T)은 V_DD이 될 수 있다. 따라서, 제1 전압 생성부와 제2 전압 생성부를 통해, 2비트 데이터의 코드인 “00”, “01”, “10”, 및 “11”을 나타내는 4개의 레벨 전압인 V_SS,

,

, 및 V_DD를 생성할 수 있게 된다.Therefore, when the first negative switch (SN_1) of the first voltage generator is enabled and the second negative switch (SN_2) of the second voltage generator is enabled as in (a) of Fig. 5, the generated voltage (V _T ) becomes V _SS , and when the first negative switch (SN_1) of the first voltage generator is enabled and the second positive switch (SP_2) of the second voltage generator is enabled as in (b) of Fig. 5, the generated voltage (VT ) becomes

, and when the first positive switch (SP_1) of the first voltage generation unit is enabled and the second negative switch (SN_2) of the second voltage generation unit is enabled, as in (c) of Fig. 5, the generated voltage (VT) is

, and when the first positive switch (SP_1) of the first voltage generation unit is enabled and the second positive switch (SP_2) of the second voltage generation unit is enabled as in (d) of Fig. 5, the generated voltage (V _T ) can be V _DD . Accordingly, through the first voltage generation unit and the second voltage generation unit, four level voltages, V _SS , representing the codes of 2-bit data, “00”, “01”, “10”, and “11”, are generated.

,

, and V _DD can be generated.

Again, referring to FIGS. 7 and 8, a specific level voltage (V _T2 ) generated from the first voltage generating unit (240_1) to the nth voltage generating unit (240_n) is applied to the first non-inverting input terminal of the operational amplifier (220).

Accordingly, the output voltage (V _OUT2 ) output through the first output terminal of the operational amplifier (220) becomes a specific level voltage (V _T2 ), and according to the negative feedback of the operational amplifier (220), the specific level voltage (V _T2 ), which is the output voltage of the operational amplifier (220), is applied to the precharged bit line (BL), thereby charging the cell capacitor (Co) with a charge corresponding to the specific level voltage (V _T2 ).

At this time, the amount of charge (Q _O ) stored in the cell capacitor (C _O ) can be expressed as follows.

After writing data to the memory cell (C _O ), the total charge (Q ₁ ) stored in the cell capacitor (C _O ), parasitic capacitor (C _P ), and feedback capacitor (C _FB ) can be expressed as follows.

Thereafter, in conjunction with the second clock signal of the light mode clock cycle, the precharge switch (SW_VM) is enabled, the cell mode switch (SW_MODE), the feedback switch (SW_NFB), and the memory cell (210) are disabled, and the kth common switch (S_1 to S_n) of the kth voltage generation unit (240_1 to 240_n) is enabled by the switch control unit (250), and among the kth positive switch and the kth negative switch, the switches (SX_1 to SX_n) that were enabled at the first clock signal of the light mode clock cycle can be disabled.

Next, the operation process in the read mode (READ) for reading n-bit data written in the memory cell (210) while the bit line (BL) is precharged is described as follows. At this time, it is assumed that a specific level voltage (V _T2 ) input in the write mode is stored in the cell capacitor (Co).

First, in conjunction with the first clock signal and the second clock signal of the first read mode clock cycle (AMPLIFY), the memory cell (210), the cell mode switch (SW_MODE), and the sampling switch (SW_SAMPLE) are enabled so that the operational amplifier (220) can sense a specific voltage level (V _T2 ) stored in the memory cell (210) through capacitive feedback via the feedback capacitor (C _FB ) and output an output voltage (V _OUT3 ) through the first output terminal.

That is, as the memory cell (210) and the cell mode switch (SW_MODE) are enabled, the operational amplifier (220) can amplify the difference between the voltage applied to the first inverting input terminal and the voltage applied to the first non-inverting input terminal and output the output voltage (V _OUT3 ) through the first output terminal. In addition, the feedback capacitor (C _FB ) can feed back the output voltage (V _OUT3 ) of the operational amplifier (220) to the first inverting input terminal.

At this time, the first inverting input terminal of the operational amplifier (220) becomes floating, and since the first inverting input terminal and the first non-inverting input terminal of the operational amplifier (220) are in a virtual short state while the amplification factor (A) of the operational amplifier (220) is very high, the voltage (V _B ) applied to the first inverting input terminal of the operational amplifier (220) becomes the pre-difference voltage (V _M ).

And, in the circuit, charge redistribution occurs between the cell capacitor (Co), the parasitic capacitor (C _P ), and the feedback capacitor (C _FB ), and accordingly, the total charge (Q ₂ ) stored in the redistributed cell capacitor (Co), the parasitic capacitor (C _P ), and the feedback capacitor (C _FB ) can be expressed as follows.

At this time, since the amount of charge before and after charge redistribution is the same according to the law of conservation of charge, the output voltage (V _OUT3 ) of the op amp (220) can be expressed as follows.

At this time, the output voltage (V _OUT3 ) of the op-amp (220) can be stored in the sampling capacitor (C _S ) by the minimum level voltage (V _SS ) supplied according to the enable of the sampling switch (SW_SAMPLE).

Thereafter, in conjunction with the first clock signal of the second read mode clock cycle (MSB), the memory cell (210), the cell mode switch (SW_MODE), and the sampling switch (SW_SAMPLE) are disabled, the flip switch (SW_FLIP) is enabled so that the output voltage (V _OUT3 ) output through the first output terminal of the operational amplifier (220) is flipped to a specific level voltage (V _T2 ), and the comparator (230) is enabled so that the first priority bit data is output by comparing the first reference voltage, which is the precharge voltage (V _M ), applied through the second inverting input terminal with the specific level voltage (V _T2 ) applied through the second non-inverting input terminal.

와 같이 나타낼 수 있으며, 이 출력 전압(V_OUT3)이 그대로 비교기(230)에 인가되어 디지털 코드로 변환되면, 이후에 설명되는 리제너레이션에서 출력 전압(V_OUT3)이 그대로 재생성되며, 이를 이용하여 리프레시를 수행할 경우, 최초 기록한 메모리 셀(210)의 특정 레벨 전압(V_T2)과는 다른 전압이 리프레시에 의해 메모리 셀(210)에 기록될 수 있다.At this time, assuming that the capacitance of the cell capacitor (Co) and the capacitance of the feedback capacitor (C _FB ) are the same, the output voltage (V _OUT3 ) of the op-amp (120) is

It can be expressed as follows, and when this output voltage (V _OUT3 ) is applied as it is to the comparator (230) and converted into a digital code, the output voltage (V _OUT3 ) is regenerated as it is in the regeneration described later, and when a refresh is performed using this, a voltage different from the specific level voltage (V _T2 ) of the initially recorded memory cell (210) can be written to the memory cell (210) by the refresh.

Therefore, to prevent this, the flip switch (SW_FLIP) is enabled to supply a flip voltage (V _FLIP ) so that the output voltage of the op-amp (220) stored in the sampling capacitor (C _S ) can be flipped to a specific level voltage (V _T2 ).

이 저장된 상태에서, 샘플링 캐패시터(C_S)의 제3 일측단에 플립 전압(V_FLIP)이 인가되면, 샘플링 캐패시터(C_S)의 제3 타측단에는 전압

이 생성되므로, 플립 전압(V_FLIP)을

으로 설정함으로써 샘플링 캐패시터(C_S)의 제3 타측단에 메모리 셀(110)에 기록한 것과 동일한 특정 레벨 전압

이 생성되도록 할 수 있다.That is, the output voltage of the op-amp (120) to the sampling capacitor (C _S ).

In this stored state, when a flip voltage (V _FLIP ) is applied to the third terminal of the sampling capacitor (C _S ), a voltage is applied to the third terminal of the sampling capacitor (C _S ).

Since this is generated, the flip voltage (V _FLIP )

By setting the third terminal of the sampling capacitor (C _S ) to a specific level voltage identical to that recorded in the memory cell (110).

This can be created.

And, in conjunction with the second clock signal of the second read mode clock cycle (MSB), the precharge switch (SW_VM), the first common switch (S_1) of the first voltage generator (240_1), and the comparator (230) can be disabled.

Thereafter, when j is an integer greater than or equal to 2 and less than or equal to (n-1), in conjunction with the first clock signal of the (j+1)th read mode clock cycle, one of the (j-1)th positive switch and the (j-1)th negative switch of the (j-1)th voltage generation unit is enabled by the switch control unit (250) corresponding to the (j-1)th rank bit data output from the second output terminal of the comparator (230) to generate the jth reference voltage by the first capacitor (C1) to the nth capacitor (Cn), and the comparator (230) is enabled to compare the jth reference voltage applied through the second inverting input terminal with the specific level voltage (V _T2 ) applied through the second non-inverting input terminal, so that the jth rank bit data is output through the second output terminal, and in conjunction with the second clock signal of the (j+1)th read mode clock cycle, the jth common switch and the jth common switch of the jth voltage generation unit are The comparator (230) can be disabled.

That is, in conjunction with the first clock signal of the third read mode clock cycle (MSB-1), the switch control unit (250) enables one of the first positive switch and the first negative switch of the first voltage generation unit (240_1) according to the first priority bit data output from the second output terminal of the comparator (230), so that the second reference voltage can be generated by the first capacitor (C1) to the n-th capacitor (Cn). And, the comparator (230) is enabled to output the second priority bit data obtained by comparing the second reference voltage applied through the second inverting input terminal with the specific level voltage (V _T2 ) applied through the second non-inverting input terminal through the second output terminal, and the second common switch and the comparator (230) of the second voltage generation unit (240_2) can be disabled in conjunction with the second clock signal of the third read mode clock cycle (MSB-1). This operation is repeated from the fourth read mode clock cycle to the n-th read mode clock cycle, and the third priority bit data to the (n-1)th priority bit data can be read from the specific voltage level (V _T2 ).

Thereafter, in conjunction with the first clock signal of the (n+1)th read mode clock period (LSB), one of the (n-1)th positive switch (SP_(n-1)) and the (n-1)th negative switch (SN_(n-1)) of the (n-1)th voltage generation unit (240_(n-1)) is enabled by the switch control unit (250) corresponding to the (n-1)th rank bit data output from the second output terminal of the comparator (230) to generate an nth reference voltage by the first capacitor (C1) to the nth capacitor (Cn), and the comparator (230) is enabled to compare the nth reference voltage applied through the second inverting input terminal with the specific level voltage (V _T2 ) applied through the second non-inverting input terminal, thereby outputting the nth rank bit data through the second output terminal.

And, in conjunction with the second clock signal of the (n+1)th lead mode clock cycle (LSB), the nth common switch (S_n), the comparator (230), and the flip switch (SW_FLIP) of the nth voltage generation unit (240_n) can be disabled.

Thereafter, in conjunction with the (n+2) read mode clock cycle (REGEN), one of the nth positive switch (SP_n) and the nth negative switch (SN_n) of the nth voltage generation unit (240_n) is enabled by the switch control unit (250) corresponding to the nth bit data output from the second output terminal of the comparator (230), so that a specific level voltage (V _T2 ) can be regenerated by the first capacitor (C1) to the nth capacitor (Cn).

Meanwhile, the above describes a general concept for reading n-bit data, and a brief explanation is given below for the case where n-bit data is 1-bit data or 2-bit data.

When the memory device according to the present invention is applied to 1-bit data using only the first voltage generator (240_1), after performing the first read mode clock cycle (AMPLIFY), the cell mode switch (SW_MODE) and the sampling switch (SW_SAMPLE) are disabled and the flip switch (SW_FLIP) is enabled in conjunction with the first clock signal of the second read mode clock cycle (MSB) so that the output voltage (V _OUT3 ) output through the first output terminal of the op-amp (220) is flipped to a specific level voltage (V _T2 ), and the comparator (230) is enabled so that the 1-bit data is output by comparing the first reference voltage, which is the precharge voltage (V _M ), applied through the second inverting input terminal with the specific level voltage (V _T2 ) applied through the second non-inverting input terminal, and in conjunction with the second clock signal of the second read mode clock cycle (MSB), the precharge The switch (SW_VM), the first common switch (S_1) of the first voltage generator (240_1), the comparator (230), and the flip switch (SW_FLIP) can be disabled. Then, in conjunction with the third read mode clock cycle (REGEN), one of the first positive switch (SP_1) and the first negative switch (SN_1) of the first voltage generator (240_1) can be enabled by the switch control unit (250) corresponding to 1-bit data output from the second output terminal of the comparator (230) so that a specific level voltage (V _T2 ) can be regenerated by the first capacitor (C1).

In addition, when the memory device according to the present invention is applied to 2-bit data using only the first voltage generation unit (240_1) and the second voltage generation unit (240_2), after performing the first read mode clock cycle (AMPLIFY) and the second read mode clock cycle (MSB), in conjunction with the first clock signal of the third read mode clock cycle (LSB), one of the first positive switch (SP_1) and the first negative switch (SN_1) of the first voltage generation unit (240_1) is enabled by the switch control unit (250) corresponding to the first priority bit data output from the second output terminal of the comparator (230) to generate a second reference voltage by the first capacitor (C1) and the second capacitor (C2), and the comparator (230) is enabled to generate the second reference voltage applied through the second inverting input terminal and the specific level voltage (V) applied through the second non-inverting input terminal. _T2 ) can be output through the second output terminal. Then, in conjunction with the second clock signal of the third read mode clock cycle (LSB), the second common switch (S_2), the comparator (230), and the flip switch (SW_FLIP) of the second voltage generation unit (240_2) can be disabled. Thereafter, in conjunction with the fourth read mode clock cycle (REGEN), the switch control unit (250) corresponding to the second priority bit data output from the second output terminal of the comparator (230) enables one of the second positive switch (SP_2) and the second negative switch (SN_2) of the second voltage generation unit (240_2), so that a specific level voltage (V _T2 ) can be regenerated by the first capacitor (C1) and the second capacitor (C2).

Meanwhile, although the precharge switch (SW_VM) is described as being disabled in conjunction with the second clock signal of the second read mode clock cycle (MSB) in the read mode above, it may be disabled in conjunction with the first clock signal of the third read mode clock cycle, differently. Also, although the flip switch (SW_FLIP) is described as being disabled in conjunction with the second clock signal of the (n+1)th read mode clock cycle (LSB) in the read mode above, it may be disabled in conjunction with the (n+2)th read mode clock cycle (REGEN). In addition, although the common switches are described as being disabled in conjunction with the second clock signal of their respective corresponding read mode clock cycles in the read mode above, it may be disabled in conjunction with the first clock signal of the read mode clock cycle immediately following the corresponding read mode clock cycle.

Next, in a state where a specific level voltage (V _T2 ) is regenerated by the first capacitor (C1) to the nth capacitor (Cn), in the refresh mode of the memory cell (210), in response to a first clock signal of the refresh mode clock cycle (REFRESH), the memory cell (210), the cell mode switch (SW_MODE), and the feedback switch (SW_NFB) are enabled so that the specific level voltage (V _T2 ) regenerated by the first capacitor (C1) to the nth capacitor (Cn) can be written to the memory cell (110).

And, in conjunction with the second clock signal of the refresh mode clock cycle (REFRESH), among the k-th positive switch and the k-th negative switch of the k-th voltage generation unit (240_1 to 240_n), the switches (SX_1 to SX_n), the memory cell (210), the cell mode switch (SW_MODE), and the feedback switch (SW_NFB) that maintain an enabled state at the time of the first clock signal of the refresh mode clock cycle are disabled, and the precharge switch (SW_VM) and the k-th common switch (S_1 to S_n) of the k-th voltage generation unit (240_1 to 240_n) can be enabled.

Meanwhile, in the above, the memory cell (210) is enabled in conjunction with the first clock signal of the first read mode clock cycle (AMPLIFY), then disabled in conjunction with the second clock signal of the first read mode clock cycle (AMPLIFY), then enabled in response to the first clock signal of the refresh mode clock cycle (REFRESH), then disabled in conjunction with the second clock signal of the refresh mode clock cycle (REFRESH). However, alternatively, the memory cell (210) may be enabled in conjunction with the first clock signal of the first read mode clock cycle (AMPLIFY), then disabled in conjunction with the second clock signal of the refresh mode clock cycle (REFRESH) while maintaining an enabled state in the read mode (READ).

According to one embodiment of the present invention, the first voltage generating unit (240_1) to the nth voltage generating unit (240_n) generate a specific level voltage for writing to the memory cell (210) and generate a reference voltage of the comparator (230) for reading out the specific level voltage written to the memory cell (210). Therefore, even if the first voltage generating unit (240_1) to the nth voltage generating unit (240_n) has nonlinearity, the comparator (230) reads out the data written to the memory cell (210) using the reference voltage reflecting this, and accordingly, it is possible to solve a problem related to non-ideality due to nonlinearity of a digital-to-analog converter in a conventional memory device.

Although the present invention has been described above with specific details such as specific components and limited examples and drawings, these have been provided only to help a more general understanding of the present invention, and the present invention is not limited to the above examples, and those with common knowledge in the technical field to which the present invention belongs can make various modifications and variations from this description.

Therefore, the idea of the present invention should not be limited to the embodiments described above, and not only the claims described below but also all modifications equivalent to or equivalent to the claims are included in the scope of the idea of the present invention.

Claims (18)

In a memory device including a memory cell storing n-bit data by the operation of a word line and a bit line, An operational amplifier having a first inverting input terminal coupled to a first other end of a cell mode switch having a first one end coupled to a bit line coupled to a memory cell, a first non-inverting input terminal coupled to a second other end of a precharge switch having a second one end coupled to a precharge voltage terminal, and a feedback switch coupled between a first output terminal and the first inverting input terminal; A comparator having a second output terminal, a second inverting input terminal coupled to the second other side terminal of the precharge switch, a second non-inverting input terminal coupled to the third other side terminal of a sampling capacitor, a third one side terminal of which is coupled to the first output terminal of the operational amplifier; A flip switch having a fourth side terminal coupled between the first output terminal of the op-amp and the third side terminal of the sampling capacitor, and a fourth other side terminal coupled to a flip voltage terminal; A fifth side terminal is coupled between the third other side terminal of the sampling capacitor and the second non-inverting input terminal of the comparator, and the fifth other side terminal is coupled to a minimum level voltage terminal providing a minimum level voltage, wherein the minimum level voltage is a first level voltage among the first level voltage to the 2^n level voltage that distinguishes n-bit data, and n is an integer greater than or equal to 1; (i) a first voltage generating unit including a first capacitor having a first one-side terminal coupled between the second other-side terminal of the precharge switch and the second inverting input terminal of the comparator, a first common switch having a first one-side terminal coupled to the first other-side terminal of the first capacitor and a first other-side terminal coupled to the precharge voltage terminal, a first positive switch having a first one-side terminal coupled to the first other-side terminal of the first capacitor and a first other-side terminal coupled to a maximum level voltage terminal providing a maximum level voltage, wherein the maximum level voltage is the 2^n level voltage, and a first negative switch having a first one-side terminal coupled to the first other-side terminal of the first capacitor and a first other-side terminal coupled to the minimum level voltage terminal; and (ii) between the second other-side terminal of the precharge switch and the second inverting input terminal of the comparator. An nth voltage generating unit including an nth capacitor having an nth side terminal coupled to the nth other side terminal of the nth capacitor, an nth common switch having an nth side terminal coupled to the nth other side terminal of the nth capacitor and the nth other side terminal coupled to the precharge voltage terminal, an nth positive switch having an nth side terminal coupled to the nth other side terminal of the nth capacitor and the nth other side terminal coupled to the maximum level voltage terminal, and an nth negative switch having an nth side terminal coupled to the nth other side terminal of the nth capacitor and the nth other side terminal coupled to the minimum level voltage terminal; and A switch control unit that controls the first voltage generation unit to the nth voltage generation unit in response to output digital data output from the second output terminal of the comparator or n-bit input digital data input to write the n-bit data into the memory cell, thereby generating an analog signal corresponding to the output digital data or the n-bit input digital data; A memory device characterized by including a . In the first paragraph, A memory device, characterized in that when k is an integer greater than or equal to 1 and less than or equal to n, the kth capacitance of the kth capacitor is (the first capacitance of the first capacitor)/2^(k-1). In the first paragraph, A memory device characterized in that, while the precharge switch maintains an enabled state and the first common switch to the nth common switch maintain an enabled state, the cell mode switch and the feedback switch are enabled in conjunction with a first clock signal of a precharge clock cycle of the precharge mode so that the bit line is precharged by the precharge voltage, and the cell mode switch and the feedback switch are disabled in conjunction with a second clock signal of the precharge clock cycle. In the third paragraph, In a write mode for storing the n-bit data in the memory cell while the bit line is precharged, In response to a first clock signal of a light mode clock cycle, the precharge switch is disabled, the cell mode switch, the feedback switch, and the memory cell are enabled, and by the switch control unit corresponding to the input n-bit input data, when k is an integer greater than or equal to 1 and less than or equal to n, the k-th common switch of the k-th voltage generation unit is disabled, and one of the k-th positive switch and the k-th negative switch is enabled, so that a specific level voltage corresponding to the n-bit input data generated by the first capacitor to the n-th capacitor is written to the memory cell. A memory device characterized in that, in conjunction with a second clock signal of the light mode clock cycle, the precharge switch is enabled, the cell mode switch, the feedback switch, and the memory cell are disabled, the kth common switch of the kth voltage generation unit is enabled by the switch control unit, and a switch among the kth positive switch and the kth negative switch that was enabled at the time of the first clock signal of the light mode clock cycle is disabled. In the third paragraph, In a read mode for reading 1-bit data, which is the n-bit data written to the memory cell, while the bit line is precharged, (i) in conjunction with a first clock signal of a first read mode clock cycle, the memory cell is enabled so that the bit line is charge-shared with the memory cell, in conjunction with a second clock signal of the first read mode clock cycle, the memory cell is disabled, the cell mode switch and the sampling switch are enabled so that the operational amplifier senses an output voltage, which is a difference between the precharge voltage applied through the first non-inverting input terminal and a specific level voltage recorded in the memory cell applied through the first inverting input terminal, and outputs the output voltage through the first output terminal, (ii) in conjunction with a first clock signal of a second read mode clock cycle, the cell mode switch and the sampling switch are disabled, and the flip switch is enabled so that the output voltage output through the first output terminal of the operational amplifier is flipped to the specific level voltage, and the comparator is enabled so that the first reference voltage, which is the precharge voltage applied through the second inverting input terminal, and A memory device characterized in that the 1-bit data is output by comparing the specific level voltage applied through the second non-inverting input terminal, and in conjunction with the second clock signal of the second read mode clock cycle, the precharge switch, the first common switch of the first voltage generation unit, the comparator, and the flip switch are disabled, and (iii) in conjunction with the third read mode clock cycle, one of the first positive switch and the first negative switch of the first voltage generation unit is enabled by the switch control unit corresponding to the 1-bit data output from the second output terminal of the comparator, so that the specific level voltage is regenerated by the first capacitor. In the third paragraph, In a read mode for reading 2-bit data, which is the n-bit data written to the memory cell, while the bit line is precharged, (i) in response to a first clock signal of a first read mode clock cycle, the memory cell is enabled so that the bit line is charge-shared with the memory cell, in response to a second clock signal of the first read mode clock cycle, the memory cell is disabled, the cell mode switch and the sampling switch are enabled so that the operational amplifier senses an output voltage, which is a difference between the precharge voltage applied through the first non-inverting input terminal and a specific level voltage written to the memory cell applied through the first inverting input terminal, and outputs the output voltage through the first output terminal, (ii) (ii_1) in response to a first clock signal of a second read mode clock cycle, the cell mode switch and the sampling switch are disabled, and the flip switch is enabled so that the output voltage output through the first output terminal of the operational amplifier is flipped to the specific level voltage, and the comparator is enabled so that the precharge voltage applied through the second inverting input terminal is (ii_2) in conjunction with the first clock signal of the third read mode clock cycle, one of the first positive switch and the first negative switch of the first voltage generation unit is enabled by the switch control unit corresponding to the first priority bit data output from the second output terminal of the comparator to generate a second reference voltage by the first capacitor and the second capacitor, and the comparator is enabled to output second priority bit data obtained by comparing the second reference voltage applied through the second inverting input terminal with the specific level voltage applied through the second non-inverting input terminal, and the third read mode clock A memory device characterized in that in conjunction with a second clock signal of a cycle, a second common switch of a second voltage generation unit, the comparator, and the flip switch are disabled, and (iii) in conjunction with a fourth read mode clock cycle, one of a second positive switch and a second negative switch of the second voltage generation unit is enabled by the switch control unit corresponding to the second priority bit data output from the second output terminal of the comparator, so that the specific level voltage is regenerated by the first capacitor and the second capacitor. In the third paragraph, In a read mode for reading the n-bit data of 3 or more bits written in the memory cell while the bit line is precharged, (i) in response to a first clock signal of a first read mode clock cycle, the memory cell is enabled so that the bit line is charge-shared with the memory cell, in response to a second clock signal of the first read mode clock cycle, the memory cell is disabled, the cell mode switch and the sampling switch are enabled so that the operational amplifier senses an output voltage, which is a difference between the precharge voltage applied through the first non-inverting input terminal and a specific level voltage written to the memory cell applied through the first inverting input terminal, and outputs the output voltage through the first output terminal, (ii) (ii_1) in response to a first clock signal of a second read mode clock cycle, the cell mode switch and the sampling switch are disabled, and the flip switch is enabled so that the output voltage output through the first output terminal of the operational amplifier is flipped to the specific level voltage, and the comparator is enabled so that the precharge voltage applied through the second inverting input terminal is The first priority bit data is output by comparing the first reference voltage and the specific level voltage applied through the second non-inverting input terminal, and in conjunction with the second clock signal of the second read mode clock cycle, the precharge switch, the first common switch of the first voltage generation unit, and the comparator are disabled, and (ii_2) when j is an integer greater than or equal to 2 and less than or equal to (n-1), in conjunction with the first clock signal of the (j+1)-th read mode clock cycle, one of the (j-1) positive switch and the (j-1) negative switch of the (j-1)-th voltage generation unit is enabled by the switch control unit corresponding to the (j-1)-th priority bit data output from the second output terminal of the comparator, so that the j-th reference voltage is generated by the first capacitor to the n-th capacitor, and the comparator is enabled to generate the j-th reference voltage by the j-th reference voltage applied through the second inverting input terminal and the second non-inverting input terminal. The jth order bit data obtained by comparing the applied specific level voltage is output through the second output terminal, and in conjunction with the second clock signal of the (j+1)th read mode clock cycle, the jth common switch of the jth voltage generation unit and the comparator are disabled, (ii_3) in conjunction with the first clock signal of the (n+1)th read mode clock cycle, one of the (n-1)th positive switch and the (n-1)th negative switch of the (n-1)th voltage generation unit is enabled by the switch control unit corresponding to the (n-1)th order bit data output from the second output terminal of the comparator to generate an nth reference voltage by the first capacitor to the nth capacitor, and the comparator is enabled so that the nth order bit data obtained by comparing the nth reference voltage applied through the second inverting input terminal and the specific level voltage applied through the second non-inverting input terminal is output through the second output terminal, and A memory device characterized in that, in conjunction with a second clock signal of the (n+1)th read mode clock cycle, the nth common switch, the comparator, and the flip switch of the nth voltage generation unit are disabled, and (iii) in conjunction with the (n+2)th read mode clock cycle, one of the nth positive switch and the nth negative switch of the nth voltage generation unit is enabled by the switch control unit corresponding to the nth bit data output from the second output terminal of the comparator, so that the specific level voltage is regenerated by the first capacitor to the nth capacitor. In any one of paragraphs 5 to 7, In the refresh mode of the memory cell, in a state where the specific level voltage is regenerated by the first capacitor to the nth capacitor, A memory device, characterized in that in response to a first clock signal of a refresh mode clock cycle, the memory cell, the cell mode switch, and the feedback switch are enabled so that the specific level voltage regenerated by the first capacitor to the nth capacitor is written to the memory cell, and in response to a second clock signal of the refresh mode clock cycle, among the k-th positive switch and the k-th negative switch of the k-th voltage generation unit, a switch that maintains an enabled state at the time of the first clock signal of the refresh mode clock cycle, the memory cell, the cell mode switch, and the feedback switch are disabled, and the precharge switch and the k-th common switch of the k-th voltage generation unit are enabled. In Article 8, A memory device characterized in that the memory cell is enabled and maintained in an enabled state in conjunction with a first clock signal of the first read mode clock cycle, and is disabled in conjunction with a second clock signal of the refresh mode clock cycle. In a memory device including a memory cell storing n-bit data by the operation of a word line and a bit line, An operational amplifier having a first inverting input terminal coupled to a first other end of a cell mode switch having a first one end coupled to a bit line to which a memory cell is coupled, a first non-inverting input terminal coupled to a second other end of a precharge switch having a second one end coupled to a precharge voltage terminal, and a feedback capacitor and a feedback switch coupled in parallel between a first output terminal and the first inverting input terminal; A comparator having a second output terminal, a second inverting input terminal coupled to the second other side terminal of the precharge switch, a second non-inverting input terminal coupled to the third other side terminal of a sampling capacitor, a third one side terminal of which is coupled to the first output terminal of the operational amplifier; A flip switch having a fourth side terminal coupled between the first output terminal of the op-amp and the third side terminal of the sampling capacitor, and a fourth side terminal coupled to a flip voltage terminal; A fifth side terminal is coupled between the third other side terminal of the sampling capacitor and the second non-inverting input terminal of the comparator, and the fifth other side terminal is coupled to a minimum level voltage terminal providing a minimum level voltage, wherein the minimum level voltage is a first level voltage among the first level voltage to the 2^n level voltage that distinguishes n-bit data, and n is an integer greater than or equal to 1; (i) a first voltage generating unit including a first capacitor having a first-side terminal coupled between the second other-side terminal of the precharge switch and the second inverting input terminal of the comparator, a first common switch having a first-side terminal coupled to the first-side terminal of the first capacitor and a first-side terminal coupled to the precharge voltage terminal, a first positive switch having a first-side terminal coupled to the first-side terminal of the first capacitor and a first-side terminal coupled to a maximum level voltage terminal providing a maximum level voltage, wherein the maximum level voltage is the 2^n level voltage, and a first negative switch having a first-side terminal coupled to the first-side terminal of the first capacitor and a first-side terminal coupled to the minimum level voltage terminal; and (ii) between the second other-side terminal of the precharge switch and the second inverting input terminal of the comparator. An nth voltage generating unit including an nth capacitor having an nth side terminal coupled to the nth other side terminal of the nth capacitor, an nth common switch having an nth side terminal coupled to the nth other side terminal of the nth capacitor and the nth other side terminal coupled to the precharge voltage terminal, an nth positive switch having an nth side terminal coupled to the nth other side terminal of the nth capacitor and the nth other side terminal coupled to the maximum level voltage terminal, and an nth negative switch having an nth side terminal coupled to the nth other side terminal of the nth capacitor and the nth other side terminal coupled to the minimum level voltage terminal; and A switch control unit that controls the first voltage generation unit to the nth voltage generation unit in response to output digital data output from the second output terminal of the comparator or n-bit input digital data input to write n-bit data to the memory cell, thereby generating an analog signal corresponding to the output digital data or the n-bit input digital data; A memory device characterized by including a . In Article 10, A memory device, characterized in that when k is an integer greater than or equal to 1 and less than or equal to n, the kth capacitance of the kth capacitor is (the first capacitance of the first capacitor)/2^(k-1). In Article 10, A memory device characterized in that, while the precharge switch maintains an enabled state and the first common switch to the nth common switch maintain an enabled state, the cell mode switch and the feedback switch are enabled in conjunction with a first clock signal of a precharge clock cycle of the precharge mode so that the bit line is precharged by the precharge voltage, and the cell mode switch and the feedback switch are disabled in conjunction with a second clock signal of the precharge clock cycle. In Article 12, In the write mode for storing the n-bit data in the memory cell while the bit line is precharged, In response to a first clock signal of a light mode clock cycle, the precharge switch is disabled, the cell mode switch, the feedback switch, and the memory cell are enabled, and by the switch control unit corresponding to the input n-bit input data, when k is an integer greater than or equal to 1 and less than or equal to n, the k-th common switch of the k-th voltage generation unit is disabled, and one of the k-th positive switch and the k-th negative switch is enabled, so that a specific level voltage corresponding to the n-bit input data generated by the first capacitor to the n-th capacitor is written to the memory cell. A memory device characterized in that, in conjunction with a second clock signal of the light mode clock cycle, the precharge switch is enabled, the cell mode switch, the feedback switch, and the memory cell are disabled, the kth common switch of the kth voltage generation unit is enabled by the switch control unit, and a switch among the kth positive switch and the kth negative switch that was enabled at the time of the first clock signal of the light mode clock cycle is disabled. In Article 12, In a read mode for reading 1-bit data, which is the n-bit data written to the memory cell, while the bit line is precharged, (i) in conjunction with the first clock signal and the second clock signal of the first read mode clock cycle, the memory cell, the cell mode switch, and the sampling switch are enabled so that the operational amplifier outputs an output voltage sensed to a specific voltage level stored in the memory cell through capacitive feedback via the feedback capacitor through the first output terminal, (ii) in conjunction with the first clock signal of the second read mode clock cycle, the memory cell, the cell mode switch, and the sampling switch are disabled, and the flip switch is enabled so that the output voltage outputted through the first output terminal of the operational amplifier is flipped to the specific level voltage, and the comparator is enabled so that the 1-bit data is output by comparing the first reference voltage, which is the precharge voltage applied through the second inverting input terminal, with the specific level voltage applied through the second non-inverting input terminal, and in conjunction with the second clock signal of the second read mode clock cycle, the precharge switch, the A memory device characterized in that the first common switch, the comparator, and the flip switch of the first voltage generation unit are disabled, and (iii) in conjunction with a third read mode clock cycle, one of the first positive switch and the first negative switch of the first voltage generation unit is enabled by the switch control unit corresponding to the 1-bit data output from the second output terminal of the comparator, so that the specific level voltage is regenerated by the first capacitor. In Article 12, In a read mode for reading 2-bit data, which is the n-bit data written to the memory cell, while the bit line is precharged, (i) in conjunction with the first clock signal and the second clock signal of the first read mode clock cycle, the memory cell, the cell mode switch, and the sampling switch are enabled so that the operational amplifier outputs an output voltage sensed to a specific voltage level stored in the memory cell through capacitive feedback via the feedback capacitor through the first output terminal, (ii) (ii_1) in conjunction with the first clock signal of the second read mode clock cycle, the memory cell, the cell mode switch, and the sampling switch are disabled, and the flip switch is enabled so that the output voltage outputted through the first output terminal of the operational amplifier is flipped to the specific level voltage, and the comparator is enabled so that the first priority bit data is output by comparing the first reference voltage, which is the precharge voltage applied through the second inverting input terminal, with the specific level voltage applied through the second non-inverting input terminal, and in conjunction with the second clock signal of the second read mode clock cycle, the The precharge switch, the first common switch of the first voltage generation unit, and the comparator are disabled, (ii_2) in conjunction with the first clock signal of the third read mode clock cycle, one of the first positive switch and the first negative switch of the first voltage generation unit is enabled by the switch control unit corresponding to the first priority bit data output from the second output terminal of the comparator to generate a second reference voltage by the first capacitor and the second capacitor, and the comparator is enabled to output second priority bit data obtained by comparing the second reference voltage applied through the second inverting input terminal with the specific level voltage applied through the second non-inverting input terminal through the second output terminal, and in conjunction with the second clock signal of the third read mode clock cycle, the second common switch of the second voltage generation unit, the comparator, and the flip switch are disabled, (iii) in conjunction with the fourth read mode clock cycle, the A memory device characterized in that one of the second positive switch and the second negative switch of the second voltage generation unit is enabled by the switch control unit corresponding to the second priority bit data output from the second output terminal, so that the specific level voltage is regenerated by the first capacitor and the second capacitor. In Article 12, In a read mode for reading the n-bit data of 3 or more bits written in the memory cell while the bit line is precharged, (i) in conjunction with the first clock signal and the second clock signal of the first read mode clock cycle, the memory cell, the cell mode switch, and the sampling switch are enabled so that the operational amplifier outputs an output voltage sensed to a specific voltage level stored in the memory cell through capacitive feedback via the feedback capacitor through the first output terminal, (ii) (ii_1) in conjunction with the first clock signal of the second read mode clock cycle, the memory cell, the cell mode switch, and the sampling switch are disabled, and the flip switch is enabled so that the output voltage outputted through the first output terminal of the operational amplifier is flipped to the specific level voltage, and the comparator is enabled so that the first priority bit data is output by comparing the first reference voltage, which is the precharge voltage applied through the second inverting input terminal, with the specific level voltage applied through the second non-inverting input terminal, and in conjunction with the second clock signal of the second read mode clock cycle, the The precharge switch, the first common switch of the first voltage generation unit, and the comparator are disabled, and (ii_2) when j is an integer greater than or equal to 2 and less than or equal to (n-1), in conjunction with the first clock signal of the (j+1)th read mode clock cycle, one of the (j-1)th positive switch and the (j-1)th negative switch of the (j-1)th voltage generation unit is enabled by the switch control unit corresponding to the (j-1)th rank bit data output from the second output terminal of the comparator to generate a jth reference voltage by the first capacitor to the nth capacitor, and the comparator is enabled to compare the jth reference voltage applied through the second inverting input terminal with the specific level voltage applied through the second non-inverting input terminal, and in conjunction with the second clock signal of the (j+1)th read mode clock cycle, the jth The common switch and the comparator are disabled, (ii_3) in conjunction with the first clock signal of the (n+1)th read mode clock cycle, one of the (n-1)th positive switch and the (n-1)th negative switch of the (n-1)th voltage generation unit is enabled by the switch control unit corresponding to the (n-1)th rank bit data output from the second output terminal of the comparator to generate an nth reference voltage by the first capacitor to the nth capacitor, the comparator is enabled to compare the nth reference voltage applied through the second inverting input terminal with the specific level voltage applied through the second non-inverting input terminal, and in conjunction with the second clock signal of the (n+1)th read mode clock cycle, the nth common switch of the nth voltage generation unit, the comparator, and the flip switch are disabled, (iii) in conjunction with the (n+2)th read mode clock cycle, A memory device characterized in that, in conjunction with a mode clock cycle, one of the nth positive switch and the nth negative switch of the nth voltage generation unit is enabled by the switch control unit corresponding to the nth bit data output from the second output terminal of the comparator, so that the specific level voltage is regenerated by the first capacitor to the nth capacitor. In any one of Articles 14 to 16, In the refresh mode of the memory cell, in a state where the specific level voltage is regenerated by the first capacitor to the nth capacitor, A memory device, characterized in that in response to a first clock signal of a refresh mode clock cycle, the memory cell, the cell mode switch, and the feedback switch are enabled so that the specific level voltage regenerated by the first capacitor to the nth capacitor is written to the memory cell, and in response to a second clock signal of the refresh mode clock cycle, among the k-th positive switch and the k-th negative switch of the k-th voltage generation unit, a switch that maintains an enabled state at the time of the first clock signal of the refresh mode clock cycle, the memory cell, the cell mode switch, and the feedback switch are disabled, and the precharge switch and the k-th common switch of the k-th voltage generation unit are enabled. In Article 17, A memory device characterized in that the memory cell is enabled and maintained in an enabled state in conjunction with a first clock signal of the first read mode clock cycle, and is disabled in conjunction with a second clock signal of the refresh mode clock cycle.

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