KR102361253B1 - Circuit and method for sensing multi-level voltage of bit line - Google Patents

Abstract

The present invention provides a bit line multi-level voltage sensing circuit for multi-bit operation of a DRAM including a memory cell for storing data by operation of a word line and a bit line. The bit line multi-level voltage sensing circuit includes: a comparator having a first input terminal coupled to a first priority bit voltage source and a second input terminal coupled to the bit line; (i) a first rank bit switch module to (ii) an (n-1)^th rank bit switch module; and a bit voltage selection unit turning on a first common switch to the (n-1)^th common switch of the first rank bit switch module to the (n-1)^th rank bit switch module, sequentially increasing k from 2 to n, turning off the (k-1)^th common switch of the (k-1)^th rank bit switch module, and turning on at least one of a (k-1)^th positive switch and a (k-1)^th negative switch.

Description

CIRCUIT AND METHOD FOR SENSING MULTI-LEVEL VOLTAGE OF BIT LINE

The present invention relates to a bit-line multi-level voltage sensing circuit and method, and more particularly, to a bit-line multi-level voltage sensing circuit and method for reading data stored in a memory cell of a DRAM that stores multi-bit data in one memory cell. A bit line multi-level voltage sensing circuit and method for sensing a voltage.

DRAM, which is a typical device in a semiconductor memory device, stores data in cells composed of one transistor and one capacitor. Depending on whether or not charges are stored in the capacitor, one bit of information, for example, “0” and Store “1”.

In addition, in the DRAM, the word line determines whether to access the capacitor by turning on/off the transistor, and the bit line stores data in the capacitor or reads data stored in the capacitor.

In addition, a sense amplifier is used to read data stored in the capacitor through the bit line from the DRAM, and the sense amplifier is finely divided by charge sharing between the capacitor and the bit line as the transistor is turned on by the word line. Data “1” and “0” are read by amplifying the voltage change of the bit line that is converted to

In the sense amplifier for reading data from the DRAM, a differential inverter is formed between two adjacent bit lines to sense a voltage difference between the two bit lines.

On the other hand, unlike storing one bit information, that is, 1-bit information of “0” or “1” in a cell including one transistor and one capacitor, more than one bit of data is stored in one cell. A multi-level DRAM having an increased data storage capacity has been proposed.

However, in the multi-level DRAM, an analog-to-digital converter for converting the signal output from the sense amplifier into a byte value is required to read multi-bit data, and accordingly, an analog-to-digital converter must be additionally generated inside the DRAM. , it is an obstacle to improving the density of DRAM.

That is, the multi-level DRAM has an advantage of increasing the storage capacity of data for one cell, but on the contrary, it acts as an obstacle to improving the density of the DRAM.

Accordingly, an object of the present invention is to propose a bit-line multi-level voltage sensing circuit and a voltage sensing method capable of increasing a data storage capacity of a DRAM without impeding improvement in the degree of integration of the DRAM.

An object of the present invention is to solve all of the above problems.

Another object of the present invention is to enable a multi-level DRAM to be implemented without impeding the improvement of the degree of integration of the DRAM.

Another object of the present invention is to enable sensing of a bit line multi-level voltage through a digital-converter without using a sense amplifier.

Another object of the present invention is to accurately detect a multi-level voltage of a memory cell of a DRAM without using a sense amplifier.

Another object of the present invention is to enable reading of multi-bit data written in a memory cell of a DRAM using only an analog-to-digital converter without using a sense amplifier.

According to an embodiment of the present invention for achieving the above object, in a bit line multi-level voltage sensing circuit for multi-bit operation of a DRAM including a memory cell for storing data by operation of a word line and a bit line, a first input terminal in the memory cell, where n - the n is an integer greater than or equal to 2 - is an average voltage of the first input voltage and the n-th input voltage at a first input voltage to an n-th input voltage for writing bit data a comparator coupled to a first order bit voltage source for supplying a first order bit voltage and having a second input terminal coupled to the bit line corresponding to the memory cell; (i) a first order bit switch module, each coupled to the bit line in parallel with the memory cell, the first order bit switch module comprising: (i-1) a first capacitor coupled to the bit line; i-2) a first common switch for supplying the first order bit voltage coupled in parallel, a first positive switch for supplying a second order positive bit voltage, and a first for supplying a second order negative bit voltage a negative switch, wherein the first common switch, the first positive switch, and the first negative switch are coupled in series to the first capacitor; to (ii) an (n-1)th rank bit switch module; The (n-1)th order bit switch module includes (ii-1) a (n-1)th capacitor coupled to the bit line, and (ii-2) the first order bit voltage coupled in parallel to each other a (n-1)th common switch supplying wherein the (n-1)th common switch, the (n-1)th positive switch, and the (n-1)th negative switch are coupled in series to the (n-1)th capacitor; and the first common switch to the (n-1)th bit switch module of the first order bit switch module to the (n-1)th order bit switch module in response to a read signal for reading data written in the memory cell Turns on the common switch, sequentially increases k from 2 to n, and turns the (k-1)th common switch of the (k-1)th rank bit switch module in response to the output signal output from the output terminal of the comparator a bit voltage selector which turns off and turns on any one of the (k-1)th positive switch and the (k-1)th negative switch; It is provided as a bit line multi-level voltage sensing circuit comprising a.

In the above, the bit voltage selection unit turns on the (k-1)th negative switch of the (k-1)th rank bit switch module when the (k-1)th rank bit value is a positive bit value, When the (k-1)th rank bit value is a negative bit value, the (k-1)th positive switch of the (k-1)th rank bit switch module may be turned on.

In the above, when the maximum range of the input voltage corresponding to the first input voltage to the n-th input voltage is a full-scale voltage, the k-th order positive bit voltage is (the first order bit voltage) + (the full-scale voltage) voltage/2^k) x (cell capacitance of the memory cell/(k-1)th capacitance of the (k-1)th capacitor), and the kth order negative bit voltage is (the first order bit voltage) - (the full-scale voltage/2^k) x (the cell capacitance of the memory cell/the (k-1)th capacitance of the (k-1)th capacitor).

In the above, when the maximum range of the input voltage corresponding to the first input voltage to the n-th input voltage is a full-scale voltage, the k-th capacitance of the k-th capacitor is (the first capacitance of the first capacitor)/2 If ^(k-1), the third order positive bit voltage to the nth order positive bit voltage are the same as the second order positive bit voltage, and the third order negative bit voltage to the nth order negative bit voltage are the equal to the second order negative bit voltage, and the second order positive bit voltage is (the first order bit voltage) + (the full scale voltage/4) x (cell capacitance of the memory cell/the second order bit voltage of the first capacitor) 1 capacitance), and the second order negative bit voltage may be (the first order bit voltage) - (the full scale voltage/4) x (cell capacitance of the memory cell/first capacitance of the first capacitor) .

In the above, the first capacitance of the first capacitor to the (n-1)th capacitance of the (n-1)th capacitor may be equal to the cell capacitance of the memory cell or 1/2 of the cell capacitance.

In the above, the comparator is enabled by the read signal to output a first rank bit value and then disabled, and the bit voltage selector is a (k-1)th rank bit switch module of the (k-1)th rank bit switch module. ) may be enabled in response to an operation of turning on any one of the positive switch and the (k-1)th negative switch to output the kth order bit value and then disabled.

In the above, the first priority bit voltage source coupled to the first input terminal of the comparator is a bit line different from the bit line corresponding to the memory cell - the other bit line is a bit line in which a dummy cell is formed, or a memory It may be a bit line to which the first priority bit voltage is applied without charge sharing by cells.

According to another embodiment of the present invention, in a method of sensing a bit line multi-level voltage for a multi-bit operation of a DRAM including a memory cell storing data by operation of a word line and a bit line, (a) n the bit line - wherein n is an integer greater than or equal to 2 - A first order bit voltage that is an average voltage of the first input voltage and the n-th input voltage in a first input voltage to an n-th input voltage for writing bit data is precharged to, and through each of the first order bit switch module to the (n-1)th order bit switch module coupled in parallel with the memory cell to the bit line, the respective first order bit voltages are transferred to the respective first capacitors through the (n-1)th capacitor; (b) in response to a read signal for reading the n-bit data stored in the memory cell, the memory cell is made to conduct with the bit line by using the word line, and the first changed by conduction of the memory cell generating a first order bit value by detecting a bit line voltage and comparing the first bit line voltage with the first order bit voltage; and (c) sequentially increasing k from 2 to n, and when the (k-1)th rank bit value is a positive bit value, the (k-1)th rank bit through the (k-1)th rank bit switch module The kth order negative bit voltage is supplied instead of the first order bit voltage in the switch module, and when the (k-1)th order bit value is a negative bit value, the (k-1)th order bit voltage is supplied through the switch module A changed k-th bit line voltage is detected by supplying a k-th positive bit voltage instead of a first-order bit voltage in the (k-1)-th bit switch module, and the k-th bit line voltage and the first order bit generating a kth order bit value by comparing it with the voltage; There is provided a bit line multi-level voltage sensing method comprising a.

In the above, when the maximum range of the input voltage corresponding to the first input voltage to the nth input voltage is a full scale voltage, the kth order positive bit voltage is (the first order bit voltage) + (the full scale voltage) voltage/2^k) x (cell capacitance of the memory cell/(k-1)th capacitance of the (k-1)th capacitor), and the kth order negative bit voltage is (the first order bit voltage) - (the full-scale voltage/2^ k) x (the cell capacitance of the memory cell/the (k-1)th capacitance of the (k-1)th capacitor).

According to another embodiment of the present invention, there is further provided a DRAM including the bit line multi-level sensing circuit.

According to the present invention, the following effects are obtained.

According to the present invention, it is possible to implement a multi-level DRAM without hindering the improvement of the density of the DRAM.

According to the present invention, a bit line multi-level voltage can be sensed through a digital-converter without using a sense amplifier.

According to the present invention, it is possible to accurately detect a multi-level voltage of a memory cell of a DRAM without using a sense amplifier.

According to the present invention, multi-bit data written in a memory cell of a DRAM can be read using only an analog-to-digital converter without using a sense amplifier.

1 schematically shows a DRAM including a bit line multi-level voltage sensing circuit according to an embodiment of the present invention;
2 schematically shows a bit line multi-level voltage sensing circuit according to an embodiment of the present invention;
3 is a time graph schematically illustrating an operation process of a bit line multi-level voltage sensing circuit according to an embodiment of the present invention;
4 schematically shows a setting state for a memory cell voltage for writing and reading 3-bit data according to an embodiment of the present invention;
5A and 5B show an example in which a bit line multi-level sensing circuit according to an embodiment of the present invention is configured to be used for writing and reading 3-bit data;
6 schematically illustrates a state in which 3-bit data is read according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0010] Reference is made to the accompanying drawings, which show by way of illustration specific embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain shapes, structures, and characteristics described herein with respect to one embodiment may be implemented in other embodiments without departing from the spirit and scope of the invention. In addition, it should be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the present invention. Accordingly, the detailed description set forth below is not intended to be taken in a limiting sense, and the scope of the present invention, if properly described, is limited only by the appended claims, along with all scope equivalents as those claimed. Like reference numerals in the drawings refer to the same or similar functions throughout the various aspects.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to enable those of ordinary skill in the art to easily practice the present invention.

1 schematically illustrates a DRAM including a bit line multi-level voltage sensing circuit according to an embodiment of the present invention.

Referring to FIG. 1 , the DRAM 100 includes a plurality of bit lines BL0, BL1, BL2, ... and a plurality of word lines WL0, WL1, WL2, ..., and each It may include memory cells C ₀ generated by a bit line and each word line.

In this case, each memory cell may include one transistor and one capacitor. In addition, whether to access the memory cell is determined by the word line, and n-bit data may be written to the memory cell or n-bit data written to the memory cell may be read by the bit line. The n may be an integer of 2 or more.

In addition, each bit line includes a digital-to-analog converter 10 for inputting an input voltage corresponding to n-bit data to a memory cell and an analog-to-digital converter 20 for reading n-bit data written in the memory cell. can be combined.

At this time, the digital-to-analog converter 10 converts n-bit data to be written in the memory cell into an analog signal. A specific input voltage corresponding to specific n-bit data among the first input voltage to 2^n input voltage set for data input is applied to the bit line, so that the memory cell is charged with a charge corresponding to the specific input voltage. have.

In addition, the analog-to-digital converter 20 converts a cell voltage according to the charges charged in the memory cell into a digital signal of n-bit data, and detects the voltage of the memory cell whose access is selected by the word line, and the detected cell It is possible to read n-bit data according to the voltage.

Hereinafter, a bit line multi-level voltage sensing circuit according to an embodiment of the present invention including the analog-to-digital converter 20 will be described in more detail.

2 schematically illustrates a bit line multi-level voltage sensing circuit according to an embodiment of the present invention.

Referring to FIG. 2 , the bit line multi-level voltage sensing circuit 20 includes a comparator 21 and a first rank bit switch module 22_1 to (n-1) rank bit switch module 22_(n-1)) , and a bit voltage selector 23 .

First, the comparator 21 has a first input terminal coupled to a first order bit voltage source for supplying a first order bit voltage V _M , and a second input end of the bit line BL corresponding to the memory cell C ₀ . may be coupled to , and may output a binary bit value according to a voltage difference between the first input terminal and the second input terminal.

In this case, the first priority bit voltage V _M is the first input voltage and the second ^n input voltage in the first input voltage to the 2^n input voltage for writing n-bit data to the memory cell C ₀ . may be the average voltage of That is, the first priority bit voltage V _M may be expressed as (2^n second input voltage - first input voltage)/2.

In addition, the first priority bit voltage (V _M ) is the minimum scale voltage and the maximum scale voltage when the maximum range of the input voltage corresponding to the first input voltage to the second ^ n input voltage is the full scale voltage (V _FS ). may be the average voltage of That is, the full scale voltage V _FS may be expressed as (maximum scale voltage - minimum scale voltage)/2. In this case, the minimum scale voltage may be a voltage obtained by subtracting a least significant bit (LSB) voltage from the first input voltage, and the maximum scale voltage may be a voltage obtained by adding a least significant bit voltage to the 2^n second voltage.

In addition, the first order bit voltage source supplying the first order bit voltage V _M is a bit line different from the bit line BL corresponding to the memory cell C ₀ , and is a bit line in which a dummy cell is formed, or a memory cell C 0 . It may be a bit line to which the first priority bit voltage V _M is applied without charge sharing by the cell.

Next, the first rank bit switch module 22_1 to the (n-1)th rank bit switch module 22_(n-1) are respectively coupled in parallel with the memory cell C ₀ to the bit line BL. can

And, each of the first rank bit switch module 22_1 to (n-1) rank bit switch module 22_(n-1)) is a respective first capacitor coupled to the bit line BL (C ₁ ) to (n-1)th capacitor C _(n-1) ).

In addition, each of the first rank bit switch module 22_1 to the (n-1) rank bit switch module 22_(n-1) is coupled to each other in parallel and each common to each capacitor coupled in series switch, positive switch, and negative switch.

That is, the (k-1)th order switch module includes a (k-1)th common switch for supplying a first order bit voltage, a kth positive switch for supplying a kth order positive bit voltage, and a kth order negative bit voltage It may include a kth negative switch for supplying The k may be an integer of 2 or more and n or less.

For example, the first priority switch module 22_1 includes a first common switch S ₁ for supplying a first priority bit voltage V _M , and a first positive switch for supplying a second priority positive bit voltage V _P1 . (S _P1 ), and a first negative switch (S _N1 ) for supplying a second rank negative bit voltage (V _N1 ), (n-1) rank switch module 22_(n-1)) is the (n-1)th common switch (S _(n-1) ) for supplying the first order bit voltage (V _M ), the (n-1)th for supplying the nth order positive bit voltage (V _P(n-1) ) n-1) a positive switch S _{P (n-1)} , and an (n-1)th negative switch S _N(n- 1) supplying an nth order negative bit voltage V _N(n-1) ) ₎ ) may be included.

In this case, the kth order positive bit voltage and the kth order negative bit voltage may be expressed as follows.

kth order positive bit voltage = (first order bit voltage) + (full scale voltage/2^k) x (cell capacitance of memory cell/(k-1)th capacitance of (k-1)th capacitor)

kth order negative bit voltage = (first order bit voltage) - (full scale voltage/2^k) x (cell capacitance of memory cell/(k-1)th capacitance of (k-1)th capacitor)

On the other hand, if the kth capacitance of the kth capacitor is (the first capacitance of the first capacitor)/2^(k-1), the third order positive bit voltage to the nth order positive bit voltage is the second order positive bit The voltage may be the same, and the third order negative bit voltage to the nth order negative bit voltage may be the same as the second order negative bit voltage.

In addition, the second order positive bit voltage may be (first order bit voltage) + (full scale voltage/4) x (cell capacitance of the memory cell/first capacitance of the first capacitor), and the second order negative bit voltage may be (first order bit voltage) - (full scale voltage/4) x (cell capacitance of the memory cell/first capacitance of the first capacitor).

In addition, the first capacitance of the first capacitor to the (n-1)th capacitance of the (n-1)th capacitor may be equal to the cell capacitance of the memory cell or 1/2 of the cell capacitance.

Next, the bit voltage selector 23 corresponds to a read signal for reading data written in the memory cell, the first order bit switch module 22_1 to (n-1)th order bit switch module 22_(n) -1)) of the first common switch to (n-1)th common switch is turned on, k is sequentially increased from 2 to n, and in response to the output signal output from the output terminal of the comparator 21, the (k-th)th common switch is turned on. -1) The (k-1)th common switch of the rank bit switch module may be turned off, and any one of the (k-1)th positive switch and the (k-1)th negative switch may be turned on.

At this time, when the (k-1)th rank bit value is a positive bit value, the bit voltage selector 23 turns on the (k-1)th negative switch of the (k-1)th rank bit switch module, k-1) When the rank bit value is a negative bit value, the (k-1)th positive switch of the (k-1)th rank bit switch module may be turned on.

On the other hand, the comparator 21 is enabled by a read signal for reading n-bit data written in the memory cell to output a first-order bit value and then disabled, and the bit voltage selector 23 selects the (k-th)th bit. -1) is enabled in response to an operation of turning on any one of the (k-1)th positive switch and the (k-1)th negative switch of the rank bit switch module to output the kth rank bit value and then to be disabled can

A process of reading n-bit data stored in a memory cell using the bit line multi-level voltage sensing circuit according to an embodiment of the present invention configured as described above will be described in more detail with reference to FIGS. 2 and 3 as follows. .

In a state in which the switch P ₂ is turned on through the word line WL to access the memory cell C ₀ for writing data, the first input voltage to the second ^ for writing n-bit data Among the n input voltages, a specific input voltage for writing specific n-bit data is input to the bit line BL so that the memory cell C ₀ is charged with a charge corresponding to the specific input voltage _. It is possible to cause specific n-bit data to be written.

In this state, the bit line BL is precharged to the first order bit voltage V _M , and the first order bit switch modules 22_1 to ( n-1) each of the first rank bit voltages (V _M ) through each of the rank bit switch module 22_(n- ₁ )) _(n-1) ) can be supplied.

That is, in response to the precharging signal for reading specific n-bit data written in the memory cell C ₀ , the memory turns on the switch P ₁ t ₀ , and converts the first bit voltage to the pre-charging voltage ( V _M ) is applied to the bit line BL, and the bit voltage selector 23 or the memory uses the first rank bit switch module 22_1 to (n-1) rank bit switch module 22_(n-1). )) of the first common switch (S ₁ ) to (n-1)th common switch (S _(n-1) ) is turned on (t ₀ ) to turn on each of the first capacitors (C ₁ ) to the n-th capacitors (C) The first order bit voltage V _M may be applied to _(n-1) ).

In this case, the amount of charge in the capacitors corresponding to the bit line BL may be expressed as follows.

Q ₁ = C _P V _M + C ₀ V _cell + C ₁ (V _M - V _M ) + C ₂ (V _M - V _M ) + … + C _(n-1) (V _M - V _M )

In the above, V _CELL may be a cell voltage of the memory cell, and _CP may be a parasitic capacitor generated in the bit line BL.

Next, the switch P ₁ is turned off (t ₁ ) in response to a read signal for reading specific n-bit data stored in the memory cell C0, and the memory cell C ₀ using the word line WL. ) of the switch P ₂ is turned on (t ₁ ) so that the memory cell C ₀ conducts with the bit line BL, so that charge sharing is achieved in the bit line BL by the memory cell C ₀ . can make it go away Through this, it is possible to detect the bit line voltage changed by the charge sharing.

That is, when the changed voltage of the bit line BL due to charge sharing is the first bit line voltage V ₁ , the amount of charges in the capacitors corresponding to the charge-sharing bit line BL is as follows. can be shown.

Q ₂ = (C _P + C ₀ )V ₁ + C ₁ (V ₁ - V _M ) + C ₂ (V ₁ - V _M ) + … + C _(n-1) (V ₁ - V _M )

Accordingly, since Q1 and Q2 must be equal to each other according to the law of conservation of charge amount, the relational expression between charge amount before and after charge sharing can be expressed as follows.

C _P V _M + C ₀ V _cell = (C _P + C ₀ )V ₁ + C ₁ (V ₁ - V _M ) + C ₂ (V ₁ - V _M ) + … + C _(n-1) (V ₁ - V _M )

And, from the above relational expression, the first bit line voltage V ₁ may be expressed as follows.

In the above, C _total is the total capacitance C _total = C _P + C ₀ + C ₁ + C ₂ + . + C _(n-1) .

Next, the first order bit value may be generated by comparing the first bit line voltage changed by the conduction of the memory cell with the first order bit voltage.

That is, by enabling the comparator 21 (t ₂ ), the comparator 21 compares the first bit line voltage (V ₁ ) with the first order bit voltage (V _M ) and outputs the first order bit value ( D _out ) can be made. Then, the comparator 21 may be disabled after outputting the first priority bit value.

At this time, the comparator 21 outputs a positive bit value when the first bit line voltage V ₁ is greater than the first priority bit voltage V _M , and the first bit line voltage V ₁ is the first priority When it is less than the bit voltage V _M , a negative bit value may be output. In addition, when the first bit line voltage V ₁ and the first priority bit voltage V _M are the same, any one of a positive bit value and a negative bit value may be output.

Next, the bit voltage selection unit 23 turns off the first common switch S ₁ of the first order bit switch module 22_1 according to the first order bit value output from the comparator 21 (t ₃ ) And, the first positive switch (S _P1 ) and the first negative switch (S _N1 ) of any one switch (S _X1 ) is turned on (t ₃ ) to the first capacitor (C ₁ ) to the second order positive bit voltage ( V _P1 ) and the second order negative bit voltage V _N1 , any one voltage V _X1 may be applied.

At this time, instead of the first order bit voltage (V _M ) to the first capacitor (C ₁ ), any one voltage (V _X1 ) of the second order positive bit voltage (V _P1 ) and the second order negative bit voltage (V _N1 ) As this is applied, the first bit line voltage V ₁ of the bit line BL is changed. When the changed voltage of the bit line BL is referred to as the second bit line voltage V ₂ , the second bit line voltage V 1 is applied. (V ₂ ) can be expressed as follows.

That is, the amount of charge Q3 in a state in which the voltage of the bit line BL is changed from the first bit line voltage V ₁ to the second bit line voltage V ₂ may be expressed as follows.

Q ₃ = (C _P + C ₀ )V ₂ + C ₁ (V ₂ - V _X1 ) + C ₂ (V ₂ - V _M ) + … + C _(n-1) (V ₂ - V _M )

Accordingly, the second bit line voltage V ₂ may be expressed as described above from the relationship with the charge amount Q ₂ in the first bit line voltage V ₁ .

This can be expressed in another form as follows.

At this time, the bit voltage selector 23 turns on the first negative switch S _N1 when the first order bit value output from the comparator 21 is a positive bit value, and the second order negative bit voltage V _N1 is the second order 1 to be applied to the capacitor (C ₁ ), and when the first order bit value is a negative bit value, the first positive switch (S _P1 ) is turned on to turn on the second order positive bit voltage (V _P1 ) to the first capacitor (C ₁ ) can be approved for

Next, a second bit value may be generated by comparing the changed second bit line voltage with the first bit voltage.

That is, by enabling the comparator 21 , the comparator 21 compares the second bit line voltage V ₂ with the first order bit voltage V _M to output the second order bit value D _out . can do. Then, the comparator 21 may be disabled after outputting the second priority bit value.

At this time, the comparator 21 outputs a positive bit value when the second bit line voltage V ₂ is greater than the first order bit voltage V _M , and the second bit line voltage V ₂ has the first order When it is less than the bit voltage V _M , a negative bit value may be output.

Next, the bit voltage selection unit 23 turns off the first common switch S ₁ of the second order bit switch module 22_2 according to the second order bit value output from the comparator 21 (t ₄ ) And, the second positive switch (S _P2 ) and the second negative switch (S _N2 ) of any one switch (S _X2 ) is turned on (t ₄ ) to the second capacitor (C ₂ ) in the third order positive bit voltage ( V _P2 ) and the third order negative bit voltage V _N2 , any one voltage V _X2 may be applied.

At this time, any one of the third order positive bit voltage (V _P2 ) and the third order negative bit voltage (V _N2 ) instead of the first order bit voltage (V _M ) to the second capacitor (C ₂ ) Voltage (V _X2 ) As this is applied, the second bit line voltage V ₂ of the bit line BL is changed. When the changed voltage of the bit line BL is referred to as the third bit line voltage V ₃ , the third bit line voltage V 2 is applied. (V ₃ ) can be expressed as follows.

That is, the charge amount Q4 in a state in which the voltage of the bit line BL is changed from the second bit line voltage V ₂ to the third bit line voltage V ₃ may be expressed as follows.

Q ₄ = (C _P + C ₀ )V ₃ + C ₁ (V ₃ - V _X1 ) + C ₂ (V ₃ - V _X2 ) + … + C _(n-1) (V ₃ - V _M )

Accordingly, the third bit line voltage V ₃ may be expressed as described above from the relationship with the charge amount Q ₃ in the first bit line voltage V ₂ .

This can be expressed in another form as follows.

At this time, the bit voltage selector 23 turns on the second negative switch S _N2 when the second order bit value output from the comparator 21 is a positive bit value, so that the third order negative bit voltage V _N2 is the first 2 to be applied to the capacitor (C ₂ ), and when the second order bit value is a negative bit value, the second positive switch (S _P2 ) is turned on to turn on the third order positive bit voltage (V _P2 ) to the second capacitor (C ₂ ) can be approved for

Next, a third order bit value may be generated by comparing the changed third bit line voltage with the first order bit voltage.

That is, by enabling the comparator 21 , the comparator 21 compares the third bit line voltage V ₃ with the first order bit voltage V _M and outputs the third order bit value D _out . can do. Then, the comparator 21 may be disabled after outputting the third priority bit value.

In this case, the comparator 21 outputs a positive bit value when the third bit line voltage V ₃ is greater than the first priority bit voltage V _M , and the third bit line voltage V ₃ is the first priority bit voltage V 3 . When it is less than the bit voltage V _M , a negative bit value may be output.

In a state in which the (n-1)th rank bit value is obtained by repeating the above operation, the bit voltage selector 23 operates according to the (n-1)th rank bit value output from the comparator 21 , the (n-1)th rank bit value. -1) turn off (t _(n+1) ) the first common switch S _(n-1) of the rank bit switch module 22_(n-1)), and the (n-1)th positive switch ( S _{P (n-1)} ) and (n-1) th negative switch S _{N (n-1)} ) turn on any one switch (S _X(n-1) ) (t _(n+1) ) to the (n-1)th capacitor (C _(n-1) ) of the nth order positive bit voltage (V _P(n-1) ) and the nth order negative bit voltage (V _{N (n-1)} ) One voltage V _X(n-1) may be applied.

At this time, instead of the first order bit voltage (V _M ) to the (n-1)th capacitor (C _(n-1) ), the nth order positive bit voltage (V _P(n-1) ) and the nth order negative bit voltage When any one voltage V _X(n-1) of (V _{N (n-} 1) ) is applied, the (n-1)th bit line voltage V _(n-1) of the bit line BL becomes When the changed voltage of the bit line BL is referred to as an n-th bit line voltage V _n , the n-th bit line voltage V _n may be expressed as follows.

At this time, the bit voltage selector 23 turns on the (n-1)th negative switch S _N(n-1) when the (n-1)th rank bit value output from the comparator 21 is a positive bit value. so that the nth rank negative bit voltage V _{N (n-1)} ) is applied to the (n-1)th capacitor C _(n-1) , and the (n-1) rank bit value is the negative bit value When the (n-1)th positive switch (S _{P (n-1)} ) is turned on, the nth order positive bit voltage (V _P(n-1) ) is the (n-1)th capacitor (C _(n-1 ) ₎ ) can be approved.

Next, the nth order bit value may be generated by comparing the changed nth bit line voltage with the first order bit voltage.

That is, by enabling the comparator 21 , the comparator 21 compares the n-th bit line voltage V _n with the first-order bit voltage V _M to output the n-th bit value D _out . can do. Then, the comparator 21 may be disabled after outputting the nth order bit value.

In this case, the comparator 21 outputs a positive bit value when the n-th bit line voltage V _n is greater than the first-order bit voltage V _M , and the n-th bit line voltage V _n is the first-order bit line voltage V n . When it is less than the bit voltage V _M , a negative bit value may be output.

Through this operation, n-bit data stored in the memory cell can be read by detecting the first bit value to the n-th bit value.

Meanwhile, a method of setting the first order bit voltage to the nth order bit voltage will be described as follows.

As described above, the first bit line voltage V ₁ to the n-th bit line voltage V _n changed according to the operation for reading n-bit data may be expressed as follows.

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으로 나타내어질 수 있다.above,

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can be expressed as

Accordingly, the first order bit voltage is V _M , and the kth order positive bit voltage (V _P(k-1) ) and the kth order negative bit voltage (V _N(k-1) ) can be expressed as have.

An example in which the bit line multi-level voltage sensing circuit for reading the n-bit data configured as described above is applied to 3-bit data will be described with reference to FIGS. 4 to 6 as follows. Hereinafter, detailed description of parts that can be easily understood from the above description will be omitted.

First, referring to FIG. 4 , the input voltage for 3-bit data, that is, the memory cell voltage, is set to eight input voltages from 0V to 0.7V in units of 0.1V, and the full-scale voltage (V _FS ) may be 0.8V, and the first order bit voltage VM may be 0.35V.

Next, referring to FIGS. 5A and 5B , as a sensing circuit for reading 3-bit data, the first priority switch module 22_1 and the second priority switch module 22_2 are respectively connected to the bit line BL in parallel with the memory cell. ) can be coupled in parallel.

In this case, the first capacitor of the first priority switch module 22_1 and the second capacitor of the second priority switch module 22_2 have the same capacitance as the capacitance of the memory cell, or the first capacitor has the same capacitance as the capacitance of the memory cell To have a capacitance, the second capacitor may be set to have a capacitance of 1/2 of the capacitance of the memory cell.

In addition, the set second order bit voltage and third order bit voltage of the first capacitor and the second capacitor may be set using the following relational expression.

That is, referring to FIG. 5A , the capacitances of the first capacitor and the second capacitor are configured to be the same as the capacitance of the memory cell.

At this time, the second order positive bit voltage becomes 0.35V + 0.8V/4 = 0.55V, and the second order negative bit voltage becomes 0.35V - (0.8V)/4 = 0.15V.

In addition, the third order positive bit voltage becomes 0.35V + 0.8V/8 = 0.45V, and the third order positive bit voltage becomes 0.35V - 0.8V/8 = 0.25V.

Meanwhile, referring to FIG. 5B , the capacitance of the first capacitor is configured to be the same as the capacitance of the memory cell, and the capacitance of the second capacitor is configured to be 1/2 the capacitance of the memory cell.

In this case, the second order positive bit voltage and the third order positive bit voltage are equal to 0.55V, and the second order negative bit voltage and the third order negative bit voltage are equal to 0.15V.

Next, a process of reading 3-bit data written in a memory cell will be briefly described with reference to FIG. 6 .

First, when charge-sharing is performed by the memory cells in a state in which the first common switch S1 and the second common switch S2 are turned on, the first bit line voltage V ₁ is as follows.

Accordingly, the comparator 21 detects whether the first bit line voltage V ₁ is greater than the first order bit voltage V _M . This is expressed as:

That is, the comparator 21 checks whether the voltage of the memory cell is greater than the first priority bit voltage.

At this time, when the voltage of the memory cell is 0.2V, since the voltage of the memory cell is 0.2V is less than the first order bit voltage of 0.35V, a negative bit value, for example, “0” is output as the first order bit value.

Then, the bit voltage selector 23 turns off the first common switch S ₁ and turns on the first positive switch S _P1 according to the output value of “0”.

In this case, the second bit line voltage V ₂ may be expressed as follows.

Therefore, the comparator 21 checks whether V _cell + V _FS /4 = 0.2V + 0.8V/4 = 0.4V is greater than the first order bit voltage of 0.35V, and as a result, a positive bit value, for example “ 1” is output as the second priority bit value. That is, it is checked whether the changed memory cell voltage is greater than the first order bit voltage by adding V _FS /4 to the voltage of the memory cell.

Then, the bit voltage selector 23 turns off the second common switch S ₂ and turns on the second negative switch S _N2 according to the output value of “1”.

In this case, the third bit line voltage V ₃ may be expressed as follows.

Therefore, the comparator 21 checks whether V _cell + V _FS /4 + V _FS /8 = 0.2V + 0.8V/4 - 0.8V/8 = 0.3V is greater than the first order bit voltage 0.35V, As a result, a negative bit value, for example, “0” is output as the third priority bit value.

In this way, 3-bit data of “010” is read with respect to a memory cell voltage of 0.2V.

On the other hand, when the voltage of the memory cell is 0.5V, (i) 0.5V is compared with 0.35V, and as a result, “1” is output as the first priority bit value, (ii) the output value is “1”, 0.3V by subtracting 08V/4 from 0.5V is compared with 0.35V, and as a result, “0” is output as the second bit value, (iii) Since the output value is “0”, 0.8V/8 to 0.3V By adding 0.4V to 0.35V and outputting “1” as the third priority bit value as a result, 3-bit data of “101” corresponding to 0.5V is read.

That is, according to an embodiment of the present invention, in the absence of a sense amplifier for separately sensing the voltage of the memory cell, the voltage of the memory cell is gradually converged to the first bit voltage and can be converted into a digital code.

In addition, the embodiments according to the present invention described above may be implemented in a DRAM to allow the DRAM to perform a multi-bit operation.

In the above, the present invention has been described with specific matters such as specific components and limited embodiments and drawings, but these are provided to help a more general understanding of the present invention, and the present invention is not limited to the above embodiments. , various modifications and variations can be devised from these descriptions by those of ordinary skill in the art to which the present invention pertains.

Therefore, the spirit of the present invention should not be limited to the above-described embodiments, and not only the claims described below but also all modifications equivalently or equivalently to the claims described below belong to the scope of the spirit of the present invention. will do it

100: DRAM,
10: digital-to-analog converter;
20: analog-to-digital converter;
21: comparator,
22_1 to 22_(n-1): a first rank bit switch module to (n-1) rank bit switch module;
23: bit voltage selector

Claims (10)

A bit line multi-level voltage sensing circuit for multi-bit operation of a DRAM including a memory cell storing data by operation of a word line and a bit line, the bit line multi-level voltage sensing circuit comprising:
a first input terminal in the memory cell, where n - the n is an integer greater than or equal to 2 - the first input voltage and the 2^n input voltage at a first input voltage to 2^n input voltage for writing bit data a comparator coupled to a first order bit voltage source for supplying a first order bit voltage that is an average voltage of , and a second input terminal coupled to the bit line corresponding to the memory cell;
(i) a first order bit switch module, each coupled to the bit line in parallel with the memory cell, the first order bit switch module comprising: (i-1) a first capacitor coupled to the bit line; i-2) a first common switch for supplying the first order bit voltage coupled in parallel, a first positive switch for supplying a second order positive bit voltage, and a first for supplying a second order negative bit voltage a negative switch, wherein the first common switch, the first positive switch, and the first negative switch are coupled in series to the first capacitor; to (ii) an (n-1)th rank bit switch module; The (n-1)th order bit switch module includes (ii-1) a (n-1)th capacitor coupled to the bit line, and (ii-2) the first order bit voltage coupled in parallel to each other a (n-1)th common switch supplying wherein the (n-1)th common switch, the (n-1)th positive switch, and the (n-1)th negative switch are coupled in series to the (n-1)th capacitor; and
In response to a read signal for reading data written in the memory cell, the first common switch to the (n-1) common switch of the first order bit switch module to the (n-1)th order bit switch module Turns on the switch, sequentially increases k from 2 to n, and turns off the (k-1)th common switch of the (k-1)th rank bit switch module in response to the output signal output from the output terminal of the comparator a bit voltage selector for turning on any one of the (k-1)th positive switch and the (k-1)th negative switch;
A bit line multi-level voltage sensing circuit comprising a. According to claim 1,
The bit voltage selector,
turning on the (k-1)th negative switch of the (k-1)th rank bit switch module when the (k-1)th rank bit value is a positive bit value;
A bit line multi-level voltage sensing circuit for turning on the (k-1)th positive switch of the (k-1)th rank bit switch module when the (k-1)th rank bit value is a negative bit value. According to claim 1,
When the maximum range of the input voltage corresponding to the first input voltage to the second ^ n input voltage is a full-scale voltage,
The kth order positive bit voltage is (the first order bit voltage) + (the full scale voltage/2^k) x (cell capacitance of the memory cell/(k-1)th capacitance of the (k-1)th capacitor ) and
The kth order negative bit voltage is (the first order bit voltage) - (the full scale voltage/2^k) x (the cell capacitance of the memory cell/the (k-)th of the (k-1)th capacitor 1) a bit-line multi-level voltage sensing circuit with capacitance). According to claim 1,
When the maximum range of the input voltage corresponding to the first input voltage to the second ^ n input voltage is a full-scale voltage,
If the kth capacitance of the kth capacitor is (the first capacitance of the first capacitor)/2^(k-1),
The third order positive bit voltage to the nth order positive bit voltage are the same as the second order positive bit voltage, and the third order negative bit voltage to the nth order negative bit voltage are the same as the second order negative bit voltage do,
a second order positive bit voltage is (the first order bit voltage) + (the full scale voltage/4) x (cell capacitance of the memory cell/the first capacitance of the first capacitor),
A second order negative bit voltage is (the first order bit voltage) - (the full scale voltage/4) x (cell capacitance of the memory cell/first capacitance of the first capacitor) bit line multi-level voltage sensing circuit . According to claim 1,
A bit line multi-level voltage sensing circuit in which the first capacitance of the first capacitor to the (n-1)th capacitance of the (n-1)th capacitor are equal to or 1/2 of the cell capacitance of the memory cell . According to claim 1,
The comparator is
It is enabled by the read signal to output the first priority bit value and then disabled,
The bit voltage selector is enabled in response to an operation of turning on any one of a (k-1)th positive switch and a (k-1)th negative switch of the (k-1)th order bit switch module to be enabled in the kth A bit line multi-level voltage sensing circuit that is disabled after outputting the rank bit value. According to claim 1,
The first priority bit voltage source coupled to the first input terminal of the comparator is a bit line different from the bit line corresponding to the memory cell, wherein the other bit line is a bit line on which a dummy cell is formed, or A bit line to which the first order bit voltage is applied without charge sharing - an in-bit line multi-level voltage sensing circuit. A method of sensing a bit line multi-level voltage for a multi-bit operation of a DRAM including a memory cell storing data by operation of a word line and a bit line, the method comprising:
(a) n of the bit line - wherein n is an integer greater than or equal to 2 - Average of the first input voltage and the 2^n input voltage at a first input voltage to 2^n input voltage for writing bit data Pre-charging with a first order bit voltage that is a voltage, and through each of the first order bit switch module to the (n-1)th order bit switch module coupled in parallel with the memory cell to the bit line, each first order bit causing voltages to be supplied through each of the first to (n-1)th capacitors;
(b) in response to a read signal for reading the n-bit data stored in the memory cell, the memory cell is made to conduct with the bit line by using the word line, and the first changed by conduction of the memory cell generating a first order bit value by detecting a bit line voltage and comparing the first bit line voltage with the first order bit voltage; and
(c) sequentially increasing k from 2 to n, and when the (k-1)th rank bit value is a positive bit value, the (k-1)th rank bit is switched through the (k-1)th rank bit switch module A kth order negative bit voltage is supplied instead of the first order bit voltage in the module, and when the (k-1)th order bit value is a negative bit value, the (k-1)th order bit switch module is used to supply the kth order bit voltage. (k-1) detecting a changed k-th bit line voltage by supplying a k-th positive bit voltage instead of a first-order bit voltage in the order bit switch module, and the k-th bit line voltage and the first order bit voltage generating a kth rank bit value by comparing with ;
A bit line multi-level voltage sensing method comprising a. 9. The method of claim 8,
When the maximum range of the input voltage corresponding to the first input voltage to the second ^ n input voltage is a full-scale voltage,
The kth order positive bit voltage is (the first order bit voltage) + (the full scale voltage/2^k) x (cell capacitance of the memory cell/(k-1)th capacitance of the (k-1)th capacitor ) and
The kth order negative bit voltage is (the first order bit voltage) - (the full scale voltage/2^k) x (the cell capacitance of the memory cell/the (k-)th of the (k-1)th capacitor 1) How to be capacitance). A DRAM comprising the bit line multi-level sensing circuit according to any one of claims 1 to 7.

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