WO2024212509A1 - Command generation circuit and memory - Google Patents

Abstract

The present disclosure provides a command generation circuit and a memory. A first sampling circuit is used for performing sampling processing on a first command signal according to a first clock signal to obtain a first intermediate signal; a base delay circuit is used for performing sampling and shifting processing on the first intermediate signal according to a first control signal and the first clock signal to obtain a second intermediate signal; a second sampling circuit is used for performing setting processing on the second sampling circuit according to the first intermediate signal, and performing sampling processing on the second intermediate signal according to the first clock signal to obtain a third intermediate signal; and a command adjustment circuit is used for performing pulse-width adjustment processing on the first command signal according to the first intermediate signal and the third intermediate signal to obtain a second command signal.

Description

A command generation circuit and memory

CROSS-REFERENCE TO RELATED APPLICATIONS

This disclosure claims the priority of the Chinese patent application filed with the Chinese Patent Office on April 11, 2023, with application number 202310381529.1 and application name “A command generating circuit and memory”, the entire contents of which are incorporated by reference in this disclosure.

Technical Field

The present disclosure relates to, but is not limited to, a command generating circuit and a memory.

Background Art

With the continuous development of semiconductor technology, people have put forward higher and higher requirements for data transmission speed when manufacturing and using computers and other equipment. In order to obtain faster data transmission speed, a series of memory devices such as memory that can transmit data at double data rate (DDR) have emerged.

In a dynamic random access memory (DRAM) chip, for the on-die termination (ODT) function of the chip, the resistance switching of the terminal resistor needs to follow certain timing requirements.

Summary of the invention

Embodiments of the present disclosure provide a command generation circuit and a memory.

In a first aspect, an embodiment of the present disclosure provides a command generation circuit, the command generation circuit comprising a first sampling circuit, a basic delay circuit, a second sampling circuit and a command adjustment circuit, the output end of the first sampling circuit is connected to the input end of the basic delay circuit, the output end of the basic delay circuit is connected to the input end of the second sampling circuit, and the output end of the first sampling circuit and the output end of the second sampling circuit are both connected to the command adjustment circuit, wherein:

A first sampling circuit is used to receive a first command signal and a first clock signal, and to sample the first command signal according to the first clock signal to obtain a first intermediate signal;

A basic delay circuit is used to receive a first intermediate signal, a first clock signal and a first control signal, and to sample and shift the first intermediate signal according to the first control signal and the first clock signal to obtain a second intermediate signal; wherein a shift length between the second intermediate signal and the first intermediate signal is associated with the first control signal;

a second sampling circuit, configured to receive the first clock signal, the first intermediate signal, and the second intermediate signal, perform a setting process on the second sampling circuit according to the first intermediate signal, and perform a sampling process on the second intermediate signal according to the first clock signal to obtain a third intermediate signal;

The command adjustment circuit is used to receive the first intermediate signal and the third intermediate signal, perform pulse width adjustment processing on the first command signal according to the first intermediate signal and the third intermediate signal, and generate a second command signal, wherein the pulse width of the second command signal is greater than the pulse width of the first command signal.

In some embodiments, the value of the first control signal is associated with the data burst length BL.

In some embodiments, the pulse width of the second command signal is equal to the shift length between the third intermediate signal and the first intermediate signal, and the pulse width of the second command signal is associated with the data burst length BL; wherein:

When the data burst length BL increases, the shift length between the second intermediate signal and the first intermediate signal is controlled to increase according to the first control signal, so that the pulse width of the second command signal is widened;

When the data burst length BL is reduced, the shift length between the second intermediate signal and the first intermediate signal is controlled to be reduced according to the first control signal, so that the pulse width of the second command signal is narrowed.

In some embodiments, the command generation circuit further comprises a clock processing circuit, wherein:

A clock processing circuit, configured to receive a clock gating signal and a second clock signal, and control and process the second clock signal according to the clock gating signal to generate a first clock signal;

When the clock gating signal is in a first level state, the first clock signal has the same frequency as the second clock signal; when the clock gating signal is in a second level state, the first clock signal is in a low level state.

In some embodiments, the clock processing circuit includes a first NAND gate and a first inversion module, wherein:

The first input end of the first NAND gate is used to receive a clock gating signal, the second input end of the first NAND gate is used to receive a second clock signal, the output end of the first NAND gate is connected to the input end of the first inverting module, and the output end of the first inverting module is used to output the first clock signal.

In some embodiments, the first sampling circuit includes a first trigger, wherein:

The input end of the first trigger is used to receive a first command signal, the clock end of the first trigger is used to receive a first clock signal, and the first output end of the first trigger is used to output a first intermediate signal; wherein, the first output end of the first trigger is used to reflect the value of the input end of the first trigger after being sampled by the first clock signal.

In some embodiments, the basic delay circuit includes M second flip-flops and N selection units, and the clock terminals of the M second flip-flops are all used to receive the first clock signal, and each sub-control signal in the first control signal is respectively connected to the control terminals of the N selection units; wherein:

The input terminal of the first second trigger is used to receive the first intermediate signal, and the first output terminal of the first second trigger is connected to the input terminal of the second second trigger and the first input terminals of the N selection units respectively;

The first output terminal of the kth second flip-flop is connected to the input terminal of the next second flip-flop, until the first output terminal of the jth second flip-flop is connected to the second input terminal of the ith selection unit, the output terminal of the ith selection unit is connected to the input terminal of the j+1th second flip-flop, and the first output terminal of the j+1th second flip-flop is connected to the input terminal of the next second flip-flop;

A first output terminal of the Mth second trigger is connected to a second input terminal of the Nth selection unit, and an output terminal of the Nth selection unit is used to output a second intermediate signal;

Among them, i is an integer greater than or equal to 1 and less than N, k is an integer greater than 1 and less than j, and j is an integer greater than k and less than M; the first output end of each second trigger is used to reflect the value of the input end of the second trigger after being sampled by the first clock signal.

In some embodiments, when the value of M is equal to 7 and the value of N is equal to 2, the first control signal includes a first sub-control signal and a second sub-control signal, and the clock terminals of the seven second flip-flops are all used to receive the first clock signal; wherein:

The control end of the first selection unit is connected to the first sub-control signal, and the control end of the second selection unit is connected to the second sub-control signal;

The input terminal of the first second trigger is used to receive the first intermediate signal, and the first output terminal of the first second trigger is respectively connected to the input terminal of the second second trigger, the first input terminal of the first selection unit, and the first input terminal of the second selection unit;

The first output terminal of the second second trigger is connected to the input terminal of the third second trigger, the first output terminal of the third second trigger is connected to the input terminal of the fourth second trigger, the first output terminal of the fourth second trigger is connected to the input terminal of the fifth second trigger, the first output terminal of the fifth second trigger is connected to the second input terminal of the first selection unit, the output terminal of the first selection unit is connected to the input terminal of the sixth second trigger, the first output terminal of the sixth second trigger is connected to the input terminal of the seventh second trigger, the first output terminal of the seventh second trigger is connected to the second input terminal of the second selection unit, and the output terminal of the second selection unit is used to output the second intermediate signal.

In some embodiments, the second sampling circuit includes a third trigger, wherein:

The input end of the third trigger is used to receive the second intermediate signal, the clock end of the third trigger is used to receive the first clock signal, the set end of the third trigger is used to receive the first intermediate signal, and the first output end of the third trigger is used to output the third intermediate signal; wherein, the first output end of the third trigger is used to reflect the value of the input end of the third trigger after being sampled by the first clock signal.

In some embodiments, when the first sub-control signal and the second sub-control signal are both in the second level state, the shift length between the third intermediate signal and the first intermediate signal is equal to 8 preset clock cycles;

When the first sub-control signal is in the first level state and the second sub-control signal is in the second level state, the shift length between the third intermediate signal and the first intermediate signal is equal to 4 preset clock cycles;

When the first sub-control signal is in the second level state and the second sub-control signal is in the first level state, the shift length between the third intermediate signal and the first intermediate signal is equal to 2 preset clock cycles;

The preset clock period is equal to the clock period of the first clock signal.

In some embodiments, the third trigger is used to control the third intermediate signal to be in the first level state when the first intermediate signal is in the second level state.

In some embodiments, the first level state is a high level, and the second level state is a low level.

In some embodiments, the command adjustment circuit includes an SR latch and a second inversion module, and the SR latch includes a second NAND gate and a third NAND gate; wherein:

The first input terminal of the second NAND gate is used to receive the first intermediate signal, and the second input terminal of the second NAND gate is connected to the output terminal of the third NAND gate;

The second input terminal of the third NAND gate is used to receive the third intermediate signal, the first input terminal of the third NAND gate is connected to the output terminal of the second NAND gate, and the output terminal of the second NAND gate is also connected to the input terminal of the second inverting module, and the output terminal of the second inverting module is used to output the second command signal.

In some embodiments, the command generation circuit further includes a delay shift circuit, wherein:

The delay shift circuit is used to receive a first clock signal and a second command signal, sample and shift the second command signal according to the first clock signal, and obtain a third command signal; wherein the third command signal is used to control the resistance switching of the terminal resistor.

In a second aspect, an embodiment of the present disclosure provides a memory, the memory at least comprising a command generating circuit as described in any one of the first aspects.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of an ODT functional circuit;

FIG2 is a schematic diagram of a signal timing sequence of an ODT function;

FIG3 is a schematic diagram of a structure of a command generating circuit provided in an embodiment of the present disclosure;

FIG4 is a second schematic diagram of the structure of a command generating circuit provided in an embodiment of the present disclosure;

FIG5 is a partial structural schematic diagram 1 of a command generating circuit provided in an embodiment of the present disclosure;

FIG6 is a schematic diagram of a basic delay circuit according to an embodiment of the present disclosure;

FIG. 7 is a second schematic diagram of the structure of a basic delay circuit provided in an embodiment of the present disclosure;

FIG8 is a second partial structural diagram of a command generating circuit provided in an embodiment of the present disclosure;

FIG9 is a schematic diagram of the structure of a command adjustment circuit provided in an embodiment of the present disclosure;

FIG10 is a third schematic diagram of the structure of a command generating circuit provided in an embodiment of the present disclosure;

FIG11 is a first detailed structural diagram of a command generating circuit provided in an embodiment of the present disclosure;

FIG12 is a first schematic diagram of a signal timing sequence provided by an embodiment of the present disclosure;

FIG13 is a second schematic diagram of a signal timing sequence provided by an embodiment of the present disclosure;

FIG14 is a second detailed structural diagram of a command generating circuit provided in an embodiment of the present disclosure;

FIG15 is a third signal timing diagram provided by an embodiment of the present disclosure;

FIG. 16 is a schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

Dynamic Random Access Memory (DRAM);

Double Data Rate (DDR);

The third generation double data rate (Double Data Rate 3, DDR3);

The fourth generation of double data rate (Double Data Rate 4, DDR4);

The fifth generation of double data rate (Double Data Rate 5, DDR5);

On Die Termination (ODT);

Termination resistance/terminal resistance (Termination Resistance, RTT);

Mode Register (MR);

Command (CMD);

Data (DQ);

Preset clock cycle (tck);

Read (RD);

Write (WR);

Non-Target Write (NTWR);

Non-Target Read (NTRD);

Burst Length (BL);

Write Latency (WL);

D-type flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF);

Set/Reset Latch (SR latch);

Central Processing Unit (CPU);

Mode Register Setting (MRS).

With the rapid development of semiconductor technology, the transmission rate of signals is getting faster and faster, resulting in increasingly prominent signal integrity issues. In the process of high-speed signal propagation, the discontinuity of impedance causes signal reflection, which will cause inter-symbol interference (ISI) errors. In order to better improve the signal integrity of the data, in the design of DDR3, DDR4 and DDR5, ODT resistors can be added to the DQ pin for the WR/NTRD/NTWR mode. Here, by using ODT resistors to match the impedance of the transmission line to set the terminal resistance to a suitable value, the reflection and energy loss of the signal during transmission can be reduced, thereby ensuring the integrity of the signal received at the DQ end.

Taking DDR5DRAM as an example, DDR5DRAM supports ODT function, which can adjust the terminal resistance (also called "termination resistance") of the DQ, DQS_t/c, DM_n and TDQS_t/c ports of each device through ODT pin control, write command or mode register setting default resistance value. In addition, the purpose of the ODT function is to reduce reflections and effectively improve the signal integrity on the memory interface by independently controlling the terminal resistance of all or any DRAM by the controller. As shown in Figure 1, it shows a structural schematic diagram of an ODT functional circuit. In Figure 1, the ODT functional circuit may include at least a switch S1, a terminal resistor RTT and a power supply VDDQ. Among them, one end of the switch S1 is connected to one end of the terminal resistor RTT, the other end of the terminal resistor RTT is connected to the power supply VDDQ, and the other end of the switch S1 is connected to other circuits, as well as DQ, DQS, DM, and TDQS ports. It should be noted that DQS can be a pair of differential data selection signals DQS_t and DQS_c, and TDQS can be a pair of differential data selection signals TDQS_t and TDQS_c.

In addition, switch S1 in Figure 1 is controlled by the ODT control logic. The ODT control logic contains external ODT pin input, mode register configuration, and other control information. The value of RTT is controlled by the configuration information in the mode register. In addition, if RTT_NOM is disabled in self-refresh mode or mode register configuration, the control of the ODT pin is ignored.

Specifically, when the configuration bits MR1{A10,A9,A8} or MR2{A10:A9} or MR5{A8:A6} are not all zero, the ODT function is turned on. In this case, the actual resistance of the ODT resistor is determined by these configuration bits. After entering the self-refresh mode, the DDR5 DRAM automatically disables the ODT function, and the terminal resistor is set to high impedance (Hi-Z) to discard all mode register settings.

Exemplarily, FIG2 shows a signal timing diagram of an ODT function, specifically a control timing diagram of an ODT function during a write operation in DDR5. As shown in FIG2, when DDR5 receives a command (CMD), it needs to transmit the command to the DQ end to control the resistance change of RTT. When DDR5 receives a write (Write) command, the resistance of RTT needs to be switched from RTT_PARK to RTT_WR, that is, when the resistance of RTT is in the RTT_PARK stage, the DQ end does not receive data. When the Write command is transmitted to the DQ end, the resistance of RTT is switched to the RTT_WR stage, and the DQ end receives and writes data; the time for the resistance switching of RTT is represented by tODTLon_WR. That is to say, when the resistance value of RTT switches from RTT_PARK to RTT_WR, it is necessary to wait for tODTLon_WR preset clock cycles, where tODTLon_WR = WL + ODTLon_WR_offset, ODTLon_WR_offset is the adjustment value of the tODTLon_WR parameter issued by the controller, and the value of ODTLon_WR_offset can be set to -3, -2, -1, 0 or 1 preset clock cycles according to the mode register. In addition, the resistance value switching of RTT does not occur immediately, but takes time to change. The time for the resistance value switching of RTT is represented by tADC, where the maximum and minimum values of tADC can be set, respectively represented as: tADC.Max and tADC.Min.

When DDR5 receives a Write command, if it is to control the resistance change of RTT, it needs to convert the Write command into an internal ODT command to control the resistance change of RTT. As shown in Figure 2, the width of the data is equal to the burst length (Burst Length, BL), so the pulse width of the ODT command must be at least equal to BL times the preset clock cycle, that is, ODT_width1 = BL. In addition, before the DQ end receives data, the resistance of RTT needs to be switched from RTT_PARK to RTT_WR. After the DQ end receives data, the resistance of RTT is switched from RTT_WR to RTT_PARK. That is to say, in the actual process, the pulse width of the ODT command needs to have an additional compensation amount (ODT_offset) so as to meet the timing requirements of the RTT resistance switching, that is, ODT_width1 = BL + ODT_offset, where ODT_offset is determined according to the instructions issued by the CPU and is used to further widen the pulse width of the ODT command.

Table 1 shows the relevant provisions of DDR5 regarding BL, as shown below.

Table 1

It can be understood that the above content is the relevant provisions for the ODT function in the technical specifications of DDR5. In simple terms, the resistance value of the terminal resistor can be switched, but how to switch needs to follow certain timing requirements. When the DRAM is in WR/NTRD/NTWR mode, a suitable terminal resistor can be set at the DQ pin to improve signal integrity.

It can also be understood that the technical specifications of DDR5 require that the data burst length can support BL8, BL16, BL32, etc. Correspondingly, for different data burst lengths, the ODT command needs to support different pulse widths so as to control the resistance switching of the terminal resistor according to the final generated ODT pulse.

In the disclosed embodiment, for the ODT circuit, when two consecutive ODT commands arrive, if the time interval between the two ODT commands is a specific clock cycle, and the shift length of the ODT command also happens to be a specific clock cycle, the second ODT command may have no output, thereby affecting the ODT function of the memory.

Based on this, an embodiment of the present disclosure provides a command generating circuit, in which a first command signal is first sampled and processed by a first sampling circuit to obtain a first intermediate signal; then, the first intermediate signal is sampled and shifted according to a first control signal and a first clock signal by a basic delay circuit to obtain a second intermediate signal; the first intermediate signal is then used as a set signal of a second sampling circuit, and the second intermediate signal is sampled and processed according to the first clock signal to obtain a third intermediate signal; finally, a command adjustment circuit is used to adjust the pulse width of the first command signal according to the first intermediate signal and the third intermediate signal to generate a second command signal, and the pulse width of the second command signal is greater than the pulse width of the first command signal. In this way, the shift length between the second intermediate signal and the first intermediate signal obtained by the basic delay circuit is affected by the first control signal, and the value of the first control signal is associated with BL, that is, the shift length between the second intermediate signal and the first intermediate signal is associated with BL; in addition, since the first intermediate signal is used as the set signal of the second sampling circuit, when the first intermediate signal is at a low level, the sampled third intermediate signal can be kept at a high level, so that when there are two consecutive ODT commands, not only can the second ODT command be prevented from having no output, but the pulse width of the second command signal is equal to the shift length between the third intermediate signal and the first intermediate signal, that is, the pulse width of the second command signal is also affected by BL, and the pulse width of the second command signal can be adaptively adjusted according to the length of BL; in addition, considering the on-chip termination compensation value set by the controller, the second command signal can continue to be pulse-width adjusted, so that the resistance switching of the terminal resistor is controlled according to the finally generated ODT pulse, and the energy loss and reflection of the signal during transmission can be reduced, the signal integrity is improved, and the memory performance is improved.

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In one embodiment of the present disclosure, referring to FIG3, it shows a schematic diagram of a composition structure of a command generation circuit provided by an embodiment of the present disclosure. As shown in FIG3, the command generation circuit 30 may include a first sampling circuit 301, a basic delay circuit 302, a second sampling circuit 303 and a command adjustment circuit 304. The output end of the first sampling circuit 301 is connected to the input end of the basic delay circuit 302, the output end of the basic delay circuit 302 is connected to the input end of the second sampling circuit 303, and the output end of the first sampling circuit 301 and the output end of the second sampling circuit 303 are both connected to the command adjustment circuit 304, wherein:

The first sampling circuit 301 is used to receive a first command signal and a first clock signal, and to sample the first command signal according to the first clock signal to obtain a first intermediate signal;

The basic delay circuit 302 is used to receive the first intermediate signal, the first clock signal and the first control signal, and to sample and shift the first intermediate signal according to the first control signal and the first clock signal to obtain a second intermediate signal; wherein the shift length between the second intermediate signal and the first intermediate signal is associated with the first control signal;

The second sampling circuit 303 is used to receive the first clock signal, the first intermediate signal and the second intermediate signal, set the second sampling circuit according to the first intermediate signal, and sample the second intermediate signal according to the first clock signal to obtain a third intermediate signal;

The command adjustment circuit 304 is used to receive the first intermediate signal and the third intermediate signal, perform pulse width adjustment processing on the first command signal according to the first intermediate signal and the third intermediate signal, and generate a second command signal, and the pulse width of the second command signal is greater than the pulse width of the first command signal.

It should be noted that, in the disclosed embodiment, the command generation circuit 30 can be applied to a memory. The memory can be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., which is not specifically limited here.

It should also be noted that in the embodiment of the present disclosure, the command generating circuit 30 is specifically a circuit for generating an ODT command, which can support the ODT function introduced in DDR5. Here, the first intermediate signal is used as the set signal of the second sampling circuit 303, so that in the second sampling circuit 303, when the first intermediate signal is at a low level, the third intermediate signal sampled at this time remains at a high level; in this way, when there are two consecutive ODT commands, the phenomenon of no output of the second ODT command is effectively avoided.

In some embodiments, the value of the first control signal is associated with the data burst length BL.

It should be noted that, in the embodiment of the present disclosure, different values of the first control signal may correspond to different BLs, wherein the value of BL may be 8, 16, 32, etc., which is not specifically limited here.

It should also be noted that, in the embodiment of the present disclosure, the value of the first control signal can be set by the mode register. If the value of the first control signal is the first value, the value of BL can be 8; if the value of the first control signal is the second value, the value of BL can be 16; if the value of the first control signal is the third value, the value of BL can be 32.

Here, the first value, the second value and the third value are all different. Taking the first control signal including the first sub-control signal SEL1 and the second sub-control signal SEL0 as an example, for the value of the first control signal, illustratively, the first value can be set to 01, that is, the value of SEL1 is 0, and the value of SEL0 is 1; the second value can be set to 10, that is, the value of SEL1 is 1, and the value of SEL0 is 0; the third value can be set to 00, That is, the value of SEL1 is 0, and the value of SEL0 is 0; there is no specific limitation on this here.

It should also be noted that, in the embodiment of the present disclosure, the shift length between the second intermediate signal and the first intermediate signal is associated with the first control signal, that is, the shift length between the second intermediate signal and the first intermediate signal is also associated with BL. Exemplarily, if the value of BL is larger, the shift length between the second intermediate signal and the first intermediate signal is longer; if the value of BL is smaller, the shift length between the second intermediate signal and the first intermediate signal is shorter.

In some embodiments, a pulse width of the second command signal is equal to a shift length between the third intermediate signal and the first intermediate signal, and the pulse width of the second command signal is associated with a data burst length BL.

Further, in some embodiments, when BL increases, the shift length between the second intermediate signal and the first intermediate signal is controlled to increase according to the first control signal so that the pulse width of the second command signal is widened; when BL decreases, the shift length between the second intermediate signal and the first intermediate signal is controlled to decrease according to the first control signal so that the pulse width of the second command signal is narrowed.

It should be noted that, in the embodiment of the present disclosure, assuming that the shift length between the third intermediate signal and the first intermediate signal is A, the shift length between the second intermediate signal and the first intermediate signal is B, and the shift length between the third intermediate signal and the second intermediate signal is C, then A=B+C, and C is equal to one clock cycle of the first clock signal. Since the length of B is affected by BL, the length of A is also affected by BL accordingly, that is, the shift length between the third intermediate signal and the first intermediate signal (i.e., the pulse width of the second command signal) is affected by BL.

Exemplarily, if the value of BL is larger, the shift length between the second intermediate signal and the first intermediate signal controlled by the first control signal is longer, and the shift length between the third intermediate signal and the first intermediate signal is also longer. Correspondingly, the pulse width of the second command signal is wider. Conversely, if the value of BL is smaller, the shift length between the second intermediate signal and the first intermediate signal controlled by the first control signal is shorter, and the shift length between the third intermediate signal and the first intermediate signal is also shorter. Correspondingly, the pulse width of the second command signal is narrower.

In short, in the embodiment of the present disclosure, different BLs may correspond to different values of the first control signal. In addition, the larger the value of BL, the longer the shift length generated by the basic delay circuit 302, and the wider the pulse width of the second command signal generated at this time, so that the width of the finally generated ODT pulse can cover the entire DQ data writing process.

In some embodiments, based on the command generation circuit 30 shown in FIG. 3 , referring to FIG. 4 , the command generation circuit 30 may further include a clock processing circuit 305 , wherein:

The clock processing circuit 305 is used to receive the clock gating signal and the second clock signal, and control the second clock signal according to the clock gating signal to generate the first clock signal.

In the disclosed embodiment, when the clock gating signal is in the first level state, the frequency of the first clock signal is the same as that of the second clock signal; when the clock gating signal is in the second level state, the first clock signal is in a low level state.

In the embodiment of the present disclosure, the first level state may be a high level, such as logic 1; the second level state may be a low level, such as logic 0, but this is not specifically limited.

In this way, if the clock gating signal is at a high level, the first clock signal output at this time is the second clock signal; if the clock gating signal is at a low level, the second clock signal is shielded at this time, so that the output first clock signal is at a low level and no longer has a clock function.

In some embodiments, based on the command generating circuit 30 shown in FIG. 4 , referring to FIG. 5 , the clock processing circuit 305 may include a first NAND gate A1 and a first inverting module A2 , wherein:

The first input end of the first NAND gate A1 is used to receive a clock gating signal, the second input end of the first NAND gate A1 is used to receive a second clock signal, the output end of the first NAND gate A1 is connected to the input end of the first inverting module A2, and the output end of the first inverting module A2 is used to output the first clock signal.

It should be noted that, in the embodiment of the present disclosure, the first inversion module A2 may be composed of first NOT gates, and the number of the first NOT gates is an odd number. The more the number of the first NOT gates, the longer the delay time between the first clock signal and the second clock signal; therefore, in the embodiment of the present disclosure, the number of the first NOT gates may be set to 1, but is not specifically limited.

Further, in some embodiments, as shown in FIG5 , the first sampling circuit 301 may include a first trigger A3, wherein:

The input end of the first trigger A3 is used to receive a first command signal, the clock end of the first trigger A3 is used to receive a first clock signal, and the first output end of the first trigger A3 is used to output a first intermediate signal; wherein, the first output end of the first trigger A3 is used to reflect the value of the input end of the first trigger A3 after being sampled by the first clock signal.

It should be noted that, in the disclosed embodiment, the first trigger A3 may be a D-type trigger (Data Flip-Flop or Delay Flip-Flop, DFF). The D-type trigger is an information storage device with a memory function and two stable states. It is the most basic logic unit constituting a variety of sequential circuits and an important unit circuit in digital logic circuits. Here, the D-type trigger has two stable states, namely "0" and "1", and can flip from one stable state to another stable state under the action of the signal received at the clock end.

It should also be noted that, in the embodiment of the present disclosure, the first trigger A3 may include a clock terminal (CK), an input terminal (D), a first output terminal (Q), and a second output terminal (Q). And the first output terminal (Q) and the second output terminal There is an anti-correlation between In addition, the first trigger A3 may also include a set terminal (SET) and a reset terminal (RST), but they are not shown in the figure.

That is, in the first sampling circuit 301 , the first clock signal can sample the first command signal through the first trigger A3 , thereby outputting a first intermediate signal, which can be used as a set signal for the subsequent second sampling circuit 303 .

In some embodiments, for the basic delay circuit 302, referring to FIG. 6, the basic delay circuit 302 may include M second flip-flops (U1, U2, ...UM) and N selection units (D1, D2, ...DN), and the clock terminals of the M second flip-flops are all used to receive the first clock signal, and each sub-control signal in the first control signal is respectively connected to the control terminals of the N selection units; wherein:

An input terminal of the first second trigger U1 is used to receive a first intermediate signal, and a first output terminal of the first second trigger U1 is connected to an input terminal of the second second trigger U2 and first input terminals of the N selection units respectively;

The first output terminal of the kth second trigger Uk is connected to the input terminal of the next second trigger, until the first output terminal of the jth second trigger Uj is connected to the second input terminal of the ith selection unit Di, the output terminal of the ith selection unit Di is connected to the input terminal of the j+1th second trigger Uj+1, and the first output terminal of the j+1th second trigger Uj+1 is connected to the input terminal of the next second trigger;

A first output terminal of the Mth second flip-flop UM is connected to a second input terminal of the Nth selection unit DN, and an output terminal of the Nth selection unit DN is used to output a second intermediate signal;

Among them, i is an integer greater than or equal to 1 and less than N, k is an integer greater than 1 and less than j, and j is an integer greater than k and less than M; the first output end of each second trigger is used to reflect the value of the input end of the second trigger after being sampled by the first clock signal.

In the embodiment of the present disclosure, the first control signal may include N sub-control signals (SEL0, SEL1, ..., SELN-1), and these N sub-control signals are respectively connected to the control terminals of the N selection units. Specifically, the control terminal of the first selection unit D1 is connected to the first sub-control signal SELN-1, the control terminal of the second selection unit D2 is connected to the second sub-control signal SELN-2, the control terminal of the i-th selection unit Di is connected to the i-th sub-control signal SELN-i, and the control terminal of the N-th selection unit DN is connected to the N-th sub-control signal SEL0. In this way, according to the values of these N sub-control signals, the number of second triggers that actually play a shifting role on the first intermediate signal can be determined, and then the shift length between the second intermediate signal and the first intermediate signal can be determined. Exemplarily, according to the values of the N sub-control signals, if the number of second triggers that actually play a shifting role on the first intermediate signal is greater, the shift length between the second intermediate signal and the first intermediate signal is longer; conversely, if the number of second triggers that actually play a shifting role on the first intermediate signal is smaller, the shift length between the second intermediate signal and the first intermediate signal is shorter.

Further, in the embodiment of the present disclosure, the value of M may be equal to 7, and the value of N may be equal to 2. In this case, the first control signal may include a first sub-control signal SEL1 and a second sub-control signal SEL0. In some embodiments, referring to FIG. 7 , the basic delay circuit 302 may include seven second flip-flops (U1, U2, ... U7) and two selection units (D1, D2), and the clock terminals of the seven second flip-flops are all used to receive the first clock signal; wherein:

The control end of the first selection unit D1 is connected to the first sub-control signal SEL1, and the control end of the second selection unit D2 is connected to the second sub-control signal SEL0;

An input terminal of the first second trigger U1 is used to receive a first intermediate signal, and a first output terminal of the first second trigger U1 is respectively connected to an input terminal of the second second trigger U2, a first input terminal of the first selection unit D1, and a first input terminal of the second selection unit D2;

The first output end of the second second trigger U2 is connected to the input end of the third second trigger U3, the first output end of the third second trigger U3 is connected to the input end of the fourth second trigger U4, the first output end of the fourth second trigger U4 is connected to the input end of the fifth second trigger U5, the first output end of the fifth second trigger U5 is connected to the second input end of the first selection unit D1, the output end of the first selection unit D1 is connected to the input end of the sixth second trigger U6, the first output end of the sixth second trigger U6 is connected to the input end of the seventh second trigger U7, the first output end of the seventh second trigger U7 is connected to the second input end of the second selection unit D2, and the output end of the second selection unit D2 is used to output the second intermediate signal.

It should also be noted that, in the embodiment of the present disclosure, according to the values of the first sub-control signal SEL1 and the second sub-control signal SEL0, the number of second triggers in the basic delay circuit 302 that actually play a shifting role on the first intermediate signal can be determined, and then the shift length between the second intermediate signal and the first intermediate signal can be determined. Here, if the first sub-control signal and the second sub-control signal are both in the second level state (for example, the value of SEL1 is equal to 0, and the value of SEL0 is equal to 0), then there are seven second triggers in the basic delay circuit 302 that actually play a shifting role on the first intermediate signal, specifically the second triggers U1 to U7, and at this time, the shift length between the second intermediate signal and the first intermediate signal is equal to 7 preset clock cycles; if the first sub-control signal is in the first level state, and the second sub-control signal is in the second level state (for example, the value of SEL1 is equal to 1, and the value of SEL0 is equal to 0), then the basic delay circuit 302 has seven second triggers .... There are three second triggers that actually play a shifting role for an intermediate signal, specifically the second triggers U1, U6 and U7, and at this time the shift length between the second intermediate signal and the first intermediate signal is equal to 3 preset clock cycles; if the first sub-control signal is in the second level state, and the second sub-control signal is in the first level state (for example, the value of SEL1 is equal to 0, and the value of SEL0 is equal to 1), then there is only one second trigger in the basic delay circuit 302 that actually plays a shifting role for the first intermediate signal, specifically the second trigger U1, and at this time the shift length between the second intermediate signal and the first intermediate signal is equal to 1 preset clock cycle. The preset clock cycle can be the clock cycle of the first clock signal.

In some embodiments, based on the basic delay circuit 302 shown in FIG. 7 , referring to FIG. 8 , the second sampling circuit 303 may include a first Three triggers U8, where:

The input end of the third trigger U8 is used to receive the second intermediate signal, the clock end of the third trigger U8 is used to receive the first clock signal, the set end of the third trigger U8 is used to receive the first intermediate signal, and the first output end of the third trigger U8 is used to output the third intermediate signal; wherein, the first output end of the third trigger U8 is used to reflect the value of the input end of the third trigger U8 after being sampled by the first clock signal.

It should be noted that in the embodiments of the present disclosure, both the second trigger and the third trigger may be D-type triggers.

It should also be noted that in the embodiment of the present disclosure, the sampling processing of the second intermediate signal by the first clock signal can be realized through the third trigger U8, so that the third intermediate signal can be output, and the shift length between the third intermediate signal and the second intermediate signal is equal to 1 preset clock cycle.

Further, in some embodiments, when the first sub-control signal and the second sub-control signal are both in the second level state, the shift length between the third intermediate signal and the first intermediate signal is equal to 8 preset clock cycles;

When the first sub-control signal is in the first level state and the second sub-control signal is in the second level state, the shift length between the third intermediate signal and the first intermediate signal is equal to 4 preset clock cycles;

When the first sub-control signal is in the second level state and the second sub-control signal is in the first level state, the shift length between the third intermediate signal and the first intermediate signal is equal to 2 preset clock cycles.

The preset clock period is equal to the clock period of the first clock signal.

It should be noted that, in the embodiment of the present disclosure, when the first sub-control signal and the second sub-control signal are both in the second level state (for example, the value of SEL1 is equal to 0, and the value of SEL0 is equal to 0), since the shift length between the second intermediate signal and the first intermediate signal is equal to 7 preset clock cycles, the shift length between the third intermediate signal and the second intermediate signal is equal to 1 preset clock cycle; therefore, the shift length between the third intermediate signal and the first intermediate signal is equal to 8 preset clock cycles.

It should also be noted that, in the embodiment of the present disclosure, when the first sub-control signal is in the first level state and the second sub-control signal is in the second level state (for example, the value of SEL1 is equal to 1, and the value of SEL0 is equal to 0), since the shift length between the second intermediate signal and the first intermediate signal is equal to 3 preset clock cycles, the shift length between the third intermediate signal and the second intermediate signal is equal to 1 preset clock cycle; therefore, the shift length between the third intermediate signal and the first intermediate signal is equal to 4 preset clock cycles.

It should also be noted that, in the embodiment of the present disclosure, when the first sub-control signal is in the second level state and the second sub-control signal is in the first level state (for example, the value of SEL1 is equal to 0, and the value of SEL0 is equal to 1), since the shift length between the second intermediate signal and the first intermediate signal is equal to 1 preset clock cycle, the shift length between the third intermediate signal and the second intermediate signal is equal to 1 preset clock cycle; therefore, the shift length between the third intermediate signal and the first intermediate signal is equal to 2 preset clock cycles.

In short, in the embodiment of the present disclosure, the shift length between the third intermediate signal and the first intermediate signal is related to the value of the first control signal, or it can be said that the shift length between the third intermediate signal and the first intermediate signal is related to the value of BL.

Furthermore, in some embodiments, the third trigger U8 is used to control the third intermediate signal to be in the first level state when the first intermediate signal is in the second level state.

In the embodiment of the present disclosure, the first level state may be a high level, and the second level state may be a low level. Alternatively, the first level state may be a logic 1, and the second level state may be a logic 0.

In the embodiment of the present disclosure, for the third trigger U8, since the first intermediate signal is used as the set signal of the third trigger U8, according to the function of the set signal, when the set signal is at a low level, the third intermediate signal output by the third trigger U8 is always at a high level; in this way, when there are two consecutive ODT commands, the second ODT command can be effectively prevented from having no output.

It should be noted that for the set end of the third trigger U8, if some additional inverters are added, the logic here can also be: when the first intermediate signal is at a high level, the third intermediate signal output by the third trigger U8 is always at a high level. That is to say, in the embodiment of the present disclosure, the first level state can also be a low level (i.e., logic 0), and the second level state can also be a high level (i.e., logic 1). Among them, for different operation logics, it can be considered to add some inverters here, and then the subsequent logic needs to be adjusted accordingly, so that the same effect can be achieved.

In some embodiments, for the command adjustment circuit 304, referring to FIG. 9, the command adjustment circuit 304 may include an SR latch 401 and a second inversion module 402, and the SR latch 401 includes a second NAND gate B1 and a third NAND gate B2; wherein:

The first input terminal of the second NAND gate B1 is used to receive the first intermediate signal, and the second input terminal of the second NAND gate B1 is connected to the output terminal of the third NAND gate B2;

The second input terminal of the third NAND gate B2 is used to receive the third intermediate signal, the first input terminal of the third NAND gate B2 is connected to the output terminal of the second NAND gate B1, and the output terminal of the second NAND gate B1 is also connected to the input terminal of the second inverting module 402, and the output terminal of the second inverting module 402 is used to output the second command signal.

It should be noted that, in the embodiment of the present disclosure, the output end of the SR latch 401 is used to output the fourth intermediate signal, and then the input end of the second inverting module 402 is used to receive the fourth intermediate signal, and the output end of the second inverting module 402 is used to output the second command signal. Here, there is a delay and inversion relationship between the fourth intermediate signal and the second command signal.

It should also be noted that, in the embodiment of the present disclosure, for the SR latch 401, the rising edge of the fourth intermediate signal may be generated according to the level flipping moment of the first intermediate signal (specifically, flipping from a high level to a low level), and the falling edge of the fourth intermediate signal may be generated according to the level flipping moment of the first intermediate signal. The fourth intermediate signal is generated according to the level flipping moment of the third intermediate signal (specifically, from a high level to a low level). In addition, because the third intermediate signal is delayed by a preset shift length compared to the first intermediate signal, after the SR latch 401 performs logic processing on the first intermediate signal and the third intermediate signal, the fourth intermediate signal is a high-level effective pulse signal, and the pulse width is widened to the preset shift length.

That is, the SR latch 401 is used to generate a fourth intermediate signal that is widened compared to the pulse width of the first command signal, and the pulse width of the fourth intermediate signal is a preset shift length. Exemplarily, for the first control signal, if the value of SEL1 is equal to 0 and the value of SEL0 is equal to 0, then the preset shift length can be equal to 8 preset clock cycles; if the value of SEL1 is equal to 1 and the value of SEL0 is equal to 0, then the preset shift length can be equal to 4 preset clock cycles; if the value of SEL1 is equal to 0 and the value of SEL0 is equal to 1, then the preset shift length can be equal to 2 preset clock cycles.

In addition, in the disclosed embodiment, the second inverting module 402 may be composed of a second NOT gate B3, and the number of the second NOT gates B3 may be an odd number. Because the second inverting module 402 includes an odd number of second NOT gates, the output signal of the SR latch 401 is not only delayed, but also the level state of the output signal is changed. Here, the second inverting module 402 may be composed of one second NOT gate B3, or may be composed of three, five, or more second NOT gates B3 connected in series. Exemplarily, the number of the second NOT gate B3 may be set to 1, but this is not specifically limited.

It should also be noted that, in the embodiment of the present disclosure, the more the number of second NOT gates, the longer the delay time between the output signal of the SR latch 401 and the second command signal. In other words, according to the different numbers of second NOT gates in the second inversion module 402, the delay time between the output signal of the SR latch 401 and the second command signal is also different accordingly. In this way, the embodiment of the present disclosure can determine the specific number of second NOT gates in the second inversion module 402 according to the required delay time.

In some embodiments, based on the command generation circuit 30 shown in FIG. 4 , referring to FIG. 10 , the command generation circuit 30 may further include a delay shift circuit 306 , wherein:

The delay shift circuit 306 is used to receive the first clock signal and the second command signal, sample and shift the second command signal according to the first clock signal to obtain a third command signal; wherein the third command signal is used to control the resistance switching of the terminal resistor.

It should be noted that, in the embodiment of the present disclosure, the pulse width difference between the third command signal and the second command signal is associated with the on-chip termination compensation value set by the controller.

It should also be noted that in the embodiment of the present disclosure, in order to ensure that the reflection of the DQ pin is reduced when receiving DQ data, the delay shift circuit 306 can further widen the pulse width of the ODT command according to the ODT_offset required by the CPU to generate the final ODT pulse at the DQ pin, that is, the third command signal here. Here, the pulse width difference between the third command signal and the second command signal can be expressed as ODT_offset, and different on-chip termination compensation values can be set by the controller; in addition, ODT_offset can have nine possibilities such as 0 to 8tck, which are not specifically limited here.

In addition, in the embodiment of the present disclosure, for the third command signal, the pulse width of the third command signal is not only related to the value of BL, but also related to ODT_offset, so that the reflection of the DQ pin can be well reduced when receiving DQ data.

The present embodiment provides a command generation circuit, which includes a first sampling circuit, a basic delay circuit, a second sampling circuit and a command adjustment circuit. In which, since the first intermediate signal is used as a set signal of the second sampling circuit, when the first intermediate signal is at a low level, the sampled third intermediate signal can be kept at a high level, so that when there are two consecutive ODT commands, the second ODT command can be effectively prevented from having no output; in addition, the pulse width of the second command signal is equal to the shift length between the third intermediate signal and the first intermediate signal, and the shift length between the third intermediate signal and the first intermediate signal is related to BL, that is, the pulse width of the second command signal will be affected by BL, and the pulse width of the second command signal can be adaptively adjusted according to the length of BL; in addition, considering the on-chip termination compensation value set by the controller, the second command signal can continue to be pulse-width adjusted, so that the resistance switching of the terminal resistor is controlled according to the finally generated ODT pulse, and the energy loss and reflection of the signal during transmission can be reduced, the signal integrity is improved, and the memory performance is improved.

In another embodiment of the present disclosure, based on the command generation circuit 30 described in the above embodiment, see Figure 11, which shows a detailed structural diagram of a command generation circuit provided by the embodiment of the present disclosure. As shown in Figure 11, the command generation circuit 30 may include a first NAND gate 501, a first NOT gate 502, a first trigger 503, a second trigger 504, a third trigger 505, a fourth trigger 506, a fifth trigger 507, a sixth trigger 508, a seventh trigger 509, an eighth trigger 510, a ninth trigger 511, a first selection unit 512, a second selection unit 513, an SR latch 514 and a second NOT gate 515, and the specific connection relationship is shown in Figure 11.

In FIG11 , the first sub-control signal can be represented by SEL1, and the second sub-control signal can be represented by SEL0; the first command signal can be represented by CMD_IN, the first clock signal can be represented by CLK1, the clock gating signal can be represented by CLK_Gating, the second clock signal can be represented by CLK, the first intermediate signal can be represented by Q1, the second intermediate signal can be represented by Q2, and the third intermediate signal can be represented by CMD_shift; the first delay signal can be represented by CMD_delay; and the second command signal can be represented by OUTPUT. It should be noted that there is a slight delay between the first intermediate signal Q1 and the first delay signal CMD_delay due to the transmission path. Normally, this delay can be ignored, and the first intermediate signal Q1 and the first delay signal CMD_delay can be regarded as one signal.

It should be noted that, for FIG. 11 , when the first command signal CMD_IN includes a single command, and the value of the first sub-control signal SEL1 is 1, and the value of the second sub-control signal SEL0 is 0, the corresponding signal timing is shown in FIG. 12 . The trigger 503 samples the first command signal CMD_IN to obtain a first intermediate signal Q1 and a first delayed signal CMD_delay. Here, the delay time between the first intermediate signal Q1 and the first delayed signal CMD_delay is _t1 . Since _t1 is generated by the transmission path, _t1 is relatively small and can usually be ignored.

Further, the first intermediate signal Q1 is sampled by the second trigger 504 to obtain the fifth intermediate signal Q3, and the delay time between the fifth intermediate signal Q3 and the first intermediate signal Q1 is 1tck (i.e., one preset clock cycle). In addition, since the value of the first sub-control signal SEL1 is 1 and the value of the second sub-control signal SEL0 is 0, the fifth intermediate signal Q3 needs to continue to be sampled by the seventh trigger 509, the eighth trigger 510 and the ninth trigger 511 to obtain the third intermediate signal CMD_shift, and the delay time between the third intermediate signal CMD_shift and the first intermediate signal Q1 is 4tck (i.e., four preset clock cycles). Finally, through the SR latch 514 and the second NOT gate 515, the first delay signal CMD_delay and the third intermediate signal CMD_shift can generate the falling edge and the rising edge of the second command signal OUTPUT respectively, and the pulse width of the second command signal OUTPUT is equal to the delay time between the third intermediate signal CMD_shift and the first intermediate signal Q1 (i.e., 4tck).

It should also be noted that, for FIG. 11 , when the first command signal CMD_IN includes two consecutive commands, and the time interval between the two commands is 4tck; and the value of the first sub-control signal SEL1 is 1, and the value of the second sub-control signal SEL0 is 0, the corresponding signal timing is shown in FIG. 13 . Among them, the first intermediate signal Q1 and the first delayed signal CMD_delay can be obtained by the first trigger 503 sampling and processing the first command signal CMD_IN; wherein the delay time between the first delayed signal CMD_delay and the first command signal CMD_IN is t ₂ , and t ₂ can be jointly generated by the device delay of the first trigger 503 and the transmission path delay. Here, the device delay of the first trigger 503 is mainly manifested as the delay time between the first command signal CMD_IN and the first intermediate signal Q1, and the transmission path delay is mainly manifested as the delay time between the first intermediate signal Q1 and the first delayed signal CMD_delay. The delay time of the transmission path is small and can usually be ignored.

Furthermore, since the value of the first sub-control signal SEL1 is 1 and the value of the second sub-control signal SEL0 is 0, the first intermediate signal Q1 is sampled and processed by the second trigger 504, the seventh trigger 509, the eighth trigger 510 and the ninth trigger 511 in sequence, thereby generating the third intermediate signal CMD_shift. Here, considering the delay of the second trigger 504, the seventh trigger 509, the eighth trigger 510 and the ninth trigger 511 and the delay of the transmission path, the delay time caused by these delays is set to _t3 ; then the delay time between the third intermediate signal CMD_shift and the first delayed signal CMD_delay is the sum of 4tck and _t3 . In an ideal case, _t3 can be ignored, that is, the delay time between the third intermediate signal CMD_shift and the first delayed signal CMD_delay can be regarded as 4tck.

For the command generating circuit 30 shown in FIG11 , if two consecutive commands are received, and the time interval between the two commands is 4tck, and the delay time between the third intermediate signal CMD_shift and the first delay signal CMD_delay is also 4tck, at this time, the second command in the first command signal CMD_IN does not output the correct level through the second command signal OUTPUT, resulting in the inability to set the correct terminal resistance value at the DQ end. As can be seen from FIG. 13, for the second command in the first command signal CMD_IN, when the CMD_delay corresponding to the second command is at a low level, the third intermediate signal CMD_shift is also at a low level (this is because the time interval between the two commands is 4tck, and the signal shift is also exactly 4tck), so at the end of the second pulse of CMD_delay, the second command signal OUTPUT changes from a low level to a high level; but at this time, the third intermediate signal CMD_shift is still at a low level. According to the logic processing of the SR latch 514 and the second NOT gate 515, the second command signal OUTPUT finally output is still at a high level, and there is no situation where the second command signal OUTPUT changes to a low level afterwards, that is, the OUTPUT corresponding to the second command remains at a high level. That is to say, in the second command signal OUTPUT, only the pulse corresponding to the first command is output as a low-level valid pulse and the pulse width is widened to cover the process of writing the DQ data corresponding to the first command; but the second command does not output the correct level through the second command signal OUTPUT, resulting in the DQ end being unable to set the correct resistance value of the terminal resistor.

In summary, in the embodiment of the present disclosure, when two consecutive ODT commands arrive, if the time interval between the two ODT commands is a specific number of preset clock cycles, and the shift length of the ODT command also happens to be a specific number of preset clock cycles, for example, the specific number is 4; then for the command generating circuit, the second ODT command will not be output in the final output ODT pulse.

Based on this, for the command generating circuit 30 described in the above embodiment, FIG14 is a detailed structural diagram of another command generating circuit 30 provided in the embodiment of the present disclosure. As shown in FIG14, the command generating circuit 30 may include a first NAND gate 601, a first NOT gate 602, a first trigger 603, a second trigger 604, a third trigger 605, a fourth trigger 606, a fifth trigger 607, a sixth trigger 608, a seventh trigger 609, an eighth trigger 610, a ninth trigger 611, a first selection unit 612, a second selection unit 613, an SR latch 614 and a second NOT gate 615. For specific connection relationships, see FIG14.

In FIG14 , the first sub-control signal can be represented by SEL1, and the second sub-control signal can be represented by SEL0; the first command signal is represented by CMD_IN, the first clock signal is represented by CLK1, the clock gating signal is represented by CLK_Gating, the second clock signal is represented by CLK, the first intermediate signal can be represented by Q1, the second intermediate signal can be represented by Q2, and the third intermediate signal can be represented by CMD_shift; the first delay signal can be represented by CMD_delay; and the second command signal can be represented by OUTPUT. In addition, compared with the command generation circuit 30 shown in FIG11 , in FIG14 , the set terminal (SET) of the ninth flip-flop 611 is used to receive the first delay signal CMD_delay.

In addition, it should be noted that there is a slight delay between the first intermediate signal Q1 and the first delayed signal CMD_delay due to the transmission path. Usually, this delay can be ignored. In other words, in the embodiment of the present disclosure, the first intermediate signal Q1 and the first delayed signal CMD_delay are slightly delayed due to the transmission path. The first delay signal CMD_delay may be regarded as one signal.

It should also be noted that, for FIG. 14 , when the first command signal CMD_IN is two consecutive commands and the time interval between the two commands is 4tck; and the value of the first sub-control signal SEL1 is 1, and the value of the second sub-control signal SEL0 is 0, the corresponding signal timing is shown in FIG. 15 . Among them, the first delay signal CMD_delay can be obtained by the sampling process of the first command signal CMD_IN by the first trigger 603. Here, there is a delay between the first delay signal CMD_delay and the first command signal CMD_IN, and the delay time can be jointly generated by the device delay of the first trigger 603 and the transmission path delay.

Further, since the value of the first sub-control signal SEL1 is 1 and the value of the second sub-control signal SEL0 is 0, then for the first intermediate signal Q1, after being sampled by the second trigger 604, the fifth intermediate signal Q3 can be obtained; then the fifth intermediate signal Q3 continues to be sampled by the seventh trigger 609, the eighth trigger 610 and the ninth trigger 611, so as to generate the third intermediate signal CMD_shift. Next, the first command signal is pulse widened by the SR latch 614 and the second NOT gate 615, specifically, the first falling edge of the first delay signal CMD_delay generates the falling edge of the second command signal OUTPUT, and the falling edge of the third intermediate signal CMD_shift generates the rising edge of the second command signal OUTPUT, and the pulse width of the second command signal OUTPUT is equal to 8tck (i.e., eight preset clock cycles). The falling edge here refers to the time when the high level changes to the low level, and the rising edge refers to the time when the low level changes to the high level.

In addition, based on the command generating circuit 30 shown in FIG14 , if two consecutive commands are received, and the time interval between the two commands is 4tck, and the delay time between the third intermediate signal CMD_shift and the first delay signal CMD_delay is also 4tck, it can be seen from FIG15 that for the second command in the first command signal CMD_IN, when the first delay signal CMD_delay corresponding to the second command is at a low level, the third intermediate signal CMD_shift remains at a high level (this is because CMD_delay is the set signal of the ninth flip-flop 611), so at the end of the second pulse of CMD_delay, the second command signal OUTPUT still remains at a low level; according to the logic processing of the SR latch 614 and the second NOT gate 615, the second command signal OUTPUT is finally output at a low level until the second command signal OUTPUT changes from a low level to a high level at the falling edge of the third intermediate signal CMD_shift, and at this time, the pulse width of the second command signal OUTPUT that is effective at a low level is 8tck.

In the embodiment of the present disclosure, since the first delay signal CMD_delay is used as the set signal of the ninth trigger 611, the third intermediate signal CMD_shift can be kept at a high level all the time when the first delay signal CMD_delay is at a low level. In this way, by setting the third intermediate signal CMD_shift through the first delay signal CMD_delay, the second command signal OUTPUT output after passing through the SR latch and the second NOT gate can be effectively prevented from being reset to a high level, so that the pulse width of the second command signal OUTPUT when it is at a low level is equal to 8tck, thereby avoiding the phenomenon that the second ODT command has no output when there are two consecutive ODT commands, so that the resistance value of the terminal resistor can be correctly set.

This embodiment provides a command generation circuit, which can support data burst lengths such as BL8, BL16, and BL32; and when in WR/NTRD/NTWR mode, a suitable terminal resistor can be set at the DQ pin. In this way, when there are two consecutive ODT commands, not only can the second ODT command be prevented from having no output, but also the energy loss and reflection of the signal during transmission can be reduced, the signal integrity is improved, and the memory performance is improved.

In another embodiment of the present disclosure, referring to Fig. 16, a schematic diagram of the composition structure of a memory provided by the embodiment of the present disclosure is shown. As shown in Fig. 16, the memory 160 at least includes the command generating circuit 30 as described in the above embodiment.

In some embodiments, the memory 160 may include a DRAM chip. The DRAM chip may not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but may also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6, which are not specifically limited here.

In the embodiment of the present disclosure, for the memory 160, the first intermediate signal is used as a set signal, so that when the first intermediate signal is at a low level, the sampled third intermediate signal can be maintained at a high level, thereby effectively avoiding the second ODT command from having no output when there are two consecutive ODT commands; in addition, the pulse width of the second command signal is equal to the shift length between the third intermediate signal and the first intermediate signal, and the pulse width of the second command signal will be affected by BL, and the pulse width of the second command signal can be adaptively adjusted according to the length of BL; in addition, considering the on-chip termination compensation value set by the controller, the second command signal can continue to be pulse-width adjusted, so that the resistance switching of the terminal resistor is controlled according to the finally generated ODT pulse, which can also reduce the energy loss and reflection of the signal during transmission, improve the signal integrity, and thus improve the memory performance.

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new methods. Example.

The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Industrial Applicability

The present embodiment provides a command generating circuit and a memory, in which a first sampling circuit is used to receive a first command signal and a first clock signal, and perform sampling processing on the first command signal according to the first clock signal to obtain a first intermediate signal; a basic delay circuit is used to receive a first intermediate signal, a first clock signal and a first control signal, and perform sampling and shift processing on the first intermediate signal according to the first control signal and the first clock signal to obtain a second intermediate signal; a second sampling circuit is used to receive a first clock signal, a first intermediate signal and a second intermediate signal, and perform setting processing on the second sampling circuit according to the first intermediate signal, and perform sampling processing on the second intermediate signal according to the first clock signal to obtain a third intermediate signal; a command adjustment circuit is used to receive a first intermediate signal and a third intermediate signal, and perform pulse width adjustment processing on the first command signal according to the first intermediate signal and the third intermediate signal to generate a second command signal, and a pulse width of the second command signal is greater than a pulse width of the first command signal. In this way, the sampling and shift processing of the first intermediate signal can be realized through the basic delay circuit, and the shift length between the obtained second intermediate signal and the first intermediate signal is affected by the first control signal, and the value of the first control signal is associated with BL, that is, the shift length between the second intermediate signal and the first intermediate signal is associated with BL; in addition, since the first intermediate signal is used as the set signal of the second sampling circuit, when the first intermediate signal is at a low level, the sampled third intermediate signal can be kept at a high level, so that when there are two consecutive ODT commands, not only can the second ODT command be prevented from having no output, but the pulse width of the second command signal is equal to the shift length between the third intermediate signal and the first intermediate signal, that is, the pulse width of the second command signal is also affected by BL, and the pulse width of the second command signal can be adaptively adjusted according to the length of BL; in addition, considering the on-chip termination compensation value set by the controller, the second command signal can continue to be pulse-width adjusted, so that the resistance switching of the terminal resistor is controlled according to the finally generated ODT pulse, and the energy loss and reflection of the signal during transmission can be reduced, the signal integrity is improved, and the memory performance is improved.

Claims (15)

A command generating circuit (30), the command generating circuit (30) comprising a first sampling circuit (301), a basic delay circuit (302), a second sampling circuit (303) and a command adjusting circuit (304), the output end of the first sampling circuit (301) being connected to the input end of the basic delay circuit (302), the output end of the basic delay circuit (302) being connected to the input end of the second sampling circuit (303), and the output end of the first sampling circuit (301) and the output end of the second sampling circuit (303) being both connected to the command adjusting circuit (304), wherein: The first sampling circuit (301) is used to receive a first command signal and a first clock signal, and perform sampling processing on the first command signal according to the first clock signal to obtain a first intermediate signal; The basic delay circuit (302) is used to receive the first intermediate signal, the first clock signal and the first control signal, and perform sampling and shift processing on the first intermediate signal according to the first control signal and the first clock signal to obtain a second intermediate signal; wherein the shift length between the second intermediate signal and the first intermediate signal is associated with the first control signal; The second sampling circuit (303) is used to receive the first clock signal, the first intermediate signal and the second intermediate signal, perform setting processing on the second sampling circuit according to the first intermediate signal, and perform sampling processing on the second intermediate signal according to the first clock signal to obtain a third intermediate signal; The command adjustment circuit (304) is used to receive the first intermediate signal and the third intermediate signal, perform pulse width adjustment processing on the first command signal according to the first intermediate signal and the third intermediate signal, and generate a second command signal, wherein the pulse width of the second command signal is greater than the pulse width of the first command signal. The command generating circuit (30) according to claim 1, wherein the value of the first control signal is associated with a data burst length BL. The command generating circuit (30) according to claim 1, wherein the pulse width of the second command signal is equal to the shift length between the third intermediate signal and the first intermediate signal, and the pulse width of the second command signal is associated with the data burst length BL; wherein: When the data burst length BL increases, controlling the shift length between the second intermediate signal and the first intermediate signal to increase according to the first control signal, so that the pulse width of the second command signal is widened; When the data burst length BL decreases, the shift length between the second intermediate signal and the first intermediate signal is controlled to decrease according to the first control signal, so that the pulse width of the second command signal is narrowed. The command generating circuit (30) according to any one of claims 1 to 3, wherein the command generating circuit (30) further comprises a clock processing circuit (305), wherein: The clock processing circuit (305) is used to receive a clock gating signal and a second clock signal, and to control and process the second clock signal according to the clock gating signal to generate the first clock signal; When the clock gating signal is in a first level state, the first clock signal has the same frequency as the second clock signal; when the clock gating signal is in a second level state, the first clock signal is in a low level state. The command generating circuit (30) according to claim 4, wherein the clock processing circuit (305) comprises a first NAND gate (A1) and a first inverting module (A2), wherein: The first input end of the first NAND gate (A1) is used to receive the clock gating signal, the second input end of the first NAND gate (A1) is used to receive the second clock signal, the output end of the first NAND gate (A1) is connected to the input end of the first inverting module (A2), and the output end of the first inverting module (A2) is used to output the first clock signal. The command generating circuit (30) according to claim 1, wherein the first sampling circuit (301) comprises a first trigger (A3), wherein: The input end of the first trigger (A3) is used to receive the first command signal, the clock end of the first trigger (A3) is used to receive the first clock signal, and the first output end of the first trigger (A3) is used to output the first intermediate signal; wherein the first output end of the first trigger (A3) is used to reflect the value of the input end of the first trigger (A3) after being sampled by the first clock signal. The command generating circuit (30) according to any one of claims 1 to 6, wherein the basic delay circuit (302) comprises M second flip-flops (U1, U2, ... UM) and N selection units (D1, D2, ... DN), and the clock terminals of the M second flip-flops are all used to receive the first clock signal, and each sub-control signal in the first control signal is respectively connected to the control terminals of the N selection units; wherein: The input end of the first second trigger (U1) is used to receive the first intermediate signal, and the first output end of the first second trigger (U1) is connected to the input end of the second second trigger (U2) and the first input ends of the N selection units respectively; The first output terminal of the kth second trigger (Uk) is connected to the input terminal of the next second trigger, until the first output terminal of the jth second trigger (Uj) is connected to the second input terminal of the i-th selection unit (Di). The output end of (Di) is connected to the input end of the j+1th second flip-flop (Uj+1), and the first output end of the j+1th second flip-flop (Uj+1) is connected to the input end of the next second flip-flop; The first output terminal of the Mth second trigger (UM) is connected to the second input terminal of the Nth selection unit (DN), and the output terminal of the Nth selection unit (DN) is used to output the second intermediate signal; Wherein, i is an integer greater than or equal to 1 and less than N, k is an integer greater than 1 and less than j, and j is an integer greater than k and less than M; the first output end of each second trigger is used to reflect the value of the input end of the second trigger after being sampled by the first clock signal. The command generating circuit (30) according to claim 7, wherein, when the value of M is equal to 7 and the value of N is equal to 2, the first control signal includes a first sub-control signal and a second sub-control signal, and the clock terminals of the seven second flip-flops are all used to receive the first clock signal; wherein: The control end of the first selection unit (D1) is connected to the first sub-control signal, and the control end of the second selection unit (D2) is connected to the second sub-control signal; The input end of the first second trigger (U1) is used to receive the first intermediate signal, and the first output end of the first second trigger (U1) is respectively connected to the input end of the second second trigger (U2), the first input end of the first selection unit (D1) and the first input end of the second selection unit (D2); The first output end of the second second trigger (U2) is connected to the input end of the third second trigger (U3), the first output end of the third second trigger (U3) is connected to the input end of the fourth second trigger (U4), the first output end of the fourth second trigger (U4) is connected to the input end of the fifth second trigger (U5), the first output end of the fifth second trigger (U5) is connected to the second input end of the first selection unit (D1), the output end of the first selection unit (D1) is connected to the input end of the sixth second trigger (U6), the first output end of the sixth second trigger (U6) is connected to the input end of the seventh second trigger (U7), the first output end of the seventh second trigger (U7) is connected to the second input end of the second selection unit (D2), and the output end of the second selection unit (D2) is used to output the second intermediate signal. The command generating circuit (30) according to claim 8, wherein the second sampling circuit (303) comprises a third trigger (U8), wherein: The input end of the third trigger (U8) is used to receive the second intermediate signal, the clock end of the third trigger (U8) is used to receive the first clock signal, the set end of the third trigger (U8) is used to receive the first intermediate signal, and the first output end of the third trigger (U8) is used to output the third intermediate signal; wherein the first output end of the third trigger (U8) is used to reflect the value of the input end of the third trigger (U8) after being sampled by the first clock signal. The command generating circuit (30) according to claim 9, wherein: When the first sub-control signal and the second sub-control signal are both in the second level state, the shift length between the third intermediate signal and the first intermediate signal is equal to 8 preset clock cycles; When the first sub-control signal is in a first level state and the second sub-control signal is in a second level state, a shift length between the third intermediate signal and the first intermediate signal is equal to 4 preset clock cycles; When the first sub-control signal is in the second level state and the second sub-control signal is in the first level state, the shift length between the third intermediate signal and the first intermediate signal is equal to 2 preset clock cycles; The preset clock period is equal to the clock period of the first clock signal. The command generating circuit (30) according to claim 9, wherein: The third trigger (U8) is used to control the third intermediate signal to be in the first level state when the first intermediate signal is in the second level state. The command generating circuit (30) according to claim 4, 10 or 11, wherein the first level state is a high level and the second level state is a low level. The command generating circuit (30) according to any one of claims 1 to 12, wherein the command adjusting circuit (304) comprises an SR latch (401) and a second inverting module (402), and the SR latch (401) comprises a second NAND gate (B1) and a third NAND gate (B2); wherein: The first input end of the second NAND gate (B1) is used to receive the first intermediate signal, and the second input end of the second NAND gate (B1) is connected to the output end of the third NAND gate (B2); The second input end of the third NAND gate (B2) is used to receive the third intermediate signal, the first input end of the third NAND gate (B2) is connected to the output end of the second NAND gate (B1), and the output end of the second NAND gate (B1) is also connected to the input end of the second inverting module (402), and the output end of the second inverting module (402) is used to output the second command signal. The command generation circuit (30) according to any one of claims 1 to 13, wherein the command generation circuit (30) further comprises a delay shift circuit (306), wherein: The delay shift circuit (306) is used to receive the first clock signal and the second command signal, and to sample and shift the second command signal according to the first clock signal to obtain a third command signal; wherein the third command signal is used to control the terminal The resistance value of the terminal resistor is switched. A memory (160), the memory (160) comprising at least the command generating circuit (30) according to any one of claims 1 to 14.