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WO2024078223A1 - 一种电子设备及其PCIe拓扑配置方法和装置 - Google Patents

一种电子设备及其PCIe拓扑配置方法和装置 Download PDF

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Publication number
WO2024078223A1
WO2024078223A1 PCT/CN2023/117989 CN2023117989W WO2024078223A1 WO 2024078223 A1 WO2024078223 A1 WO 2024078223A1 CN 2023117989 W CN2023117989 W CN 2023117989W WO 2024078223 A1 WO2024078223 A1 WO 2024078223A1
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Prior art keywords
information
switching
electronic device
pcie
management chip
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PCT/CN2023/117989
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English (en)
French (fr)
Inventor
冉懋良
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超聚变数字技术有限公司
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Application filed by 超聚变数字技术有限公司 filed Critical 超聚变数字技术有限公司
Priority to EP23876428.6A priority Critical patent/EP4589446A1/en
Publication of WO2024078223A1 publication Critical patent/WO2024078223A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of computer technology, and in particular to an electronic device and a PCIe topology configuration method and device thereof.
  • GPU (graphics processing unit) servers can have a variety of GPU options. Different types of GPUs are usually suitable for training, reasoning, and high-performance computing (HPC) scenarios. Enterprise users expect to use a GPU server to cover as many scenarios as possible, but in each scenario, the high-speed peripheral component interconnect PCIe bus topology architecture used to support GPU communication in the GPU server needs to be configured accordingly. Currently, the configuration of the PCIe bus topology architecture is mostly manually adjusted by professionals, which is inefficient.
  • the present application provides an electronic device and a PCIe topology configuration method and device thereof, which can realize adaptive switching of PCIe topology structure in a server.
  • the present application provides an electronic device, which includes at least one main processor, multiple graphics processors and a management chip, each main processor and the multiple graphics processors are connected to at least one switching device via a peripheral component interconnect (PCIe) bus, and each switching device is in communication with the management chip.
  • the management chip is used to generate switching information corresponding to the target application scenario based on first information, the first information includes type identification information and/or configuration information of each graphics processor, and the switching device is used to switch the PCIe bus connection relationship between the multiple graphics processors and the corresponding main processor according to the switching information.
  • PCIe peripheral component interconnect
  • the electronic device may be a workstation, a GPU server, a hyperterminal, etc.
  • the multiple graphics processors may be GPUs for training/inference scenarios in deep learning, GPUs for graphics rendering scenarios, or GPUs for HPC scenarios, but are not limited thereto.
  • the multiple graphics processors are connected to a switching device via a PCIe bus, and the switching device may switch the communication path from the GPU to the corresponding main processor.
  • the management chip of the electronic device can monitor and obtain the type identification information or other configuration information of these graphics processors after the graphics processors are connected to the electronic device, generate switching information corresponding to the target application scenario applicable to the current graphics processor, control the switching device to perform corresponding actions, complete the configuration of the PCIe bus topology between the multiple graphics processors and the corresponding main processor, so that the configured topology structure adapts to the current target application scenario, and facilitates the electronic device to achieve
  • manual intervention can be reduced, which is conducive to greatly improving the configuration efficiency of the PCIe bus topology in electronic devices.
  • the electronic device includes a firmware module, and the firmware module is used to read type identification information of each graphics processor to report the type identification information to the management chip as the first information.
  • the firmware module may be a BIOS firmware stored in a memory of an electronic device, which uses the BIOS to automatically read the type identification information of the GPU and report it to the BMC, without the need for manual input of configuration information.
  • the management chip is specifically configured to determine, according to a predefined mapping relationship between the type identification information and the application scenario, a target application scenario corresponding to the type identification information in the first information.
  • the management chip is specifically used to query a preset scenario dictionary according to the target application scenario, and match the target PCIe bus topology structure corresponding to the target application scenario.
  • the scenario dictionary is used to record the mapping relationship between multiple application scenarios and multiple PCIe bus topology structures, and generate corresponding switching information according to the target PCIe bus topology structure.
  • the management chip determines the target application scenario, it can quickly and efficiently determine the PCIe bus topology structure that is adapted to the scenario.
  • the configuration information may include target application scenario information and/or target PCIe bus topology information.
  • the management chip may generate corresponding switching information by querying the scenario dictionary or directly generating it.
  • the user's need to directly configure the PCIe bus topology structure can be met, which is conducive to improving the compatibility of electronic devices.
  • main processors there are multiple main processors, each of which is connected to a switching device via a PCIe bus, adjacent switching devices are connected via a PCIe bus, and multiple graphics processors are connected to corresponding switching devices via PCIe buses, respectively.
  • Each switching device is specifically used to switch the PCIe bus connection relationship between the graphics processor, the main processor, and/or the adjacent switching device connected thereto according to the switching information.
  • the PCIe bus network formed by multiple main processors and multiple switching devices is conducive to meeting the needs of users to access corresponding graphics processors according to different application scenarios and flexibly configure the PCIe bus topology.
  • an embodiment of the present application provides a PCIe topology configuration method, which is applied to an electronic device, wherein the electronic device includes at least one main processor, multiple graphics processors, and a management chip, each main processor and multiple graphics processors are connected to at least one switching device via a peripheral component interconnect (PCIe) bus, and each switching device is communicatively connected to the management chip;
  • PCIe peripheral component interconnect
  • the method includes: a management chip acquires first information, the first information includes device information and/or configuration information of each graphics processor, and the management chip generates switching information corresponding to a target application scenario based on the first information; the management chip also transmits the switching information to a switching device, so that the switching device switches the PCIe bus connection relationship between multiple graphics processors and the corresponding main processor.
  • the method before the management chip acquires the first information, the method includes: a firmware module in the electronic device reads type identification information of each graphics processor to report the type identification information to the management chip as the first information.
  • the management chip generates a switching operation corresponding to the target application scenario according to the first information.
  • the method comprises: determining a target application scenario corresponding to the type identification information in the first information according to a mapping relationship between predefined type identification information and application scenarios; querying a preset scenario dictionary according to the target application scenario, and matching a target PCIe bus topology structure corresponding to the target application scenario, wherein the scenario dictionary is used to record a mapping relationship between multiple application scenarios and multiple PCIe bus topology structures; and generating corresponding switching information according to the target PCIe bus topology structure.
  • the configuration information includes target application scenario information and/or target PCIe bus topology information.
  • the present application provides a computer-readable storage medium, which stores a computer program.
  • the processor executes the method described in the second general aspect or any possible implementation of the second aspect.
  • the present application provides a computer program product, characterized in that when the computer program product runs on a processor, the processor executes the method described in the second aspect or any possible implementation of the second aspect.
  • the present application provides a chip, characterized in that it includes at least one processor and an interface; at least one processor obtains program instructions or data through the interface; at least one processor is used to execute program line instructions to implement the method described in the second aspect or any possible implementation method of the second aspect.
  • FIG1 is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application.
  • FIG2 is a schematic diagram of the hardware structure of an electronic device provided in a specific embodiment of the present application.
  • FIG3 is a schematic diagram of the architecture of an electronic device provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of a flow chart of a PCIe topology configuration method provided in an embodiment of the present application.
  • FIG5 is a flow chart of a PCIe topology configuration method provided by a specific embodiment of the present application.
  • FIG6 is a schematic diagram of the structure of a PCIe topology configuration device provided in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of the structure of a chip provided in an embodiment of the present application.
  • a and/or B in this article is a description of the association relationship of associated objects, indicating that there can be three relationships.
  • a and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone.
  • the symbol "/" in this article indicates that the associated objects are in an or relationship, for example, A/B means A or B.
  • first and second in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of objects.
  • first information and second information are used to distinguish different information rather than to describe a specific order of information.
  • words such as “exemplary” or “for example” are used to indicate examples, illustrations or descriptions. Any embodiment or design described as “exemplary” or “for example” in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as “exemplary” or “for example” is intended to present related concepts in a specific way.
  • multiple means two or more than two.
  • multiple processing units refer to two or more processing units, etc.; multiple elements refer to two or more elements, etc.
  • GPU graphics processing unit
  • Graphics processor also known as display core, visual processor, display chip, is a microprocessor specially used to perform image and graphics related calculations on electronic devices (such as personal computers, workstations, servers and some mobile devices).
  • GPU card A board that carries a GPU, also known as a graphics card.
  • CPU central processing unit
  • the central processing unit which is the computing and control core of the computer system, is the final execution unit of information processing and program running.
  • PCIe peripheral component interconnect express
  • PCI-Express Peripheral Component Interconnect Express
  • PCIe Peripheral Component Interconnect Express
  • the connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot plugging, and quality of service (QOS) and other functions.
  • QOS quality of service
  • P2P peer to peer: peer-to-peer network, end-to-end transmission network.
  • BIOS basic input output system: basic input and output system. In fact, it is a set of programs fixed to a ROM (read-only memory) chip on the motherboard of the computer, also known as "BIOS firmware". It stores the most important basic input and output programs of the computer, the self-test program after powering on, and the system self-starting program. It can read and write specific information of system settings from the random access memory CMOS RAM.
  • BIOS basic input output system
  • BIOS basic input and output system.
  • BIOS firmware read-only memory
  • BMC baseboard management controller
  • Baseboard management controller which is the remote management controller of the server. It can perform some operations on the machine such as firmware upgrade and machine equipment check when the machine is not turned on.
  • RAID redundant arrays of independent disks: redundant disk array.
  • GPU servers can be equipped with multiple GPU cards to perform graphics and intensive computing tasks. They are suitable for scenarios such as deep learning training, scientific computing, graphics and image processing, and video encoding and decoding. They can provide fast, stable, and flexible computing power support for automatic optical inspection, assisted driving, and image processing in the medical industry, as well as edge AI acceleration computing.
  • the GPUs in GPU servers usually have their focused functions according to their types (or models). For example, some GPUs focus on training/inference, some GPUs focus on graphics rendering, and some GPUs focus on high-density computing. Users select GPUs according to scenario requirements, and after connecting the selected GPU of the corresponding type to the server, in order to achieve the best performance of the GPU server, the PCIe topology structure where the GPU is located needs to be adapted. However, the traditional method of manually configuring the PCIe topology is inefficient and reduces operational efficiency.
  • the embodiments of the present application provide a PCIe topology configuration method, device, electronic device, computer storage medium and computer program product, which mainly adaptively switches the PCIe topology structure in the server according to the application scenario of the electronic device (such as a GPU server), thereby achieving efficient configuration of the PCIe topology and improving the operational efficiency of the server.
  • the electronic device such as a GPU server
  • FIG1 shows a schematic diagram of the hardware structure of an electronic device.
  • the electronic device 100 can be a hardware device that can provide data processing functions, computing functions, and storage functions, such as a workstation, a GPU server, or a super terminal, but is not limited to this.
  • the electronic device 100 provided in the embodiment of the present application may include a processor 101, a memory 102, a graphics processor 103, a management chip 104, and a communication interface 105. These components in the electronic device 200 can be integrated on the mainboard, and the components can be connected through a bus 110 to complete mutual communication.
  • the processor 101 may include various processing devices, such as a central processing unit (CPU), a system on chip (SOC), a processor integrated on a SOC, a separate processor chip or a controller, etc.
  • the processor 101 may also include a dedicated processing device, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), etc.
  • the processor 101 may be a processor group composed of multiple processors, and the multiple processors are coupled to each other through one or more buses. For example, the hardware structure diagram of the electronic device 100 in some specific examples shown in FIG.
  • CPU 101a may include two CPUs (101a, 101b) on its main board, and the CPU 101a and the CPU 101b are coupled through a three-way ultra path interconnect (UPI) bus to achieve high-speed communication between the two processors.
  • UPI ultra path interconnect
  • both CPU101a and CPU101b have multiple interfaces to connect other components (such as hard disk 1021, GPU10 card 103, PCIe standard card 120, etc.).
  • the memory 102 may be coupled to the processor 101. Specifically, the memory 102 may be coupled to the processor 101 via one or more memory controllers.
  • the memory 102 may be used to store computer program instructions, including a computer operating system (OS), BIOS firmware, and various programs.
  • the memory 102 may be a non-volatile memory (NVM), such as an embedded multi media card (EMMC), universal flash storage (UFS) or read-only memory (ROM), or other types of static storage devices that can store static information and instructions. It may also be a volatile memory (volatile memory), such as a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions.
  • NVM non-volatile memory
  • EMMC embedded multi media card
  • UFS universal flash storage
  • ROM read-only memory
  • RAM random access memory
  • each CPU (101a, 101b) may be connected to a memory 102 such as a hard disk 1021 or a disk array (RAID) 1022 through an interface to support the calculation, processing, and other operations of the CPU (101a, 101b).
  • a memory 102 such as a hard disk 1021 or a disk array (RAID) 1022 through an interface to support the calculation, processing, and other operations of the CPU (101a, 101b).
  • the graphics processing unit (GPU) 103 may include various types of microprocessors for graphics and intensive computing, such as a GPU for deep learning training/inference, a GPU for graphics rendering, and a GPU for HPC computing, but is not limited thereto.
  • Multiple GPUs 103 may be coupled to the processor (i.e., the main processor) 101, and perform corresponding tasks according to the control of the processor 101.
  • multiple GPUs 103 may be coupled to the processor 101, and when the processor 101 runs an application, they share the workload of the computationally intensive part of the application.
  • the processor 101 may include M (M ⁇ 2) CPUs, and multiple GPUs 103 are mounted on the M CPUs through N (N ⁇ 1) switching chips (PCIe Switch, PCIe SW) 106.
  • the CPU and GPU 103 are connected to the switching chip 106 through a high-speed peripheral component interconnect PCIe bus.
  • N ⁇ 2 two adjacent switching chips 106 are also connected through the PCIe bus.
  • PCIe SW 106 as a switching device, can provide expansion or aggregation capabilities and allow more devices (such as processor 101, GPU 103, etc.) to be connected to a PCle port.
  • PCIe SW 106 can identify which path a given packet needs to take based on the address or other routing information, and is a PCIe to PCIe bridge.
  • two CPUs (101a, 101b) mount eight GPUs (103a-103h) through two switching chips (106a, 106b), and the two switching chips (106a, 106b) are also connected through a PCIe bus.
  • the PCIe connection relationship between all GPUs (103a-103h) and the CPUs (101a, 101b) can be controlled, so that the configuration of the connection channel between GPU103 and CPU (101a, 101b) can be realized.
  • the switching chip 106b closes the connection channel between it and CPU101b, and conducts the connection channel between it and the switching chip 106a, and to GPU103e-103h.
  • the PCIe topology structure obtained by such configuration enables eight GPUs (103a-103h) to be mounted on CPU101a.
  • the electronic device 100 also includes a management chip 104, which may be a baseboard management controller BMC, and the BMC 104 is used to monitor and control the hardware (including each GPU 103) of the electronic device 100 and the connected hardware devices (such as hard disk 10221, disk array 1022, PCIe card 120, etc.). For example, the temperature, voltage and other information of the electronic device 100 may be monitored, and corresponding adjustments may be made to ensure that the electronic device 100 is in a normal operating state.
  • the BMC 104 may also record information and logs of various hardware or nodes, provide event logs, recovery control and configuration and other monitoring and management functions. It should be noted that the BMC 104 is an independent device, which does not depend on other hardware (such as processor 101 or memory 102, etc.) in the electronic device 100, nor on the OS, but the BMC 104 may interact with the OS.
  • the BIOS 130 in the electronic device 100 can read the type identification information (such as model, identity ID and other parameters) of each GPU (103a ⁇ 103h) connected to the PCIe bus, and report it to the BMC 104. Then, the BMC 104 can analyze the current target application scenario based on the acquired information, and control the switching chip (106a, 106b) to adapt to the target application scenario to perform the corresponding switching action to complete the configuration operation of the PCIe topology structure, thereby adapting to the target application scenario to mount the connected GPU to the corresponding CPU to enable the device to achieve optimal performance.
  • type identification information such as model, identity ID and other parameters
  • a complex programmable logic device (CPLD) 107 is provided between BMC 104 and each switching chip (106a, 106b).
  • BMC 104 can be connected to the input end of the logic device 107 through a bus (such as a CPU bus local bus, a serial bus I2C), and the output end of the logic device 107 is connected to each switching chip (106a, 106b) through a bus (such as a serial bus I2C).
  • a bus such as a CPU bus local bus, a serial bus I2C
  • a bus such as a serial bus I2C
  • the communication interface 105 is mainly used to implement communication between various modules, devices, units and/or equipment in the embodiments of the present application.
  • the bus 110 includes a bus of one or more communication protocols.
  • the bus 110 includes hardware, software, or both, coupling the components of the electronic device 100 to each other.
  • the bus 110 may include the above-mentioned PCIe bus, UPI bus, localbus bus, I2C bus, etc., and may also include an acceleration bus.
  • AGP Graphics port
  • EISA enhanced industry standard architecture
  • FBB front side bus
  • HT hypertransport
  • ISA industry standard architecture
  • LPC low pin count
  • MCA micro channel architecture
  • PCI peripheral component interconnect
  • SATA serial advanced technology attachment
  • VLB video electronics standard association local
  • the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 100.
  • the electronic device 100 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently.
  • the components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.
  • exemplary embodiments of the electronic device 100 include but are not limited to electronic devices equipped with iOS, Android, Windows, Harmony OS or other operating systems.
  • FIG. 4 is a flow chart of a PCIe topology configuration method provided in an embodiment of the present application. It can be understood that the method can be performed by the electronic device 100 shown in FIG. 1, FIG. 2 and FIG. 3, or by other devices or equipment with computing and processing capabilities. As shown in FIG. 4, the PCIe topology configuration method may include S401 to S403:
  • the management chip obtains first information, where the first information includes type identification information and/or configuration information of each graphics processor.
  • the graphics processor GPU when configuring an electronic device 100 such as a GPU server, can be selected according to business needs. For example, if the user needs to use the device for deep learning training/inference scenarios, a GPU model that focuses on training/inference functions can be selected, such as a GPU model of NVIDIA A100. If the user needs to use the device for graphics processing scenarios, a GPU model that focuses on graphics rendering functions can be selected, such as a GPU model of NVIDIA A40. After the user selects a corresponding type of GPU 103 to be mounted on the processor (hereinafter referred to as "CPU" as an example) 101, the communication path between each GPU 103 and the CPU it is mounted on is adaptively switched by the switching chip 106.
  • CPU corresponding type of GPU 103 to be mounted on the processor
  • the PCIe bus topology structure where each GPU and CPU are located can be configured by the switching chip 106.
  • the first information monitored by the management chip BMC 104 is analyzed to identify the application scenario of the current user's needs, thereby performing corresponding switching control on the switching chip 106 to reduce manual intervention in the deployment of the PCIe bus topology structure.
  • the first information acquired by BMC 104 may be information reported by BIOS 130 through S1a , or may be configuration information input by a user based on a management interface provided by BMC 104 through S1b .
  • the BIOS reads the type identification information of each graphics processor and reports the information to the BMC 104 as the first information.
  • BIOS 130 in the electronic device 100 can automatically read the model, identity ID and other type identification information of each GPU 103, and report these type identification information to the management chip BMC 104. It can be understood that the information reported by BIOS 130 to the management chip BMC 104 is the aforementioned first information.
  • the management chip BMC 104 can subsequently perform the following steps S402 to S403 to analyze and determine the scenario that the user wants the device to apply based on the type identification information of each GPU 103, thereby adaptively generating switching information for indicating the configuration of the PCIe bus topology structure suitable for the scenario.
  • multiple GPUs can be evenly connected to the switch chips 106 connected to multiple CPUs, as shown in FIG. 2 and FIG. 3, CPU 101a and CPU 101b are connected to four GPUs 103 through switch chips 106a and 106b, respectively.
  • multiple GPUs when multiple GPUs are connected to the switch chips 106 connected to multiple CPUs, they can also be deployed unevenly, such as connecting two GPUs to one CPU and connecting four GPUs to another CPU. In this way, flexible deployment of GPUs is achieved.
  • the management chip obtains configuration information input by the user.
  • the user may also input corresponding configuration information based on some peripherals of the electronic device 100 (such as a keyboard).
  • the configuration information may include information about the target application scenario and information about the target PCIe bus topology structure to be switched.
  • the user may input configuration information for describing a target application scenario (such as a graphics rendering scenario, a training scenario, or an HPC scenario, etc.) based on an interface (such as a BMC management interface provided by BMC 104), and the configuration information may be transmitted as first information to BMC 104.
  • a target application scenario such as a graphics rendering scenario, a training scenario, or an HPC scenario, etc.
  • an interface such as a BMC management interface provided by BMC 104
  • the interface may be displayed by a hardware device such as a display connected to electronic device 100.
  • each PCIe bus lane of each switching chip 106 has a unique channel identifier, and the user can also directly input information for controlling the PCIe bus channels on the switching chip 106 based on the interface, that is, information for controlling which channels of each switching chip 106 are turned on and which channels are turned off, thereby generating configuration information describing the target PCIe bus topology structure to be switched currently, and the configuration information can be transmitted to BMC104 as the first information.
  • the BMC 104 after the BMC 104 obtains the first information transmitted from the BIOS 130 or the interface through the aforementioned S401, it can execute:
  • S402 The management chip generates switching information corresponding to the target application scenario according to the first information.
  • BMC 104 may analyze the first information obtained from the BIOS 130 or the management interface to generate switching information, thereby controlling the switching chip 106 connected to each GPU 103 to enable the switching chip 106 to switch the PCIe bus channel.
  • the first information is information reported by BIOS 130, when BMC 104 executes S402, it may specifically include S4021 to S4023:
  • the management chip determines a target application scenario corresponding to the type identification information in the first information according to a predefined mapping relationship between the type identification information and the application scenario.
  • the mapping relationship between the type identification information and the application scenario can be predefined, for example, the GPU model "A100" is set to correspond to the training/inference scenario, the GPU model "A40" is set to correspond to the graphics rendering scenario, etc.
  • the BMC 104 obtains the first information, it can automatically identify the target application scenarios applicable to these GPUs according to the type identification information in the first information, that is, the scenarios that the user wants the electronic device 100 to apply.
  • the type identification information reported by BIOS 130 includes information about the models "A100" and "A30". If BMC 104 determines the two models through the mapping relationship between the predefined type identification information and the application scenario, If the GPU corresponds to the training/inference scenario, the training/inference scenario will be determined as the target application scenario, so that BMC104 can analyze the user's needs (that is, the target application scenario that the user wants to adapt) without user intervention.
  • BIOS130 includes information of four models "A40", “A30”, “A10” and “A2”
  • BMC104 determines through the mapping relationship between the predefined type identification information and the application scenario that the majority of these four models of GPUs are used for graphics rendering and virtual desktops, that is, all currently connected GPUs focus on graphics rendering/virtual desktop scenarios, then the graphics rendering/virtual desktop scenario can be determined as the target application scenario.
  • the management chip queries the scenario dictionary according to the target application scenario, and determines the target PCIe bus topology structure corresponding to the target application scenario.
  • the application scenario can be analyzed by calling the scenario dictionary.
  • the scenario dictionary is a predefined dictionary to record the mapping relationship between each application scenario and the PCIe bus topology structure, wherein the PCIe bus topology structure includes the connection relationship between the CPU and the switching chip, between each switching chip, and between the switching chip and the GPU.
  • the PCIe bus topology K1 corresponding to the training/inference scenario can be defined in the scenario dictionary.
  • the switch chip 106a can be set to conduct all PCIe bus channels connected to it, and the switch chip 106b closes the connection channel between itself and CPU101b, and conducts the PCIe bus channels between itself and the switch chip 106a, and to GPU103e ⁇ 103h.
  • the PCIe bus topology K2 corresponding to the graphics rendering scenario can also be defined in the scenario dictionary.
  • the topology K2 can evenly distribute all GPUs under each CPU.
  • the PCIe bus topology K3 adapted to the HPC scenario can also be defined in the scenario dictionary, and so on. This embodiment does not make specific limitations.
  • BMC104 determines the target application scenario that the user wants to configure based on the first information, it can query the scenario dictionary and quickly and efficiently determine the target PCIe bus topology structure applicable to the target application scenario based on the mapping relationship between the scenarios defined in the scenario dictionary and the PCIe bus topology structure.
  • the management chip generates switching information according to the target PCIe bus topology.
  • BMC 104 may generate switching information according to the topology.
  • the switching information may be used to indicate the communication state (eg, on or off) of each PCIe bus channel of each switching chip 106 .
  • the generated switching information indicates that the switching chip 106a turns on all PCIe bus channels connected to it, and the switching chip 106b turns off the connection channel between itself and the CPU 101b, and turns on the PCIe bus channels between itself and the switching chip 106a, and to the GPUs 103e to 103h.
  • the target PCIe bus topology is the above-mentioned topology K2 or K3, etc.
  • the generated switching information indicates that each switching chip 106 is configured with the connection relationship set by the topology K2 or K3.
  • the management chip transmits the switching information to the corresponding switching device, so that the switching device switches the PCIe bus connection relationship between the plurality of graphics processors and the corresponding main processor.
  • BMC 104 generates switching information, which can be transmitted to logic device CPLD 107 through its interface, and CPLD 107 executes S2 to decode and translate it into control instructions. Then, S3 is executed and transmitted from the corresponding bus to the switch chip 106, so that these switch chips 106 execute S4 to act (or not act) according to the instruction, turn on/off the PCIe bus channel of the GPU, and form a PCIe bus topology structure that adapts to the user's demand scenario.
  • the switching information is translated by CPLD 107 and sent to the switching chips 106a and 106b respectively, so that the switching chip 106a conducts all PCIe bus channels connected to it, and the switching chip 106b closes the connection channel between itself and CPU 101b, and conducts the PCIe bus channels between itself and the switching chip 106a, and to GPU 103e-103h.
  • the switching information is translated by CPLD107 and sent to the switching chips 106a and 106b respectively, so that the switching chips 106a and 106b respectively turn on the channels between the CPUs and GPUs to which they are connected, so that the GPU (103a ⁇ 103d) is mounted under CPU101a, and the GPU (103e ⁇ 103h) is mounted under CPU101b.
  • the method of this embodiment can automatically identify the GPU type, thereby automatically matching the PCIe high-speed topology, realizing adaptive control of PCIe bus topology configuration, enabling the electronic device 100 to achieve the best application performance, reducing manual intervention, improving the deployment efficiency of the machine, and bringing improved operational efficiency to customers.
  • BMC104 can directly execute the aforementioned steps S4022 to S4023 and the aforementioned S403 based on the configuration information, and adaptively generate a switching information and send it to the switching chip 106 to control the switching chip 106 to configure a PCIe bus topology suitable for the application scenario.
  • BMC104 can directly execute the aforementioned S4023 and the aforementioned S403 steps to generate a switching information and send it to the switching chip 106 to control the switching chip 106 to configure a PCIe bus topology structure suitable for the application scenario.
  • the embodiment of the present application provides a PCIe topology configuration device.
  • Figure 6 is a structural schematic diagram of a PCIe topology configuration device provided by the embodiment of the present application. It can be understood that the device can be deployed in the electronic device 100 shown in Figures 1, 2 and 3 above, and can also be deployed in other devices and equipment with computing and processing capabilities.
  • the PCIe topology configuration device 600 may include an acquisition module 601 and a processing module 602.
  • the acquisition module 601 may be used to acquire first information, which includes type identification information and/or configuration information of each graphics processor.
  • the processing module 602 may be used to generate switching information corresponding to the target application scenario based on the first information.
  • the processing module 602 may also be used to transmit the switching information to the corresponding switching device.
  • the switching device switches the PCIe bus connection relationship between the multiple graphics processors and the corresponding main processor.
  • the processing module 602 can be specifically used to determine the target application scenario corresponding to the type identification information in the first information based on the mapping relationship between the predefined type identification information and the application scenario, query the preset scenario dictionary based on the target application scenario, and match the target PCIe bus topology structure corresponding to the target application scenario.
  • the scenario dictionary is used to characterize the mapping relationship between multiple application scenarios and multiple PCIe bus topology structures, and generate corresponding switching information based on the target PCIe bus topology structure.
  • the above-mentioned device is used to execute the method in the above-mentioned embodiment.
  • the implementation principle and technical effect of the corresponding program module in the device are similar to those described in the above-mentioned method.
  • the working process of the device can refer to the corresponding process in the above-mentioned method, which will not be repeated here.
  • an embodiment of the present application provides a computer-readable storage medium, which stores a computer program.
  • the computer program runs on a processor, the processor executes the method in the above embodiment.
  • an embodiment of the present application provides a computer program product, characterized in that when the computer program product runs on a processor, the processor executes the method in the above embodiment.
  • the embodiment of the present application further provides a chip.
  • Figure 7 is a schematic diagram of the structure of a chip provided in the embodiment of the present application.
  • the chip 700 includes one or more processors 701 and an interface circuit 702.
  • the chip 700 may also include a bus 703. Among them:
  • the processor 701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 701 or an instruction in the form of software.
  • the above-mentioned processor 701 can be a general-purpose processor, a digital communicator (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • DSP digital communicator
  • ASIC application-specific integrated circuit
  • FPGA field programmable gate array
  • the disclosed methods and steps in the embodiments of the present application can be implemented or executed.
  • the general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.
  • the interface circuit 702 can be used to send or receive data, instructions or information.
  • the processor 701 can use the data, instructions or other information received by the interface circuit 702 to process, and can send the processing completion information through the interface circuit 702.
  • the chip 700 further includes a memory, which may include a read-only memory and a random access memory, and provides operation instructions and data to the processor.
  • a portion of the memory may also include a non-volatile random access memory (NVRAM).
  • NVRAM non-volatile random access memory
  • the memory stores executable software modules or data structures
  • the processor can perform corresponding operations by calling operation instructions stored in the memory (the operation instructions can be stored in the operating system).
  • the interface circuit 702 may be used to output the execution result of the processor 701 .
  • processor 701 and the interface circuit 702 can be implemented through hardware design, software design, or a combination of hardware and software, which is not limited here.
  • each step of the above method embodiment can be completed by a hardware-based logic circuit or a software-based instruction in a processor.
  • each step in the above embodiment can be selectively executed according to actual conditions, and can be partially executed or fully executed, which is not limited here.
  • the method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions.
  • the software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium.
  • the storage medium can also be a component of the processor.
  • the processor and the storage medium can be located in an ASIC.
  • the computer program product includes one or more computer instructions.
  • the computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer-readable storage medium or transmitted via the computer-readable storage medium.

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Abstract

一种电子设备及其PCIe拓扑配置方法和装置，涉及计算机技术领域。其中，电子设备（100）中包括至少一个主处理器（101）、多个图形处理器（103）以及管理芯片（104），每个主处理器（101）与多个图形处理器（103）之间通过外围组件互联PCIe总线连接至少一个切换器件（106），每个切换器件（106）均与管理芯片（104）通信连接。其中，管理芯片（104）用于根据第一信息，生成对应目标应用场景的切换信息（S402），第一信息包括每个图形处理器（103）的类型标识信息和/或配置信息，切换器件用于根据切换信息，切换多个图形处理器（103）与对应主处理器（101）之间的PCIe总线连接关系（S403），使配置的拓扑结构适配当前目标应用场景，利于电子设备（100）达到最佳应用性能。这样，在配置拓扑结构过程中，可以减少人工的干预，利于极大程度地提高电子设备（100）中PCIe总线拓扑的配置效率。

Description

一种电子设备及其PCIe拓扑配置方法和装置
本申请要求于2022年10月13日提交中国专利局、申请号为202211253037.6、申请名称为“一种电子设备及其PCIe拓扑配置方法和装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，尤其涉及一种电子设备及其PCIe拓扑配置方法和装置。
背景技术
GPU(graphics processing unit)服务器可以有多种GPU选型，不同类型的GPU通常可以对应适用于训练、推理以及高性能计算(high performance computing,HPC)等场景中。企业用户期望利用一台GPU服务器来尽可能覆盖多种场景，但是每种场景下，都需要对应配置GPU服务器内用于支持GPU通信的高速外围组件互联PCIe总线拓扑架构，目前配置PCIe总线拓扑架构时多是通过专业人员手动调整，效率低下。
发明内容
本申请提供了一种电子设备及其PCIe拓扑配置方法和装置，能够实现服务器中自适应切换PCIe拓扑结构。
第一方面，本申请提供一种电子设备，电子设备中包括至少一个主处理器、多个图形处理器以及管理芯片，每个主处理与该多个图形处理器之间通过外围组件互联PCIe总线连接至少一个切换器件，每个切换器件均与管理芯片通信连接。其中，管理芯片用于根据第一信息，生成对应目标应用场景的切换信息，第一信息包括每个图形处理器的类型标识信息和/或配置信息，切换器件用于根据切换信息，切换多个图形处理器与对应主处理器之间的PCIe总线连接关系。
本实施例中，电子设备可以是工作站、GPU服务器以及超级终端等，多个图形处理器可以是用于深度学习中的训练/推理场景的GPU，用于图形渲染场景的GPU或者用于HPC场景的GPU，但不限于此。多个图形处理器通过PCIe总线连接在切换器件上，可以由切换器件切换GPU至对应主处理器的通信路径。
在本实施例可能的实现方式中，电子设备的管理芯片(如baseboard management controller，BMC)可以在图形处理器接入电子设备之后，监测获取这些图形处理器的类型标识信息或其他配置信息，生成对应当前图形处理器所适用的目标应用场景的切换信息，以控制切换器件执行相应的动作，完成多个图形处理器与对应主处理器之间的PCIe总线拓扑的配置，使配置的拓扑结构适配当前目标应用场景，利于电子设备达 到最佳应用性能。并且，在配置拓扑结构过程中，可以减少人工的干预，利于极大程度地提高电子设备中PCIe总线拓扑的配置效率。
在一些可能的实现方式中，电子设备中包括固件模块，该固件模块用于读取各个图形处理器的类型标识信息，以作为第一信息上报至管理芯片。
本实现方式中，固件模块可以是存储在电子设备存储器中的BIOS固件，利用BIOS自动读取GPU的类型标识信息上报到BMC，不必人工输入配置信息，形成了从自动采集GPU相关信息，到BMC自动生成切换信息，最后由切换器件根据切换信息配置GPU所在拓扑结构的一系列闭环控制，实现配置的自动化。
在一些可能的实现方式中，管理芯片具体用于根据预定义的类型标识信息与应用场景的映射关系，确定第一信息中的类型标识信息对应的目标应用场景。
本实现方式中，利用预先定义的类型标识信息与应用场景的映射关系，可以在管理芯片获取第一信息之后，快速高效地确定用户想要将设备适用的目标应用场景。
在一些可能的实现方式中，管理芯片具体还用于根据目标应用场景查询预设的场景字典，匹配得到目标应用场景对应的目标PCIe总线拓扑结构，场景字典用于记录多个应用场景与多种PCIe总线拓扑结构的映射关系，并根据目标PCIe总线拓扑结构，生成对应的切换信息。
本实现方式中，利用预先定义的场景字典，可以在管理芯片确定目标应用场景之后，快速高效地确定适配该场景的PCIe总线拓扑结构。
在一些可能的实现方式中，配置信息中可以包括目标应用场景信息和/或目标PCIe总线拓扑结构信息。这样，根据用户输入的目标应用场景信息或目标PCIe总线拓扑结构信息，管理芯片可以通过查询场景字典或直接生成的方式，生成对应的切换信息。这样，可以满足用户直接配置PCIe总线拓扑结构的需求，利于提高电子设备的兼容性。
在一些可能的实现方式中，主处理为多个，每个主处理通过PCIe总线连接一个切换器件，相邻的切换器件之间通过PCIe总线连接，多个图形处理器分别通过PCIe总线连接在对应的切换器件上，每个切换器件，具体用于根据切换信息，切换其所连接的图形处理器、主处理器和/或与之相邻切换器件之间的PCIe总线连接关系。这样，多个主处理以及多个切换器件形成的PCIe总线网络，利于满足用户根据不同应用场景接入对应图形处理器，灵活配置PCIe总线拓扑结构的需求。
第二方面，本申请实施例提供了一种PCIe拓扑配置方法，方法应用于电子设备，电子设备中包括至少一个主处理器、多个图形处理器以及管理芯片，每个主处理与多个图形处理器之间通过外围组件互联PCIe总线连接至少一个切换器件，每个切换器件均与管理芯片通信连接；
方法包括：管理芯片获取第一信息，第一信息包括每个图形处理器的器件信息和/或配置信息，管理芯片根据第一信息，生成对应目标应用场景的切换信息；管理芯片还将切换信息传输至切换器件，以使切换器件切换多个图形处理器与对应主处理器的PCIe总线连接关系。
在一些可能的实现方式中，在管理芯片获取第一信息之前，方法包括：电子设备中的固件模块读取各个图形处理器的类型标识信息，以作为第一信息上报至管理芯片。
在一些可能的实现方式中，管理芯片根据第一信息，生成对应目标应用场景的切 换信息，包括：根据预定义的类型标识信息与应用场景的映射关系，确定第一信息中的类型标识信息对应的目标应用场景；根据目标应用场景查询预设的场景字典，匹配得到目标应用场景对应的目标PCIe总线拓扑结构，场景字典用于记录多个应用场景与多种PCIe总线拓扑结构的映射关系；根据目标PCIe总线拓扑结构，生成对应的切换信息。
在一些可能的实现方式中，配置信息中包括目标应用场景信息和/或目标PCIe总线拓扑结构信息。
第三方面，本申请提供一种计算机可读存储介质，计算机可读存储介质存储有计算机程序，当计算机程序在处理器上运行时，使得处理器执行第二通方面或第二方面的任一种可能的实现方式所描述的方法。
第四方面，本申请提供一种计算机程序产品，其特征在于，当计算机程序产品在处理器上运行时，使得处理器执行第二方面或第二方面的任一种可能的实现方式所描述的方法。
第五方面，本申请提供一种芯片，其特征在于，包括至少一个处理器和接口；至少一个处理器通过接口获取程序指令或者数据；至少一个处理器用于执行程序行指令，以实现第二方面或第二方面的任一种可能的实现方式所描述的方法。
可以理解的是，上述第二方面至第五方面的有益效果可以参见上述第一方面中的相关描述，在此不再赘述。
附图说明
图1是本申请实施例提供的一种电子设备的硬件结构示意图；
图2是本申请一个具体实施例提供的电子设备的硬件结构示意图；
图3是本申请实施例提供的一种电子设备的架构示意图；
图4是本申请实施例提供的一种PCIe拓扑配置方法的流程示意图；
图5是本申请一个具体实施例提供的一种PCIe拓扑配置方法的流程示意图；
图6是本申请实施例提供的一种PCIe拓扑配置方装置的结构示意图；
图7是本申请实施例提供的一种芯片的结构示意图。
具体实施方式
本文中术语“和/或”，是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。本文中符号“/”表示关联对象是或者的关系，例如A/B表示A或者B。
本文中的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序。例如，第一信息和第二信息等是用于区别不同的信息，而不是用于描述信息的特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或者两个以上，例如，多个处理单元是指两个或者两个以上的处理单元等；多个元件是指两个或者两个以上的元件等。
为便于理解本申请的技术方案，下面对本文中涉及的相关术语进行解释。
GPU(graphics processing unit)：图形处理器，又称显示核心、视觉处理器、显示芯片，是一种专门在电子设备(如个人电脑、工作站、服务器和一些移动设备等)上做图像和图形相关运算工作的微处理器。
GPU卡：承载GPU的板卡，也可以称为显卡。
CPU(central processing unit)：中央处理器，其作为计算机系统的运算和控制核心，是信息处理、程序运行的最终执行单元。
PCIe(peripheral component interconnect express，PCI-Express)：高速外围组件互连，是一种高速串行计算机扩展总线标准，PCIe属于高速串行点对点双通道高带宽传输，所连接的设备分配独享通道带宽，不共享总线带宽，主要支持主动电源管理，错误报告，端对端的可靠性传输，热插拔以及服务质量(QOS)等功能。
P2P(peer to peer):对等网络，端到端的传输网络。
BIOS(basic input output system):基本输入输出系统。其实，它是一组固化到计算机内主板上一个ROM(read-only memory，只读存储器)芯片的程序，也称为“BIOS固件”，它保存着计算机最重要的基本输入输出的程序、开机后自检程序和系统自启动程序，它可从随机存取存储器CMOS RAM中读写系统设置的具体信息。BIOS的主要功能是为计算机提供最底层的、最直接的硬件设置和控制。此外，BIOS还向作业系统提供一些系统参数。
BMC(baseboard management controller):基板管理控制器，即执行伺服器远端管理控制器，它可以在机器未开机的状态下，对机器进行固件升级、查看机器设备等一些操作。
RAID(redundant arrays of independent disks)：冗余磁盘阵列。
GPU服务器中可以搭载多个GPU卡来执行图形和密集型计算任务，适用于深度学习训练、科学计算、图形图像处理、视频编解码等场景，可以为自动光学检测、辅助驾驶和医疗行业的图像处理和边缘AI人工智能加速运算等领域提供快速、稳定、弹性的计算力支持。
其中，GPU服务器中的GPU通常根据类型(或型号)的不同，而具有其侧重的功能。例如，有一些GPU侧重训练/推理，有一些GPU侧重图形渲染，还有一些GPU侧重高密性计算等。用户根据场景需求对GPU选型，并且在将所选的对应类型的GPU接入服务器后，为了使GPU服务器达到最佳性能，还需要对GPU所在的PCIe拓扑结构进行适配。但是，传统的人工手动配置PCIe拓扑的方式效率低下，降低了运营效率。
为了提高服务器中PCIe拓扑的配置效率，减少人工干预，本申请实施例中提供了PCIe拓扑配置方法、装置、电子设备、计算机存储介质及计算机程序产品，其主要是根据电子设备(如GPU服务器)的应用场景，自适应切换服务器中的PCIe拓扑结构，从而实现PCIe拓扑的高效配置，提升服务器的运营效率。
为便于理解本申请的技术方案，下面首先对本申请实施例提供的电子设备进行阐述。
示例性的，图1示出了一种电子设备的硬件结构示意图。其中，电子设备100可以是一种能够提供数据处理功能、运算功能以及存储功能等的硬件设备，例如，工作站、GPU服务器或者是超级终端，但不限于此。如图1所示，本申请实施例提供的电子设备100可以包括处理器101、存储器102、图形处理器103、管理芯片104以及通信接口105，电子设备200中这些部件可以集成在主板上，且部件之间可以通过总线110连接以完成相互间的通信。
其中，处理器101可以包括各种处理设备，例如可以是中央处理器(central processing unit，CPU)、片上系统(system on chip，SOC)、集成在SOC上的处理器、单独的处理器芯片或控制器等：该处理器101还可以包括专用处理设备，例如专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field programmable gate array，FPGA)、数字信号处理器(digital signal processor，DSP)等。该处理器101可以是多个处理器构成的处理器组，多个处理器之间通过一个或多个总线彼此耦合。例如图2中示出的一些具体示例中的电子设备100的硬件结构示意图，其主板上可以包括2个CPU(101a,101b),CPU101a和CPU101b之间通过三路超级通道互联(ultra path interconnect,UPI)总线耦合，实现这两个处理器之间的高速通信。另外，CPU101a和CPU101b上均具有多个接口以连接其他部件(如硬盘1021、GPU10卡103、PCIe标卡120等)。
存储器102可以耦合到处理器101，具体的，该存储器102可以通过一个或多个存储器控制器耦合到处理器101。存储器102可以用于存储计算机程序指令，包括计算机操作系统(operation system，OS)、BIOS固件和各种程序。该存储器102可以是非掉电易失性存储器(non-volatile memory，NVM)，例如是嵌入式多媒体卡(embedded multi media card，EMMC)、通用闪存存储(universal flash storage，UFS)或只读存储器(read-only memory，ROM)，或者是可存储静态信息和指令的其他类型的静态存储设备，还可以是掉电易失性存储器(volatile memory)，例如随机存取存储器(random access memory，RAM)或者可存储信息和指令的其他类型的动态存储设备，也可以是电可擦可编程只读存储器(electrically erasable programmable read-only memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其他光盘存储、磁盘存储介质或者其他存储设备、或者能够用于携带或存储具有指令或数据结构形式的程序代码并能够由计算机存取的任何其他计算机可读存储介质，但不限于此。存储器102可以是独立存在，存储器102也可以和处理器101集成在一起。在一些示例中，如图2所示的，各个CPU(101a,101b)上可以通过接口连接硬盘1021、磁盘阵列(RAID)1022等存储器102，以支持CPU(101a,101b)的计算、处理等操作。
图形处理器(GPU)103可以包括各种类型的用于图形和密集型计算的微处理器，例如是用于进行深度学习训练/推理的GPU，用于进行图形渲染的GPU，以及用于进行HPC计算的GPU等，但不限于此。多个GPU103可以耦合到处理器(即主处理器)101，根据处理器101的控制执行相应任务，例如多个GPU103可以耦合在处理器101上，并在处理器101运行应用程序时，分担应用程序计算密集部分的工作负载。
在一些示例中，处理器101可以包括M(M≥2)个CPU，多个GPU103通过N(N≥1)个切换芯片(PCIe Switch，PCIe SW)106挂载在M个CPU上，CPU和GPU103均与切换芯片106通过高速外围组件互连PCIe总线连接。当N≥2时，相邻两个切换芯片106之间也通过PCIe总线连接。可以理解，PCIe SW106作为切换器件，能够提供扩展或聚合能力,并允许更多的设备(如处理器101、GPU103等)连接到一个PCle端口，PCIe SW106可以根据地址或其他路由信息识别给定的包需要走哪条路径，是一种PCIe转PCIe的桥。
举例说明，参考图2所示，两个CPU(101a,101b)通过两个切换芯片(106a，106b)挂载8个GPU(103a～103h)，两个切换芯片(106a，106b)之间也通过PCIe总线连接，这样，通过两个切换芯片(106a，106b)的协同切换，可以控制所有GPU(103a～103h)与CPU(101a,101b)之间的PCIe连接关系，从而可以实现对GPU103与CPU(101a,101b)连接通道的配置。例如，切换芯片106b关闭其与CPU101b之间的连接通道，并导通其与切换芯片106a之间、以及至GPU103e～103h的连接通道，这样配置得到的PCIe拓扑结构使CPU101a上挂载8个GPU(103a～103h)。
示例性的，继续参考图1和图2所示，电子设备100中还包括管理芯片104，管理芯片104可以是基板管理控制器BMC，BMC104用于对电子设备100的硬件(包括各个GPU103)以及接入的硬件设备(如硬盘10221、磁盘阵列1022、PCIe标卡120等)进行监视和控制。例如，可以监视电子设备100的温度、电压等信息，并做相应的调节工作，以保证电子设备100处于正常运行的状态。BMC104还可以记录各种硬件或节点的信息和日志、提供事件日志、恢复控制和配置等监控管理功能。需要说明的是，BMC104是一个独立的器件，它不依赖于电子设备100中的其它硬件(例如处理器101或者存储器102等)，也不依赖于OS，但是BMC104可以与OS交互。
在本示例中，参考图3所示，电子设备100中的BIOS130可以读取PCIe总线上连接的各个GPU(103a～103h)的类型标识信息(如型号、身份ID等参数)，并将其上报给BMC104，接着，BMC104可以根据获取的这些信息后可以分析当前的目标应用场景，并控制切换芯片(106a，106b)适应该目标应用场景来执行对应的切换动作，以完成PCIe拓扑结构的配置操作，从而适应目标应用场景将接入的GPU挂载到对应的CPU上，以使设备达到最佳性能。
在一些具体示例中，继续参考图3所示的，BMC104与各个切换芯片(106a，106b)之间设置有逻辑器件(complex programmable logic device，CPLD)107。BMC104可以通过总线(如CPU总线localbus、串行总线I2C)连接该逻辑器件107的输入端，该逻辑器件107的输出端分别通过总线(如串行总线I2C)连接至各个切换芯片(106a，106b)。这样，BMC104可以将切换信息传输至逻辑器件107进行解码、转译，生成控制指令输出到对应的切换芯片(106a，106b)，执行切换动作。
通信接口105主要用于实现本申请实施例中各模块、装置、单元和/或设备之间的通信。
本实施例中，总线110包括一种或多种通信协议的总线。并且，总线110包括硬件、软件或两者，将电子设备100的部件彼此耦接在一起。举例来说而非限制，总线110可以包括上述PCIe总线、UPI总线、localbus总线、I2C总线等，还可以包括加速 图形端口(AGP)或其他图形总线、增强工业标准架构(EISA)总线、前端总线(FSB)、超传输(HT)互连、工业标准架构(ISA)总线、无限带宽互连、低引脚数(LPC)总线、存储器总线、微信道架构(MCA)总线、外围组件互连(PCI)总线、串行高级技术附件(SATA)总线、视频电子标准协会局部(VLB)总线或其他合适的总线或者两个或更多个以上这些的组合。应理解的是，尽管本申请实施例描述和示出了特定的总线，但本申请考虑任何合适的总线或互连。
可以理解的是，本申请实施例示意的结构并不构成对电子设备100的具体限定。在本申请另一些实施例中，电子设备100可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
并且，可以理解的是，本方案中，电子设备100的示例性实施例包括但不限于搭载iOS、android、Windows、鸿蒙系统(Harmony OS)或者其他操作系统的电子设备。
接下来，基于上文所描述的内容，对本申请实施例提供的一种PCIe拓扑配置方法进行介绍。可以理解的是，该方法是基于上文所描述的内容提出，该方法中的部分或全部内容可以参见上文中的描述。
请参阅图4，图4是本申请实施例提供的一种PCIe拓扑配置方法的流程示意图。可以理解，该方法可以通过图1、图2以及图3中所示的电子设备100来执行，也可以通过其他具有计算、处理能力的装置、设备来执行。如图4所示，该PCIe拓扑配置方法可以包括S401至S403：
S401，管理芯片获取第一信息，该第一信息包括每个图形处理器的类型标识信息和/或配置信息。
本实施例中，在配置GPU服务器等电子设备100时，可以根据业务需求对图形处理器GPU选型，例如，若用户需要将设备用于深度学习的训练/推理场景，可以选择侧重训练/推理功能的型号的GPU，如英伟达(NVIDIA)A100型号的GPU，若用户需要将设备用于图形处理场景，可以选择侧重图形渲染功能的型号的GPU，如英伟达A40型号的GPU等。用户选择相应类型的GPU103挂载在处理器(下文以“CPU”为例阐述)101下之后，各GPU103与其所挂载的CPU之间的通信路径由切换芯片106进行适应性切换，换言之，各GPU和CPU所在的PCIe总线拓扑结构可以通过切换芯片106实现配置。其中，配置PCIe总线拓扑结构时，是依据管理芯片BMC104监测到的第一信息进行分析，识别当前用户需求的应用场景，从而对切换芯片106进行对应的切换控制，以减少人工对PCIe总线拓扑结构部署的干预。
示例性的，结合图5所示的，BMC104获取的第一信息可以是通过S1a，由BIOS130上报的信息，也可以是通过S1b，由用户基于BMC104提供的管理界面输入的配置信息。
下面对第一信息的不同来源的示例进行详细说明。
示例性的，在S1a,BIOS读取各个图形处理器的类型标识信息,以作为第一信息上报至BMC104。
本示例中，继续参考图1-图3所示，在用户将选定的GPU103接入电子设备100 主板上，连接切换芯片106之后，当整机系统开始工作，电子设备100中的BIOS130可以自动读取各个GPU103的型号、身份ID等类型标识信息，并将这些类型标识信息上报给管理芯片BMC104。可以理解，BIOS130上报给管理芯片BMC104的这些信息即前述第一信息。这样，管理芯片BMC104后续可以进行下文S402至S403的步骤，以根据各个GPU103的类型标识信息，分析确定用户想要设备应用的场景，从而自适应生成用于指示配置适合该场景的PCIe总线拓扑结构的切换信息。
在一些具体示例中，可以将多个GPU均匀接入多个CPU各自所连接的切换芯片106下，如参考图2和图3所示的，CPU101a和CPU101b分别通过切换芯片106a和切换芯片106b接入4个GPU103。在一些其他示例中，多个GPU接入多个CPU所连接的切换芯片106时，也可以不均匀地部署，如一个CPU下接入2个GPU，另一个CPU下接入4个GPU等。这样，利于实现GPU的灵活部署。
示例性的，在S1b,管理芯片获取用户输入的配置信息。
本示例中，用户也可以基于一些电子设备100的外设(如键盘)输入相应的配置信息，该配置信息可以包括目标应用场景的信息，也可以包括当前要切换的目标PCIe总线拓扑结构的信息等。
例如，用户可以基于界面(如BMC104提供的BMC管理界面)输入用于描述目标应用场景(如图形渲染场景、训练场景或HPC场景等)的配置信息，该配置信息可以作为第一信息传输到BMC104。可以理解，该界面可以由电子设备100连接的显示器等硬件设备显示。
或者，每个切换芯片106的各PCIe总线通道(lane)都具有唯一的通道标识，用户还可以基于界面直接输入控制切换芯片106上PCIe总线通道的信息，即控制各切换芯片106哪些通道导通以及哪些通道关闭的信息，进而生成描述当前要切换的目标PCIe总线拓扑结构的配置信息，该配置信息可以作为第一信息传输给BMC104。
在本实施例中，当BMC104通过前述S401，获取从BIOS130或界面传输的上述第一信息后，可以执行：
S402，管理芯片根据第一信息，生成对应目标应用场景的切换信息。
本实施例中，BMC104可以根据从上述BIOS130或管理界面获取的第一信息，进行分析以生成切换信息，从而对各个GPU103所连接的切换芯片106控制，使切换芯片106进行PCIe总线通道切换。
示例性的，若第一信息是BIOS130上报的信息，则当BMC104执行S402时，具体可以包括S4021至S4023：
S4021，管理芯片根据预定义的类型标识信息与应用场景的映射关系，确定第一信息中的类型标识信息对应的目标应用场景。
本实施例中，可以预先定义类型标识信息与应用场景的映射关系，例如设定型号为“A100”的GPU对应训练/推理场景，型号为“A40”的GPU对应图形渲染场景等。这样，当BMC104获取第一信息后，可以根据第一信息中的类型标识信息自动识别出这些GPU适用的目标应用场景，即用户想要电子设备100应用的场景。
例如，BIOS130上报的类型标识信息中，包括“A100”和“A30”型号的信息，若BMC104通过预定义的类型标识信息与应用场景的映射关系，确定这两个型号的 GPU对应训练/推理场景，则将训练/推理场景确定为目标应用场景，这样不必用户干预，BMC104就能够分析出用户的需求(即用户要适配的目标应用场景)。
同理，如果BIOS130上报的类型标识信息中，包括“A40”、“A30”、“A10”、“A2”四个型号的信息，接着BMC104通过预定义的类型标识信息与应用场景的映射关系，确定这四个型号的GPU中用于图形渲染、虚拟桌面的型号占多数，即当前接入的所有GPU侧重图形渲染/虚拟桌面的场景，则可以将图形渲染/虚拟桌面的场景确定为目标应用场景。
S4022，管理芯片根据目标应用场景查询场景字典，确定该目标应用场景对应的目标PCIe总线拓扑结构。
本实施例中，在BMC104生成切换信息过程中，可以通过调用场景字典进行应用场景的分析。其中，该场景字典为预先定义的字典，以记录各个应用场景与PCIe总线拓扑结构之间的映射关系，其中，PCIe总线拓扑结构包括CPU与切换芯片之间、各个切换芯片之间、以及切换芯片与GPU之间的PCIe总线构成的连接关系。
举例说明，在场景字典中可以定义训练/推理场景对应PCIe总线拓扑结构K1，结合图3所示，由于训练场景需要支持单根(single root)拓扑，即所有的GPU挂在1个CPU下面，所以在该拓扑结构K1中，可以设定切换芯片106a导通自身所连接的所有PCIe总线通道，且切换芯片106b关闭自身与CPU101b之间的连接通道，并导通自身与切换芯片106a之间、以及至GPU103e～103h的PCIe总线通道。同理，在场景字典中还可以定义图形渲染场景对应PCIe总线拓扑结构K2，该拓扑结构K2能够使所有GPU均匀分布在各CPU下，此外，在场景字典中还可以定义适配HPC场景的PCIe总线拓扑结构K3，等等，本实施例不做具体限定。
这样，BMC104根据第一信息确定用户要配置的目标应用场景后，就可以通过查询场景字典，依据场景字典中定义的场景与PCIe总线拓扑结构的映射关系，快速高效地确定该目标应用场景适用的目标PCIe总线拓扑结构。
S4023，管理芯片根据目标PCIe总线拓扑结构，生成切换信息。
本实施例中，BMC104确定目标PCIe总线拓扑结构后，可以根据该拓扑结构生成切换信息，该切换信息可以用于指示各切换芯片106的各PCIe总线通道处于何种通信状态(如导通或关闭)。
例如，如果目标PCIe总线拓扑结构为上述拓扑结构K1，则生成的切换信息中指示切换芯片106a导通自身所连接的所有PCIe总线通道，且切换芯片106b关闭自身与CPU101b之间的连接通道，并导通自身与切换芯片106a之间、以及至GPU103e～103h的PCIe总线通道。同理，如果目标PCIe总线拓扑结构为上述拓扑结构K2或K3等，则生成的切换信息中对应指示各切换芯片106配置出拓扑结构K2或K3设定的连接关系。
本实施例中，当BMC104通过前述S402生成切换信息之后，可以执行以下S403：
在S403，管理芯片将切换信息传输至对应的切换器件，以使该切换器件切换多个图形处理器与对应主处理器的PCIe总线连接关系。
本实施例中，参考图5所示，BMC104生成切换信息，可以通过其接口将该切换信息传输到逻辑器件CPLD107，由CPLD107执行S2，进行解码，并翻译为控制指令， 接着执行S3，从相应的总线传输到切换芯片106，使这些切换芯片106执行S4按照指令动作(或不动作)，导通/关闭GPU的PCIe总线通道，形成适配用户需求场景的PCIe总线拓扑结构。
例如，参考图3所示，若切换信息对应的目标PCIe总线拓扑结构是上述拓扑结构K1，则切换信息由CPLD107转译后分别发送到切换芯片106a和106b，使切换芯片106a导通自身所连接的所有PCIe总线通道，且使切换芯片106b关闭自身与CPU101b之间的连接通道，并导通自身与切换芯片106a之间、以及至GPU103e～103h的PCIe总线通道。这样形成的PCIe总线拓扑中,GPU(103a～103d)与GPU(103e～103h)之间可以通过切换芯片(106a，106b)实现P2P通信，所有GPU(103a～103h)均挂在CPU101a下面。
同理，若切换信息对应的目标PCIe总线拓扑结构是上述拓扑结构K2，则切换信息由CPLD107转译后分别发送到切换芯片106a和106b，使切换芯片106a和106b分别导通各自所接入的CPU和GPU之间的通道，使GPU(103a～103d)挂载在CPU101a下面，且GPU(103e～103h)挂载在CPU101b下面。
这样，从BIOS130对GPU103类型标识信息的自动采集，到BMC104的自动识别应用场景和确定切换信息，再经由逻辑器件107转译传输，最后由切换芯片106执行切换GPU103与GPU的通信通道，形成了“GPU103→BMC104→CPLD107→PCIe SW106→GPU103”的一个闭环的控制链，以GPU103为输入控制点，根据GPU使用的不同场景来决定不同的PCIe拓扑。即，本实施例的方法能够自动识别GPU类型，从而自动匹配PCIe高速拓扑，实现自适应控制PCIe总线拓扑配置，使电子设备100达到最佳的应用性能，减少人工干预，提升了机器的部署效率，给客户带来运营效率的提升。
在另一些可能的实现方式中，若第一信息是从管理界面获取的用于描述应用场景信息的配置信息，则BMC104可以直接根据该配置信息，执行前述S4022至S4023以及前述S403的步骤，自适应生成一个切换信息发送到切换芯片106，以控制切换芯片106配置适合该应用场景的PCIe总线拓扑结构。
若第一信息是从管理界面获取的用于描述当前要切换的PCIe总线拓扑结构信息的配置信息，则BMC104可以直接执行前述S4023以及前述S403的步骤，生成一个切换信息发送到切换芯片106，以控制切换芯片106配置适合该应用场景的PCIe总线拓扑结构。
基于上述实施例中的方法，本申请实施例提供了一种PCIe拓扑配置装置。请参阅图6，图6是本申请实施例提供的一种PCIe拓扑配置装置的结构示意图。可以理解，该装置可以部署在上述图1、图2以及图3所示的电子设备100中，也可以部署在其他具有计算、处理能力的装置、设备中。
如图6所示，该PCIe拓扑配置装置600，可以包括获取模块601和处理模块602。其中，获取模块601可以用于获取第一信息，该第一信息包括每个图形处理器的类型标识信息和/或配置信息。处理模块602可以用于根据第一信息，生成对应目标应用场景的切换信息。另外，处理模块602还可以用于将切换信息传输至对应的切换器件， 以使该切换器件切换多个图形处理器与对应主处理器的PCIe总线连接关系。
在一些实施例中，处理模块602具体可以用于根据预定义的类型标识信息与应用场景的映射关系，确定第一信息中的类型标识信息对应的目标应用场景，根据目标应用场景查询预设的场景字典，匹配得到目标应用场景对应的目标PCIe总线拓扑结构，场景字典用于表征多个应用场景与多种PCIe总线拓扑结构的映射关系，根据目标PCIe总线拓扑结构，生成对应的切换信息。
应当理解的是，上述装置用于执行上述实施例中的方法，装置中相应的程序模块，其实现原理和技术效果与上述方法中的描述类似，该装置的工作过程可参考上述方法中的对应过程，此处不再赘述。
基于上述实施例中的方法，本申请实施例提供了一种计算机可读存储介质，计算机可读存储介质存储有计算机程序，当计算机程序在处理器上运行时，使得处理器执行上述实施例中的方法。
基于上述实施例中的方法，本申请实施例提供了一种计算机程序产品，其特征在于，当计算机程序产品在处理器上运行时，使得处理器执行上述实施例中的方法。
基于上述实施例中的方法，本申请实施例还提供了一种芯片。请参阅图7，图7为本申请实施例提供的一种芯片的结构示意图。如图7所示，芯片700包括一个或多个处理器701以及接口电路702。可选的，芯片700还可以包含总线703。其中：
处理器701可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器701中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器701可以是通用处理器、数字通信器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或者其它可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本申请实施例中的公开的各方法、步骤。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
接口电路702可以用于数据、指令或者信息的发送或者接收，处理器701可以利用接口电路702接收的数据、指令或者其它信息，进行加工，可以将加工完成信息通过接口电路702发送出去。
可选的，芯片700还包括存储器，存储器可以包括只读存储器和随机存取存储器，并向处理器提供操作指令和数据。存储器的一部分还可以包括非易失性随机存取存储器(NVRAM)。
可选的，存储器存储了可执行软件模块或者数据结构，处理器可以通过调用存储器存储的操作指令(该操作指令可存储在操作系统中)，执行相应的操作。
可选的，接口电路702可用于输出处理器701的执行结果。
需要说明的，处理器701、接口电路702各自对应的功能既可以通过硬件设计实现，也可以通过软件设计来实现，还可以通过软硬件结合的方式来实现，这里不作限制。
应理解，上述方法实施例的各步骤可以通过处理器中的硬件形式的逻辑电路或者软件形式的指令完成。
可以理解的是，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后， 各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。此外，在一些可能的实现方式中，上述实施例中的各步骤可以根据实际情况选择性执行，可以部分执行，也可以全部执行，此处不做限定。
本申请的实施例中的方法步骤可以通过硬件的方式来实现，也可以由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(random access memory，RAM)、闪存、只读存储器(read-only memory，ROM)、可编程只读存储器(programmable rom，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、CD-ROM或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者通过所述计算机可读存储介质进行传输。
可以理解的是，在本申请的实施例中涉及的各种数字编号仅为描述方便进行的区分，并不用来限制本申请的实施例的范围。

Claims (10)

  1. 一种电子设备，其特征在于，所述电子设备中包括至少一个主处理器、多个图形处理器以及管理芯片，每个所述主处理与所述多个图形处理器之间通过外围组件互联PCIe总线连接至少一个切换器件，每个所述切换器件均与所述管理芯片通信连接；
    所述管理芯片用于根据第一信息，生成对应目标应用场景的切换信息，所述第一信息包括每个所述图形处理器的类型标识信息和/或配置信息；
    所述切换器件，用于根据所述切换信息，切换所述多个图形处理器与对应主处理器之间的PCIe总线连接关系。
  2. 根据权利要求1所述的电子设备，其特征在于，所述电子设备中包括固件模块，
    所述固件模块，用于读取各个所述图形处理器的类型标识信息，以作为所述第一信息上报至所述管理芯片。
  3. 根据权利要求1或2所述的电子设备，其特征在于，所述管理芯片具体用于：
    根据预设类型标识信息与应用场景的映射关系，确定所述第一信息中的类型标识信息对应的所述目标应用场景。
  4. 根据权利要求3所述的电子设备，其特征在于，所述管理芯片，具体还用于：
    根据所述目标应用场景查询预设的场景字典，匹配得到所述目标应用场景对应的目标PCIe总线拓扑结构，所述场景字典用于记录多个应用场景与多种PCIe总线拓扑结构的映射关系；
    根据所述目标PCIe总线拓扑结构，生成对应的切换信息。
  5. 根据权利要求1所述的电子设备，其特征在于，所述配置信息中包括目标应用场景信息和/或目标PCIe总线拓扑结构信息。
  6. 根据权利要求1-5任一所述的电子设备，其特征在于，所述主处理为多个，每个所述主处理通过PCIe总线连接一个切换器件，相邻的所述切换器件之间通过PCIe总线连接，
    所述多个图形处理器分别通过PCIe总线连接在对应的所述切换器件上，
    每个所述切换器件，具体用于根据所述切换信息，切换其所连接的图形处理器、主处理器和/或与其相邻切换器件之间的PCIe总线连接关系。
  7. 一种PCIe拓扑配置方法，其特征在于，所述方法应用于电子设备，所述电子设备中包括至少一个主处理器、多个图形处理器以及管理芯片，每个所述主处理与所述多个图形处理器之间通过外围组件互联PCIe总线连接至少一个切换器件，每个所述切换器件均与所述管理芯片通信连接；
    所述方法包括：
    所述管理芯片获取第一信息，所述第一信息包括每个所述图形处理器的器件信息和/或配置信息；
    所述管理芯片根据所述第一信息，生成对应目标应用场景的切换信息；
    所述管理芯片将所述切换信息传输至所述切换器件，以使所述切换器件切换所述多个图形处理器与对应主处理器的PCIe总线连接关系。
  8. 根据权利要求7所述的方法，其特征在于，在所述管理芯片获取第一信息之前，所述方法包括：
    所述电子设备中的固件模块读取各个所述图形处理器的类型标识信息，以作为所述第一信息上报至所述管理芯片。
  9. 根据权利要求7或8所述的方法，其特征在于，所述管理芯片根据所述第一信息，生成对应目标应用场景的切换信息，包括：
    根据预设的类型标识信息与应用场景的映射关系，确定所述第一信息中的类型标识信息对应的所述目标应用场景；
    根据所述目标应用场景查询预设的场景字典，匹配得到所述目标应用场景对应的目标PCIe总线拓扑结构，所述场景字典用于记录多个应用场景与多种PCIe总线拓扑结构的映射关系；
    根据所述目标PCIe总线拓扑结构，生成对应的切换信息。
  10. 根据权利要求7所述的方法，其特征在于，所述配置信息中包括目标应用场景信息和/或目标PCIe总线拓扑结构信息。
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