WO2024023397A1 - Quantum electronic device - Google Patents

Abstract

The present invention relates to an electronic device (1) comprising a silicon-on-insulator strip (100) laterally defined by insulating trenches (106); a first gate (112) supported by the strip; a second gate (114), or a third gate (116), parallel to the strip (100), supported by the strip and being separated from the first gate (112) a first gap (e1) or a second gap (e2); two first semiconductor regions (110), or two second semiconductor regions (108), doped and arranged along and on either side of the second gate (114) or the third gate (116); at least one fourth gate (122A, 122B), or at least one fifth gate (126A, 126B), arranged facing the first gap (e1) or the second gap (e2); and a region (130) for biasing a substrate under the strip.

Description

DESCRIPTION

QUANTUM ELECTRONIC DEVICE

[0001] The present application claims the priority of Greek patent application 20220100602 filed on July 26, 2022 and having the title "Electronic device", which is considered to be an integral part of this description within the limits provided by law.

Technical area

[0002] The present description generally concerns electronic devices, and, more particularly, integrated devices implemented on silicon on insulator (SOI).

Prior art

[0003] Numerous electronic devices integrated on silicon have been proposed, which make it possible to create, in silicon, one or more quantum dots, for use as a storage device for a or several quantum bits (Qubit from English “quantum bit”).

Summary

[0004] There is a need to overcome all or part of the drawbacks of the known electronic devices mentioned above.

[0005] One embodiment overcomes all or part of the drawbacks of the known electronic devices mentioned above.

[0006] One embodiment provides an electronic device comprising: an intrinsically doped P-type silicon strip, the strip resting on an insulating layer itself resting on a semiconductor substrate; insulating trenches laterally delimiting said strip; at least a first grid resting on a central region of said strip; a second grid extending longitudinally in a first direction parallel to the length of said strip, the second grid resting on said strip and being separated from said at least one first grid by a first space; a third grid extending longitudinally in the first direction, the third grid resting on said strip and being separated from said at least one first grid by a second space; two first semiconductor regions doped with a first type of conductivity, arranged along and on either side of a portion of the second gate resting on a corresponding portion of the strip; two second semiconductor regions doped with the first type of conductivity, arranged along and on either side of a portion of the third gate resting on a corresponding portion of the strip; at least a fourth grid arranged opposite and beyond the first space in a second direction orthogonal to the first direction, each fourth grid having at least one portion arranged on the side of the first space which rests entirely on the insulating trenches; at least a fifth grid disposed opposite and beyond the second space in the second direction, each fifth grid having at least one portion disposed on the side of the second space which rests entirely on the insulating trenches; and a silicon region in contact with the substrate to polarize the substrate under said band.

[0007] According to one embodiment, said at least one first grid comprises exactly a first grid, the second and third grids being arranged on either side and other of said first grid in the first direction, and the first, second and third grids being aligned in the first direction.

[0008] According to one embodiment, each fourth grid and each fifth grid rests entirely on the insulating trenches.

[0009] According to one embodiment, the device comprises a control circuit configured to apply a control voltage to the region in contact with the substrate, at least one control voltage to said first gate, a control voltage to the second gate, a control voltage to the third gate, at least one control voltage to said at least one fourth gate and a control voltage to said at least one fifth gate.

[0010] According to one embodiment, said at least one first grid comprises at least two first grids aligned in the first direction and separated in pairs by a third space.

[0011] According to one embodiment, each fourth grid and each fifth grid rests entirely on the insulating trenches

[0012] According to one embodiment, the device comprises, for each third space, at least one sixth grid arranged opposite and beyond the third space, each sixth grid having at least one portion arranged on the side of the corresponding third space which rests entirely on the insulating trenches.

[0013] According to one embodiment, each sixth grid rests entirely on the insulating trenches.

[0014] According to one embodiment, the device comprises a control circuit configured to apply a control voltage to the region in contact with the substrate, at least a control voltage to said at least one first gate, a control voltage to the second gate, a control voltage to the third gate, at least one control voltage to said at least one fourth gate, a control voltage to said at least one fifth gate and at least one control voltage to said at least one sixth gate.

[0015] According to one embodiment, for each third space, said at least one sixth grid comprises exactly two sixth grids arranged on either side of said third space in the second direction, said exactly two grids being aligned in the second direction .

[0016] According to one embodiment, said at least one fourth grid comprises exactly a fourth grid and/or said at least one fifth grid comprises exactly a fifth grid.

[0017] According to one embodiment, said at least one fourth grid comprises exactly two fourth grids arranged on either side of the first space in the second direction and said at least one fifth grid comprises two fifth grids arranged on either side of 'other of the second space in the second direction.

[0018] According to one embodiment, the device comprises a zone devoid of silicidation, said zone comprising at least said at least one first grid, one end of the second grid disposed on the side of said at least one first grid, one end of the third grid disposed on the side of said at least one first grid, at least one portion disposed on the side of the first space of said at least one fourth grid and at least one portion disposed on the side of the second space of said at least one fifth grid. [0019] According to one embodiment, the device is adapted to implement at least one quantum dot and/or a Qubit.

Brief description of the drawings

[0020] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given on a non-limiting basis in relation to the attached figures, among which:

[0021] Figure 1 shows, in top view, an embodiment of an electronic device;

[0022] Figure 2 shows a sectional view of the device of Figure 1 along a section plane AA of Figure 1;

[0023] Figure 3 shows a sectional view of the device of Figure 1 along a section plane BB of Figure 1;

[0024] Figure 4 shows a sectional view of the device of Figure 1 along a section plane CC of Figure 1;

[0025] Figure 5 shows, in top view, an alternative embodiment of the device of Figure 1;

[0026] Figure 6 illustrates by curves the operation of the device of Figure 1;

[0027] Figure 7 illustrates by other curves the operation of the device of Figure 1; And

[0028] Figure 8 illustrates by still other curves the operation of the device of Figure 1.

Description of embodiments

The same elements have been designated by the same references in the different figures. In particular, the structural and/or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. [0030] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been represented and are detailed. In particular, the usual circuits and the usual applications in which one or more electronic devices can be implemented making it possible to form quantum dots, for example to store Qubits, have not been detailed, the embodiments and variants described being compatible with these usual circuits and these usual applications.

Unless otherwise specified, when we refer to two elements connected together, this means directly connected without intermediate elements other than conductors, and when we refer to two connected elements (in English "coupled") between them, this means that these two elements can be connected or be linked via one or more other elements.

[0032] In the description which follows, when reference is made to absolute position qualifiers, such as the terms "front", "rear", "top", "bottom", "left", "right", etc., or relative, such as the terms "above", "below", "superior", "lower", etc., or to qualifiers of orientation, such as the terms "horizontal", "vertical", etc. ., reference is made unless otherwise specified to the orientation of the figures.

Unless otherwise specified, the expressions "approximately", "approximately", "appreciably", and "of the order of" mean within 10%, preferably within 5%.

[0034] Figure 1, Figure 2, Figure 3 and Figure 4 represent in top and sectional views an embodiment of an integrated electronic device 1, for example an integrated electronic device 1 suitable for training of at least one quantum dot. For exemple, when exactly one quantum dot is formed, the device 1 can make it possible to produce a Qubit.

[0035] More particularly, Figure 1 represents a top view of the device 1, Figure 2 represents a sectional view of the device 1 along the plane AA of Figure 1, Figure 3 represents a sectional view of the device 1 according to the plane BB of Figure 1 and Figure 4 represents a sectional view of the device 1 according to the plane CC of Figure 1.

The device 1 comprises a strip 100 of silicon. The silicon in band 100 is intrinsic P type. In other words, the silicon in band 100 has intrinsic P-type doping. For example, the concentration of P-type doping atoms in band 100 is between 5*10 ¹³ and 10 ¹⁵ at. cm ^-3 , for example equal to 10 ¹⁴ at. cm ^-3 . The silicon strip 100 rests on and in contact with an insulating layer 102, for example made of silicon oxide. Layer 102 rests on and in contact with a semiconductor substrate 104, for example made of silicon. The vertical stack of strip 100, layer 102 and substrate 104 forms a silicon on insulator (SOI) type structure.

The strip 100 is delimited laterally by insulating trenches 106, that is to say trenches filled with an insulating material such as silicon oxide. In other words, the trenches 106 form an insulating wall laterally delimiting the strip 100. For example, the trenches 106 are STI (Shallow Trench Insulation) type trenches. The trenches 106 penetrate vertically into the device 1 from an upper face of the device 1 at least up to the insulating layer 104, the upper face of the device being coplanar with the upper face of the strip 100. The strip 100 is delimited laterally by the trenches 106 means that the strip 100 is delimited by the trenches in a first direction parallel to the length of the strip 100 and in a second direction parallel to the width of the strip 100. first and second directions are orthogonal to each other and to the vertical direction of the stack.

By way of example, the strip 100 corresponds to a portion of a layer of silicon on insulator, that is to say that the strip 100 is defined in this layer of silicon on insulator by the trenches 106.

[0040] The device 1 further comprises at least one grid 112 resting on a central part of the strip 100. More particularly, in the embodiment of Figures 1 to 4, the device 1 comprises exactly one grid 112. Preferably, when viewed from above, the grid 112 has a substantially square shape, although, in other examples, the grid 112 may have a substantially circular shape and/or be stretched in the longitudinal direction of the strip 100 (first direction). An electrical contact 113 with the gate 112 can be provided, so as to allow the application of a voltage to the gate 112, and, more precisely, to the gate electrode of the gate 112.

[0041] In the remainder of the description, a "grid" designates a vertical stack of a grid electrode and a gate insulator, and "a grid rests on an element" means that the insulator of this grid rests on and in contact with said element. The definition of "grid" and the meaning of the expression "a grid rests on an element" given above do not apply to the concept of "back grid".

[0042] The device 1 further comprises a grid 114 and a grid 116. Each of the grids 114 and 116 extends in length in the first direction, and width in the second direction. Grids 114 and 116 are aligned with each other in the first direction. The grids 114 and 116 are arranged on either side of the grid 112 in the first direction.

The grid 114 rests on the strip 100, and can also include one end resting on the trenches 106 as shown in Figure 2.

[0044] The grid 114 is separated from the grid 112 by a space el. Said more precisely, the longitudinal end of the grid 114 which is closest to the grid 112 is separated from the grid 112 by a space el. For example, in the first direction, the space el separates the grids 114 and 112 from each other. One or more electrical contacts 115 with the grid 114 can be provided, so as to allow the application of a voltage to the grid 114. Preferably, these contacts 115 are arranged on the side of the end of the grid 114 which is furthest from grid 112, although this is not essential.

[0045] The device 1 further comprises two semiconductor regions 110, for example made of silicon, the regions being doped with a first type of conductivity, for example type N. The regions 110 rest on the insulating layer 102. As For example, the regions 110 correspond to portions of a layer of silicon on insulator, for example the layer of silicon on insulator in which the strip 100 is defined. As illustrated in Figure 4, the two regions 110 are arranged on either side and on the other side of grid 114 in the second direction. More particularly, the two regions 110 border a portion of the grid 114, a first of the two regions 110 being arranged along a first edge of this portion of the grid 114, this first edge being parallel to the first direction, and a second of the two regions 110 being arranged along a second edge of this portion of the grid 114, this second edge being parallel to the first direction and the two regions 110 being opposite each other in the second direction. In particular, each of the regions 110 borders a portion of the strip 100 which is arranged under the portion of the grid 114 bordered by this region 110. The two regions 110 are arranged on the side of one of the longitudinal ends of the strip 100, at namely the longitudinal end of the strip 100 which is on the side of the grid 114 (on the left in Figure 1). Region 110 is said to be "arranged on the side of a longitudinal end of the strip" for example when region 110 is closer to this longitudinal end than to the center of the strip 100 taken in the direction of its length.

[0046] Thus, the regions 110 are exposed and one or more electrical contacts 118 with each of the regions 110 can be provided. These contacts 118 make it possible to apply a voltage to each region 110.

[0047] By way of example, the grid 114 is configured to allow the circulation of charges between the space el and the region 110, in the portion of the strip 100 placed under the grid 114.

[0048] Similarly, the grid 116 rests on the strip 100, and can also include one end resting on the trenches 106 as shown in Figure 2.

Grid 116 is separated from grid 112 by a space e2. Said more precisely, the longitudinal end of the grid 116 which is closest to the grid 112 is separated from the grid 112 by a space e2. For example, in the first direction, the space e2 separates the grids 116 and 112 from each other. One or more electrical contacts 117 with the gate 116 can be provided, so as to allow the application of a voltage to the gate 116. Preferably, these contacts 117 are arranged on the side of the end of the grid 116 which is furthest from the grid 112, although this is not essential.

The device 1 further comprises two semiconductor regions 108, for example made of silicon, the regions being doped with the first type of conductivity, for example the N type, like the regions 110. The regions 108 rest on the insulating layer 102. By way of example, the regions 108 correspond to portions of a layer of silicon on insulator, for example the layer of silicon on insulator in which the band 100 is defined. Although this is not illustrated by a figure, from similarly to regions 110 and to grid 110, the two regions 108 border a portion of grid 116, a first of the two regions 108 being arranged along a first edge of this portion of grid 116, this first edge being parallel to the first direction, and a second of the two regions 108 being arranged along a second edge of this portion of the grid 116, this second edge being parallel to the first direction and the two regions 108 being opposite one on the other in the second direction. In particular, each of the regions 108 borders a portion of the strip 100 which is arranged under the portion of the grid 114 bordered by this region 110. The two regions 108 are arranged on the side of one of the longitudinal ends of the strip 100, at namely the longitudinal end of the strip 100 which is on the side of the grid 116 (on the right in Figure 1). Region 108 is said to be "arranged on the side of a longitudinal end of the strip" for example when region 108 is closer to this longitudinal end than to the center of the strip 100 taken in the direction of its length.

[0051] Thus, the regions 108 are exposed and one or more electrical contacts 120 with each of the regions 108 can be expected. These contacts 120 make it possible to apply a voltage to each region 108.

[0052] By way of example, the grid 116 is configured to allow the circulation of charges between the space e2 and the region 108, in the portion of the strip 100 placed under the grid 116.

[0053] For example, the spaces el and e2 are substantially equal, preferably equal.

[0054] In the example of Figures 1 to 4, the width of the strip 100 (measured in the second direction) is equal to the width of each of the grids 114, 112 and 116. The grids 112, 114 and 116 are then aligned with the strip 100. Thus, the trenches 106 and the regions 110 and 108 completely surround the strip 100 in the first and second directions. In other words, the strip 100 is bordered on its entire lateral periphery by the trenches 106 and the regions 110 and 108. In other words, the strip 100 is entirely delimited laterally by the trenches the regions 108 and 110.

[0055] In another example not illustrated, the strip 100 has a width (measured in the second direction) which is greater than those of the grids 112, 114 and 116. Thus, portions of the strip 100 are arranged on either side other of the grids 112, 114 and 116 in the second direction. In this other example, the regions 110 and 108 are for example entirely surrounded by the silicon of the band 100, or, put differently, extend across the band 100 in a direction orthogonal to the first and second directions. In this other example, preferably, the trenches 106 completely surround the strip 100 in the first and second directions, or, put differently, the strip 100 is bordered on its entire lateral periphery by the trenches 106. Said again another way, the strip 100 is then for example entirely delimited laterally by the trenches 106. The device 1 further comprises at least one grid 122. In the embodiment of Figures 1 to 4, the device 1 more particularly comprises two grids 122, respectively referenced 122A and 122B in Figures 1 to 4.

[0056] Each grid 122A, 122B rests on the upper face of the device 1. Each grid 122A, 112B is arranged opposite the space el in the second direction, and has no portion resting on the strip 100. In other words, at least the portion of each of the grids 122A and 122b which is arranged on the side of the space rests entirely on the trenches 106, and, preferably, each of the grids 122A and 122B rests entirely on the trenches 106.

[0057] In this example with two grids 122, the grids 122A and 122B are therefore arranged on either side of the space el in the second direction. Preferably, the grids 122A and 122B are aligned with each other in the second direction. Preferably, the grids 122A and 122B face each other in the second direction. In the example of Figure 1, the grid 122A is arranged at the top, the grid 122B being arranged at the bottom in Figure 1.

[0058] The grids 122A, 122B are, for example, configured to allow control of the electrostatic potential in the portion of the strip 100 disposed in the space el between the grid 112 and the grid 114. For example, when a barrier tunnel is present in the space el between the grid 112 and the grid 114, the grids 122A and 112B allow the control of this tunnel barrier, a tunnel barrier being, for example, an electrostatic potential barrier which can be crossed by tunnel effect .

One or more electrical contacts 124 with each gate 122A, 122B can be provided, so as to allow the application of a voltage to each gate 122A, 122B. There voltage applied to gate 122A may be different from that applied to gate 122B.

[0060] In the example of Figures 1 to 4, the grids 122A and 122B each have, in top view (Figure 1) a substantially rectangular shape. In this case, each grid 122A, 122B extends in length in the second direction and has one end facing the space el. Preferably, for each grid 122A, 122B, the contact(s) 124 with the grid are then arranged on the side of the end of the grid which is furthest from the space el.

[0061] In another example not illustrated, each grid 122A, 122B has, when viewed from above, a substantially square shape.

[0062] By way of example, each grid 122A, 122B has an edge parallel to the second direction which is aligned with the end of the grid 114 disposed on the side of the space el, and another edge parallel to the second direction which is aligned with the edge of the grid 112 disposed on the side of the space el. In this case, the width of each grid 122A, 122B is equal to the dimension of the space el taken in the first direction. However, in alternative examples, the width of each grid 122A, 122B may be greater or less than the dimension of the space el taken in the first direction.

[0063] By way of example, a space e3 separates the portion of the strip 100 which is arranged in the space el of each grid 122A, 112B, that is to say from the edge of each grid 122A, 122B which is of side of space el and parallel to the first direction. In device 1, no grid rests on the portion of the strip 100 disposed between the grid 112 and the grid 114, or, put differently, no grid rests on the portion of the strip 100 corresponding to the space el. [0064] In an example not illustrated where the width of the strip 100 is greater than those of the grids 112, 114 and 116, the trenches 106 may include extensions in the second direction forming a notch or a recess in the strip 100, opposite of space el in the second direction, so that each grid 122A, 122B is devoid of any portion resting on the strip 100, or, put differently, so that the grids 122A, 122B rest entirely on the insulating trenches 106.

[0065] Similarly, the device 1 further comprises at least one grid 126. In the embodiment of Figures 1 to 4, the device 1 more particularly comprises two grids 126, referenced respectively 126A and 126B in Figure 1. In particular, the sectional view of the device 1 in a plane BB parallel to the second direction and passing through the grids 126A, 126B would be similar to the sectional view illustrated in Figure 3.

[0066] Each grid 126A, 126B rests on the upper face of the device 1. Each grid 126A, 126B is arranged opposite the space e2 in the second direction, and has no portion resting on the strip 100. In other words, at least the portion of each of the grids 126A and 126B which is arranged on the side of the space e2 rests entirely on the trenches 106, and, preferably, each of the grids 126A and 126B rests entirely on the trenches 106.

[0067] In this example with two grids 126, the grids 126A and 126B are arranged on either side of the space e2 in the second direction. Preferably, the grids 126A and 126B are aligned with each other in the second direction. Preferably, the grids 126A and 126B face each other in the second direction.

[0068] In the example of Figure 1, the grid 126A is arranged at the top, the grid 126B being arranged at the bottom. [0069] The grids 126A, 126B are, for example, configured to allow control of the electrostatic potential in the portion of the strip 100 disposed in the space e2 between the grid 112 and the grid 116. For example, when a barrier tunnel is present in the space e2 between the grid 112 and the grid 116, the grids 126A and 126B allow the control of this tunnel barrier.

[0070] One or more electrical contacts 128 with each gate 126A, 126B can be provided, so as to allow the application of a voltage to each gate 126A, 126B. The voltage applied to gate 126A may be different from that applied to gate 126B.

[0071] In the example of Figures 1 to 4, each grid 126A, 126B has, in top view (Figure 1), a substantially rectangular shape. In this case, each grid 126A, 126B extends in length in the second direction and has one end facing the space e2. Preferably, for each grid 126A, 126B, the contact(s) 128 with the grid are then arranged on the side of the end of the grid which is furthest from space e2.

[0072] In another example not illustrated, each grid 126A, 126B has, when viewed from above, a substantially square shape.

[0073] By way of example, each grid 126A, 126B has an edge parallel to the second direction which is aligned with the end of the grid 116 disposed on the side of the space e2, and another edge parallel to the second direction which is aligned with the edge of the grid 112 disposed on the side of the space e2. In this case, the width of each grid 126A, 126B is equal to the dimension of the space e2 taken in the first direction. However, in alternative examples, the width of each grid 126A, 126B may be greater or less than the dimension of the space e2 taken in the first direction. [0074] For example, the space e3 separates the portion of the strip 100 which is arranged in the space e2 from each grid 126A, 126B, that is to say from the edge of each grid 126A, 126B which is on the side of space e2 and parallel to the first direction. In device 1, no grid rests on the portion of the strip 100 disposed between the grid 112 and the grid 116, or, put differently, no grid rests on the portion of the strip 100 corresponding to the space e2.

[0075] In an example not illustrated where the width of the strip 100 is greater than those of the grids 112, 114 and 116, the trenches 106 may include extensions in the second direction forming a notch or a recess in the strip 100, opposite of space e2 in the second direction, so that each grid 126A, 126B has no portion resting on the strip 100.

[0076] By way of example, the dimension of the space e3 taken in the second direction is sufficiently small so that the grids 122A and 122B, respectively 126A and 126B, can make it possible to modify the electrostatic potential of the strip portion 100 corresponding to the space el, respectively e2, for example so that the grids 122A, 122B, respectively 126A, 126B, make it possible to modify a tunnel barrier formed in the space el, respectively e2.

[0077] The device 1 further comprises a region 130 made of silicon. The region 130 is in contact with the substrate 104, so as to allow the application of a voltage to the substrate 104 under the strip 100, that is to say so as to allow the application of a voltage to the portion of the substrate 104 which is under the strip 100 and separated and isolated from this strip 100 by the layer 102.

[0078] The substrate 104 and the insulating layer 102 therefore form a rear gate for the silicon strip 100, for example respectively an electrode of this rear gate and a gate insulator of this rear grid, the rear grid extending under the entire strip 100. Region 130 therefore allows the application of a voltage to the rear grid disposed under and in contact with the strip 100, or, put differently , region 130 is a rear gate contact recovery region. Region 130 is electrically isolated from strip 100 by trenches 106 and layer 102. For example, the application of this voltage is implemented via one or more electrical contacts 131 with region 130, and, more particularly, with the face of region 130 which is part of the upper face of device 1.

[0079] For example, region 130 extends through trenches 106 and, for example layer 102, from the upper face of device 1 to substrate 104.

[0080] In the example of Figures 1 to 4, the region 130 is arranged in the alignment of the grids 114, 112 and 116, although this region 130 can be arranged at other locations in the device 1. For example , although not shown here, the region 130 could be a substantially rectangular region when viewed from above, extending longitudinally in the first direction parallel to the grids 112, 114 and 116, and being arranged beyond the grids 122B, 126B (bottom in Figure 1). Such a region 130 would then preferably include several contacts 131.

[0081] Although it is usual to provide silicidation at the level of the contact between an electrical contact and the silicon or a gate electrode, preferably, the device 1 comprises a zone 132 (delimited by dotted lines in Figure 1 and represented by dotted lines in Figures 2 and 3) devoid of silicidation. In practice, zone 132 corresponds to a location where, during the manufacture of device 1, a mask was formed to prevent any silicidation of the silicon covered by this mask. Preferably, zone 132 also corresponds to a zone of the device where no implantation of doping atoms has been implemented, for example because the mask used during manufacturing to prevent silicidation in zone 132 also makes it possible to prevent doping atoms from reaching zone 132 of the device.

[0082] The grid 112 is then placed in the zone 132, preferably in a central part of the zone 132. Thus, the grid 112 is devoid of silicidation.

[0083] Preferably, the ends of the grids 114 and 116 which are on the side of the grid 112 also form part of the zone 132, the other ends of the grids 114 and 116 being able to be silicided, for example at least at the locations of the contacts 115 and 117.

[0084] Preferably, each grid 122A, 122B has at least its end on the side of the space el which is part of the zone 132, the rest of each grid 122A, 122B being able or not to be silicided, for example to be silicided with less at the contact locations 124.

[0085] Preferably, each grid 126A, 126B has at least its end on the side of the space e2 which is part of the zone 132, the rest of each grid 126A, 126B being able or not to be silicided, for example to be silicided with less at the contact locations 128.

[0086] For example, regions 108 and 110 are arranged outside zone 132, and can be silicided, for example at least at the locations of contacts 118 and 120.

0087] In the exemplary embodiment illustrated by Figures 1 to 4, the device 1 comprises two grids 122, namely the grids 122A and 122B. In variations of embodiment, one or the other of the grids 122A and 122B can be omitted. Similarly, in alternative embodiments, either of the grids 126A and 126B may be omitted.

[0088] Although this is not illustrated in Figures 1 to 4, the device 1 preferably comprises a control circuit configured to apply control voltages to each of the gates 122A, 122B, 112, 126A, 126B, 114 , 116, 130 of device 1. The different operating modes that device 1 allows as a function of the control voltages that it receives on its gates will be described in relation to Figures 6, 7 and 8.

[0089] In the embodiment of Figures 1 to 4, the device 1 comprises a single grid 112. In alternative embodiments, the device 1 comprises at least two grids 112.

[0090] Figure 5 shows an example of such a variant embodiment of the device 1. More particularly, Figure 5 is a top view of the device 1 according to this variant embodiment, this top view being similar to that of Figure 1, and the sectional views in the planes BB and CC of Figure 5 would be similar to those of respective Figures 3 and 4. More generally, the device 1 of Figure 5 includes many similarities with that of Figures 1 to 4, and only the differences between these two devices 1 are highlighted here.

[0091] In the example of Figure 5, the device 1 comprises three grids 112, referenced respectively 112A, 112B and 112C (from right to left in Figure 5). However, the person skilled in the art will be able to adapt the description given below for a device 1 comprising three grids 112 to a device 1 comprising any number of grids 112 greater than or equal to two.

[0092] The grids 112 (112A, 112B and 112C in Figure 5) are aligned with the grids 114 and 116 in the first direction (longitudinal direction of the strip 100). Similar to device 1 of Figures 1 to 4, in device 1 of Figure 5, the grids 114 and 116 are arranged on either side of the grids 112 (112A, 112B and 112C in Figure 5) in the first direction. More particularly, as in device 1 of Figures 1 to 5, in device 1 of Figure 5, the grid 114 is separated from the grids 112 by the space el, and the grid 116 is separated from the grids 112 by the space e2. For example, the space el separates the grid 114 from that of the grids 112 to which it is closest, namely the grid 112C in the example of Figure 5, and the space e2 separates the grid 116 from that of the grids 112 to which it is closest, namely grid 112A in the example of Figure 5.

[0093] The device 1 comprises, as in Figures 1 to 4, at least one grid 122, for example the two grids 122A and 122B in the example shown in Figure 5, although one or the other of these grids 122A and 122B may be omitted. The grids 122A and 122B are arranged in a manner similar to what has been described in relation to Figures 1 to 4 with respect to the space el, the grid 114 and the grids 112. Thus, the grids 122A, 122B are aligned with each other and are arranged on either side of the space el in the second direction, each of the grids 122A, 122B facing the space el in the second direction. Similarly, the device 1 comprises, as in Figures 1 to 4, at least one grid 126, for example the two grids 126A and 126B in the example shown in Figure 5, although one or the other of these grids 126A and 126B can be omitted. THE grids 126A and 126B are arranged in a manner similar to what has been described in relation to Figures 1 to 4 with respect to space e2, to grid 116 and to grids 112. Thus, grids 126A, 126B are aligned l 'one with the other in the second direction and are arranged on either side of the space e2 in the second direction, each of the grids 126A and 126B facing the space e2 in the second direction.

[0094] The grids 112 are separated from each other, two by two, by a corresponding space e4. For example, the space e4 is substantially equal to the spaces el and e2, or even equal to these spaces el and e2. Thus, in the example of Figure 5, in the first direction, the space el separates the grid 114 from the grid 112C, a space e4 separates the grid 112C from the grid 112B, another space e4 separates the grid 112B from the grid 112A and the space e2 separates the grid 112A from the grid 116. Although the space between each two adjacent grids 112 has been designated by the same reference e4 and is preferably identical between each two adjacent grids 112, in alternative examples, the space e4 between two adjacent grids 112 (for example the grids 112C and 112B in the example of Figure 5) can be different from the space e4 between two other adjacent grids 112 (for example the grids 112B and 112A in the example of Figure 5), that is to say that these two spaces e4 can have different dimensions taken in the first direction.

[0095] Each grid 122 makes it possible to control the electrostatic potential in the portion of the band 100 corresponding to the space el and each grid 126 makes it possible to control the electrostatic potential in the portion of the band 100 corresponding to the space e2. For example, each grid 122 makes it possible to control a tunnel barrier formed in the portion of the strip 100 corresponding to the space el and each grid 126 makes it possible to control a tunnel barrier formed in the portion of the strip 100 corresponding to space e2.

[0096] Similarly, according to one embodiment, the device 1 comprises, for each space e4, at least one grid 500 arranged opposite the space e4 in the second direction and devoid of any portion resting on the strip 100. In other words, at least the portion of each grid 500 which is arranged on the side of the space e4 corresponding to this grid, rests entirely on the trenches 106, and, preferably, each grid 500 rests entirely on the trenches 106.

[0097] In this example where the device 1 comprises two grids 500 for each space e4, the two grids 500 are arranged on either side of the space e4 in the second direction. Preferably, for each space e4, the two grids 500 facing this space e4 in the second direction are aligned with one another in this second direction.

[0098] For each space e4, the grid(s) 500 having their ends arranged opposite this space e4 are configured to allow control of the electrostatic potential in the portion of the strip 100 placed in the space e4 considered, for example for allow the control of a tunnel barrier formed in this space e4.

[0099] One or more electrical contacts 502 with each gate 500 may be provided, so as to allow the application of a voltage to each gate 500. The voltage applied to one gate 500 may be different from that applied to another gate. 500, even when the two grids 500 are arranged on either side of the same space e4. [0100] In the example of Figure 5, the grids 500 each have, in top view, a substantially rectangular shape. In this case, each grid 500 extends in length in the second direction and has one end facing the corresponding space e4. Preferably, for each grid 500, the contact(s) 124 with the grid are then arranged on the side of the end of the grid which is furthest from the space e4 corresponding to this grid.

[0101] In another example not illustrated, the grids 500 each have, when viewed from above, a substantially square shape.

[0102] By way of example, for each space e4, each grid 500 which has an end facing this space e4 also has a first edge parallel to the second direction which is aligned with an edge of a first grid 112 adjacent to this space e4, this edge of the first grid 112 being adjacent to the space e4, and a second edge parallel to the second direction which is aligned with an edge of a second grid 112 adjacent to this space e4, this edge of the second grid 112 being adjacent to space e4. In this case, each grid 500 facing a corresponding space e4 has a dimension taken in the first direction which is equal to the dimension of this space e4 taken in the first direction. However, in alternative examples, the dimension of each grid 500 taken in the first direction may be greater or less than the dimension of the space e4 facing which it is arranged.

[0103] By way of example, for each grid 500 facing a corresponding space e4, a space e5 separates the portion of the strip 100 which is arranged in this space e4 from each grid 500 facing this space in the second direction. In device 1, no grid rests on the portion of the strip 100 disposed between each two adjacent grids 112, or, in other words, no grid does not rest on the portion of the band 100 corresponding to each space e4.

[0104] In an example not illustrated where the width of the strip 100 is greater than those of the grids 112, 114 and 116, for each grid 500, the trenches 106 can include an extension in the second direction forming a notch or a recess in the strip 100, opposite the space e4 corresponding to this grid 500, so that the grid 500 is devoid of any portion resting on the strip 500.

[0105] By way of example, for each grid 500 facing a corresponding space e4 in the second direction, the dimension of the space e5 taken in the second direction is sufficiently small so that the grid 500 can make it possible to modify the electrostatic potential of the portion of strip 100 corresponding to this space e4, for example so as to control a tunnel barrier formed in this space e4. For example, each space e5 has, in the second direction, the same dimension as the spaces e3.

[0106] As in Figure 1 to 4, preferably the device 1 of Figure 5 comprises the zone 132 devoid of silicide zone (delimited by dotted lines in Figure 5), the zone 132 comprising the grids 112 for example arranged in a part central of the zone 132. In the example of Figure 5, the zone 132 comprises the grids 112, preferably the end of the grid 114 disposed on the side of the space el, preferably the end of the grid 116 arranged on the side of the space e2, and preferably the end of each of the grids 122A and 122B, respectively 126A and 126B, arranged on the side of the space el, respectively e2. Furthermore, preferably, this zone 132 comprises the end of each grid 500 which is arranged on the side of, or which faces, a space e4, the other end of the grid 500 being able to be silicide, for example at least at the locations of the contact(s) 502.

[0107] Although this is not illustrated in Figure 5, the device 1 preferably comprises a control circuit configured to apply control voltages to each of the gates 122A, 122B, 112, 126A, 126B, 114, 116 , 130 and 500 of the device 1. The different operating modes that the device 1 of Figure 5 allows for several gates 122 as a function of the control voltages that it receives on its gates can be deduced by the person skilled in the art from the description below of the operating modes of the device 1 of Figures 1 to 4, made in relation to Figures 6, 7 and 8.

[0108] In alternative embodiments not illustrated, for at least one space e4, for example for each space e4, the device 1 comprises only one grid 500 facing this space e4 in the second direction or is devoid of grid 500 facing this space 500 in the second direction.

[0109] Figure 6 illustrates by curves 600, 602 and 604 the operation of the device 1 of Figure 1. More particularly, curves 600, 602 and 604 illustrate the shape of the electrostatic potential EC, in electron volt (eV), in the strip 100 taken in the plane AA, that is to say in a portion of the strip 100 extending under the gates 114, 112 and 116 and comprising the spaces el and e2, as a function of the applied voltage VC to grid 112. Regions 110 and 108, spaces el and e2 and grid 112 have been represented on the abscissa axis.

[0110] In Figure 6, the rear gate receives a constant voltage and the other gates 122A, 122B, 126A, 126B receive zero voltage (i.e. ground), although they could have been left floating . Furthermore, the curve 600 illustrates the case where VC is equal to -0.5 V, curve 602 illustrating the case where VC is equal to 0 V and curve 604 illustrating the case where VC is equal to 0.5 V.

[0111] Curve 602 shows that device 1 can operate as a single electron transistor (SET) or as a Qubit. Indeed, the potential barriers in the spaces el and e2 define a quantum box under the grid 112. In particular, by bringing the device 1 to a cryogenic temperature, electrons can be accumulated under the grids 114 and 116 by applying voltages appropriate on the grids of device 1.

[0112] It is then possible to control the electrostatic barriers in the spaces el and e2 using the voltage VC to obtain a single electron transistor. For example, the application of a first positive voltage VC to the gate 112, for example lower than the voltage VC corresponding to the curve 604, makes it possible to place the quantum dot in a conducting state, so that electrons can cross the quantum box by crossing the potential barriers of the spaces el and e2 by tunneling effect, while the application of a second positive voltage VC and greater than the first voltage VC, for example the voltage VC corresponding to the curve 604, makes it possible to put the quantum dot in a blocking state. More generally, the height of the potential barriers in the spaces el and e2 can, for example, be adjusted by the voltage VC, so that the electron placed in the potential well defined by these two potential barriers can exit the well only by tunnel effect.

[0113] Furthermore, by applying a magnetic field to device 1, it is possible to separate the spin states of a single electron trapped in the quantum dot under grid 112, device 1 then implementing a Qubit. [0114] Curve 604 shows that device 1 can operate as a memory. Indeed, the potential well under the grid 112 is deeper for curve 604 than for curve 602, which makes it possible to prevent an electron stored in the potential well corresponding to curve 604 from leaving the well through a jump (“hopping” in English). In addition, the potential barriers delimiting the potential well under the grid 112 are thicker (wider) for curve 604 than for curve 602, which makes it possible to prevent an electron stored in the potential well corresponding to the curve 604 leaves the well by crossing one or the other of these barriers by tunnel effect. This curve 604 also shows that the device 1 can function as a sensor, for example a sensor based on the Coulomb blocking effect. In a sensor based on the Coulomb blocking effect, when an electron is trapped in the quantum dot under gate 112, by adjusting the depth of confinement potential under gate 112 thanks, for example, to the voltage VC, it is possible to detect when the electron escapes from this potential well when it receives enough energy, for example energy provided by a photon reaching the electron. In other words, the device 1 can function as a sensor to detect when at least a certain energy has been supplied to the electron trapped under the grid 112.

[0115] Curve 600 shows that voltage VC can completely block the circulation of charges between zones 108 and 110, by generating a sufficiently high potential barrier under gate 112.

[0116] Figure 7 illustrates by curves 700, 702 and 704 the operation of the device 1 of Figure 1. More particularly, curves 700, 702 and 704 illustrate the shape of the electrostatic potential EC, in electron volt (eV), in the strip 100 taken in the plane AA, that is to say in a portion of the strip 100 extending under the gates 114, 112 and 116 and comprising the spaces el and e2, as a function of the applied voltage VB to the rear grid of device 1. Regions 110 and 108, spaces el and e2 and grid 112 have been represented on the abscissa axis.

[0117] In Figure 7, the gate 112 receives a constant voltage and the other gates 122A, 122B, 126A, 126B receive zero voltage (i.e. ground), although they could also have been left floating. In addition, curve 700 illustrates the case where VB is equal to 3 V, curve 702 illustrating the case where VB is equal to 4 V and curve 704 illustrating the case where VB is equal to 5 V.

[0118] These curves show that the rear gate of device 1 can by itself modify the electrostatic potential in band 100 to allow or prevent the circulation of a current between regions 110 and 108. In other words, the circulation of a current in band 100 and the conduction band in band 100 can be controlled or adjusted using the voltage VB applied to the rear gate.

[0119] In particular, curve 700 shows that two potential wells or quantum dots can be formed respectively in space el and in space e2. Curves 702 and 704 show that the barriers around these two potential wells can be lowered until they disappear thanks to the voltage VB, so as to then allow the flow of current.

[0120] Figure 8 illustrates by curves 800, 802, 804,

806 and 808 the operation of the device 1 of Figure 1. More particularly, the curves 800, 802, 804, 806 and 808 illustrate the shape of the electrostatic potential EC, in electron volt (eV), in the band 100 taken in the plane AA, that is to say in a portion of the strip 100 extending under the gates 114, 112 and 116 and comprising the spaces el and e2, as a function of the voltage Ve2CTRL applied to the gates 126A and 126B. Regions 110 and 108, spaces el and e2 and grid 112 have been represented on the abscissa axis.

[0121] In Figure 8, the gate 112 receives a constant voltage, the rear gate receives a constant voltage and the other gates 122A and 122B receive zero voltage (i.e. ground), although they would have could also be left floating. In addition, curves 800, 802, 804, 806 and 808 illustrate the cases where Ve2CTRL is equal to 0 V, 2 V, 4 V, 6 V and 8 V respectively.

[0122] As curves 800 to 808 show, the voltage Ve2CTRL applied to gates 216A and 126B makes it possible to control the height of the potential barrier in space e2. It is thus possible to select, thanks to the voltage Ve2CTRL, whether an electron trapped in the potential well under the gate 112 can pass the barrier in the space e2 by tunneling effect or over this barrier ("hopping" in English ), or only by tunneling.

[0123] Although what is described in relation to Figure 8 concerns a case where the device 1 comprises two grids 126, namely the grid 126A and the grid 126B, what has been described above remains valid when the device 1 only includes grid 126A or grid 126B.

[0124] Furthermore, although Figure 8 illustrates the impact of the voltage Ve2CTRL applied to the gates 126 on the potential barrier in the space e2, in the same way the height of the potential barrier in the space el can be controlled by a voltage VelCTRL applied to gates 122A and 122B, or, in the case where device 1 only includes a single gate 122, to this single gate 122. [0125] Thus, it is possible to implement Boolean functions between the voltages applied to each gate 122A, 122B, 126A, and 126B.

[0126] For example, an electron can only circulate from one to the other of regions 108 and 110 if the potential barriers in the spaces el and e2 are sufficiently low, and cannot circulate if one and /or the other of the potential barriers in these spaces el and e2 are too high, the control of these two potential barriers can be implemented with a single grid 122 or two grids 122A and 122B and with a single grid 126 or two grids 126A and 126B. Thus, it is possible to implement a Boolean logic function of the AND type between the control of the grid(s) 122 on the one hand, and the control of the grid(s) 126 on the other hand.

[0127] According to another example in which the device 1 comprises two gates 126A and 126B, it is possible to implement a Boolean logic function of the OR type between a voltage Ve2CTRLA applied to the gate 126A and a voltage Ve2CTRLB applied to the gate 126B. Indeed, considering that an electron is trapped under the grid 112, this electron can reach region 108 if one and/or the other of the voltages Ve2CTRLA and Ve2CTRLB makes it possible to sufficiently lower the barrier in space e2 so that the electron escapes from the potential well under the gate 112. Similarly, it is possible to implement a Boolean logic function OR between a voltage VelCTRLA applied to the gate 122A and a voltage VelCTRLB applied to the gate 122B.

[0128] Although this is not illustrated in a figure, in a manner similar to the grid(s) 122 for the potential barrier in space el, and to the grid(s) 126 for the potential barrier in space e2, for each space e4 when the device 1 includes several grids 112, the potential barrier in this space e4 can be controlled by the grid(s) 500 which have one end facing this space e4.

[0129] More generally, and although this is not illustrated by the figures, when the device 1 comprises several grids 112, in a manner similar to what has been described in relation to Figures 6, 7 and 8 for a single grid 112, the height of the potential (tunnel barrier) in each of the spaces el, e2 and e4 and the height of the confinement potential under each grid 112 can be controlled so as to form one or more potential wells each capable of storing an electron, for example to implement one or more quantum boxes, or to implement a Qubit.

[0130] As an example of dimensions, in the devices 1 described above:

- each grid 112 has, in top view, a square shape with a side of between 50 and 95 nm;

- the gates 114 and 116 have a width of between 50 and 60 nm;

- the band 100 has a width of between 50 and 230 nm;

- the spaces el and e2 each have, in the first direction, a dimension of between 30 and 50 nm;

- the e4 spaces each have, in the first direction, a dimension of between 30 and 60 nm; And

- the spaces e3 and e5 each have, in the second direction, a dimension of between 45 and 90 nm.

[0131] Of course the examples of dimensions above are not limiting and the person skilled in the art is able to dimension the device 1 differently while maintaining operation similar to what has been described in relation to Figures 6 to 8 . [0132] Various embodiments and variants have been described. Those skilled in the art will understand that certain characteristics of these various embodiments and variants could be combined, and other variants will become apparent to those skilled in the art. In particular, although we have described the case where the regions 108 and 110 are doped with type N, the person skilled in the art is able, from the description given above, to implement devices 1 in which regions 108 and 110 are P-type doped. In the latter case, preferably the silicon of the band 100 remains intrinsically doped with type P, and the regions 110 and 108 are doped with a doping level at least 10 times higher than that of the silicon of the band 100, for example with a doping level between 10 ²⁰ and 10 ²¹ at. cm-3.

[0133] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art based on the functional indications given above.

Claims

CLAIMS Electronic device (1) comprising: a silicon strip (100) intrinsically doped with P type, the strip resting on an insulating layer (102) itself resting on a semiconductor substrate (104); insulating trenches (106) laterally delimiting said strip (100); at least one first gate (112; 112A, 112B, 112C) resting on a central region of said strip (100); a second grid (114) extending longitudinally in a first direction parallel to the length of said strip (100), the second grid (114) resting on said strip and being separated from said at least one first grid (112; 112A, 112B , 112C) by a first space (el); a third grid (116) extending longitudinally in the first direction, the third grid resting on said strip and being separated from said at least one first grid (112; 112A, 112B, 112C) by a second space (e2); two first semiconductor regions (110) doped with a first type of conductivity, arranged along and on either side of a portion of the second gate (114) resting on a corresponding portion of the strip (100); two second semiconductor regions (108) doped with the first conductivity type, arranged along and on either side of a portion of the third gate (116) resting on a corresponding portion of the strip (100); at least a fourth grid (122A, 122B) arranged opposite and beyond the first space (el) in a second direction orthogonal to the first direction, each fourth grid (122A, 122B) having at least one portion arranged on the side of the first space (el) which rests entirely on the insulating trenches (106); at least a fifth grid (126A, 126B) arranged opposite and beyond the second space (e2) in the second direction, each fifth grid (126A, 126B) having at least one portion disposed on the side of the second space (e2) which rests entirely on the insulating trenches (106); and a silicon region (130) in contact with the substrate (104) for polarizing the substrate under said band. Electronic device according to claim 1, wherein said at least one first grid comprises exactly a first grid (112), the second and third grids (114, 116) being arranged on either side of said first grid (112) in the first direction, and the first, second and third grids being aligned in the first direction. Electronic device according to claim 2, wherein each fourth gate and each fifth gate rests entirely on the insulating trenches (106). Electronic device according to claim 2 or 3, wherein the device comprises a control circuit configured to apply a control voltage to the region (130) in contact with the substrate, at least one control voltage to said first gate (112) , a control voltage at the second gate (114), a control voltage at the third gate (116), at least one control voltage at said at least one fourth gate (122A, 122B) and a control voltage at said at least a fifth grid (126A, 126B). Electronic device according to claim 1, wherein said at least one first grid comprises at least two first grids (112A, 112B, 112C) aligned in the first direction and separated in pairs by a third space (e4). Electronic device according to claim 5, in which each fourth gate and each fifth gate rests entirely on the insulating trenches (106) Electronic device according to claim 5 or 6, in which the device comprises, for each third space (e4), at least a sixth grid (500) arranged opposite and beyond the third space (e4), each sixth grid (126A, 126B) having at least one portion arranged on the side of the corresponding third space (e4) which rests entirely on the insulating trenches (106). Device according to claim 7, in which each sixth grid (500) rests entirely on the insulating trenches (106). Electronic device according to claim 7 or 8, wherein the device comprises a control circuit configured to apply a control voltage to the region (130) in contact with the substrate, at least one control voltage to said at least one first gate (112A, 112B and 112C), a control voltage at the second gate (114), a control voltage at the third gate (116), at least one control voltage at said at least one fourth gate (12A, 126B) , a control voltage to said at least one fifth gate (126A, 126B) and at least one control voltage to said at least one sixth gate (500). Electronic device according to any one of claims 7 to 9, in which, for each third space (e4), said at least one sixth grid (500) comprises exactly two sixth grids arranged on either side of said third space (e4). ) in the second direction, said exactly two grids (500) being aligned in the second direction. Electronic device according to any one of claims 1 to 10, wherein said at least one fourth grid comprises exactly a fourth grid and/or said at least one fifth grid comprises exactly a fifth grid. Electronic device according to any one of claims 1 to 10, in which said at least one fourth grid comprises exactly two fourth grids (122A, 122B) arranged on either side of the first space (el) in the second direction and said at least a fifth grid comprises two fifth grids (126A, 126B) arranged on either side of the second space (e2) in the second direction. Electronic device according to any one of claims 1 to 12, in which the device comprises a zone (132) devoid of silicidation, said zone comprising at least said at least one first grid, one end of the second grid disposed on the side of said at least one first grid, one end of the third grid disposed on the side of said at least one first grid, at least one portion disposed on the side of the first space (el) of said at least one fourth grid and at least one portion disposed of the side of the second space (e2) of said at least one fifth grid. Electronic device according to any one of claims 1 to 13, in which the device is adapted to implement at least one quantum dot and/or a Qubit.