FR3091786A1 - PIN type diode having a conductive layer, and method of manufacturing - Google Patents

Abstract

The diode (DD1) comprises a polysilicon (PL2) bar comprising a first doped region of a first type of conductivity (P +), a second doped region of a second type of conductivity (N +) and an intrinsic region (INT ), and comprises a conductive layer (PL1) capable of being polarized, parallel to the polysilicon bar (PL2) and separated from said bar by a dielectric layer (CD). Abstract figure: figure 1

Description

PIN-type diode comprising a conductive layer, and manufacturing method

Embodiments and implementations relate to diodes, in particular formed in polycrystalline silicon and comprising an intrinsic zone.

The leakage current in diode P+N- or N+P- junctions is strongly related to the dopant density of the least doped side (N- or P-). The higher the doping, the greater the leakage current under reverse bias. However, if the doping is reduced, the on-state current of the diode is also reduced.

This compromise has made it difficult to achieve polysilicon side diodes with high on-state current and low leakage current.

PIN diodes (for “Positive Intrinsic Negative”) are diodes comprising an intrinsic zone, i.e. undoped, interposed between two P-type and N-type doped zones.

A reduction in the length of the intrinsic zone between the two doped regions makes it possible to improve the ratio of on-state current to leakage current, but this reduction is limited by the diffusion of dopants from the doped regions.

However, it is desirable to increase the ratio of on-state current to leakage current of the PIN diodes, while avoiding introducing additional costs into the manufacturing processes.

According to one aspect, a diode is proposed comprising a polycrystalline silicon bar comprising a first region doped with a first type of conductivity, a second region doped with a second type of conductivity and an intrinsic region located between the first doped region and the second doped region, as well as a conductive layer able to be biased, parallel to the bar of polycrystalline silicon and separated from said bar by a dielectric layer.

The conductive layer being capable of being biased, that is to say comprising for example a contact plug that can be coupled to a bias voltage, and being parallel to the bar, the conductive layer makes it possible to modulate the characteristics of the diode by as a function of the polarization, in particular the reverse leakage current in blocked regime. A positive or negative polarization makes it possible respectively to favor or to moderate the reverse leakage current crossing the intrinsic region of polycrystalline silicon. Such modulation of the current makes it possible to reduce the leakage current and thus to increase the on-state current to leakage current ratio.

For example, the polycrystalline silicon bar has a thickness of 150 nm or 100 nm.

According to one embodiment, the dielectric layer comprises a finer portion than the rest of the dielectric layer, facing the intrinsic region.

This makes it possible in particular to size the effect of favoring and moderating the current at potentials of an order of magnitude available in a given circuit.

For example, the thinner portion has a thickness of substantially 2.3 nm or a thickness of between 7 nm and 9 nm, and the rest of the dielectric layer has a thickness of substantially 15 nm or substantially 18 nm.

According to one embodiment, the polycrystalline silicon bar rests on the dielectric layer itself resting on the conductive layer capable of being polarized.

According to an exemplary embodiment, the conductive layer is located on a surface at a front side of a semiconductor substrate.

According to another exemplary embodiment, the conductive layer is located in a trench extending vertically in a semiconductor substrate from a front face of the semiconductor substrate.

The front face of the semiconductor substrate corresponds to the surface of the substrate at which the semiconductor components are made (otherwise referred to by the acronym FEOL from the usual English term “Front End Of Line”).

According to one embodiment, the diode comprises an electrical circuit coupling the first doped region of the polycrystalline silicon bar with the conductive layer.

Of course, the first doped region corresponds to an anode region of the diode to benefit advantageously from the moderating effect of the leakage current in the blocked state.

According to one embodiment, the diode comprises a second conductive layer capable of being biased, parallel to the bar of polycrystalline silicon and separated from said bar by a second dielectric layer.

In this embodiment, a first and a second conductive layer, respectively on either side of the polycrystalline silicon bar, can allow a double current modulation effect. The second conductive layer also allows an advantageous implementation of the manufacture of the diode.

For example, the second conductive layer has a thickness of 150 nm, while the polycrystalline silicon bar has a thickness of 100 nm.

Advantageously, the second dielectric layer comprises a finer portion than the rest of the second dielectric layer, facing the intrinsic region.

The second conductive layer can rest on the second dielectric layer itself resting on said polycrystalline silicon bar.

For example, said thinner portion of the second dielectric layer has a thickness of substantially 2.3 nm, while the rest of the second dielectric layer has a thickness of substantially 15 nm.

Likewise, the diode can comprise a second electrical circuit coupling the first doped region of the polycrystalline silicon bar with the second conductive layer.

Further, the diode may include an insulating region, electrically isolating the diode from a semiconductor substrate.

For example, the insulating region can be of the shallow insulation trench type, or form a dielectric layer on the parts of the conductive region facing the substrate.

The polycrystalline silicon bar may further comprise fluorine atoms, at least in said intrinsic region.

This makes it possible to further improve the on-state current to leakage current ratio of the diode.

According to another aspect, there is proposed a method for manufacturing a diode comprising forming a bar of polycrystalline silicon, implanting dopants of a first type of conductivity in a first region of the bar, and implanting dopants of a second type of conductivity in a second region of the bar, a region of the bar located between the first region and the second region being left intrinsic, as well as the formation of a conductive layer capable of being polarized parallel to the polycrystalline silicon bar , and formation of a dielectric layer separating the conductive layer and the polycrystalline silicon bar.

For example, said formation of the polycrystalline silicon rod is configured to form a polycrystalline silicon rod having a thickness of 150nm or 100nm.

According to one mode of implementation, the formation of the dielectric layer includes the formation of a thinner portion than the rest of the dielectric layer, facing the intrinsic region.

For example, said formation of the dielectric layer is configured to form the thinner portion having a thickness of substantially 2.3 nm or a thickness between 7 nm and 9 nm, and to form the rest of the dielectric layer having a thickness of substantially 15 nm or substantially 18nm.

According to one mode of implementation, said formation of the polysilicon bar is carried out on the dielectric layer, and said formation of the dielectric layer is carried out on the conductive layer.

According to an exemplary mode of implementation, the formation of the conductive layer is carried out on a surface located at the level of a front face of a semiconductor substrate.

According to another exemplary embodiment, forming the conductive layer comprises etching a vertically extending trench in a semiconductor substrate from a front face of the substrate, and filling the trench with the conductive layer.

According to one mode of implementation, the method comprises a production of an electrical circuit coupling the first doped region of the polycrystalline silicon bar with the conductive layer.

According to one mode of implementation, the method comprises forming a second conductive layer capable of being polarized parallel to the bar of polycrystalline silicon, and forming a second dielectric layer separating the second conductive layer and the bar of polycrystalline silicon .

In addition to producing a diode having the advantages mentioned above, this mode of implementation makes it possible to avoid introducing a step of protection against silicidation, possibly not provided for in a manufacturing process, by using a step of deposition of a second conductive layer, optionally provided in the process.

For example, the formation of the second conductive layer is configured to form the second conductive layer having a thickness of 150nm, the formation of the first conductive layer is configured to form the first conductive layer having a thickness of 100nm.

Advantageously, the formation of the second dielectric layer includes the formation of a finer portion than the rest of the second dielectric layer, facing the intrinsic region.

For example, the formation of the second conductive layer is performed on the second dielectric layer, and said formation of the second dielectric layer is performed on the polycrystalline silicon bar.

For example, said formation of the second dielectric layer is configured to form the thinner portion having a thickness of substantially 2.3 nm.

The method may include a production of a second electrical circuit coupling the first doped region of the polycrystalline silicon bar with the second conductive layer.

Further, the method may include forming an insulating region, electrically isolating the diode from a semiconductor substrate.

The method according to this aspect advantageously presents steps for forming elements which are already provided for in usual methods for manufacturing semiconductor components on the same integrated circuit as the diode. The method according to this aspect is even fully compatible with an example of a non-volatile floating-gate transistor memory embodiment, and therefore “free”.

The method may also comprise an implantation of fluorine atoms at least in said intrinsic region of the polycrystalline silicon bar, and optionally in the whole of the polycrystalline silicon bar.

Other advantages and characteristics of the invention will appear on examination of the detailed description of embodiments and implementations, in no way limiting, and of the appended drawings in which:

illustrates an embodiment of the invention;

illustrates an example of implementation of the invention;

illustrates results of an exemplary embodiment of the invention;

illustrates an embodiment of the invention;

illustrates an embodiment of the invention;

illustrates an example of implementation of the invention.

FIG. 1 illustrates an embodiment of a diode DD1 of the PIN type (for "Positive Intrinsic Negative" in English) comprising a first doped region of the P+ type, a second doped region of the N+ type, and an intrinsic region INT, not doped, interposed between the first P+ doped region and the second N+ doped region.

The first P+ doped region, the intrinsic region INT and the second N+ doped region are made in a bar of polycrystalline silicon PL2, that is to say a layer or a wafer of polycrystalline silicon, possibly elongated.

For example, the polycrystalline silicon bar can have a thickness of 150 nm.

The term polysilicon may be used to designate polycrystalline silicon.

The first P+ doped region forms the anode A of the diode DD1, and the second N+ doped region forms the cathode C of the diode DD1.

Metal anode A and cathode C contacts are shown and are coupled to the first P+ doped region and the second N+ doped region via SAL metal silicide films.

Diode DD1 comprises a conductive layer PL1 parallel to polycrystalline silicon bar PL2 and separated from said bar by a dielectric layer CD.

The conductive layer PL1 can for example be formed from doped and conductive polysilicon. The conductive layer PL1 may comprise a film of metal silicide allowing ohmic coupling with a metal contact Cnt. This is an example allowing the conductive layer PL1 to be able to be polarized.

For example, the conductive layer PL1 can have a thickness of 100 nm.

The dielectric layer CD comprises a portion LV and a portion ONO. The LV portion is thinner than the rest of the ONO dielectric layer (ONO portion). The finer layer (LV portion) is located next to the intrinsic region INT.

The finer portion LV of the dielectric layer comprises for example a layer of silicon oxide used to produce gate oxides of logic transistors of the MOS type. For example, the LV portion may have a thickness of substantially (i.e. to within 10%) 2.3 nm.

The remainder of the thicker CD dielectric layer comprises, for example, an ONO stack of silicon oxide, silicon nitride and silicon oxide layers. For example, the ONO portion may have a thickness of substantially 15 nm.

In this example, the polycrystalline silicon bar PL2 rests on the dielectric layer itself resting on the conductive layer PL1.

The conductive layer rests on a surface at the level of a front face FA of a semiconductor substrate SUB on which the diode DD1 is made. The front face FA of the substrate SUB is the face on which the semiconductor components are formed, such as the diode DD1, transistors or others.

The conductive layer PL1 rests in this example on an area of the substrate provided with a shallow insulation trench STI. The shallow insulation trenches STI comprise an electrically insulating region filling trenches whose upper level is aligned with the surface of the front face FA.

The shallow isolation trench here forms an insulating region that electrically insulates the diode DD1 from the semiconductor substrate SUB.

Figure 2 illustrates a top view of a device after certain steps of an exemplary process for manufacturing a diode, such as the diode DD1 previously described in relation to Figure 1.

Thus, this exemplary method includes forming an STI insulating region, to electrically isolate the diode from a semiconductor substrate. The insulating region is fabricated using a conventional method of forming shallow insulation trenches. The upper surface of the insulating region STI is thus aligned with the level of the front face FA of the semiconductor substrate on which the diode is made.

The method comprises forming the conductive layer PL1 on the surface located at the level of the front face FA of the semiconductor substrate.

The formation of the conductive layer PL1 comprises for example a growth of a polysilicon layer and a doping of this layer to make it conductive.

The method then comprises forming the dielectric layer intended to separate the conductive layer PL1 and the future polycrystalline silicon bar PL2.

The formation of the dielectric layer includes growths or deposits of ONO stacked oxide, nitride, and silicon oxide.

Then, the stack ONO is completely etched on a part LV, located opposite the future intrinsic region INT of the polysilicon bar PL2. An oxide finer than the ONO stack is formed in the etched part LV.

On the dielectric layer (comprising the ONO stack and the finer oxide LV) is then formed the polysilicon bar PL2.

The polysilicon bar PL2 can be formed by depositing a layer of polysilicon, then masking defining parts to be removed, and etching.

The method comprises an implantation of dopants of a first type of conductivity in a first region of the bar forming an anode, and an implantation of dopants of a second type of conductivity in a second region of the bar forming a cathode, mutually spaced apart by a region of the bar left intrinsic (not shown).

In addition, an SiPRT protective mask is deposited in order to protect in particular the intrinsic region INT against silicidation.

The uncovered parts of the polysilicon bar PL2, facing the anode and cathode regions are then silicided, i.e. they contain a film of metal silicide, and can be connected by ohmic contact.

Similarly, the parts of the conductive layer PL1 which are covered neither by the protective mask SiPRT, nor by the bar PL2, nor by the dielectric layer ONO, are also silicided.

Thus a contact point coupled to the metal silicide film makes it possible to polarize the conductive layer PL1.

The different layers PL1, ONO, PL2 are formed in a “pyramidal” fashion, the surface of each layer being globally included inside the surface of the underlying layer.

FIG. 3 illustrates characteristic curves of the anode current Ia as a function of the anode voltage Va of a diode, such as the diode DD1 previously described in relation to FIG. 1, for different polarization Vpol of the conductive layer PL1.

Five curves are shown for five bias voltages Vpol, and are referenced Cm2 for Vpol=-2V, Cm1 for Vpol=-1V, C0 for Vpol=0V, Cp1 for Vpol=+1V, Cp2 for Vpol=+2V.

In on-state, that is to say for positive anode voltages Va, the different polarizations Vpol of the conductive layer PL2 have no real effect on the anode current Ia, in particular for voltages anodes greater than 1.5V.

In blocked mode, that is to say for negative anode voltages Va, the impact of the polarization Vpol of the conductive layer PL2 is on the other hand clearly visible on the values of the leakage current Ia.

Indeed, the polarization of the conductive layer PL2, parallel to the polysilicon bar PL1, generates an effect comparable to a transistor effect in the intrinsic region INT, which modulates the concentration of carriers in the intrinsic region and the conductivity of the diode.

The intensity of the leakage current Ia is thus modulated by the bias voltage Vpol, and for example at an anode voltage Va of -4V, the leakage current of Cm2 (Vpol=-2V) is substantially 10 ^-11 amperes, the leakage current of Cp2 (Vpol=+2V) is substantially 10 ^-8 amperes while the leakage current of C0 (Vpol=0V) is substantially 10 ^-9 amperes.

Thus, the leakage current can be lowered by 2 to 3 orders of magnitude (“decades”) thanks to a polarization Vpol of the conductive layer PL1 parallel to the bar PL2, of the order of 2V.

It is remarkable that bias voltages Vpol of the order of +/-2V make it possible to obtain a tangible effect of moderating the leakage current of the diode in blocked mode. This comes from the presence of a thinner portion LV in the dielectric layer than the rest of the layer, located opposite the intrinsic region INT.

If the dielectric layer comprises only an ONO stack, without a finer portion, the bias voltages Vpol giving a comparable effect are of the order of 10 to 15V. This can be considered in the case where the circuit can easily benefit from such voltage levels, and possibly if it is desirable to avoid the formation of the thinner portion LV in the dielectric layer.

To benefit advantageously from the effect of reducing the leakage current, Vpol=Va will be chosen.

The diode of the diode DD1 type described in relation to FIG. 1 can thus advantageously comprise an electrical circuit connecting the anode region P+ of the polysilicon bar PL2 with the conductive layer PL1.

Thus, a bias voltage Vpol making it possible to obtain an advantageous effect of reducing the leakage current at a given anode voltage Va, is directly transmitted by the electrical coupling of the conductive layer PL1 with the anode region, and Vpol = Go.

FIG. 4 illustrates another embodiment of a PIN-type diode DD2a in a polysilicon bar P1 and comprising a conductive layer P0, parallel to the bar P1 and separated from said bar by a dielectric layer CD1.

As in the embodiment described previously, the diode DD2a comprises in the bar P1, a first anode region A doped with a first type P+ of conductivity, a second cathode region C doped with a second type N+ of conductivity and an intrinsic region INT.

However, in this example, the conductive layer P0 is located in a trench extending vertically in a semiconductor substrate PSUB from the front face FA of the substrate.

The substrate PSUB, for example of P type, optionally comprises an N type well NW in which and on which the diode DD2a is produced.

The conductive layer P0 comprises, on the bottom and the sides of the trench in which it is formed, an insulating envelope TRD, such as a silicon oxide used as gate oxide for vertical transistors.

The insulating envelope TRD on the bottom and the sides of the trench forms an insulating region making it possible to electrically isolate the diode from the semiconductor substrate, in this case from the well NW of the semiconductor substrate PSUB.

In the orientation of the figure, the polysilicon bar P1 rests on the dielectric layer CD1 itself resting on the conductive layer P0. For example, the polysilicon bar P1 can have a thickness of 100 nm.

For example, the dielectric layer CD1 comprises a so-called high voltage oxide layer HV, thick enough to withstand voltages greater than 10V, and a thinner portion TN than the rest of the layer, for example of the tunnel oxide type of transistors with floating grid. The finer portion TN is located opposite the intrinsic region INT of the polysilicon bar P1.

For example, the high voltage oxide layer HV can have a thickness of substantially 18 nm, while the thinner portion TN can have a thickness between 7 nm and 9 nm.

The diode also has anode A and cathode C contacts coupled to the P+, N+ doped regions via a metal silicide film. A contact Cnt0 is coupled to the conductive layer P0 in polysilicon, via a film of metal silicide SAL.

Similarly to the example described previously in relation to FIG. 3, diode DD2a may comprise an electric circuit connecting the anode contact A with the contact Cnt0 of the conductive layer P0, according to an advantageous embodiment.

The metal silicide films on the P+, N+ doped regions and the polysilicon P0 conductive layer are produced during the same silicidation step.

Silicidation may require the use of a protective mask, of the type of the SiPRT protective mask mentioned above in relation to FIG. 2, to avoid a short circuit between the anode and the cathode by a silicided film along the P1 polysilicon bar.

However, this type of SiPRT protection layer may not be provided in a given integrated circuit manufacturing process, and thus it may be desirable to avoid it.

Figure 5 presents an alternative making it possible to avoid the use of such a protective layer against silicidation in the production of the diode DD2a.

The common references with the preceding figures designate the same things and will not be detailed again.

In this alternative, the diode DD2b comprises an additional layer P2 resting on a second dielectric layer CD2 covering the polysilicon bar P1, except at the level of the anode A and cathode C contacts.

The additional layer P2 is for example also a layer of polysilicon, advantageously conductive, and can include spacers SP on its sides. The spacers are the dielectric elements which typically frame the sides of the gates of the transistors, of conventional design and known per se. For example, the additional layer P2 can have a thickness of 150 nm.

The additional layer P2 thus forms a second conductive layer, and is separated from the bar P1 by a second dielectric layer CD2, and by the spacers SP, if applicable.

Thus, the additional layer P2 protects the central part of the bar P1 from silicidation over its entire length, in particular all along the intrinsic region INT.

Being formed of polysilicon, the surface of the additional layer P2 comprises a silicide film. The second dielectric layer CD2 and the spacers SP make it possible to avoid the short circuit between the anode and the cathode.

Thus, the second conductive layer P2 comprising a film of metal silicide forms an embodiment of a second conductive layer P2 capable of being polarized, parallel to the bar of polycrystalline silicon P1.

The second dielectric layer CD2, in the present embodiment, can be assimilated to the production of the dielectric layer (CD) which separates the polysilicon bar PL2 from the conductive layer PL1 of the embodiment DD1 previously described in relation to Figure 1.

Thus, the second dielectric layer CD2 comprises a finer portion LV than the rest of the second dielectric layer ONO, facing the intrinsic region INT of the polysilicon bar P1.

In the orientation of this configuration, the second conductive layer P2 rests on the second dielectric layer CD2 itself resting on said polysilicon bar P1.

The effect described previously in relation to FIG. 3 can both be obtained via a biasing of the conductive layer P0, and via a biasing of the second conductive layer P2.

Thus, the diode can advantageously comprise a second electrical circuit electrically coupling the anode region A and the second conductive layer P2. In this regard, the second conductive layer P2 may comprise a contact Cnt2 electrically connected to the anode contact A and possibly also to the contact Cnt0 of the conductive layer P0 formed in a trench.

FIG. 6 illustrates examples of the implementation of methods for manufacturing diodes DD1, DD2a, DD2b of the type of those previously described in relation to FIGS. 1, 4 and 5.

The term “first alternative” will denote the manufacture of a diode DD1 of the type described in relation to FIG. 1, the term “second alternative” the manufacture of a diode DD2a of the type described in relation to FIG. 4, and by "third alternative" the manufacture of a diode DD2b of the type described in relation to FIG. 5.

The examples according to these three alternatives are presented in relation to eleven steps provided for an example of a method of manufacturing a non-volatile memory. Thus the examples described here constitute advantageous implementations because they are free in the context of manufacturing a non-volatile memory.

In the following, each step 600-610 will be described according to the example of manufacturing a non-volatile memory, then in correspondence with each diode manufacturing alternative.

An initial step 600 includes forming shallow isolation trenches in a semiconductor substrate.

In the first alternative, the initial step 600 may correspond to forming an insulating region STI in a semiconductor substrate, to electrically isolate the diode from the substrate. The second and third alternatives may or may not include the initial step 600 for possible other purposes.

A first step 601 comprises forming a buried gate region of a vertical gate transistor, for example a memory cell access transistor.

Formation of the buried gate region includes etching a vertically extending trench TR in a semiconductor substrate from a front side of the substrate, forming an insulating gate oxide region TRD on the sidewalls and the bottom of the trench TR, and a filling of the trench with a conductive layer P0, for example polysilicon.

In the first alternative, this step is not implemented to produce diode DD1.

In the second and third alternatives, this may correspond to the formation of a conductive layer P0 capable of being polarized parallel to the polycrystalline silicon bar, and to the formation of an insulating region TRD, electrically isolating the diode from a semiconductor substrate .

A second step 602 includes formation of a floating gate dielectric layer CD1, of a floating gate transistor of a memory cell. The formation of the floating gate dielectric layer CD1 comprises a formation of a high voltage oxide HV, an etching GR of an opening in the oxide HV and a formation of a thinner tunnel oxide TN in the opening .

For example, the HV oxide layer may have a thickness of substantially 18 nm and the TN tunnel oxide layer may have a thickness of between 7 nm and 9 nm.

In the first alternative, this step is not implemented to produce diode DD1.

In the second and third alternatives, this may correspond to the formation of a dielectric layer CD1 separating the conductive layer P0 and the (future) polysilicon bar P1, comprising the formation of a finer portion TN than the rest of the layer HV dielectric, next to the intrinsic region.

A third step 603 comprises forming the floating gate of the floating-gate transistor, in conductive doped polysilicon P1/PL1, on the floating-gate dielectric layer CD1.

For example, the P1/PL1 polysilicon layer can have a thickness of 100 nm.

In the first alternative, this may correspond to the formation of a conductive layer PL1 parallel to the (future) bar of polycrystalline silicon (PL2), produced on a surface located at the level of a front face of a semiconductor substrate.

In the second and third alternatives, this may correspond to the formation of a polycrystalline silicon bar P1.

A fourth step 604 includes forming a control gate dielectric layer CD/CD2 of the floating gate transistor, including forming an ONO stack of oxide, nitride, and silicon oxide layers. The ONO layer is removed in a logical part of the non-volatile memory by GR etching. A gate oxide LV of logic MOS transistors is formed in the logic part.

For example, the ONO stack may have a thickness of substantially 15 nm and the gate oxide layer LV may have a thickness of substantially 2.3 nm.

In the first alternative, this may correspond to the formation of a dielectric layer CD separating the conductive layer P1 and the polysilicon bar P2, comprising the formation of a finer portion LV than the rest of the dielectric layer ONO, facing of the intrinsic region.

In the second alternative, this step is not implemented to produce diode DD2a.

In the third alternative, this may correspond to the formation of a second dielectric layer CD2 separating the (future) second conductive layer (P2) and the polysilicon bar P1, comprising the formation of a finer portion LV than the rest of the second dielectric layer ONO, facing the intrinsic region.

A fifth step 605 comprises forming the control gate of the floating-gate transistor (and the gate of the logic MOS transistor), in P2/PL2 conductive doped polysilicon, on the control gate dielectric layer CD/CD2 (ONO and LV)

For example, the P2/PL1 polysilicon layer can have a thickness of 150 nm.

In the first alternative, this may correspond to the formation of a polycrystalline silicon bar PL2.

In the second alternative, this step is not implemented to produce diode DD2a.

In the third alternative, this may correspond to a formation of a second conductive layer P2 parallel to the polycrystalline silicon bar P1.

A sixth step 606 comprises formation of a protective mask against silicidation, possibly provided for part of the non-volatile memory circuit.

In the first and second alternatives, this can prevent a short circuit between the poles of the diode during a subsequent silicidation (SAL).

In the third alternative, this step is not implemented to produce the diode DD2b, the third alternative notably making it possible to avoid this step.

A seventh step 607 comprises implantations of P+, N+ doped regions in the non-volatile memory part and the logic part, for example source and drain regions of the MOS transistors.

In the three alternatives, this corresponds to an implantation of dopants of a first type of conductivity P+ in a first region of the bar PL2/P1, and to an implantation of dopants of a second type of conductivity N+ in a second region of the bar PL2/P1, the first region and the second region being spaced apart by an intrinsic region (INT) of the bar PL2/P1.

An eighth step 608 comprises a siliciding of the uncovered parts of the various polysilicon layers of the circuit.

The silicidation forms a film of metal silicide allowing ohmic contacts with the corresponding polysilicon regions. The conductive layers PL1/P0, and the second conductive layer P2 are thus capable of being biased according to a particular example.

A ninth step 609 comprises contact realizations on silicided parts to electrically connect different parts of the previous realizations together.

In the three alternatives, this may correspond to a realization of an electrical circuit coupling the first P+ doped region of the polysilicon bar PL2/P1 with the conductive layer PL1/P0.

In the third alternative, this may also correspond to a production of a second electrical circuit coupling the first P+ doped region of the polysilicon bar P1 with the second conductive layer P2.

A tenth step 610 may correspond to the embodiments of said diodes as described previously in relation to FIGS. 1, 4 and 5.

Furthermore, the invention is not limited to these embodiments and implementations but encompasses all the variants thereof, for example the method can of course be implemented independently or benefit from “free” compatibility with d other accomplishments. Similarly, other elements known and not described here whose effects are equivalent to those of the examples of elements described in the embodiments, such as the materials used for the conductive and dielectric layers, or the ability to be polarized of said conductive layers, are possible.

In addition, an implantation of fluorine in the intrinsic region of the diode, as described in the French patent application filed on the same day by the same applicant as the present application and entitled "Polycrystalline silicon diode with intrinsic region and process of manufacture”, can make it possible to further improve the current ratio in passing regime on leakage current of the diode according to the present invention.

Claims (26)

Diode including:
- a polycrystalline silicon rod (PL2, P1) comprising a first region doped with a first type of conductivity (P+), a second region doped with a second type of conductivity (N+) and an intrinsic region (INT) located between the first doped region (P+) and the second doped region (N+),
- a conductive layer (PL1, P0) able to be polarized, parallel to the bar of polycrystalline silicon (PL2, P1) and separated from said bar by a dielectric layer (CD, CD1), in which the dielectric layer (CD, CD1) comprises a finer portion (LV, TN) than the rest of the dielectric layer (ONO, HV), facing the intrinsic region (INT). Diode according to Claim 1, in which the polycrystalline silicon rod (PL2, P1) has a thickness of 150nm or 100nm. Diode according to one of Claims 1 or 2, in which the thinner portion (LV, TN) has a thickness of substantially 2.3 nm or a thickness of between 7 nm and 9 nm, and the remainder of the dielectric layer (ONO, HV ) has a thickness of substantially 15 nm or substantially 18 nm. Diode according to one of Claims 1 to 3, in which the said conductive layer (PL1) is located on a surface at the level of a front face (FA) of a semiconductor substrate (SUB). Diode according to one of Claims 1 to 3, in which the said conductive layer (P0) is located in a trench extending vertically in a semiconductor substrate (NW/PSUB) from a front face (FA) of the semiconductor substrate . Diode according to one of the preceding claims, comprising an electrical circuit coupling the first doped region (P+) of the polycrystalline silicon bar (PL2, P1) with the conductive layer (PL1, P0). Diode according to one of the preceding claims, comprising a second conductive layer (P2) capable of being biased, parallel to the bar of polycrystalline silicon (P1) and separated from said bar by a second dielectric layer (CD2). Diode according to Claim 7, in which the second conductive layer (P2) has a thickness of 150 nm, while the polycrystalline silicon bar (P1) has a thickness of 100 nm. Diode according to one of Claims 7 or 8, in which the said second dielectric layer (CD2) comprises a thinner portion (LV) than the rest of the second dielectric layer (ONO), facing the intrinsic region (INT). Diode according to claim 9, wherein said thinner portion (LV) of the second dielectric layer has a thickness of substantially 2.3nm, while the remainder of the second dielectric layer (ONO) has a thickness of substantially 15nm. Diode according to one of Claims 7 to 10, comprising a second electrical circuit coupling the first doped region (P+) of the polycrystalline silicon bar (P1) with the second conductive layer (P2). Diode according to one of the preceding claims, further comprising an insulating region (STI, TRD), electrically isolating the diode from a semiconductor substrate (SUB, NW/PSUB). Diode according to one of the preceding claims, in which the polycrystalline silicon bar (PL1, P0) comprises fluorine atoms at least in the said intrinsic region (INT). Method of manufacturing a diode comprising forming a bar of polycrystalline silicon (605, 603), implanting (607) dopants of a first conductivity type in a first region of the bar, and implanting (607) of dopants of a second conductivity type in a second region of the bar, a region of the bar located between the first region and the second region being left intrinsic (INT), as well as a formation (603, 601) of a layer conductor capable of being polarized parallel to the polycrystalline silicon bar, and a formation (604, 602) of a dielectric layer separating the conductive layer and the polycrystalline silicon bar, in which the formation (604, 602) of the dielectric layer comprises formation (GR/LV, GR/TN) of a finer portion than the rest of the dielectric layer, facing the intrinsic region. A method according to claim 14, wherein said forming the polysilicon bar (605, 603) is configured to form a polysilicon bar (PL2, P1) having a thickness of 150nm or 100nm. Method according to one of Claims 14 or 15, in which the said formation (604, 602) of the dielectric layer is configured to form the thinner portion (LV, TN) having a thickness of substantially 2.3 nm or a thickness comprised between 7nm and 9nm, and to form the remainder of the dielectric layer (ONO, HV) having a thickness of substantially 15nm or substantially 18nm. Method according to one of Claims 14 to 16, in which the formation (603) of the conductive layer is carried out on a surface located at the level of a front face of a semiconductor substrate. Method according to one of Claims 14 to 16, in which the formation (601) of the conductive layer comprises etching (TR) of a trench extending vertically in a semiconductor substrate from a front face of the substrate, and filling (P0) of the trench with the conductive layer. Method according to one of Claims 14 to 18, comprising an embodiment (609) of an electrical circuit coupling the first doped region of the polycrystalline silicon bar with the conductive layer. Method according to one of Claims 14 to 19, comprising a formation (605) of a second conductive layer able to be polarized parallel to the bar of polycrystalline silicon, and a formation (604) of a second dielectric layer separating the second layer conductor and the polycrystalline silicon bar. The method of claim 20, wherein the second conductive layer formation (605) is configured to form the second conductive layer having a thickness of 150nm, the first conductive layer formation (603) being configured to form the first conductive layer having a thickness of 100 nm. Method according to one of Claims 20 or 21, in which the said formation (604) of the second dielectric layer comprises a formation (GR/LV) of a finer portion than the rest of the second dielectric layer, facing the intrinsic region. A method according to claim 22, wherein said forming (604) of the second dielectric layer is configured to form the thinner portion (LV) having a thickness of substantially 2.3nm. Method according to one of Claims 20 to 23, comprising a production (609) of a second electrical circuit coupling the first doped region of the polycrystalline silicon bar with the second conductive layer. Method according to one of claims 14 to 24, further comprising forming (600, 601/TRD) an insulating region, electrically isolating the diode from a semiconductor substrate. Process according to one of Claims 14 to 24, further comprising an implantation of fluorine atoms at least in the said intrinsic region (INT) of the bar of polycrystalline silicon (P2, PL1), and optionally in the whole of the bar of polycrystalline silicon (P2, PL1).