[go: up one dir, main page]

WO2024007360A1 - 反熔丝单元结构、反熔丝阵列及其操作方法以及存储器 - Google Patents

反熔丝单元结构、反熔丝阵列及其操作方法以及存储器 Download PDF

Info

Publication number
WO2024007360A1
WO2024007360A1 PCT/CN2022/105661 CN2022105661W WO2024007360A1 WO 2024007360 A1 WO2024007360 A1 WO 2024007360A1 CN 2022105661 W CN2022105661 W CN 2022105661W WO 2024007360 A1 WO2024007360 A1 WO 2024007360A1
Authority
WO
WIPO (PCT)
Prior art keywords
fuse
transistor
gate line
selection transistor
transistor gate
Prior art date
Application number
PCT/CN2022/105661
Other languages
English (en)
French (fr)
Inventor
侯闯明
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US18/295,839 priority Critical patent/US12277981B2/en
Publication of WO2024007360A1 publication Critical patent/WO2024007360A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components

Definitions

  • the present disclosure relates to the field of integrated circuit technology, and in particular to an antifuse unit structure, an antifuse array and its operating method, and a memory.
  • An antifuse device is a semiconductor device composed of two conductive layers and a dielectric layer between the conductive layers. When not programmed, the conductive layer is separated by the dielectric layer, and both ends of the antifuse are open. During programming (applied high voltage), the dielectric layer is broken down by the high electric field, an electrical connection is formed between the conductive layers on both sides, and the antifuse is short-circuited (melted). This melting process is physically one-time, permanent, and irreversible. The two states before and after the antifuse are used can represent logic "0" and logic "1" respectively.
  • the current antifuse unit structure and the antifuse array composed of multiple antifuse unit structures have problems such as the risk of breakdown of the selection transistor, as well as occupying a large chip area and poor uniformity.
  • embodiments of the present disclosure provide an antifuse unit structure, an antifuse array and an operating method thereof, and a memory.
  • an antifuse unit structure including: a first antifuse transistor having a first terminal and a second terminal; a first selection transistor , the first selection transistor has a first end and a second end, the first end of the first selection transistor is electrically connected to the second end of the first antifuse transistor; the enable signal line is connected to the The first end of the first anti-fuse transistor is electrically connected, and the enable signal line is used to perform a programming operation on the first anti-fuse transistor.
  • the method further includes: an active region extending along a first direction; a first anti-fuse transistor gate line extending along a second direction, and covering part of the active area to define a first antifuse transistor, the first direction intersecting the second direction; a first selection transistor gate line, the first selection transistor gate line along the second direction Extend and cover part of the active area to define a first selection transistor.
  • the method further includes: a bit line electrically connected to the second end of the first selection transistor, the bit line being located above the active area and extending along the first direction;
  • the enable signal line is located above one side of the active area.
  • the enable signal line is arranged parallel to the active area and extends along the first direction.
  • the method further includes: a first doping region and a first common doping region, respectively located in the active regions on both sides of the first anti-fuse transistor gate line; the first common doping region and the first common doping region.
  • Two common doping regions are respectively located in the active regions on both sides of the gate line of the first selection transistor; wherein the second common doping region is electrically connected to the bit line; the first doping region is electrically connected to the bit line;
  • the enable signal line is electrically connected.
  • the method further includes: a second selection transistor gate line extending along the second direction and covering part of the active area to define a second selection transistor; A fuse transistor gate line, the second anti-fuse transistor gate line extends along the second direction and covers part of the active area to define a second anti-fuse transistor.
  • it also includes: a second common doping region and a third common doping region, respectively located in the active regions on both sides of the gate line of the second selection transistor; a third common doping region and a second common doping region. Doping regions are respectively located in the active regions on both sides of the gate line of the second anti-fuse transistor; wherein the second doping region is electrically connected to the enable signal line.
  • the width of the first anti-fuse transistor gate line along the first direction is less than or equal to the width of the first selection transistor gate line along the first direction; the second anti-fuse transistor The width of the gate line along the first direction is less than or equal to the width of the second selection transistor gate line along the first direction.
  • the width of the first anti-fuse transistor gate line along the first direction is equal to the width of the second anti-fuse transistor gate line along the first direction
  • the width of the first selection transistor gate line The width along the first direction is equal to the width of the second selection transistor gate line along the first direction
  • the combination of the first antifuse transistor gate line and the first selection transistor gate line is The combination of the second selection transistor gate line and the second anti-fuse transistor gate line is distributed axially symmetrically.
  • the method further includes: a first contact plug located on the first doped region; a first connector through which the enable signal line is connected to the first contact plug.
  • the plug is electrically connected; a second contact plug located on the second common doped region; a second connector, the bit line is electrically connected to the second contact plug through the second connector; located on the a third contact plug on the second doped region; a third connector through which the enable signal line is electrically connected to the third contact plug.
  • an antifuse array including: a plurality of first antifuse transistors and a plurality of first selection transistors arranged in an array, the first antifuse transistors has a first terminal and a second terminal, the first selection transistor has a first terminal and a second terminal, wherein a first anti-fuse transistor corresponds to a first selection transistor, and the first selection transistor of each first selection transistor has a first terminal and a second terminal.
  • One end is electrically connected to the second end of the corresponding first antifuse transistor; a plurality of bit lines, each bit line is electrically connected to the second end of a column of first selection transistors; a plurality of enable signal lines, each Each enable signal line is electrically connected to a first end of a row of first anti-fuse transistors, and the enable signal line is used to perform a programming operation on the first anti-fuse transistor.
  • the method further includes: a plurality of active areas arranged as a plurality of active area rows extending along the second direction and a plurality of active area columns extending along the first direction.
  • the first direction is perpendicular to the second direction, each active region extends along the first direction; a plurality of first anti-fuse transistor gate lines, a plurality of first anti-fuse transistors The gate lines are arranged parallel to each other and extend along the second direction.
  • Each of the first anti-fuse transistor gate lines covers a plurality of active areas in one of the active area rows to define multiple thirds of the array arrangement.
  • An anti-fuse transistor a plurality of first selection transistor gate lines, the plurality of first selection transistor gate lines are arranged parallel to each other and extend along the second direction, and each first selection transistor gate line covers a corresponding A plurality of active areas within the active area row are used to define a plurality of first selection transistors arranged in an array.
  • the method further includes: a plurality of second selection transistor gate lines, the plurality of second selection transistor gate lines are arranged parallel to each other and extend along the second direction, and each second selection transistor gate line corresponds to Covering a plurality of active areas in one active area row to define a plurality of second selection transistors arranged in an array; a plurality of second anti-fuse transistor gate lines, and a plurality of second anti-fuse transistor gates The lines are arranged parallel to each other and extend along the second direction. Each second anti-fuse transistor gate line covers a plurality of active areas in one of the active area rows to define a plurality of second anti-fuse transistor gate lines arranged in the array. Antifuse transistor.
  • a plurality of the enable signal lines are arranged along the second direction and extend along the first direction, wherein each of the enable signal lines and each of the active areas are listed in the are arranged alternately in the second direction; a plurality of the bit lines are arranged parallel to each other and extend along the first direction, each bit line corresponds to an active area column, and each bit line is located in each corresponding One above the active area array.
  • a method of operating an antifuse array including:
  • An antifuse array according to any one of the above embodiments is provided; a programming operation or a read operation is performed on the antifuse array.
  • the programming operation includes: selecting an anti-fuse transistor to be programmed, applying a first voltage to the gate line of the anti-fuse transistor to be programmed, leaving other anti-fuse transistor gate lines floating; The transistor gate line is suspended; a second voltage is applied to the enable signal line electrically connected to the anti-fuse transistor to be programmed; wherein the absolute value of the difference between the first voltage and the second voltage is greater than the anti-fuse transistor.
  • the read operation includes: selecting an anti-fuse transistor to be read, applying a third voltage to a selection transistor gate line electrically connected to the anti-fuse transistor to be read, and switching the gates of other selection transistors to The line is floating; a fourth voltage is applied to the bit line electrically connected to the anti-fuse transistor to be read, and the other bit lines are left floating; a fifth voltage is applied to the gate line of the anti-fuse transistor to be read, and the other anti-fuse transistors are The transistor gate line is suspended; all enable signal lines are suspended; wherein, the third voltage is the turn-on voltage of the selection transistor, and the absolute value of the difference between the fourth voltage and the fifth voltage is less than the The breakdown voltage of the gate dielectric layer of the antifuse transistor.
  • a memory including the antifuse unit structure as described in any one of the above embodiments.
  • the anti-fuse unit structure provided by the embodiment of the present disclosure adds an enable signal line (BE, Blow enable) control end.
  • the enable signal line is electrically connected to one end of the anti-fuse transistor, and the other end of the anti-fuse transistor is electrically connected to the selection transistor. connect.
  • Figure 1 is a circuit diagram of an antifuse unit structure provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of an antifuse unit structure provided by an embodiment of the present disclosure
  • Figure 3 is a circuit diagram of another antifuse array provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of another antifuse array provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic flowchart of an operating method of an antifuse array provided by an embodiment of the present disclosure.
  • the antifuse transistor is electrically connected to the bit line through the selection transistor, and the voltage difference between the bit line (BL) and the gate of the antifuse transistor is used to make the thin gate of the antifuse transistor
  • the oxide is broken down under high voltage and the resistance drops significantly, achieving the purpose of programming or writing.
  • the current architecture often has problems such as the risk of failure and occupying a large chip area.
  • Figure 1 is a circuit diagram of the anti-fuse unit structure provided by the embodiment of the present disclosure.
  • Figure 2 is the structure of the anti-fuse unit structure provided by the embodiment of the present disclosure. Schematic diagram.
  • the anti-fuse unit structure includes: a first anti-fuse transistor 11, the first anti-fuse transistor 11 has a first end and a second end; a first selection transistor 12, the first selection transistor 12 It has a first end and a second end, and the first end of the first selection transistor 12 is electrically connected to the second end of the first anti-fuse transistor 11; the enable signal line 15 is connected to the first end of the first anti-fuse transistor 11.
  • the terminals are electrically connected, and the enable signal line 15 is used for programming the first anti-fuse transistor 11 .
  • the second terminal of the first selection transistor 12 may be electrically connected to the bit line 16 .
  • the anti-fuse unit structure provided by the embodiment of the present disclosure adds an enable signal line (BE, Blow enable) control end.
  • the enable signal line is electrically connected to one end of the anti-fuse transistor, and the other end of the anti-fuse transistor is electrically connected to the selection transistor. connect.
  • the first terminal and the second terminal of the first anti-fuse transistor 11 may be the first pole and the second pole of the transistor respectively, wherein the first pole may be the source pole and the second pole may be The drain electrode; alternatively, the first electrode can be the drain electrode and the second electrode can be the source electrode.
  • the first terminal and the second terminal of the first selection transistor 12 may be respectively the first pole and the second pole of the selection transistor, wherein the first pole may be the source and the second pole may be the drain; or, the first pole It can be the drain, and the second electrode can be the source.
  • the first antifuse transistor and the first selection transistor may include metal oxide semiconductor transistors (MOS), such as P-type metal oxide semiconductor transistors (PMOS) or N-type metal oxide semiconductor transistors (NMOS), etc. .
  • the antifuse unit structure further includes: an active region 17 extending along the first direction; a first antifuse transistor gate line 21 , a first antifuse transistor gate line 21 , and an active region 17 extending along the first direction.
  • the silk transistor gate line 21 extends along the second direction and covers part of the active area 17 to define a first anti-fuse transistor.
  • the first direction intersects the second direction; the first selection transistor gate line 22, the first selection transistor gate line 22 extends along the second direction and covers part of the active area 17 to define a first selection transistor.
  • the active region 17 is disposed on a substrate, and the substrate may be silicon, silicon germanium, germanium or other suitable semiconductors.
  • the first active region may be formed by doping n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof; and may be formed by doping n-type dopants such as boron, indium, other p-type dopants, or combinations thereof; Dopants or p-type dopants combined therewith are used to form a P-type doped region.
  • the active region 17 may include source/drain doped regions.
  • the materials of the first antifuse transistor gate line 21 and the first selection transistor gate line 22 include but are not limited to polysilicon, titanium nitride, metal tungsten or combinations thereof.
  • the first direction can be perpendicular to the second direction, which can further improve the integration of the structure.
  • a second selection transistor gate line 23 is also included.
  • the second selection transistor gate line 23 extends along the second direction and covers part of the active area 17 to define a second selection transistor. 13;
  • the second anti-fuse transistor gate line 24 extends along the second direction and covers part of the active area 17 to define the second anti-fuse transistor 14 .
  • the materials of the second selection transistor gate line 23 and the second anti-fuse transistor gate line 24 include but are not limited to polysilicon, titanium nitride, metal tungsten or combinations thereof.
  • the antifuse unit structure further includes: a bit line 16 electrically connected to the second end of the first selection transistor 12 , the bit line 16 is located above the active area 17 and along the The enable signal line 15 extends in the first direction; the enable signal line 15 is located above one side of the active area 17 , and the enable signal line 15 is arranged parallel to the active area 17 and extends along the first direction.
  • the materials of the bit line 16 and the enable signal line 15 include, but are not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN).
  • the active area may be located in the substrate
  • the enable signal line may be located in a certain metal layer on the substrate
  • the bit line 16 may be located in another metal layer on the substrate, and the other metal layer It may be located on a side of the certain metal layer away from the substrate.
  • the orthographic projection of the bit line on the substrate plane partially overlaps the orthographic projection of the active area on the substrate plane, so that the orthographic projection of the signal line on the substrate plane is located on one side of the orthographic projection of the active area on the substrate plane.
  • the antifuse unit structure further includes: a first doping region 25 and a first common doping region 26, respectively located on both sides of the first antifuse transistor gate line 21.
  • the first common doping region 26 and the second common doping region 27 are respectively located in the active region 17 on both sides of the first selection transistor gate line 22; wherein the second common doping region 27 and The bit line 16 is electrically connected; the first doped region 25 is electrically connected to the enable signal line 15 .
  • the first doping region 25 and the first common doping region 26 may be the first terminal and the second terminal of the first anti-fuse transistor 11 respectively.
  • the first common doping region 26 and the second common doping region 27 may be the first terminal and the second terminal of the first selection transistor 12 respectively.
  • the second end of the first anti-fuse transistor 11 and the first end of the first selection transistor 12 are electrically connected through the first common doping region 26, which reduces the area of the doping region and improves space utilization.
  • the antifuse unit structure further includes: a second common doping region 27 and a third common doping region 28, respectively located on both sides of the second selection transistor gate line 23.
  • the third common doping region 28 and the second doping region 29 are respectively located in the active region 17 on both sides of the second anti-fuse transistor gate line 24; wherein the second doping region 29 and the The signal line 15 can be electrically connected.
  • the second common doping region 27 and the third common doping region 28 may be the first terminal and the second terminal of the second selection transistor 13 respectively.
  • the second end of the first selection transistor and the first end of the second selection transistor are electrically connected through the second common doping region 27, which can improve space utilization.
  • the third common doping region 28 and the second doping region 29 may be the first terminal and the second terminal of the second anti-fuse transistor 14 respectively.
  • the second terminal of the second selection transistor and the first terminal of the second anti-fuse transistor are electrically connected through the third common doping region 28, which can improve space utilization.
  • the first doping region 25, the first common doping region 26, the second common doping region 27, the third common doping region 28 and the second doping region 29 may be heavily doped regions.
  • the active region 17 is formed by ion implantation. Each doped region can have the same doping concentration, and can be both N-type heavily doped or both P-type heavily doped.
  • the first common doping region 26 is the common drain/source of the first antifuse transistor 11 and the first selection transistor 12
  • the second common doping region 27 is the common drain/source of the first selection transistor 12 and the second selection transistor 13 Drain/source
  • the third common doping region 28 is the common drain/source of the second selection transistor 13 and the second anti-fuse transistor 14 .
  • the width W1 of the first anti-fuse transistor gate line along the first direction is less than or equal to the width W2 of the first selection transistor gate line along the first direction;
  • the width W4 of the fuse transistor gate line along the first direction is less than or equal to the width W3 of the second selection transistor gate line along the first direction.
  • the first anti-fuse transistor gate line, the first selection transistor gate line, the second selection transistor gate line and the second anti-fuse transistor gate line can be formed simultaneously, and the formation process includes but is not limited to various patterning processes. In this way, it can be beneficial to the preparation of the mask and reduce the difficulty of the patterning process, and at the same time, it can improve the uniformity of the subsequent formation of the antifuse array.
  • both the first antifuse transistor 11 and the second antifuse transistor 14 may have smaller channel lengths (for example, the first terminal and the second terminal of the antifuse transistor There is a large leakage current between the two terminals, that is, the first terminal and the second terminal of the anti-fuse transistor can be regarded as connected to each other to a certain extent), to ensure that the gate dielectric layer of the anti-fuse transistor is broken down , the gate of the antifuse transistor is conductive to both its first terminal and its second terminal.
  • the width W1 of the first anti-fuse transistor gate line along the first direction may be equal to the width W4 of the second anti-fuse transistor gate line along the first direction, and the first selection transistor gate line is along the first direction.
  • the width W2 in one direction may be equal to the width W3 of the second selection transistor gate line in the first direction, wherein the combination of the first antifuse transistor gate line and the first selection transistor gate line is the same as the width W3 of the second selection transistor gate line.
  • the combination with the second anti-fuse transistor gate line is axially symmetrically distributed. In this way, the first antifuse transistor and the second antifuse transistor are arranged in a mirror image, and the first selection transistor and the second selection transistor are arranged in a mirror image, which can improve the uniformity of the subsequent formation of the antifuse array.
  • the distance between the first antifuse transistor gate line and the first selection transistor gate line is the first distance D1, the second selection transistor gate line and the second antifuse
  • the distance between the transistor gate lines is a second distance D2, wherein the first distance D1 is equal to the second distance D2. This can further improve the uniformity of the subsequent formation of the antifuse array.
  • the first antifuse transistor gate line has a width W1 along the first direction
  • the first selection transistor gate line has a width W2 along the first direction
  • the second selection transistor gate line has a width W1 along the first direction.
  • the width W3 of the second anti-fuse transistor gate line along the first direction, the first distance D1 and the second distance D2 are all equal.
  • the selection transistor is a thick oxide device with a long gate length, and a larger device width is required to enable the selection transistor to have sufficient current driving capability.
  • ND N-type drain region
  • PW P-type well region
  • the anti-fuse unit structure can reduce the width of the selection transistor gate line (XG) to the same width as the anti-fuse transistor gate line (FG) without significantly reducing the length of the selection transistor gate line (XG). consistent.
  • the source and drain doped regions on both sides of the anti-fuse transistor gate line will significantly reduce the reverse bias junction barrier and increase the read current under the action of the depletion layer.
  • the spacing between the anti-fuse transistor gate line and the selection transistor gate line can be further reduced.
  • the photomask for preparing the ion doping region of the antifuse transistor is omitted, which reduces the chip manufacturing cost.
  • the antifuse unit structure further includes: a first contact plug 251 located on the first doped region 25; a first connection 252 that enables the signal line 15 to pass through the first contact plug 251; A connection member 252 is electrically connected to the first contact plug 251; a second contact plug 271 located on the second common doping region 27; a second connection member 272, the bit line 16 is connected to the second contact through the second connection member 272
  • the plug 271 is electrically connected to the third contact plug 291 located on the second doped region 29 and the third connector 292, enabling the signal line 15 to be electrically connected to the third contact plug 291 through the third connector 292.
  • the first connecting member 252, the second connecting member 272 and the third connecting member 292 may be the same film layer, or may be different film layers. For example, it may be located in the same metal layer as the enable signal line 15 .
  • the antifuse unit structure further includes: a sixth contact plug 273 through which the bit line 16 is electrically connected to the second connection member 272 . In this way, the bit line 16 and the enable signal line 15 are located in different metal layers to avoid signal crosstalk and increase wiring flexibility.
  • the anti-fuse unit structure further includes: a fourth contact plug 211, through which the first anti-fuse transistor gate line 21 is electrically connected to the fourth connector 212; a fifth contact plug The first selection transistor gate line 22 is electrically connected to the fifth connection member 222 through the fifth contact plug 221 .
  • the fourth connecting member 212 and the fifth connecting member 222 may be of the same film layer, or may be of different film layers.
  • the embodiment of the present disclosure also provides an antifuse array.
  • Figure 3 is a circuit diagram of the antifuse array provided by the embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of the antifuse array provided by the embodiment of the present disclosure.
  • the antifuse array includes: a plurality of first antifuse transistors 11 and a plurality of first selection transistors 12 arranged in an array.
  • the first antifuse transistor 11 has a first end and a second end. terminal
  • the first selection transistor 12 has a first terminal and a second terminal, wherein one first anti-fuse transistor 11 corresponds to one first selection transistor 12, and the first terminal of each first selection transistor 12 has its corresponding first terminal.
  • the second end of the antifuse transistor 11 is electrically connected; a plurality of bit lines 16, each bit line 16 is electrically connected to the second end of a column of first selection transistors 12; a plurality of enable signal lines 15, each enable signal The line 15 is electrically connected to the first end of a row of first anti-fuse transistors 11 , and the enable signal line 15 is used to perform programming operations on the first anti-fuse transistors 11 .
  • the first terminal and the second terminal of the first anti-fuse transistor 11 may be the first pole and the second pole of the transistor respectively, wherein the first pole may be the source pole and the second pole may be The drain electrode; alternatively, the first electrode can be the drain electrode and the second electrode can be the source electrode.
  • the first terminal and the second terminal of the first selection transistor 12 may be respectively the first pole and the second pole of the selection transistor, wherein the first pole may be the source and the second pole may be the drain; or, the first pole It can be the drain, and the second electrode can be the source.
  • the first antifuse transistor and the first selection transistor may include metal oxide semiconductor transistors (MOS), such as P-type metal oxide semiconductor transistors (PMOS) or N-type metal oxide semiconductor transistors (NMOS), etc. .
  • the antifuse array further includes: a plurality of active regions 17 arranged into a plurality of active region rows R extending along the second direction and A plurality of active area columns C extending along a first direction, the first direction is perpendicular to the second direction, each active area 17 extends along the first direction; a plurality of first anti-fuse transistor gate lines 21, a plurality of An anti-fuse transistor gate line 21 is arranged parallel to each other and extends along the second direction. Each first anti-fuse transistor gate line 21 covers a plurality of active areas 17 in an active area row R to define an array.
  • a plurality of first anti-fuse transistors 11 are arranged; a plurality of first selection transistor gate lines 22 are arranged parallel to each other and extend along the second direction, and each first selection transistor gate The lines 22 correspond to covering a plurality of active areas 17 in an active area row R to define a plurality of first selection transistors 12 arranged in an array.
  • the active region 17 is disposed on a substrate, and the substrate may be silicon, silicon germanium, germanium or other suitable semiconductors.
  • the first active region may be formed by doping n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof; and may be formed by doping n-type dopants such as boron, indium, other p-type dopants, or combinations thereof; Dopants or p-type dopants combined therewith are used to form a P-type doped region.
  • the active region 17 may include source/drain doped regions.
  • the materials of the first antifuse transistor gate line 21 and the first selection transistor gate line 22 include but are not limited to polysilicon, titanium nitride, metal tungsten or combinations thereof.
  • the first direction can be perpendicular to the second direction, which can further improve the integration of the structure.
  • the antifuse array further includes: a plurality of second selection transistor gate lines 23, the plurality of second selection transistor gate lines 23 are arranged parallel to each other and extend along the second direction, Each second selection transistor gate line 23 covers a plurality of active areas 17 in an active area row R to define a plurality of second selection transistors 13 arranged in an array; a plurality of second anti-fuse transistor gate lines 24. A plurality of second anti-fuse transistor gate lines 24 are arranged parallel to each other and extend along the second direction. Each second anti-fuse transistor gate line 24 covers multiple active areas in an active area row R. 17 to define a plurality of second anti-fuse transistors 14 arranged in an array.
  • the materials of the second selection transistor gate line 23 and the second anti-fuse transistor gate line 24 include but are not limited to polysilicon, titanium nitride, metal tungsten or combinations thereof.
  • a plurality of enable signal lines 15 are arranged along the second direction and extend along the first direction, wherein each enable signal line 15 and each active area column C are arranged alternately in the second direction; the plurality of bit lines 16 are arranged parallel to each other and extend along the first direction.
  • Each bit line 16 corresponds to an active area column C, and each bit line 16 is located in each corresponding active area column C. Source area above column C.
  • the materials of the bit line 16 and the enable signal line 15 include, but are not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN).
  • the active area may be located in the substrate
  • the enable signal line may be located in the M0 metal layer
  • the bit line 16 may be located in the M1 metal layer.
  • the orthographic projection of each bit line 16 on the substrate plane partially overlaps the orthographic projection of the active area column C on the substrate plane.
  • the antifuse array includes any of the antifuse cell structures described above.
  • the antifuse array further includes: a first doping region 25 and a first common doping region 26 , respectively located on both sides of the first antifuse transistor gate line 21 .
  • the first common doping region 26 and the second common doping region 27 are respectively located in the active region 17 on both sides of the first selection transistor gate line 22; wherein the second common doping region 27 and the bit
  • the line 16 is electrically connected; the first doped region 25 is electrically connected to the enable signal line 15 .
  • the antifuse array further includes: a second common doping region 27 and a third common doping region 28 , respectively located on both sides of the second selection transistor gate line 23 .
  • the third common doping region 28 and the second doping region 29 are respectively located in the active region 17 on both sides of the second anti-fuse transistor gate line 24; wherein the second doping region 29 and the enable The signal line 15 is electrically connected.
  • the width W1 of the first anti-fuse transistor gate line along the first direction is less than or equal to the width W2 of the first selection transistor gate line along the first direction;
  • the width W4 of the fuse transistor gate line along the first direction is less than or equal to the width W3 of the second selection transistor gate line along the first direction.
  • the width W1 of the first anti-fuse transistor gate line along the first direction may be equal to the width W4 of the second anti-fuse transistor gate line along the first direction.
  • the width W2 of a selection transistor gate line along the first direction may be equal to the width W3 of the second selection transistor gate line along the first direction, wherein the combination of the first antifuse transistor gate line and the first selection transistor gate line.
  • the combination of the second selection transistor gate line and the second anti-fuse transistor gate line is axially symmetrically distributed. In this way, the first antifuse transistor and the second antifuse transistor are arranged in a mirror image, and the first selection transistor and the second selection transistor are arranged in a mirror image, which can improve the uniformity of the subsequent formation of the antifuse array.
  • the distance between the first antifuse transistor gate line and the first selection transistor gate line is the first distance D1
  • the second selection transistor gate line and the second antifuse The distance between the transistor gate lines is a second distance D2, wherein the first distance D1 is equal to the second distance D2. This can further improve the uniformity of the antifuse array.
  • the antifuse array further includes: a first contact plug 251 located on the first doped region 25 ; a first connector 252 enabling the signal line 15 to pass through the first
  • the connector 252 is electrically connected to the first contact plug 251; the second contact plug 271 located on the second common doping region 27; the second connector 272.
  • the bit line 16 is connected to the second contact plug through the second connector 272.
  • the plug 271 is electrically connected to the third contact plug 291 located on the second doped region 29 and the third connector 292, enabling the signal line 15 to be electrically connected to the third contact plug 291 through the third connector 292.
  • the bit line 16 and the enable signal line 15 are located in different metal layers to avoid signal crosstalk and increase wiring flexibility.
  • An embodiment of the present disclosure also provides an operation method of an antifuse array, as shown in Figure 5, including:
  • Step 501 Provide an antifuse array as in any one of the above embodiments;
  • Step 502 Perform a programming operation or a read operation on the antifuse array.
  • step 501 is performed to provide an antifuse array as in any one of the above embodiments.
  • step 502 is performed to perform a programming operation or a reading operation on the antifuse array.
  • the programming operation includes: selecting an anti-fuse transistor to be programmed, applying a first voltage to the gate line of the anti-fuse transistor to be programmed, leaving other anti-fuse transistor gate lines floating; The line is left floating; a second voltage is applied to the enable signal line electrically connected to the anti-fuse transistor to be programmed; wherein the absolute value of the difference between the first voltage and the second voltage is greater than or equal to the gate dielectric layer of the anti-fuse transistor breakdown voltage (that is, the gate dielectric layer of the antifuse transistor can be broken down).
  • the gate dielectric layer may be an oxide layer, for example.
  • the antifuse transistor to be programmed is located in the active area of the first column and first row.
  • the anti-fuse transistor to be programmed includes at least one of a first anti-fuse transistor and a second anti-fuse transistor. During the programming operation, at least one of them can be fused, that is, two of them can be completed. individual programming or simultaneous programming.
  • a first voltage is applied to the gate line of the anti-fuse transistor to be programmed, and the gate lines of other anti-fuse transistors are suspended or set to zero voltage.
  • the gate lines of the anti-fuse transistor to be programmed are electrically connected to The enable signal line applies a second voltage.
  • a first voltage is applied to the anti-fuse transistor gate line covering the active area of the first column and the first row, and the other anti-fuse transistor gate lines are left floating or set to zero voltage.
  • the anti-fuse transistor gate lines located in the first column are The enable signal line on the active area side of the first row applies a second voltage.
  • the first voltage can be, for example, 6V
  • the second voltage can be, for example, 0V
  • the difference between the first voltage and the second voltage can breakdown the antifuse.
  • the gate dielectric layer of the transistor causes the antifuse transistor to be broken down.
  • the antifuse transistor gate line includes a first antifuse transistor gate line and a second antifuse transistor gate line.
  • a first voltage may be applied to at least one of the first antifuse transistor gate line and the second antifuse transistor gate line. In this way, one or both of the first anti-fuse transistor and the second anti-fuse transistor are blown, and programming can be completed.
  • one of the first voltage and the second voltage may be a positive voltage
  • the other of the first voltage and the second voltage may be a negative voltage
  • the absolute value of the first voltage is less than a gate dielectric of the antifuse transistor.
  • the breakdown voltage of the second voltage layer and the absolute value of the second voltage are also smaller than the breakdown voltage of the gate dielectric layer of the anti-fuse transistor.
  • the absolute value of the voltage is also called the amplitude of the voltage.
  • the breakdown voltage of the gate dielectric layer of the anti-fuse transistor is 6V
  • the first voltage can be, for example, 5V
  • the second voltage can be, for example, -1V
  • the amplitude of the first voltage is 5V, which is smaller than that of the anti-fuse transistor.
  • the breakdown voltage of the gate dielectric layer, the amplitude of the second voltage is -1V, is smaller than the breakdown voltage of the gate dielectric layer of the anti-fuse transistor.
  • the amplitude of the difference between the first voltage and the second voltage is 6V, which can break down the gate dielectric layer of the anti-fuse transistor. In this way, the amplitude of the first voltage applied to the gate line of the anti-fuse transistor to be programmed is prevented from being too high.
  • the excessively high first voltage may affect other anti-fuse transistors located in the same active area row as the anti-fuse transistor to be programmed. Wire transistor is misprogrammed.
  • the above-mentioned misprogramming operation refers to other anti-fuse transistors located in the same active area row as the anti-fuse transistor to be programmed. Since the amplitude of the first voltage is too high, even when the enable signal line is floating, the May be penetrated.
  • the read operation includes: selecting an anti-fuse transistor to be read, applying a third voltage to a selection transistor gate line electrically connected to the anti-fuse transistor to be read, and leaving other selection transistor gate lines floating. ; Apply a fourth voltage to the bit line electrically connected to the anti-fuse transistor to be read, and leave other bit lines floating; Apply a fifth voltage to the gate line of the anti-fuse transistor to be read, and set the gates of other anti-fuse transistors The line is left floating; all enable signal lines are left floating; among them, the third voltage is the turn-on voltage of the selection transistor, and the absolute value of the difference between the fourth voltage and the fifth voltage is less than the breakdown voltage of the gate dielectric layer of the anti-fuse transistor. . It should be noted that the "turn-on voltage" here is the normal operating voltage of the selection transistor.
  • the antifuse transistor to be read is located in the active area of the first column and first row.
  • a third voltage is applied to the selection transistor gate line electrically connected to the anti-fuse transistor to be read, and the other selection transistor gate lines are left floating; a fourth voltage is applied to the bit line electrically connected to the anti-fuse transistor to be read. voltage, leaving other bit lines floating; applying a fifth voltage to the anti-fuse transistor gate line to be read, leaving other anti-fuse transistor gate lines floating; at the same time, leaving all enable signal lines floating.
  • a third voltage is applied to the anti-fuse transistor gate line in the active area covering the first column and the first row, and the other anti-fuse transistor gate lines are suspended; in the active area located in the first column and the first row A fourth voltage is applied to the upper bit line, and the fourth voltage may be, for example, 1V; a fifth voltage is applied to the antifuse transistor gate line covering the active area of the first column and first row, and the fifth voltage may be, for example, 0V.
  • the third voltage is the turn-on voltage of the selection transistor. In this way, the current can be read at the bit line end, and the storage state can be determined by the magnitude of the current to implement the read operation.
  • An embodiment of the present disclosure also provides a memory, including the antifuse unit structure as in any one of the above embodiments.
  • the anti-fuse unit structure provided by the embodiment of the present disclosure adds an enable signal line (BE, Blow enable) control end.
  • the enable signal line is electrically connected to one end of the anti-fuse transistor, and the other end of the anti-fuse transistor is One end is electrically connected to the selection transistor.
  • the voltage difference between the control terminal of the enable signal line and the gate of the anti-fuse transistor causes the anti-fuse transistor to breakdown. There is no need to open the selection transistor, and the high voltage that is broken down by the anti-fuse transistor does not need to pass through the selection transistor, thereby preventing damage to the selection transistor.
  • the antifuse unit structure, antifuse array and its operating method and memory provided by the embodiments of the present disclosure can be applied to any integrated circuit including the structure.
  • the technical features in the technical solutions described in each embodiment can be combined arbitrarily as long as there is no conflict.
  • Those skilled in the art can change the order of steps in the above forming method without departing from the protection scope of the present disclosure. If there is no conflict between the steps in the embodiments of the present disclosure, some steps can be executed at the same time, or they can be executed sequentially. .
  • the anti-fuse unit structure provided by the embodiment of the present disclosure adds an enable signal line (BE, Blow enable) control end.
  • the enable signal line is electrically connected to one end of the anti-fuse transistor, and the other end of the anti-fuse transistor is electrically connected to the selection transistor. connect.

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

本公开实施例公开了一种反熔丝单元结构、反熔丝阵列及其操作方法以及存储器，其中，所述反熔丝单元结构包括：第一反熔丝晶体管，所述第一反熔丝晶体管具有第一端和第二端；第一选择晶体管，所述第一选择晶体管具有第一端和第二端，所述第一选择晶体管的第一端与所述第一反熔丝晶体管的第二端电连接；使能信号线，与所述第一反熔丝晶体管的第一端电连接，所述使能信号线用于对所述第一反熔丝晶体管进行编程操作。

Description

反熔丝单元结构、反熔丝阵列及其操作方法以及存储器
相关申请的交叉引用
本公开基于申请号为202210786964.8、申请日为2022年07月04日、发明名称为“反熔丝单元结构、反熔丝阵列及其操作方法以及存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及集成电路技术领域，尤其涉及一种反熔丝单元结构、反熔丝阵列及其操作方法以及存储器。
背景技术
基于反熔丝(Anti-fuse)技术的一次可编程器件被广泛应用于DRAM、NAND等存储器中。反熔丝器件是一种由两个导电层及介于导电层之间的介质层构成的半导体器件。未编程时，导电层被介质层隔开，反熔丝两端断路。编程时(外加高压)，介质层被高电场击穿，两侧的导电层之间形成电连接，反熔丝短路(熔通)。这种熔通过程在物理上是一次性的、永久性的、不可逆的。利用反熔丝熔通前、熔通后两种状态可以分别代表逻辑“0”和逻辑“1”。但是，目前的反熔丝单元结构以及由多个反熔丝单元结构构成的反熔丝阵列存在选择晶体管被击穿的风险，以及占据芯片面积较大、均匀性差等问题。
因此，如何优化反熔丝单元结构以及反熔丝阵列为现阶段亟需解决的技术问题。
发明内容
有鉴于此，本公开实施例提供一种反熔丝单元结构、反熔丝阵列及其操作方法以及存储器。
根据本公开实施例的第一方面，提供了一种反熔丝单元结构，包括：第一反熔丝晶体管，所述第一反熔丝晶体管具有第一端和第二端；第一选择晶体管，所述第一选择晶体管具有第一端和第二端，所述第一选择晶体管的第一端与所述第一反熔丝晶体管的第二端电连接；使能信号线，与所述第一反熔丝晶体管的第一端电连接，所述使能信号线用于对所述第一反熔丝晶体管进行编程操作。
在一些实施例中，还包括：有源区，所述有源区沿第一方向延伸；第一反熔丝晶体管栅线，所述第一反熔丝晶体管栅线沿第二方向延伸，且覆盖部分所述有源区以定义第一反熔丝晶体管，所述第一方向与所述第二方向相交；第一选择晶体管栅线，所述第一选择晶体管栅线沿所述第二方向延伸，且覆盖部分所述有源区以定义第一选择晶体管。
在一些实施例中，还包括：位线，与所述第一选择晶体管的第二端电连接，所述位线位于所述有源区上方，且沿所述第一方向延伸；所述使能信号线位于所述有源区一侧的上方，所述使能信号线与所述有源区平行排布且沿所述第一方向延伸。
在一些实施例中，还包括：第一掺杂区和第一共用掺杂区，分别位于所述第一反熔丝晶体管栅线两侧的有源区内；第一共用掺杂区和第二共用掺杂区，分别位于所述第一选择晶体管栅线两侧的有源区内；其中，所述第二共用掺杂区与所述位线电连接；所述第一掺杂区与所述使能信号线电连接。
在一些实施例中，还包括：第二选择晶体管栅线，所述第二选择晶体管栅线沿所述第二方向延伸，且覆盖部分所述有源区以定义第二选择晶体管；第二反熔丝晶体管栅线，所述第二反熔丝晶体管栅线沿所述第二方向延伸，且覆盖部分所述有源区以定义第二反熔丝晶体管。
在一些实施例中，还包括：第二共用掺杂区和第三共用掺杂区，分别位于所述第二选择晶体管栅线两侧的有源区内；第三共用掺杂区和第二掺杂区，分别位于第二反熔丝晶体管栅线两侧的有源区内；其中，所述第二掺杂区与所述使能信号线电连接。
在一些实施例中，所述第一反熔丝晶体管栅线沿第一方向上的宽度小于或等于所述第一选择晶体管栅线沿第一方向上的宽度；所述第二反熔丝晶体管栅线沿第一方向上的宽度小于或等于所述第二选择晶体管栅线沿第一方向上的宽度。
在一些实施例中，所述第一反熔丝晶体管栅线沿第一方向上的宽度等于所述第二反熔丝晶体管栅线沿第一方向上的宽度、所述第一选择晶体管栅线沿第一方向上的宽度等于所述第二选择晶体管栅线沿第一方向上的宽度，其中，所述第一反熔丝晶体管栅线和所述第一选择晶体管栅线的组合与所述第二选择晶体管栅线和所述第二反熔丝晶体管栅线的组合呈轴对称分布。
在一些实施例中，还包括：位于所述第一掺杂区上的第一接触插塞；第一连接件，所述使能信号线通过所述第一连接件与所述第一接触插塞电连接；位于所述第二共用掺杂区上的第二接触插塞；第二连接件，所述位线通过所述第二连接件与所述第二接触插塞电连接；位于所述第二掺杂区上的第三接触插塞；第三连接件，所述使能信号线通过所述第三连接件与所述第三接触插塞电连接。
根据本公开实施例的第二方面，提供了一种反熔丝阵列，包括：呈阵列排布的多个第一反熔丝晶体管和多个第一选择晶体管，所述第一反熔丝晶体管具有第一端和第二端，所述第一选择晶体管具有第一端和第二端，其中，一个第一反熔丝晶体管对应一个第一选择晶体管，每个所述第一选择晶体管的第一端与其对应的所述第一反熔丝晶体管的第二端电连接；多条位线，每条位线对应电连接一列第一选择晶体管的第二端；多条使能信号线，每条使能信号线对应电连接一列第一反熔丝晶体管的第一端，所述使能信号线用于对所述第一反熔丝晶体管进行编程操作。
在一些实施例中，还包括：多个有源区，所述多个有源区排布为多个沿第二方向延伸的有源区行和多个沿第一方向延伸的有源区列，所述第一方向垂直于所述第二方向，每一所述有源区沿所述第一方向延伸；多个第一反熔丝晶体管栅线，多个所述第一反熔丝晶体管栅线相互平行排布且沿第二方向延伸，每一所述第一反熔丝晶体管栅线对应覆盖一个所述有源区行内的多个有源区，以定义阵列排布的多个第一反熔丝晶体管；多个第一选择晶体管栅线，多个所述第一选择晶体管栅线相互平行排布且沿第二方向延伸，每一所述第一选择晶体管栅线对应覆盖一个所述有源区行内的多个有源区，以定义阵列排布的多个第一选择晶体管。
在一些实施例中，还包括：多个第二选择晶体管栅线，多个所述第二选择晶体管栅线相互平行排布且沿第二方向延伸，每一所述第二选择晶体管栅线对应覆盖一个所述有源区行内的多个有源区，以定义阵列排布的多个第二选择晶体管；多个第二反熔丝晶体管栅线，多个所述第二反熔丝晶体管栅线相互平行排布且沿第二方向延伸，每一所述第二反熔丝晶体管栅线对应覆盖一个所述有源区行内的多个有源区，以定义阵列排布的多个第二反熔丝晶体管。
在一些实施例中，多条所述使能信号线沿第二方向排布且沿所述第一方向延伸，其中，每条所述使能信号线和每一所述有源区列在所述第二方向上依次交替排布；多条所述位线相互平行排布且沿所述第一方向延伸，每条位线对应一个有源区列，每条所述位线位于对应的每一所述有源区列的上方。
根据本公开实施例的第三方面，提供了一种反熔丝阵列的操作方法，包括：
提供如上述实施例中任一项所述的反熔丝阵列；对所述反熔丝阵列执行编程操作或读取操作。
在一些实施例中，所述编程操作包括：选择待编程的反熔丝晶体管，在待编程的反熔丝晶体管栅线施加第一电压，将其他反熔丝晶体管栅线悬空；将所有的选择晶体管栅线悬空；在与待编程的反熔丝晶体管电连接的使能信号线施加第二电压；其中，所述第一电压与所述第二电压的差值的绝对值大于所述反熔丝晶体管的栅介质层的击穿电压。
在一些实施例中，所述读取操作包括：选择待读取的反熔丝晶体管，在与待读取的反熔丝晶体管电连接的选择晶体管栅线施加第三电压，将其他选择晶体管栅线悬空；在与待读取的反熔丝晶体管电连接的位线施加第四电压，将其他位线悬空；在待读取的反熔丝晶体管栅线施加第五电压，将其他反熔丝晶体管栅线悬空；将所有的使能信号线悬空；其中，所述第三电压为所述选择晶体管的开启电压，所述第四电压和所述第五电压的差值的绝对值小于所述反熔丝晶体管的栅介质层的击穿电压。
根据本公开实施例的第四方面，提供了一种存储器，包括如上述实施例中任一项所述的反熔丝单元结构。
本公开实施例提供的反熔丝单元结构，增加使能信号线(BE，Blow enable)控制端，使能信号线与反熔丝晶体管一端电连接，反熔丝晶体管的另一端与选择晶体管电连接。如此，在对反熔丝晶体管进行编程操作时，通过使能信号线控制端与反熔丝晶体管栅极的电压差，使得反熔丝晶体管击穿。无需打开选择晶体管，反熔丝晶体管被击穿的高压无需经过选择晶体管，从而防止损伤选择晶体管。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种反熔丝单元结构的电路图；
图2为本公开实施例提供的一种反熔丝单元结构的结构示意图；
图3为本公开实施例提供的另一种反熔丝阵列的电路图；
图4为本公开实施例提供的另一种反熔丝阵列的结构示意图；
图5为本公开实施例提供的一种反熔丝阵列的操作方法的流程示意图。
附图标记：
11-第一反熔丝晶体管；12-第一选择晶体管；13-第二选择晶体管；14-第二反熔丝晶体管；15-使能信号线；16-位线；17-有源区；21-第一反熔丝晶体管栅线；211-第四接触插塞；212-第四连接件；22-第一选择晶体管栅线；221-第五接触插塞；222-第五连接件；23-第二选择晶体管栅线；24-第二反熔丝晶体管栅线；25-第一掺杂区；251-第一接触插塞；252-第一连接件；26-第一共用掺杂区；27-第二共用掺杂区；271-第二接触插塞；272-第二连接件；273-第六接触插塞；28-第三共用掺杂区；29-第二掺杂区；291-第三接触插塞；292-第三连接件。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包 括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
目前，在一般的反熔丝单元结构中，反熔丝晶体管通过选择晶体管与位线电连接，利用位线(BL)与反熔丝晶体管栅极的电压差，使得反熔丝晶体管的薄栅氧化物在高压下被击穿而电阻显著下降，达到编程或写入的目的。但是，当前的架构往往存在失效的风险以及占据芯片面积较大等问题。
基于此，本公开实施例提供了一种反熔丝单元结构，图1为本公开实施例提供的反熔丝单元结构的电路图，图2为本公开实施例提供的反熔丝单元结构的结构示意图。
参见图1和图2，反熔丝单元结构，包括：第一反熔丝晶体管11，第一反熔丝晶体管11具有第一端和第二端；第一选择晶体管12，第一选择晶体管12具有第一端和第二端，第一选择晶体管12的第一端与第一反熔丝晶体管11的第二端电连接；使能信号线15，与第一反熔丝晶体管11的第一端电连接，使能信号线15用于对第一反熔丝晶体管11进行编程操作。在实际应用中，第一选择晶体管12的第二端可以与位线16电连接。
本公开实施例提供的反熔丝单元结构，增加使能信号线(BE，Blow enable)控制端，使能信号线与反熔丝晶体管一端电连接，反熔丝晶体管的另一端与选择晶体管电连接。如此，在对反熔丝晶体管进行编程操作时，通过使能信号线控制端与反熔丝晶体管栅极的电压差，使得反熔丝晶体管击穿。无需打开选择晶体管，反熔丝晶体管被击穿的高压无需经过选择晶体管，从而防止损伤选择晶体管。
在本公开实施例中，第一反熔丝晶体管11的第一端和第二端可以分别为晶体管的第一极和第二极，其中，第一极可以为源极，第二极可以为漏极；或者，第一极可以为漏极，第二极可以为源极。第一选择晶体管12的第一端和第二端可以分别为选择晶体管的第一极和第二极，其中，第一极可以为源极，第二极可以为漏极；或者，第一极可以为漏极，第二极可以为源极。在实际应用中，第一反熔丝晶体管和第一选择晶体管可以包括金属氧化物半导体晶体管(MOS)，例如P型金属氧化物半导体晶体管(PMOS)或N型金属氧化物半导体晶体管(NMOS)等。
在一些实施例中，参见图1和图2，反熔丝单元结构还包括：有源区17，有源区17沿第一方向延伸；第一反熔丝晶体管栅线21，第一反熔丝晶体管栅线21沿第二方向延伸，且覆盖部分有源区17以定义第一反熔丝晶 体管，第一方向与第二方向相交；第一选择晶体管栅线22，第一选择晶体管栅线22沿第二方向延伸，且覆盖部分有源区17以定义第一选择晶体管。在实际应用中，有源区17设置于衬底上，衬底可以是硅、硅锗、锗或其他合适的半导体。第一有源区可以通过掺杂诸如磷、砷、其他n型掺杂剂或其组合的n型掺杂剂来形成N型掺杂区；并且可以通过掺杂诸如硼、铟、其他p型掺杂剂或其组合的p型掺杂剂来形成P型掺杂区，在实际应用中，有源区17可以包括源/漏掺杂区。第一反熔丝晶体管栅线21和第一选择晶体管栅线22的材料包括但不限于多晶硅、氮化钛、金属钨或其组合。第一方向可以和第二方向垂直，这可以进一步提高结构的集成度。
在一些实施例中，参见图1和图2，还包括：第二选择晶体管栅线23，第二选择晶体管栅线23沿第二方向延伸，且覆盖部分有源区17以定义第二选择晶体管13；第二反熔丝晶体管栅线24，第二反熔丝晶体管栅线24沿第二方向延伸，且覆盖部分有源区17以定义第二反熔丝晶体管14。第二选择晶体管栅线23和第二反熔丝晶体管栅线24的材料包括但不限于多晶硅、氮化钛、金属钨或其组合。
在一些实施例中，参见图1和图2，反熔丝单元结构还包括：位线16，与第一选择晶体管12的第二端电连接，位线16位于有源区17上方，且沿第一方向延伸；使能信号线15位于有源区17一侧的上方，使能信号线15与有源区17平行排布且沿第一方向延伸。这里，位线16和使能信号线15的材料包括但不限于钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、多晶硅、掺杂硅、金属硅化物、金属合金或其任何组合。在实际应用中，有源区可以位于衬底中，使能信号线可以位于衬底上的某一金属层中，位线16可以位于衬底上的另一金属层中，该另一金属层可以位于该某一金属层的远离衬底的一侧。位线在衬底平面的正投影与有源区在衬底平面的正投影部分重叠，使能信号线在衬底平面的正投影位于有源区在衬底平面的正投影的一侧。
在一些实施例中，参见图1和图2，反熔丝单元结构还包括：第一掺杂区25和第一共用掺杂区26，分别位于第一反熔丝晶体管栅线21两侧的有源区17内；第一共用掺杂区26和第二共用掺杂区27，分别位于第一选择晶体管栅线22两侧的有源区17内；其中，第二共用掺杂区27与位线16电连接；第一掺杂区25与使能信号线15电连接。第一掺杂区25和第一共用掺杂区26可以分别为第一反熔丝晶体管11的第一端和第二端。第一共用掺杂区26和第二共用掺杂区27可以分别为第一选择晶体管12的第一端和第二端。第一反熔丝晶体管11的第二端和第一选择晶体管12的第一端通过第一共用掺杂区26电连接，减小掺杂区面积，可以提高空间利用率。
在一些实施例中，参见图1和图2，反熔丝单元结构还包括：第二共用掺杂区27和第三共用掺杂区28，分别位于第二选择晶体管栅线23两侧的有源区17内；第三共用掺杂区28和第二掺杂区29，分别位于第二反熔丝 晶体管栅线24两侧的有源区17内；其中，第二掺杂区29与使能信号线15电连接。第二共用掺杂区27和第三共用掺杂区28可以分别为第二选择晶体管13的第一端和第二端。第一选择晶体管的第二端和第二选择晶体管的第一端通过第二共用掺杂区27电连接，可以提高空间利用率。第三共用掺杂区28和第二掺杂区29可以分别为第二反熔丝晶体管14的第一端和第二端。第二选择晶体管的第二端和第二反熔丝晶体管的第一端通过第三共用掺杂区28电连接，可以提高空间利用率。
在实际应用中，第一掺杂区25、第一共用掺杂区26、第二共用掺杂区27、第三共用掺杂区28和第二掺杂区29可以为重掺杂区，可以通过对有源区17进行离子注入的方式形成，各个掺杂区可以具有相同的掺杂浓度，可以均为N型重掺杂，也可以均为P型重掺杂。第一共用掺杂区26为第一反熔丝晶体管11和第一选择晶体管12共同的漏极/源极，第二共用掺杂区27为第一选择晶体管12和第二选择晶体管13共同的漏极/源极，第三共用掺杂区28为第二选择晶体管13和第二反熔丝晶体管14共同的漏极/源极。
在一些实施例中，参见图1和图2，第一反熔丝晶体管栅线沿第一方向上的宽度W1小于或等于第一选择晶体管栅线沿第一方向上的宽度W2；第二反熔丝晶体管栅线沿第一方向上的宽度W4小于或等于第二选择晶体管栅线沿第一方向上的宽度W3。第一反熔丝晶体管栅线、第一选择晶体管栅线、第二选择晶体管栅线和第二反熔丝晶体管栅线可以同时形成，形成工艺包括但不限于各种图案化工艺等。如此，可以有利于掩膜的制备以及降低图案化工艺的难度，同时可以使得提高后续形成反熔丝阵列的均匀性。
可以理解的是，在本公开的实施例中，第一反熔丝晶体管11和第二反熔丝晶体管14均可以具有较小的沟道长度(例如，反熔丝晶体管的第一端和第二端之间具有较大的漏电流，即反熔丝晶体管的第一端和第二端在一定程度上可视为相互导通)，以确保反熔丝晶体管的栅介质层被击穿后，反熔丝晶体管的栅极既与其第一端导通，又与其第二端导通。
在一些实施例中，第一反熔丝晶体管栅线沿第一方向上的宽度W1可以和第二反熔丝晶体管栅线沿第一方向上的宽度W4相等，第一选择晶体管栅线沿第一方向上的宽度W2可以和第二选择晶体管栅线沿第一方向上的宽度W3相等，其中，第一反熔丝晶体管栅线和第一选择晶体管栅线的组合与第二选择晶体管栅线和第二反熔丝晶体管栅线的组合呈轴对称分布。如此，使得第一反熔丝晶体管和第二反熔丝晶体管呈镜像设置，第一选择晶体管和第二选择晶体管呈镜像设置，可以改善后续形成反熔丝阵列的均匀性。
在一些实施例中，参见图1和图2，第一反熔丝晶体管栅线与第一选择晶体管栅线之间的距离为第一距离D1、第二选择晶体管栅线与第二反熔丝晶体管栅线之间的距离为第二距离D2，其中，第一距离D1等于第二距离D2。这可以进一步改善后续形成反熔丝阵列的均匀性。在一些其他实施例 中，第一反熔丝晶体管栅线沿第一方向上的宽度W1、第一选择晶体管栅线沿第一方向上的宽度W2、第二选择晶体管栅线沿第一方向上的宽度W3、第二反熔丝晶体管栅线沿第一方向上的宽度W4、第一距离D1和第二距离D2均相等。
应当理解的是，目前，在一般的反熔丝单元结构中，选择晶体管为厚氧器件，栅极长度较长，需要较大的器件宽度来使得选择晶体管具有足够的电流驱动能力。另外，由于在读取电流路径上存在ND(N型漏区)/PW(P型阱区)的反偏结，为降低读取操作的串联电阻，一般需要在位于反熔丝晶体管栅线下方的衬底内进行掺杂形成反熔丝晶体管离子掺杂区。由于反熔丝晶体管离子掺杂区的掺杂浓度极高，这些掺杂离子可能在高温工艺中扩散到选择晶体管沟道附近，这将显著降低选择晶体管的开启电压，增加漏电。因此反熔丝晶体管栅线与选择晶体管栅线也必须保持较大的距离。从而使得反熔丝单元结构以及反熔丝阵列的面积难以进一步缩小。而本公开实施例提供的反熔丝单元结构，在不需要显著缩减选择晶体管栅线(XG)的长度下，可以缩减选择晶体管栅线的宽度至与反熔丝晶体管栅线(FG)的宽度一致。同时，可以通过降低反熔丝晶体管栅线的宽度，反熔丝晶体管栅线两侧的源漏掺杂区在耗尽层的作用下，将显著降低反偏结势垒，提高读取电流。无需设置反熔丝晶体管离子掺杂区，因此可进一步降低反熔丝晶体管栅线与选择晶体管栅线之间的间距。同时省略了制备反熔丝晶体管离子掺杂区的光罩，降低了芯片制造成本。
在一些实施例中，参见图1和图2，反熔丝单元结构还包括：位于第一掺杂区25上的第一接触插塞251；第一连接件252，使能信号线15通过第一连接件252与第一接触插塞251电连接；位于第二共用掺杂区27上的第二接触插塞271；第二连接件272，位线16通过第二连接件272与第二接触插塞271电连接；位于第二掺杂区29上的第三接触插塞291；第三连接件292，使能信号线15通过第三连接件292与第三接触插塞291电连接。这里，第一连接件252、第二连接件272和第三连接件292可以为同一膜层，也可以为不同膜层。示例性的，例如可以与使能信号线15位于同一金属层中。在一些其他实施例中，反熔丝单元结构还包括：第六接触插塞273，位线16通过第六接触插塞273与第二连接件272电连接。如此，位线16和使能信号线15位于不同的金属层中，避免信号串扰，同时增加布线的灵活性。
在一些实施例中，反熔丝单元结构还包括：第四接触插塞211，第一反熔丝晶体管栅线21通过第四接触插塞211与第四连接件212电连接；第五接触插塞221，第一选择晶体管栅线22通过第五接触插塞221与第五连接件222电连接。第四连接件212和第五连接件222可以为同一膜层，也可以为不同膜层。
本公开实施例还提供了一种反熔丝阵列，图3为本公开实施例提供的 反熔丝阵列的电路图，图4为本公开实施例提供的反熔丝阵列的结构示意图。
参见图3和图4，反熔丝阵列包括：呈阵列排布的多个第一反熔丝晶体管11和多个第一选择晶体管12，第一反熔丝晶体管11具有第一端和第二端，第一选择晶体管12具有第一端和第二端，其中，一个第一反熔丝晶体管11对应一个第一选择晶体管12，每个第一选择晶体管12的第一端与其对应的第一反熔丝晶体管11的第二端电连接；多条位线16，每条位线16对应电连接一列第一选择晶体管12的第二端；多条使能信号线15，每条使能信号线15对应电连接一列第一反熔丝晶体管11的第一端，使能信号线15用于对第一反熔丝晶体管11进行编程操作。在本公开实施例中，第一反熔丝晶体管11的第一端和第二端可以分别为晶体管的第一极和第二极，其中，第一极可以为源极，第二极可以为漏极；或者，第一极可以为漏极，第二极可以为源极。第一选择晶体管12的第一端和第二端可以分别为选择晶体管的第一极和第二极，其中，第一极可以为源极，第二极可以为漏极；或者，第一极可以为漏极，第二极可以为源极。在实际应用中，第一反熔丝晶体管和第一选择晶体管可以包括金属氧化物半导体晶体管(MOS)，例如P型金属氧化物半导体晶体管(PMOS)或N型金属氧化物半导体晶体管(NMOS)等。
在一些实施例中，参见图3和图4，反熔丝阵列还包括：多个有源区17，多个有源区17排布为多个沿第二方向延伸的有源区行R和多个沿第一方向延伸的有源区列C，第一方向垂直于第二方向，每一有源区17沿第一方向延伸；多个第一反熔丝晶体管栅线21，多个第一反熔丝晶体管栅线21相互平行排布且沿第二方向延伸，每一第一反熔丝晶体管栅线21对应覆盖一个有源区行R内的多个有源区17，以定义阵列排布的多个第一反熔丝晶体管11；多个第一选择晶体管栅线22，多个第一选择晶体管栅线22相互平行排布且沿第二方向延伸，每一第一选择晶体管栅线22对应覆盖一个有源区行R内的多个有源区17，以定义阵列排布的多个第一选择晶体管12。在实际应用中，有源区17设置于衬底上，衬底可以是硅、硅锗、锗或其他合适的半导体。第一有源区可以通过掺杂诸如磷、砷、其他n型掺杂剂或其组合的n型掺杂剂来形成N型掺杂区；并且可以通过掺杂诸如硼、铟、其他p型掺杂剂或其组合的p型掺杂剂来形成P型掺杂区，在实际应用中，有源区17可以包括源/漏掺杂区。第一反熔丝晶体管栅线21和第一选择晶体管栅线22的材料包括但不限于多晶硅、氮化钛、金属钨或其组合。第一方向可以和第二方向垂直，这可以进一步提高结构的集成度。
在一些实施例中，参见图3和图4，反熔丝阵列还包括：多个第二选择晶体管栅线23，多个第二选择晶体管栅线23相互平行排布且沿第二方向延伸，每一第二选择晶体管栅线23对应覆盖一个有源区行R内的多个有源区17，以定义阵列排布的多个第二选择晶体管13；多个第二反熔丝晶体管栅 线24，多个第二反熔丝晶体管栅线24相互平行排布且沿第二方向延伸，每一第二反熔丝晶体管栅线24对应覆盖一个有源区行R内的多个有源区17，以定义阵列排布的多个第二反熔丝晶体管14。第二选择晶体管栅线23和第二反熔丝晶体管栅线24的材料包括但不限于多晶硅、氮化钛、金属钨或其组合。
在一些实施例中，参见图3和图4，多条使能信号线15沿第二方向排布且沿第一方向延伸，其中，每条使能信号线15和每一有源区列C在第二方向上依次交替排布；多条位线16相互平行排布且沿第一方向延伸，每条位线16对应一个有源区列C，每条位线16位于对应的每一有源区列C的上方。这里，位线16和使能信号线15的材料包括但不限于钨(W)、铜(Cu)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、多晶硅、掺杂硅、金属硅化物、金属合金或其任何组合。在实际应用中，有源区可以位于衬底中，使能信号线可以位于M0金属层中，位线16可以位于M1金属层中。每条位线16在衬底平面的正投影与有源区列C在衬底平面的正投影部分重叠。
在一些实施例中，反熔丝阵列包括上述任一项的反熔丝单元结构。
在一些实施例中，参见图1至图4，反熔丝阵列还包括：第一掺杂区25和第一共用掺杂区26，分别位于第一反熔丝晶体管栅线21两侧的有源区17内；第一共用掺杂区26和第二共用掺杂区27，分别位于第一选择晶体管栅线22两侧的有源区17内；其中，第二共用掺杂区27与位线16电连接；第一掺杂区25与使能信号线15电连接。
在一些实施例中，参见图1至图4，反熔丝阵列还包括：第二共用掺杂区27和第三共用掺杂区28，分别位于第二选择晶体管栅线23两侧的有源区17内；第三共用掺杂区28和第二掺杂区29，分别位于第二反熔丝晶体管栅线24两侧的有源区17内；其中，第二掺杂区29与使能信号线15电连接。
在一些实施例中，参见图1至图4，第一反熔丝晶体管栅线沿第一方向上的宽度W1小于或等于第一选择晶体管栅线沿第一方向上的宽度W2；第二反熔丝晶体管栅线沿第一方向上的宽度W4小于或等于第二选择晶体管栅线沿第一方向上的宽度W3。如此，可以有利于掩膜的制备以及降低图案化工艺的难度，同时可以使得提高反熔丝阵列的均匀性。
在一些实施例中，参见图1至图4，第一反熔丝晶体管栅线沿第一方向上的宽度W1可以和第二反熔丝晶体管栅线沿第一方向上的宽度W4相等，第一选择晶体管栅线沿第一方向上的宽度W2可以和第二选择晶体管栅线沿第一方向上的宽度W3相等，其中，第一反熔丝晶体管栅线和第一选择晶体管栅线的组合与第二选择晶体管栅线和第二反熔丝晶体管栅线的组合呈轴对称分布。如此，使得第一反熔丝晶体管和第二反熔丝晶体管呈镜像设置，第一选择晶体管和第二选择晶体管呈镜像设置，可以改善后续形成反熔丝阵列的均匀性。
在一些实施例中，参见图1至图4，第一反熔丝晶体管栅线与第一选择晶体管栅线之间的距离为第一距离D1、第二选择晶体管栅线与第二反熔丝晶体管栅线之间的距离为第二距离D2，其中，第一距离D1等于第二距离D2。这可以进一步改善反熔丝阵列的均匀性。
在一些实施例中，参见图1至图4，反熔丝阵列还包括：位于第一掺杂区25上的第一接触插塞251；第一连接件252，使能信号线15通过第一连接件252与第一接触插塞251电连接；位于第二共用掺杂区27上的第二接触插塞271；第二连接件272，位线16通过第二连接件272与第二接触插塞271电连接；位于第二掺杂区29上的第三接触插塞291；第三连接件292，使能信号线15通过第三连接件292与第三接触插塞291电连接。如此，位线16和使能信号线15位于不同的金属层中，避免信号串扰，同时增加布线的灵活性。
本公开实施例还提供了一种反熔丝阵列的操作方法，如图5所示，包括：
步骤501：提供如上述实施例中任一项的反熔丝阵列；
步骤502：对反熔丝阵列执行编程操作或读取操作。
下面结合具体实施例对本公开实施例提供的反熔丝阵列的操作方法再作进一步详细的说明。
首先，参见图3和图4，执行步骤501，提供如上述实施例中任一项的反熔丝阵列。
接着，执行步骤502，对反熔丝阵列执行编程操作或读取操作。
在一些实施例中，编程操作包括：选择待编程的反熔丝晶体管，在待编程的反熔丝晶体管栅线施加第一电压，将其他反熔丝晶体管栅线悬空；将所有的选择晶体管栅线悬空；在与待编程的反熔丝晶体管电连接的使能信号线施加第二电压；其中，第一电压与第二电压的差值的绝对值大于或等于反熔丝晶体管的栅介质层的击穿电压(也即，反熔丝晶体管的栅介质层能够被击穿)。这里，栅介质层例如可以为氧化物层。
例如，结合图4，首先，选择待编程的反熔丝晶体管。示例性的，例如待编程的反熔丝晶体管位于第一列第一行的有源区上。在一些实施例中，待编程的反熔丝晶体管包括第一反熔丝晶体管和第二反熔丝晶体管至少之一，在进行编程操作时，可以对其中的至少一个完成熔断，即可完成二者的单独编程或同步编程。
接着，结合图4，在待编程的反熔丝晶体管栅线施加第一电压，将其他反熔丝晶体管栅线悬空或者置为零电压，同时，在与待编程的反熔丝晶体管电连接的使能信号线施加第二电压。例如，在覆盖第一列第一行的有源区上的反熔丝晶体管栅线施加第一电压，并将其他反熔丝晶体管栅线悬空或者置为零电压,同时，在位于第一列第一行的有源区一侧的使能信号线施加第二电压。以反熔丝晶体管的栅介质层的击穿电压为6V为例，第一电压 例如可以为6V，第二电压例如可以为0V，第一电压与第二电压的差值能够击穿反熔丝晶体管的栅介质层，使得反熔丝晶体管被击穿。在一些实施例中，反熔丝晶体管栅线包括第一反熔丝晶体管栅线和第二反熔丝晶体管栅线。可以在第一反熔丝晶体管栅线和第二反熔丝晶体管栅线至少之一施加第一电压。如此，第一反熔丝晶体管和第二反熔丝晶体管之间其中的一个，或者两个实现熔断，即可完成编程。
在编程过程中，将所有的选择晶体管栅线悬空。结合图4，将所有的第一选择晶体管栅线和第二反熔丝晶体管栅线悬空。如此，所有的选择晶体管呈断开状态。
在一些实施例中，第一电压和第二电压之一可以为正电压，第一电压和第二电压之另一可以为负电压，且第一电压的绝对值小于反熔丝晶体管的栅介质层的击穿电压，第二电压的绝对值也小于反熔丝晶体管的栅介质层的击穿电压。这里，电压的绝对值也称为电压的幅值。示例性的，反熔丝晶体管的栅介质层的击穿电压为6V，第一电压例如可以为5V，第二电压例如可以为-1V，第一电压的幅值为5V小于反熔丝晶体管的栅介质层的击穿电压，第二电压的幅值为-1V小于反熔丝晶体管的栅介质层的击穿电压。而第一电压与第二电压的差值的幅值为6V，能够击穿反熔丝晶体管的栅介质层。如此，防止在待编程的反熔丝晶体管栅线施加第一电压的幅值过高，过高的第一电压可能会对与待编程的反熔丝晶体管位于同一有源区行的其他反熔丝晶体管进行误编程操作。例如，上述误编程操作是指与待编程的反熔丝晶体管位于同一有源区行的其他反熔丝晶体管，由于第一电压的幅值过高，即使在使能信号线悬空的状态，也可能会被击穿。
在一些实施例中，读取操作包括：选择待读取的反熔丝晶体管，在与待读取的反熔丝晶体管电连接的选择晶体管栅线施加第三电压，将其他选择晶体管栅线悬空；在与待读取的反熔丝晶体管电连接的位线施加第四电压，将其他位线悬空；在待读取的反熔丝晶体管栅线施加第五电压，将其他反熔丝晶体管栅线悬空；将所有的使能信号线悬空；其中，第三电压为选择晶体管的开启电压，第四电压和第五电压的差值的绝对值小于反熔丝晶体管的栅介质层的击穿电压。需要说明的是，此处的“开启电压”即为选择晶体管的正常工作电压。
例如，结合图4，首先，选择待读取的反熔丝晶体管。示例性的，例如待读取的反熔丝晶体管位于第一列第一行的有源区上。
接着，在与待读取的反熔丝晶体管电连接的选择晶体管栅线施加第三电压，将其他选择晶体管栅线悬空；在与待读取的反熔丝晶体管电连接的位线施加第四电压，将其他位线悬空；在待读取的反熔丝晶体管栅线施加第五电压，将其他反熔丝晶体管栅线悬空；同时，将所有的使能信号线悬空。例如，在覆盖第一列第一行的有源区上的反熔丝晶体管栅线施加第三电压，并将其他反熔丝晶体管栅线悬空；在位于第一列第一行的有源区上 方的位线施加第四电压，第四电压例如可以为1V；在覆盖第一列第一行的有源区的反熔丝晶体管栅线施加第五电压，第五电压例如可以为0V。这里，第三电压为选择晶体管的开启电压。如此，可以在位线端读取电流，通过电流的大小来判断存储状态，以实现读取操作。
本公开实施例还提供了一种存储器，包括如上述实施例中任一项的反熔丝单元结构。
综上所述，本公开实施例提供的反熔丝单元结构，增加使能信号线(BE，Blow enable)控制端，使能信号线与反熔丝晶体管一端电连接，反熔丝晶体管的另一端与选择晶体管电连接。如此，在对反熔丝晶体管进行编程操作时，通过使能信号线控制端与反熔丝晶体管栅极的电压差，使得反熔丝晶体管击穿。无需打开选择晶体管，反熔丝晶体管被击穿的高压无需经过选择晶体管，从而防止损伤选择晶体管。
需要说明的是，本公开实施例提供的反熔丝单元结构、反熔丝阵列及其操作方法以及存储器可以应用于任何包括该结构的集成电路中。各实施例所记载的技术方案中各技术特征之间，在不冲突的情况下，可以任意组合。本领域技术人员能够对上述形成方法步骤顺序进行变换而并不离开本公开的保护范围，本公开实施例中的各步骤在不冲突的情况下，部分步骤可以同时执行，也可以调用先后顺序执行。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
工业实用性
本公开实施例提供的反熔丝单元结构，增加使能信号线(BE，Blow enable)控制端，使能信号线与反熔丝晶体管一端电连接，反熔丝晶体管的另一端与选择晶体管电连接。如此，在对反熔丝晶体管进行编程操作时，通过使能信号线控制端与反熔丝晶体管栅极的电压差，使得反熔丝晶体管击穿。无需打开选择晶体管，反熔丝晶体管被击穿的高压无需经过选择晶体管，从而防止损伤选择晶体管。

Claims (17)

  1. 一种反熔丝单元结构，包括：
    第一反熔丝晶体管，所述第一反熔丝晶体管具有第一端和第二端；
    第一选择晶体管，所述第一选择晶体管具有第一端和第二端，所述第一选择晶体管的第一端与所述第一反熔丝晶体管的第二端电连接；
    使能信号线，与所述第一反熔丝晶体管的第一端电连接，所述使能信号线用于对所述第一反熔丝晶体管进行编程操作。
  2. 根据权利要求1所述的结构，其中，还包括：
    有源区，所述有源区沿第一方向延伸；
    第一反熔丝晶体管栅线，所述第一反熔丝晶体管栅线沿第二方向延伸，且覆盖部分所述有源区以定义第一反熔丝晶体管，所述第一方向与所述第二方向相交；
    第一选择晶体管栅线，所述第一选择晶体管栅线沿所述第二方向延伸，且覆盖部分所述有源区以定义第一选择晶体管。
  3. 根据权利要求2所述的结构，其中，还包括：
    位线，与所述第一选择晶体管的第二端电连接，所述位线位于所述有源区上方，且沿所述第一方向延伸；
    所述使能信号线位于所述有源区一侧的上方，所述使能信号线与所述有源区平行排布且沿所述第一方向延伸。
  4. 根据权利要求3所述的结构，其中，还包括：
    第一掺杂区和第一共用掺杂区，分别位于所述第一反熔丝晶体管栅线两侧的有源区内；
    第一共用掺杂区和第二共用掺杂区，分别位于所述第一选择晶体管栅线两侧的有源区内；其中，
    所述第二共用掺杂区与所述位线电连接；所述第一掺杂区与所述使能信号线电连接。
  5. 根据权利要求4所述的结构，其中，还包括：
    第二选择晶体管栅线，所述第二选择晶体管栅线沿所述第二方向延伸，且覆盖部分所述有源区以定义第二选择晶体管；
    第二反熔丝晶体管栅线，所述第二反熔丝晶体管栅线沿所述第二方向延伸，且覆盖部分所述有源区以定义第二反熔丝晶体管。
  6. 根据权利要求5所述的结构，其中，还包括：
    第二共用掺杂区和第三共用掺杂区，分别位于所述第二选择晶体管栅线两侧的有源区内；
    第三共用掺杂区和第二掺杂区，分别位于第二反熔丝晶体管栅线两侧的有源区内；其中，
    所述第二掺杂区与所述使能信号线电连接。
  7. 根据权利要求6所述的结构，其中，
    所述第一反熔丝晶体管栅线沿第一方向上的宽度小于或等于所述第一选择晶体管栅线沿第一方向上的宽度；
    所述第二反熔丝晶体管栅线沿第一方向上的宽度小于或等于所述第二选择晶体管栅线沿第一方向上的宽度。
  8. 根据权利要求7所述的结构，其中，
    所述第一反熔丝晶体管栅线沿第一方向上的宽度等于所述第二反熔丝晶体管栅线沿第一方向上的宽度、所述第一选择晶体管栅线沿第一方向上的宽度等于所述第二选择晶体管栅线沿第一方向上的宽度，其中，所述第一反熔丝晶体管栅线和所述第一选择晶体管栅线的组合与所述第二选择晶体管栅线和所述第二反熔丝晶体管栅线的组合呈轴对称分布。
  9. 根据权利要求6所述的结构，其中，还包括：
    位于所述第一掺杂区上的第一接触插塞；
    第一连接件，所述使能信号线通过所述第一连接件与所述第一接触插塞电连接；
    位于所述第二共用掺杂区上的第二接触插塞；
    第二连接件，所述位线通过所述第二连接件与所述第二接触插塞电连接；
    位于所述第二掺杂区上的第三接触插塞；
    第三连接件，所述使能信号线通过所述第三连接件与所述第三接触插塞电连接。
  10. 一种反熔丝阵列，包括：
    呈阵列排布的多个第一反熔丝晶体管和多个第一选择晶体管，所述第一反熔丝晶体管具有第一端和第二端，所述第一选择晶体管具有第一端和第二端，其中，一个第一反熔丝晶体管对应一个第一选择晶体管，每个所述第一选择晶体管的第一端与其对应的所述第一反熔丝晶体管的第二端电连接；
    多条位线，每条位线对应电连接一列第一选择晶体管的第二端；
    多条使能信号线，每条使能信号线对应电连接一列第一反熔丝晶体管的第一端，所述使能信号线用于对所述第一反熔丝晶体管进行编程操作。
  11. 根据权利要求10所述的反熔丝阵列，其中，还包括：
    多个有源区，所述多个有源区排布为多个沿第二方向延伸的有源区行和多个沿第一方向延伸的有源区列，所述第一方向垂直于所述第二方向，每一所述有源区沿所述第一方向延伸；
    多个第一反熔丝晶体管栅线，多个所述第一反熔丝晶体管栅线相互平行排布且沿第二方向延伸，每一所述第一反熔丝晶体管栅线对应覆盖一个所述有源区行内的多个有源区，以定义阵列排布的多个第一反熔丝晶体管；
    多个第一选择晶体管栅线，多个所述第一选择晶体管栅线相互平行排 布且沿第二方向延伸，每一所述第一选择晶体管栅线对应覆盖一个所述有源区行内的多个有源区，以定义阵列排布的多个第一选择晶体管。
  12. 根据权利要求11所述的反熔丝阵列，其中，还包括：
    多个第二选择晶体管栅线，多个所述第二选择晶体管栅线相互平行排布且沿第二方向延伸，每一所述第二选择晶体管栅线对应覆盖一个所述有源区行内的多个有源区，以定义阵列排布的多个第二选择晶体管；
    多个第二反熔丝晶体管栅线，多个所述第二反熔丝晶体管栅线相互平行排布且沿第二方向延伸，每一所述第二反熔丝晶体管栅线对应覆盖一个所述有源区行内的多个有源区，以定义阵列排布的多个第二反熔丝晶体管。
  13. 根据权利要求12所述的反熔丝阵列，其中，
    多条所述使能信号线沿第二方向排布且沿所述第一方向延伸，其中，每条所述使能信号线和每一所述有源区列在所述第二方向上依次交替排布；
    多条所述位线相互平行排布且沿所述第一方向延伸，每条位线对应一个有源区列，每条所述位线位于对应的每一所述有源区列的上方。
  14. 一种反熔丝阵列的操作方法，包括：
    提供如权利要求10-13任一项所述的反熔丝阵列；
    对所述反熔丝阵列执行编程操作或读取操作。
  15. 根据权利要求14所述的操作方法，其中，所述编程操作包括：
    选择待编程的反熔丝晶体管，在待编程的反熔丝晶体管栅线施加第一电压，将其他反熔丝晶体管栅线悬空；
    将所有的选择晶体管栅线悬空；
    在与待编程的反熔丝晶体管电连接的使能信号线施加第二电压；其中，
    所述第一电压与所述第二电压的差值的绝对值大于所述反熔丝晶体管的栅介质层的击穿电压。
  16. 根据权利要求14所述的操作方法，其中，所述读取操作包括：
    选择待读取的反熔丝晶体管，在与待读取的反熔丝晶体管电连接的选择晶体管栅线施加第三电压，将其他选择晶体管栅线悬空；
    在与待读取的反熔丝晶体管电连接的位线施加第四电压，将其他位线悬空；
    在待读取的反熔丝晶体管栅线施加第五电压，将其他反熔丝晶体管栅线悬空；
    将所有的使能信号线悬空；其中，
    所述第三电压为所述选择晶体管的开启电压，所述第四电压和所述第五电压的差值的绝对值小于所述反熔丝晶体管的栅介质层的击穿电压。
  17. 一种存储器，包括如权利要求1-9中任一项所述的反熔丝单元结构。
PCT/CN2022/105661 2022-07-04 2022-07-14 反熔丝单元结构、反熔丝阵列及其操作方法以及存储器 WO2024007360A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/295,839 US12277981B2 (en) 2022-07-04 2023-04-04 Anti-fuse cell structure, anti-fuse array, operation method for anti-fuse array, and memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210786964.8 2022-07-04
CN202210786964.8A CN117409838A (zh) 2022-07-04 2022-07-04 反熔丝单元结构、反熔丝阵列及其操作方法以及存储器

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/295,839 Continuation US12277981B2 (en) 2022-07-04 2023-04-04 Anti-fuse cell structure, anti-fuse array, operation method for anti-fuse array, and memory

Publications (1)

Publication Number Publication Date
WO2024007360A1 true WO2024007360A1 (zh) 2024-01-11

Family

ID=89454624

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/105661 WO2024007360A1 (zh) 2022-07-04 2022-07-14 反熔丝单元结构、反熔丝阵列及其操作方法以及存储器

Country Status (2)

Country Link
CN (1) CN117409838A (zh)
WO (1) WO2024007360A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101595723A (zh) * 2006-11-16 2009-12-02 普廷数码影像控股公司 提供与像素阵列相关联的存储器单元的方法、设备和系统
US20160141049A1 (en) * 2014-11-18 2016-05-19 SK Hynix Inc. Anti-fuse type one-time programmable memory cell array and method of operating the same
CN107785053A (zh) * 2015-09-10 2018-03-09 力旺电子股份有限公司 存储器单元及存储器阵列
CN113496988A (zh) * 2020-04-08 2021-10-12 长鑫存储技术有限公司 反熔丝单元及反熔丝阵列

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101595723A (zh) * 2006-11-16 2009-12-02 普廷数码影像控股公司 提供与像素阵列相关联的存储器单元的方法、设备和系统
US20160141049A1 (en) * 2014-11-18 2016-05-19 SK Hynix Inc. Anti-fuse type one-time programmable memory cell array and method of operating the same
CN107785053A (zh) * 2015-09-10 2018-03-09 力旺电子股份有限公司 存储器单元及存储器阵列
CN113496988A (zh) * 2020-04-08 2021-10-12 长鑫存储技术有限公司 反熔丝单元及反熔丝阵列

Also Published As

Publication number Publication date
CN117409838A (zh) 2024-01-16

Similar Documents

Publication Publication Date Title
US10347646B2 (en) Anti-fuse cell structure including reading and programming devices with different gate dielectric thickness
TWI518849B (zh) 包含具有反熔絲組件之非揮發性記憶體結構之電子器件及其形成方法
US10127993B2 (en) Dielectric fuse memory circuit and operation method thereof
US20150062998A1 (en) Programmable memory
TWI528501B (zh) 包含具有反熔絲組件之非揮發性記憶體結構之電子器件及其形成方法
TW201803079A (zh) 半導體裝置
CN104347637B (zh) 反熔丝单次可编程存储胞及存储器的操作方法
KR20180061475A (ko) 3차원 반도체 장치
CN106057810A (zh) 反熔丝存储单元及其阵列
TW201638963A (zh) 具有電熔絲的半導體裝置和用於製造其之方法
US20080036033A1 (en) One-time programmable memory
CN107492553B (zh) 三晶体管otp存储器单元
TW202213370A (zh) 小面積低電壓反熔絲元件與陣列
US20250014661A1 (en) Bit cell structure for one-time-programming
WO2024007360A1 (zh) 反熔丝单元结构、反熔丝阵列及其操作方法以及存储器
US9318532B2 (en) Semiconductor memory device
US12277981B2 (en) Anti-fuse cell structure, anti-fuse array, operation method for anti-fuse array, and memory
TWI597827B (zh) 非揮發性半導體記憶裝置
US12376293B2 (en) Anti-fuse array structure, operation method thereof and memory
US20230363152A1 (en) Anti-fuse array structure, operation method thereof and memory
TWI863332B (zh) 一種反熔絲陣列結構及其操作方法以及記憶體
US6198137B1 (en) Semiconductor device
WO2025060622A1 (zh) 可编程器件、可编程器件阵列及操作方法、存储器
WO2024174395A1 (zh) 反熔丝器及制作方法、反熔丝阵列及操作方法
WO2024007394A1 (zh) 半导体结构、存储器及其操作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22949940

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22949940

Country of ref document: EP

Kind code of ref document: A1