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WO2024174395A1 - 反熔丝器及制作方法、反熔丝阵列及操作方法 - Google Patents

反熔丝器及制作方法、反熔丝阵列及操作方法 Download PDF

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Publication number
WO2024174395A1
WO2024174395A1 PCT/CN2023/094538 CN2023094538W WO2024174395A1 WO 2024174395 A1 WO2024174395 A1 WO 2024174395A1 CN 2023094538 W CN2023094538 W CN 2023094538W WO 2024174395 A1 WO2024174395 A1 WO 2024174395A1
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WIPO (PCT)
Prior art keywords
doping region
fuse
connection terminal
column
selection line
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Application number
PCT/CN2023/094538
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English (en)
French (fr)
Inventor
丁丽
Original Assignee
长鑫存储技术有限公司
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Publication of WO2024174395A1 publication Critical patent/WO2024174395A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Definitions

  • the present disclosure is based on the Chinese patent application with application number 202310182691.0, application date February 24, 2023, and application name “Anti-fuse unit and manufacturing method, anti-fuse array and operation method”, and claims the priority of the Chinese patent application.
  • the entire content of the Chinese patent application is hereby introduced into the present disclosure as a reference.
  • the present disclosure relates to, but is not limited to, an antifuse and a manufacturing method thereof, an antifuse array and an operating method thereof.
  • One Time Programmable (OTP) memory is a non-volatile memory that supports one-time programming and is widely used in analog circuits and memory chips.
  • One-time programmable memory is divided into fuse-type devices and anti-fuse devices (Anti-fuse).
  • Anti-fuse devices are currently the more commonly used one-time programmable memory.
  • a first aspect of the present disclosure provides an anti-fuse, comprising:
  • a first connection terminal includes a first doping region and a second doping region disposed below the first doping region, the first doping region and the second doping region have opposite conductivity types, and the first doping region and the second doping region are connected to form a PN junction;
  • the dielectric layer is arranged between the second connection end and the second doping region, and the second connection end and the second doping region are separated by the dielectric layer.
  • a second aspect of the present disclosure provides a method for manufacturing an anti-fuse, the method comprising:
  • a second connection end is formed, extending in a second direction intersecting with the first direction, the second connection end intersecting with the second doped region of the first connection end, and the second connection end and the second doped region are separated by the dielectric layer.
  • a third aspect of the present disclosure provides an anti-fuse array, comprising a plurality of crossed row selection lines and a plurality of column selection lines; and a plurality of anti-fuses arranged at intersections of the row selection lines and the column selection lines;
  • Each of the anti-fuses comprises:
  • a first connection terminal connected to the row selection line comprising a first doping region and a second doping region disposed below the first doping region, the first doping region and the second doping region have opposite conductivity types, and the first doping region and the second doping region are connected to form a PN junction;
  • a second connection end connected to the column selection line and covering at least the second doped region
  • a dielectric layer is provided between the second connection end and the second doping region, and the second connection end and the The second doped region is separated by the dielectric layer.
  • a fourth aspect of the present disclosure provides an operation method of an antifuse array, which is applied to the antifuse array of the third aspect of the present disclosure, and the operation method includes:
  • a programming voltage is applied to a row selection line connected to a selected anti-fuse, and a low voltage is applied to a column selection line connected to the selected anti-fuse, thereby forming a voltage difference between a first connection terminal and a second connection terminal of the selected anti-fuse to break through a dielectric layer, thereby forming a conductive path between a second doped region of the first connection terminal and the second connection terminal.
  • the anti-fuse is composed of only a first connection end, a second connection end and a dielectric layer. There is no need to configure a selection transistor around the anti-fuse, which reduces the size of the anti-fuse and can further reduce the layout area of the anti-fuse.
  • Fig. 1 is a schematic structural diagram of an anti-fuse according to an exemplary embodiment.
  • Fig. 2 is a cross-sectional view of an anti-fuse taken along line A-A according to an exemplary embodiment.
  • FIG. 3 is a top view of an anti-fuse according to an exemplary embodiment.
  • FIG. 4 is a schematic diagram showing an antifuse array according to an exemplary embodiment.
  • FIG. 5 is a cross-sectional view showing a B-B cross section of an antifuse array according to an exemplary embodiment.
  • FIG. 6 is a circuit diagram of an antifuse array according to an exemplary embodiment.
  • FIG. 7 is a circuit diagram showing a target anti-fuse after being programmed according to an exemplary embodiment.
  • FIG. 8 is a flow chart showing a method for manufacturing an anti-fuse according to an exemplary embodiment.
  • FIG. 9 is a flow chart showing a method for manufacturing an antifuse array according to an exemplary embodiment.
  • Fig. 10 is a schematic diagram of a B-B cross section after etching a substrate to form a first column according to an exemplary embodiment.
  • FIG. 11 is a schematic diagram of a B-B cross section after forming a first doping region according to an exemplary embodiment.
  • Fig. 12 is a schematic diagram of a B-B cross section after forming an isolation layer according to an exemplary embodiment.
  • Fig. 13 is a schematic diagram of a B-B cross section after forming a second column according to an exemplary embodiment.
  • FIG14 is a schematic diagram of a B-B cross section after forming a second doping region according to an exemplary embodiment.
  • Fig. 15 is a schematic diagram of a B-B cross section after forming a dielectric layer according to an exemplary embodiment.
  • First connection terminal 2. Second connection terminal; 3. Dielectric layer; 4. First doping region; 5. Second doping region; 6. Substrate; 61. First column; 62. Second column; 7. Isolation layer; 10. Anti-fuse;
  • Antifuse devices are relatively common one-time programmable devices. Antifuse devices are widely used in dynamic random access memory (DRAM) and flash memory (NAND). Antifuse devices include an antifuse structure and a selection transistor.
  • the antifuse structure is a semiconductor device composed of two conductive layers and a dielectric layer between the conductive layers.
  • the selection transistor is a transistor adjacent to the antifuse structure in the memory array.
  • a programming voltage or a programming current is applied to the antifuse structure by turning on the selection transistor.
  • the antifuse device is not programmed, the two conductive layers of the antifuse structure are separated by a dielectric layer so that the two ends of the antifuse structure are open circuited.
  • the dielectric layer in the anti-fuse structure is broken down by the high voltage, so that an electrical connection is formed between the conductive layers on both sides of the dielectric layer.
  • the anti-fuse structure is broken down, and the process of the anti-fuse structure being broken down is physically one-time, permanent, and irreversible.
  • the distance between the anti-fuse structure and the selection transistor cannot be too close. If the distance between the anti-fuse structure and the selection transistor is too close, the performance of the selection transistor will be degraded during the breakdown of the anti-fuse structure, which will affect the reliability of the circuit.
  • the structure of the anti-fuse device causes it to occupy a large area of the memory chip, which is not conducive to improving the storage density of the memory chip and achieving further miniaturization of the memory chip.
  • the exemplary embodiment of the present disclosure provides an anti-fuse, which includes a first connection terminal, a second connection terminal and a dielectric layer.
  • a programming operation of the anti-fuse is performed by applying a programming voltage to the first connection terminal to break through the dielectric layer, and a reading operation of the anti-fuse is completed by reading the potential of the second connection terminal, which eliminates the need to configure a corresponding selection transistor around the anti-fuse, thereby reducing the size of the anti-fuse, and further reducing the layout area of the anti-fuse, providing more available space for the layout of other semiconductor devices.
  • the exemplary embodiment provides an anti-fuse 10, which includes a first connection terminal 1, a second connection terminal 2 and a dielectric layer 3.
  • the first connection terminal 1 includes a first doping region 4 and a second doping region 5 disposed below the first doping region 4, and the first doping region 4 and the second doping region 5 have opposite conductivity types, and the first doping region 4 and the second doping region 5 are connected to form a PN junction; the second connection terminal 2 at least covers the second doping region 5.
  • the dielectric layer 3 is disposed between the second connection terminal 2 and the second doping region 5, and the second connection terminal 2 and the second doping region 5 are separated by the dielectric layer 3.
  • the anti-fuse 10 in this embodiment can be programmed.
  • the following operations can be performed: a programming voltage is applied to the first doped region 4 of the first connection terminal 1, and the programming voltage is higher than the breakdown voltage of the dielectric layer 3.
  • the dielectric layer 3 is broken down by the programming voltage, and a conductive path is correspondingly formed between the first connection terminal 1 and the second connection terminal 2.
  • the current in the first connection terminal 1 can leak into the second connection terminal 2 through the conductive path, and finally the programming operation of the anti-fuse 10 is completed.
  • the following operations can be performed: detecting the current between the second connection terminal 2 and the first connection terminal 1, and completing the read operation on the anti-fuse 10 based on the detected current; or, based on the current in the first connection terminal 1 leaking into the second connection terminal 2, causing the potential of the second connection terminal 2 to change, by detecting the potential of the second connection terminal 2, completing the read operation on the anti-fuse 10 based on the potential of the second connection terminal 2.
  • the anti-fuse device 10 of this embodiment is described in detail below:
  • the first connection terminal 1 is vertically arranged along the first direction D1, and in the first direction D1, the first connection terminal 1 includes a first doping region 4 and a second doping region 5 arranged below the first doping region 4.
  • the first doping region 4 and the second doping region 5 are doped with doping ions of different conductive types, respectively, and a PN junction is formed at the interface between the first doping region 4 and the second doping region 5.
  • the first doping region 4 and the second doping region 5 are equivalent to forming a PN diode in the first connection terminal 1, the first doping region 4 serves as the anode of the PN diode, and the second doping region 5 serves as the cathode of the PN diode.
  • the PN junction is used to block the electric current in the second connection terminal 2. The current is reversely leaked into the first connection terminal 1 through the conductive path, thereby improving the problem of preventing the reading error caused by the reverse leakage of current.
  • the first connection end 1 may include a semiconductor material, such as silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC), such as silicon on insulator (SOI), germanium on insulator (GOI), and other materials with semiconductor properties (III-V group compounds such as gallium arsenide).
  • a semiconductor material such as silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC), such as silicon on insulator (SOI), germanium on insulator (GOI), and other materials with semiconductor properties (III-V group compounds such as gallium arsenide).
  • the first doping region 4 includes a P-type semiconductor material
  • the second doping region 5 includes an N-type semiconductor material.
  • Conductive ions with a P-type conductivity type are implanted into the region where the first doping region 4 of the first connection terminal 1 is located, and then the conductive ions with a P-type conductivity type are activated by performing an annealing process, thereby forming the first doping region 4.
  • Conductive ions with an N-type conductivity type are implanted into the region where the second doping region 5 of the first connection terminal 1 is located, and then an annealing process is performed to activate the conductive ions with an N-type conductivity type, thereby forming the second doping region 5 below the first doping region 4.
  • the first doping region 4 may be a heavily doped region
  • the second doping region 5 may be a lightly doped region, that is, the concentration of conductive ions with P-type conductivity in the first doping region 4 is greater than the concentration of conductive ions with N-type conductivity in the second doping region 5 .
  • the material of the second connection terminal 2 may include a conductive metal.
  • the material of the second connection terminal 2 may include at least one of titanium or its alloy, tantalum or its alloy, and tungsten or its alloy.
  • the dielectric layer 3 has electrical insulation properties.
  • the dielectric layer 3 may include at least one of silicon oxide and high-k (dielectric constant) dielectric materials.
  • the resistance of the dielectric layer 3 is very large, so the first connection terminal 1 and the second connection terminal 2 are separated by the dielectric layer 3.
  • the resistance of the broken-down area of the dielectric layer 3 decreases, which corresponds to the formation of a conductive path between the second connection terminal 2 and the second doped region 5 of the first connection terminal 1.
  • the first connection terminal 1 and the second connection terminal 2 are electrically connected, and the current in the first connection terminal 1 can leak into the second connection terminal 2 through the conductive path, which will cause the potential of the second connection terminal to change.
  • the programming state of the anti-fuse 10 (specifically, the unprogrammed state or the programmed state) can be determined by detecting the current of the second connection terminal 2 or the potential of the second connection terminal 2.
  • the dielectric layer 3 surrounds and continuously covers the second doped region 5
  • the second connection terminal 2 surrounds and continuously covers the dielectric layer 3.
  • the circumferential surface of the second doped region 5 is covered by the dielectric layer 3, and the dielectric layer 3 is arranged between the second connection terminal 2 and the circumferential surface of the second doped region 5.
  • the second doped region 5 and the dielectric layer 3 have a larger contact area. Therefore, when the anti-fuse 10 is programmed, the dielectric layer 3 is more easily broken down, which reduces the programming difficulty of the anti-fuse 10 and improves the programming efficiency.
  • a radial dimension of the first doping region 4 is smaller than a radial dimension of the second doping region 5 , and a projection of the first doping region 4 on the second doping region 5 falls within the second doping region 5 .
  • the anti-fuse 10 of the present embodiment further includes an isolation layer 7 covering the first doping region 4.
  • the material of the isolation layer 7 may include at least one of silicon oxide, silicon nitride or silicon oxynitride. Based on the good electrical isolation effect of the isolation layer 7, the isolation layer 7 covering the first doping region 4 can avoid the bridge between the anti-fuse 10 and the semiconductor device adjacent thereto from short-circuiting, which is conducive to further improving the working performance and service life of the anti-fuse 10.
  • the first connection terminal 1 is connected to the row selection line 100
  • the second connection terminal 2 is connected to the column selection line 200
  • the row selection line 100 and the column selection line 200 extend in different directions
  • the row selection line 100 and the column selection line 200 are cross-connected.
  • the anti-fuse 10 is disposed at the intersection of the row selection line 100 and the column selection line 200, that is, the row selection line 100 and the column selection line 200 are connected through the anti-fuse 10.
  • the row selection line 100 and the column selection line 200 may intersect obliquely or perpendicularly.
  • this exemplary embodiment provides an antifuse array, referring to FIGS. 4 and 5,
  • the fuse array includes a plurality of row selection lines 100 and a plurality of column selection lines 200 that cross each other, and a plurality of antifuses 10 disposed at intersections of the row selection lines 100 and the column selection lines 200 .
  • each anti-fuse 10 includes a first connection terminal 1, a second connection terminal 2 and a dielectric layer 3.
  • the first connection terminal 1 is connected to the row selection line 100, and the first connection terminal 1 includes a first doping region 4 and a second doping region 5 disposed below the first doping region 4.
  • the first doping region 4 and the second doping region 5 have opposite conductivity types, and the first doping region 4 and the second doping region 5 are connected to form a PN junction.
  • the second connection terminal 2 is connected to the column selection line 200, and the second connection terminal 2 at least covers the second doping region 5.
  • the dielectric layer 3 is disposed between the second connection terminal 2 and the second doping region 5 to separate the second connection terminal 2 and the second doping region 5.
  • the anti-fuse array in this embodiment is set in a DRAM architecture
  • the row selection line 100 is connected to the word line (Word Line, WL) in the DRAM architecture
  • the column selection line 200 is connected to the bit line (Bit Line, BL) in the DRAM architecture.
  • the first connection terminal 1 of the anti-fuse 10 is connected to the gate of the word line
  • the second connection terminal 2 of the anti-fuse 10 is connected to the bit line.
  • the row selection line 100 and the column selection line 200 intersect vertically.
  • the row selection line 100 extends along the first direction D1, and a plurality of row selection lines 100 are independently arranged, and the plurality of row selection lines 100 are arranged at intervals along the second direction D2 and the third direction D3.
  • the column selection line 200 extends along the second direction D2, and a plurality of column selection lines 200 are arranged at intervals along the third direction D3.
  • the second direction D2 and the third direction D3 are located in the same plane, the second direction D2 and the third direction D3 are perpendicular, and the first direction D1 is perpendicular to the plane where the second direction D2 and the third direction D3 are located.
  • the design scheme in which the anti-fuse 10 is arranged at the intersection of the row selection line 100 and the column selection line 200 can improve the integration of the anti-fuse array 10, so that more anti-fuses 10 can be arranged per unit area of the anti-fuse array.
  • the anti-fuse array of the present embodiment When the anti-fuse array of the present embodiment performs programming operation on the selected anti-fuse 10, a programming voltage is applied to the row selection line 100 (hereinafter referred to as the selected row selection line 100) connected to the selected anti-fuse 10, and a low voltage is applied to the column selection line 200 (hereinafter referred to as the selected column selection line 200) connected to the selected anti-fuse 10, and half of the programming voltage is applied to the remaining unselected column selection lines 200 (it can be understood that the purpose of applying half of the programming voltage to the unselected column selection lines 200 is to prevent the selected row selection line 100 from breaking through the unselected anti-fuse 10. In actual applications, one-third of the programming voltage, one-quarter of the programming voltage, etc. can be applied to the unselected column selection lines 200), and the remaining unselected row selection lines 100 in the anti-fuse array can be floated.
  • the potential of the selected column selection line 200 is pulled down to a low potential of 0, and then a detection voltage is applied to the selected row selection line 100, so that the selected row selection line 100 is at a high potential of 1, and the detection voltage is lower than the breakdown voltage of the dielectric layer 3. Then, the state in which the potential of the selected column selection line 200 is pulled down to a low potential of 0 is released, so that the selected column selection line 200 can continue to receive leakage current from the selected row selection line 100.
  • the current in the first connection terminal 1 of the selected anti-fuse 10 leaks to the second connection terminal 2 through the conductive path and is stored in the second connection terminal 2, which causes the potential of the second connection terminal 2 of the selected anti-fuse 10 to rise.
  • the potential value of the second connection terminal 2 of the selected anti-fuse 10 is read, and the programming state of the selected anti-fuse 10 is determined according to the potential value of the second connection terminal 2. If the selected anti-fuse 10 is in a programmed state, the potential value of the second connection terminal 2 of the selected anti-fuse 10 is a high potential 1. If the selected anti-fuse 10 is in an unprogrammed state, the potential value of the second connection terminal 2 of the selected anti-fuse 10 is a low potential 0.
  • a conductive path is formed between the first connection terminal 1 and the second connection terminal 2, so that the current leakage in the first connection terminal 1 can leak into the second connection terminal 2 through the conductive path, causing the potential of the second connection terminal 2 to rise.
  • the potential of the second connection terminal 2 may be higher than the potential of the first connection terminal 1, which will cause the current in the second connection terminal 2 to The reverse leakage to the first connection terminal 1 is caused through the conductive path, thereby causing an inaccurate detection result obtained by detecting the potential of the second connection terminal 2, thereby causing a reading error.
  • the first connection end 1 of each anti-fuse 10 includes a first doping region 4 and a second doping region 5 of opposite conductivity types, and the first doping region 4 and the second doping region 5 form a PN junction in the first connection end 1, which is equivalent to setting a PN diode at the connection intersection of the row selection line 100 and the column selection line 200.
  • the first doping region 4 corresponds to the anode of the PN diode
  • the second doping region 5 corresponds to the cathode of the PN diode.
  • the row selection line 100 and the column selection line 200 are connected through the PN diode, which can avoid the problem that the current in the second connection end 2 leaks back to the first connection end 1 through the conductive path due to the potential value of the second connection end 2 being higher than the potential value of the first connection end 1, and the current of the second connection end 2 drops to a low potential, thereby ensuring the accuracy of the reading result when the selected anti-fuse 10 is read, avoiding erroneous reading, and further ensuring that when the second connection end 2 is detected to perform a read operation, an accurate detection result can be obtained according to the potential of the second connection end 2.
  • the first doping region 4 includes a P-type semiconductor material
  • the second doping region 5 includes an N-type semiconductor material.
  • the first doping region 4 can be a heavily doped region
  • the second doping region 5 can be a lightly doped region, that is, the concentration of conductive ions with P-type conductivity in the first doping region 4 is greater than the concentration of conductive ions with N-type conductivity in the second doping region 5.
  • the dielectric layer 3 surrounds and continuously covers the second doping region 5
  • the second connection end 2 surrounds and continuously covers the dielectric layer 3 .
  • a radial dimension of the first doping region 4 is smaller than a radial dimension of the second doping region 5 , and a projection of the first doping region 4 on the second doping region 5 falls within the second doping region 5 .
  • the exemplary embodiment provides a storage device, which includes the anti-fuse array in the above embodiment, wherein the anti-fuse array is a one-time programmable memory.
  • this exemplary embodiment provides an operation method of an antifuse array, which is applied to the antifuse array of the above embodiment, and the operation method includes the following steps:
  • S1 Apply a programming voltage to the row selection line connected to the selected anti-fuse, and at the same time apply a low voltage to the column selection line connected to the selected anti-fuse, so as to form a voltage difference between the first connection terminal and the second connection terminal of the selected anti-fuse to break through the dielectric layer, and form a conductive path between the second doped region of the first connection terminal and the second connection terminal.
  • the voltage difference between the first connection terminal and the second connection terminal is greater than the breakdown voltage of the dielectric layer.
  • the circuit of the antifuse array of the present embodiment is shown in FIG6 .
  • the circuit of the antifuse array of the present embodiment includes an antifuse array, the antifuse array includes a column selection line 200-0, a column selection line 200-1 and a column selection line 200-2 arranged in parallel, and the antifuse array also includes a row selection line 100-0 and a row selection line 100-1 arranged in parallel, the row selection line 100-0 and the row selection line 100-1 are respectively connected to the column selection line 200-0, the column selection line 200-1 and the column selection line 200-2.
  • the anti-fuse array also includes anti-fuses 10-0 to anti-fuses 10-5, anti-fuses 10-0 to anti-fuses 10-2 are respectively arranged at the intersections of the row selection line 100-0 and the column selection line 200-0, the column selection line 200-1 and the column selection line 200-2, and anti-fuses 10-3 to anti-fuses 10-5 are respectively arranged at the intersections of the row selection line 100-1 and the column selection line 200-0, the column selection line 200-1 and the column selection line 200-2.
  • the antifuse array may further include a programming control module (not shown in the figure), and a programming current is provided to the antifuse array through the programming control module.
  • a programming voltage (high voltage) is applied to the row selection line 100-0 through the programming control module, a low voltage is applied to the column selection line 200-0, and half of the programming voltage is applied to the column selection line 200-1 and the column selection line 200-2, so that the row selection line 100-1 is floated.
  • the programming voltage applied to the row selection line 100-0 may be approximately 4V to 6V, for example, the programming voltage applied to the row selection line 100-0 is 5V, and the voltage applied to the column selection line 200-1 and the column selection line 200-2 is 2.5V.
  • the column selection line 200-0 may be grounded, and the low potential of the column selection line 200-0 is 0V.
  • a voltage difference is formed between the first connection terminal 1 (refer to FIG. 5 ) and the second connection terminal 2 (refer to FIG. 5 ) of the anti-fuse 10-0 to break down the dielectric layer 3 (refer to FIG. 5 ), and a conductive path is formed between the first connection terminal 1 (refer to FIG. 5 ) and the second connection terminal 2 (refer to FIG. 5 ), thereby completing the programming operation of the anti-fuse 10-0.
  • the circuit of the anti-fuse array is shown in FIG. 7 .
  • the operation method further includes the following steps:
  • the potential of the column selection line 200 - 0 is pulled down to a low potential 0.
  • S3 A detection voltage is applied to the row selection line to which the selected anti-fuse is connected, and then the state in which the potential of the column selection line is pulled down to a low potential is released.
  • a detection voltage is applied to the row selection line 100-0, which is lower than the programming voltage, so that the row selection line 100-0 is at a high potential 1.
  • the detection voltage applied to the row selection line 100-0 may be about 2V to 3V, for example, 2.5V.
  • the current in the first connection terminal 1 (refer to FIG5) of the anti-fuse 10-0 leaks to the second connection terminal 2 (refer to FIG5) through the conductive path and is stored in the second connection terminal 2 (refer to FIG5), and the potential of the second connection terminal 2 (refer to FIG5) rises.
  • the selected anti-fuse if the potential value of the second connection terminal obtained by reading is a low potential, the selected anti-fuse is in an unprogrammed state; if the potential value of the second connection terminal obtained by reading is a high potential, the selected anti-fuse is in a programmed state.
  • a method for manufacturing an anti-fuse is provided in an exemplary embodiment of the present disclosure, as shown in Figure 8, which shows a flow chart of the method for manufacturing an anti-fuse provided according to an exemplary embodiment of the present disclosure, and Figures 10-15 are schematic diagrams of various stages of the method for manufacturing an anti-fuse.
  • the method for manufacturing an anti-fuse is introduced below in conjunction with Figures 10-15 and with reference to Figures 1-3.
  • the present embodiment does not limit the semiconductor structure.
  • the semiconductor structure will be described below by taking a dynamic random access memory (DRAM) as an example, but the present embodiment is not limited thereto.
  • DRAM dynamic random access memory
  • the semiconductor structure in the present embodiment may also be other structures.
  • a method for manufacturing an anti-fuse provided in an exemplary embodiment of the present disclosure includes the following steps:
  • Step S110 providing a substrate.
  • the substrate 6 includes an intrinsic semiconductor material, which may be silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC); or silicon on insulator (SOI), germanium on insulator (GOI); or other materials with semiconductor properties, such as III-V group compounds such as gallium arsenide.
  • the material of the substrate 6 includes polycrystalline silicon.
  • Step S120 etching and removing a portion of the substrate to form a first column extending along a first direction, and doping the first column with conductive ions having a P-type conductivity type to form a first doped region.
  • a mask (not shown) may be formed on the top surface of the substrate 6 , on which is defined a mask pattern identical to that for forming the first pillar 61 , and a portion of the substrate 6 is etched away according to the mask pattern to form the first pillar 61 , which extends along the first direction D1 .
  • the first pillar 61 is doped with conductive ions having P-type conductivity by an ion implantation process.
  • the conductive ions having P-type conductivity may include one or more of boron ions B 3+ and gallium ions Ga 3+ .
  • the first pillar 61 is annealed to activate the conductive ions with P-type conductivity in the first pillar 61, and form the first doping region 4 in the first pillar 61.
  • the first pillar 61 can be annealed in a thermal annealing device.
  • an isolation layer 7 is formed, and the isolation layer 7 covers the sidewalls and the top surface of the first pillar 61.
  • An isolation material may be deposited by a suitable deposition process, and the isolation material covers the sidewalls of the first pillar 61, the top surface of the first pillar 61 and the exposed top surface of the substrate 6. Then, an anisotropic etching process is used to etch away the isolation material located on the top surface of the substrate 6, and the isolation material covering the sidewalls and the top surface of the first pillar 61 is retained to form the isolation layer 7.
  • Step S130 etching the substrate below the first pillar to form a second pillar below the first pillar.
  • the substrate 6 below the first pillar 61 (see FIG. 10 ) is etched based on the isolation layer 7, and the substrate 6 exposed by the isolation layer 7 is removed to form the second pillar 62.
  • the width of the first pillar 61 is smaller than the width of the second pillar 62, and the projection of the first pillar 61 on the second pillar 62 falls within the second pillar 62.
  • the substrate 6 below the first pillar 61 may be etched by a dry process or a wet process to form a second pillar 62 below the first pillar 61 .
  • Step S140 doping the second column with conductive ions of N-type conductivity to form a second doping region, wherein the first doping region and the second doping region together form a first connection terminal, and the first doping region and the second doping region form a PN junction.
  • an ion implantation process may be used to dope the second pillar 62 with conductive ions having N-type conductivity.
  • the conductive ions having N-type conductivity may include one or more of phosphorus ions P 5+ , arsenic ions As 5+ , and tellurium ions Te 5+ .
  • the second pillar 62 is annealed to activate the conductive ions having N-type conductivity in the second pillar 62, and to form a second doping region 5 in the second pillar 62.
  • the second pillar 62 may be annealed in a thermal annealing device.
  • Step S150 forming a dielectric layer to cover the sidewalls of the second doped region.
  • the second doping region 5 is processed by a thermal oxidation process to form a dielectric layer 3 on the sidewall of the second doping region 5.
  • the material of the dielectric layer 3 includes silicon oxide.
  • Step S160 forming a second connection end extending in a second direction intersecting the first direction, the second connection end intersecting with the second doping region of the first connection end, and the second connection end and the second doping region being separated by a dielectric layer.
  • a suitable deposition process is selected to deposit a conductive material, the conductive material covers the dielectric layer 3 and the isolation layer 7, the conductive material covering the isolation layer 7 is etched away, and the retained conductive material forms the second connection terminal 2, and the material of the second connection terminal 2 may include at least one of metal titanium (Titanium) or its alloy, metal tantalum (Tantalum) or its alloy, and metal tungsten (Tungsten) or its alloy.
  • the method for manufacturing the anti-fuse of the present embodiment forms a first connecting end having a first doped region and a second doped region, wherein the first doped region and the second doped region form a PN junction, and then a dielectric layer and a second connecting end are formed to sequentially cover the second doped region to form an anti-fuse.
  • the programming operation of the anti-fuse can be completed by applying a programming voltage to the first connecting end to break through the dielectric layer. There is no need to additionally configure a selection transistor for the anti-fuse.
  • the anti-fuse formed in the present embodiment includes only one semiconductor device, which reduces the size of the anti-fuse and provides more available space for the semiconductor structure.
  • FIG. 9 shows a flow chart of a method for manufacturing an antifuse array according to an exemplary embodiment of the present disclosure. As shown in FIG. 9 , a method for manufacturing an antifuse array provided in this exemplary embodiment includes the following steps:
  • Step S210 providing a substrate.
  • the substrate 6 provided in this embodiment is the same as the substrate provided in step S110 in the above embodiment, and will not be described again herein.
  • Step S220 etching and removing a portion of the substrate to form a plurality of independently arranged first pillars, wherein the first pillars extend along a first direction, and the first pillars are doped with conductive ions having a P-type conductivity type to form a first doped region.
  • the first column 61 extends along the first direction D1, and a plurality of first columns 61 are spaced apart along the second direction D2 and arranged in the third direction D3.
  • the second direction D2 and the third direction D3 are located in the same plane, the second direction D2 and the third direction D3 are perpendicular, and the first direction D1 is perpendicular to the plane where the second direction D2 and the third direction D3 are located.
  • an ion implantation process is used to dope the first column 61 with a P-type conductivity type. After the first column 61 is annealed, a first doping region 4 is formed in the first column 61.
  • Step S230 forming an isolation layer, wherein the isolation layer covers the sidewall and top surface of each first column.
  • an isolation layer 7 is formed by a suitable deposition process.
  • the isolation layer 7 covers the sidewalls and top surfaces of the first pillars 61 (see FIG. 10 ) and exposes a portion of the top surface of the substrate 6 between two adjacent first pillars 61 .
  • Step S240 etching the substrate below the first pillars to form a second pillar below each first pillar.
  • the substrate 6 exposed by the isolation layer 7 is etched away to form a second column 62 under each first column 61 (refer to Figure 10).
  • the width of the first column 61 (refer to Figure 10) is smaller than the width of the second column 62, and the projection of the first column 61 (refer to Figure 10) on the second column 62 falls within the second column 62.
  • Step S250 doping the second column with conductive ions of N-type conductivity to form a second doping region, wherein the first doping region and the second doping region together form a first connection terminal, and the first doping region and the second doping region form a PN junction.
  • an ion implantation process may be used to dope conductive ions having N-type conductivity into the second pillar 62 , and the second pillar 62 may be annealed to form a second doping region 5 under each first doping region 4 .
  • the first doping region 4 and the second doping region 5 form a first connection terminal 1 having a PN junction.
  • the first connection terminal 1 also constitutes a partial structure of the row selection line 100 , that is, the first connection terminal 1 and the row selection line 100 share a partial structure.
  • Step S260 forming a dielectric layer to cover the sidewalls of the second doped region.
  • the step of forming the dielectric layer 3 in this embodiment is the same as the step of forming the dielectric layer 3 in step S150 in the above embodiment, and will not be described again.
  • Step S270 forming a second connection end extending in a second direction intersecting the first direction, the second connection end intersecting with the second doping region of the first connection end, and the second connection end and the second doping region being separated by a dielectric layer.
  • a suitable deposition process is used to deposit a conductive material, the conductive material covers the dielectric layer 3 and the isolation layer 7, and the conductive material also fills the gaps between adjacent second pillars 62. Then, a portion of the conductive material is removed by etching, and the remaining conductive material is divided into a plurality of column selection lines 200 extending along the second direction D2.
  • the column selection lines 200 may be bit lines.
  • a plurality of column selection lines 200 are spaced apart in the third direction D3, each column selection line 200 intersects with a plurality of row selection lines 100 arranged along the second direction D2, each column selection line 200 covers a second doped region 5 of a plurality of row selection lines 100 arranged in its extension direction, an anti-fuse 10 is formed at an intersection of each column selection line 200 and each row selection line 100, and a partial structure where each column selection line 200 intersects with the second doped region 5 forms a second connection terminal 2 of the anti-fuse 10.
  • first, second, etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

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Abstract

本公开提供了一种反熔丝器及制作方法、反熔丝阵列及操作方法，该反熔丝器包括第一连接端、第二连接端和介质层。第一连接端包括第一掺杂区以及设置在第一掺杂区下方的第二掺杂区，第一掺杂区和第二掺杂区的导电类型相反，第一掺杂区和第二掺杂区连接并形成PN结。第二连接端至少覆盖第二掺杂区。介质层，设置在第二连接端和第二掺杂区之间，第二连接端和第二掺杂区通过介质层隔开。

Description

反熔丝器及制作方法、反熔丝阵列及操作方法
本公开基于申请号为202310182691.0、申请日为2023年02月24日、申请名称为“反熔丝单元及制作方法、反熔丝阵列及操作方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种反熔丝器及制作方法、反熔丝阵列及操作方法。
背景技术
一次性可编程(One Time Programmable，OTP)存储器是一种支持一次性编程的非易失性存储器，广泛应用于模拟电路、存储器芯片中。一次性可编程存储器分为熔丝型器件和反熔丝器件(Anti-fuse)，反熔丝器件(Anti-fuse)是目前较为常用的一次性可编程存储器。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开的第一方面提供了一种反熔丝器，包括：
第一连接端，包括第一掺杂区以及设置在所述第一掺杂区下方的第二掺杂区，所述第一掺杂区和所述第二掺杂区的导电类型相反，所述第一掺杂区和所述第二掺杂区连接并形成PN结；
第二连接端，至少覆盖所述第二掺杂区；
介质层，设置在所述第二连接端和所述第二掺杂区之间，所述第二连接端和所述第二掺杂区通过所述介质层隔开。
本公开的第二方面提供了一种反熔丝器的制作方法，所述制作方法包括：
提供衬底；
刻蚀去除部分所述衬底，形成沿第一方向延伸的第一柱体，向所述第一柱体掺杂具有P型导电类型的导电离子，形成第一掺杂区；
刻蚀位于所述第一柱体下方所述衬底，在所述第一柱体的下方形成第二柱体；
向所述第二柱体掺杂具有N型导电类型的导电离子，形成第二掺杂区，所述第一掺杂区和所述第二掺杂区共同形成第一连接端，所述第一掺杂区和所述第二掺杂区形成PN结；
形成介质层，覆盖所述第二掺杂区的侧壁；
形成第二连接端，在与所述第一方向相交的第二方向延伸，所述第二连接端和所述第一连接端的所述第二掺杂区相交，所述第二连接端和所述第二掺杂区之间通过所述介质层隔开。
本公开的第三方面提供了一种反熔丝阵列，包括交叉的多条行选择线和多个列选择线；以及设置在所述行选择线与所述列选择线的交点处的多个反熔丝器；
每个所述反熔丝器包括：
连接至所述行选择线的第一连接端，包括第一掺杂区以及设置在所述第一掺杂区下方的第二掺杂区，所述第一掺杂区和所述第二掺杂区的导电类型相反，所述第一掺杂区和所述第二掺杂区连接并形成PN结；
连接至所述列选择线的第二连接端，至少覆盖所述第二掺杂区；
介质层，设置在所述第二连接端和所述第二掺杂区之间，所述第二连接端和所述 第二掺杂区通过所述介质层隔开。
本公开的第四方面提供了一种反熔丝阵列的操作方法，应用于本公开的第三方面的反熔丝阵列，所述操作方法包括：
向选中的反熔丝器连接的行选择线施加编程电压，同时向所述选中的反熔丝器连接的列选择线施加低电压，在所述选中的反熔丝器的第一连接端和第二连接端之间形成电压差以击穿介质层，在所述第一连接端的第二掺杂区和所述第二连接端之间形成导电路径。
本公开实施例所提供的反熔丝器及制作方法、反熔丝阵列及操作方法中，反熔丝器仅由第一连接端、第二连接端以及介质层构成，无需在反熔丝器的周边为其配置选择晶体管，减小了反熔丝器的尺寸，能够进一步减小反熔丝器的布局面积。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的反熔丝器的结构示意图。
图2是根据一示例性实施例示出的反熔丝器的A-A截面的剖面图。
图3是根据一示例性实施例示出的反熔丝器的俯视图。
图4是根据一示例性实施例示出的反熔丝阵列的示意图。
图5是根据一示例性实施例示出的反熔丝阵列的B-B截面的剖面图。
图6是根据一示例性实施例示出的反熔丝阵列的电路示意图。
图7是根据一示例性实施例示出的目标反熔丝器被编程后的电路示意图。
图8是根据一示例性实施例示出的反熔丝器的制作方法的流程图。
图9是根据一示例性实施例示出的反熔丝阵列的制作方法的流程图。
图10是根据一示例性实施例示出的刻蚀衬底形成第一柱体后的B-B截面的示意图。
图11是根据一示例性实施例示出的形成第一掺杂区后的B-B截面的示意图。
图12是根据一示例性实施例示出的形成隔离层后的B-B截面的示意图。
图13是根据一示例性实施例示出的形成第二柱体后的B-B截面的示意图。
图14是根据一示例性实施例示出的形成第二掺杂区后的B-B截面的示意图。
图15是根据一示例性实施例示出的形成介质层后的B-B截面的示意图。
附图标记：
1、第一连接端；2、第二连接端；3、介质层；4、第一掺杂区；5、第二掺杂区；6、衬底；61、第一柱体；62、第二柱体；7、隔离层；10、反熔丝器；
100、行选择线；200、列选择线；
D1、第一方向；D2、第二方向；D3、第三方向。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
反熔丝器件是比较常用的一次性可编程器件，反熔丝器件被广泛应用于动态随机存取存储器(Dynamic Random Access Memory，DRAM)和闪存存储器(NAND flash memory，NAND)中。反熔丝器件包括反熔丝结构和选择晶体管。反熔丝结构是由两个导电层及介于导电层之间的介电层构成的半导体器件。选择晶体管是在存储阵列中与该反熔丝结构相邻的晶体管。在对反熔丝器件进行编程操作时，通过将选择晶体管导通对反熔丝结构施加编程电压或编程电流。在反熔丝器件未被编程时，反熔丝结构的两个导电层被介电层隔开，以使反熔丝结构的两端为断路。在反熔丝结构被编程时(外加高压)，反熔丝结构中的介电层被高压击穿，使得介电层的两侧的导电层之间形成电连接，也就是说反熔丝结构被击穿，并且，这种反熔丝结构被击穿的过程在物理上是一次性的、永久性的、不可逆的。
通常，在进行反熔丝器件的布局时，反熔丝结构和选择晶体管之间的距离不能过近，如果反熔丝结构和选择晶体管的距离过近，因此，在反熔丝结构被击穿的过程中会造成选择晶体管的性能退化，这会影响电路的可靠性。此外，反熔丝器件的结构导致其占用存储器芯片的面积较大，这不利于提高存储器芯片的存储密度以及实现存储器芯片的继续微缩。
本公开示例性的实施例提供了一种反熔丝器，该反熔丝器包括第一连接端、第二连接端以及介质层。针对该反熔丝器来说，通过向第一连接端施加编程电压以击穿介质层来进行对反熔丝器的编程操作，并且，通过读取第二连接端的电位来完成对反熔丝器的读取操作，这就无需在反熔丝器的周边配置与其对应的选择晶体管，从而减小了反熔丝器的尺寸，进而能够进一步减小反熔丝器的布局面积，为其他半导体器件的布局提供了更多可利用的空间。
根据一示例性实施例，参照图1、图2和图3，本示例性实施例提供了一种反熔丝器10，该反熔丝器10包括第一连接端1、第二连接端2以及介质层3。第一连接端1包括第一掺杂区4以及设置在第一掺杂区4下方的第二掺杂区5，并且，第一掺杂区4和第二掺杂区5的导电类型相反，同时，第一掺杂区4和第二掺杂区5连接并形成PN结；第二连接端2至少覆盖第二掺杂区5。介质层3设置在第二连接端2和第二掺杂区5之间，第二连接端2和第二掺杂区5通过介质层3隔开。
本实施例中的反熔丝器10可以被编程，在对本实施例的反熔丝器10进行编程操作时，可以执行以下操作：向第一连接端1的第一掺杂区4施加编程电压，且该编程电压高于介质层3的击穿电压，如此，介质层3被编程电压击穿，对应的在第一连接端1和第二连接端2之间形成了导电路径，而第一连接端1中的电流可通过该导电路径泄漏到第二连接端2中，最终完成了反熔丝器10的编程操作。
在对本实施例的反熔丝器10进行读取操作时，可以执行以下操作：检测第二连接端2和第一连接端1之间的电流，根据检测到的电流来完成对反熔丝器10的读取操作，或者，基于第一连接端1中的电流泄漏到第二连接端2中，会引起第二连接端2的电位发生变化，通过检测第二连接端2的电位，根据第二连接端2的电位完成对反熔丝器10的读取操作。
下面对本实施例的反熔丝器10进行详细说明：
参照图1、图2和图3，第一连接端1沿第一方向D1竖直设置，并且在第一方向D1上，第一连接端1包括第一掺杂区4以及设置在第一掺杂区4下方的第二掺杂区5，同时，第一掺杂区4和第二掺杂区5中分别掺杂有导电类型不同的掺杂离子，第一掺杂区4和第二掺杂区5的交界面形成了PN结。本实施例中，第一掺杂区4和第二掺杂区5相当于在第一连接端1中形成了PN二极管，第一掺杂区4作为PN二极管的阳极，第二掺杂区5作为PN二极管的阴极。在反熔丝器10被编程后，PN结用于阻挡第二连接端2中的电 流通过导电路径反向泄漏到第一连接端1中，从而改善了防止电流反向泄漏导致的读取错误的问题。
第一连接端1可以包括半导体材料，例如硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)，例如绝缘体上硅(SOI)、绝缘体上锗(GOI)，再例如其它的具有半导体性能的材料(砷化镓等Ⅲ-Ⅴ族化合物)。
本实施例中，第一掺杂区4包括P型半导体材料，第二掺杂区5包括N型半导体材料。将具有P型导电类型的导电离子注入到第一连接端1的第一掺杂区4所在的区域中，然后，通过执行退火处理来激活具有P型导电类型的导电离子，从而形成第一掺杂区4。将具有N型导电类型的导电离子注入到第一连接端1的第二掺杂区5所在的区域中，然后执行退火处理来激活具有N型导电类型的导电离子，从而在第一掺杂区4的下方形成第二掺杂区5。
示例性的，第一掺杂区4可以为重掺杂区，第二掺杂区5可以为轻掺杂区，也即，第一掺杂区4中的具有P型导电类型的导电离子的浓度大于第二掺杂区5中的具有N型导电类型的导电离子的浓度。
第二连接端2的材料可以包括导电金属，示例性的，第二连接端2的材料可以包括金属钛(Titanium)或其合金、金属钽(Tantalum)或其合金、金属钨(Tungsten)或其合金中的至少一种。
介质层3具有电绝缘性，示例性的，介质层3可以包括氧化硅、高k(介电常数)介电材料中的至少一种。
在反熔丝器10未被编程前，介质层3的电阻很大，因此，第一连接端1和第二连接端2被该介质层3隔开。当反熔丝器10被编程后，介质层3的至少部分区域被击穿，而介质层3被击穿的区域的电阻会下降，这就对应的在第二连接端2和第一连接端1的第二掺杂区5之间形成了导电路径，也就是说，第一连接端1和第二连接端2电导通，第一连接端1中的电流可以通过导电路径泄漏到第二连接端2中，这会引起第二连接端的电位发生变化，如此，当反熔丝器10被编程后，通过检测第二连接端2的电流或第二连接端2的电位即可判断反熔丝器10的编程状态(具体为未编程状态或以编程状态)。
在一些实施例中，参照图1、图2和图3，在第一连接端1的径向方向上，介质层3环绕并连续覆盖第二掺杂区5，第二连接端2环绕并连续覆盖介质层3。第二掺杂区5的周向表面被介质层3覆盖，介质层3设置在第二连接端2和第二掺杂区5的周向表面之间，第二掺杂区5和介质层3具有更大的接触面积，因此，在对反熔丝器10进行编程操作时，介质层3更容易被击穿，这就降低了反熔丝器10的编程难度，提高了编程效率。
在一些实施例中，参照图1、图2和图3，第一掺杂区4的径向尺寸小于第二掺杂区5的径向尺寸，第一掺杂区4在第二掺杂区5上形成的投影落在第二掺杂区5内。
在一些实施例中，参照图1、图2和图3，本实施例的反熔丝器10还包括覆盖第一掺杂区4的隔离层7。该隔离层7的材料可以包括氧化硅、氮化硅或氮氧化硅中的至少一种。基于隔离层7具有良好的电隔离效果，隔离层7覆盖第一掺杂区4能够避免反熔丝器10和与其相邻的半导体器件之间的桥接发生短路，这有利于进一步提高反熔丝器10的工作性能和使用寿命。
在一些实施例中，参照图1、图2、图3和图4，第一连接端1连接至行选择线100，第二连接端2连接至列选择线200，行选择线100和列选择线200沿不同的方向延伸，且行选择线100和列选择线200交叉连接。反熔丝器10设置在行选择线100和列选择线200的交点处，也即，行选择线100和列选择线200通过反熔丝器10连接。示例性的，行选择线100和列选择线200可以倾斜相交或垂直相交。
根据一示例性实施例，本示例性实施例提供了一种反熔丝阵列，参照图4和图5，反 熔丝阵列包括交叉的多条行选择线100和多条列选择线200，以及设置在行选择线100与列选择线200的交点处的多个反熔丝器10。
参照图4、图5和图6，每个反熔丝器10包括第一连接端1、第二连接端2和介质层3。第一连接端1连接至行选择线100，且第一连接端1包括第一掺杂区4以及设置在第一掺杂区4下方的第二掺杂区5。第一掺杂区4和第二掺杂区5的导电类型相反，第一掺杂区4和第二掺杂区5连接并形成PN结。第二连接端2连接至列选择线200，第二连接端2至少覆盖第二掺杂区5。介质层3设置在第二连接端2和第二掺杂区5之间，将第二连接端2和第二掺杂区5隔开。
示例性的，本实施例中的反熔丝阵列设置在DRAM架构中，行选择线100连接DRAM架构中的字线(Word Line，WL)，列选择线200连接DRAM架构中的位线(Bit Line，BL)。反熔丝器10的第一连接端1和字线的栅极连接，反熔丝器10的第二连接端2和位线连接。本实施例中，行选择线100和列选择线200垂直相交。
参照图4，行选择线100沿第一方向D1延伸，多条行选择线100独立设置，并且，多条行选择线100沿第二方向D2、第三方向D3间隔设置。列选择线200沿第二方向D2延伸，并且多条列选择线200沿第三方向D3间隔设置。在本实施例中，第二方向D2和第三方向D3位于同一平面，第二方向D2和第三方向D3垂直，第一方向D1垂直于第二方向D2和第三方向D3所在的平面。反熔丝器10设置在行选择线100和列选择线200的交点处的设计方案，能够提高反熔丝阵列10的集成度，使得单位面积的反熔丝阵列能够设置更多的反熔丝器10。
本实施例的反熔丝阵列，对选中的反熔丝器10进行编程操作时，向选中的反熔丝器10连接的行选择线100(后续简称为选中的行选择线100)施加编程电压，同时将与选中的反熔丝器10连接的列选择线200(后续简称为选中的列选择线200)施加低电压，向其余未选中的列选择线200施加二分之一编程电压(可以理解的是，向未选中的列选择线200施加二分之一编程电压是为了避免选中的行选择线100击穿未选中反熔丝器10，在实际应用中，可以向未选中的列选择线200施加三分之一编程电压、四分之一编程电压等)，反熔丝阵列中的其余未选中的行选择线100可以浮置。
选中的行选择线100和选中的列选择线200之间的电压差击了穿选中的反熔丝器10的介质层3，从而在选中的反熔丝器10的第一连接端1和第二连接端2之间形成了导电路径，完成了对选中的反熔丝器10的编程操作。
在对选中的反熔丝器10进行读取操作时，将选中的列选择线200的电位下拉至低电位0，然后向选中的行选择线100施加检测电压，以使选中的行选择线100处于高电位1，且检测电压低于介质层3的击穿电压。然后，将选中的列选择线200的电位下拉至低电位0的状态解除，以使选中的列选择线200可以持续接受来自选中的行选择线100的漏电流。静置一段时间，在电位差的作用下，选中的反熔丝器10的第一连接端1中的电流通过导电路径泄漏到第二连接端2中并存储在第二连接端2中，这就导致了选中的反熔丝器10的第二连接端2的电位上升。
对选中的反熔丝器10进行读取操作时，读取选中的反熔丝器10的第二连接端2的电位值，根据第二连接端2的电位值判断选中的反熔丝器10的编程状态。如果选中的反熔丝器10处于被编程的状态，则选中的反熔丝器10的第二连接端2的电位值为高电位1。如果选中的反熔丝器10处于未被编程的状态，则选中的反熔丝器10的第二连接端2的电位值为低电位0。
可以理解的是，反熔丝器10被编程后，第一连接端1和第二连接端2之间形成了导电路径，从而使得第一连接端1中的电流泄漏可以通过该导电路径泄漏到第二连接端2中，导致第二连接端2的电位会上升。但是，如果第二连接端2的电位持续上升，可能会出现第二连接端2的电位高于第一连接端1的电位的情况，这就会使得第二连接端2中的电流 通过导电路径反向泄漏到第一连接端1，从而导致检测第二连接端2的电位获得的检测结果不准确，进而造成读取错误。
本实施例中，每个反熔丝器10的第一连接端1包括导电类型相反的第一掺杂区4和第二掺杂区5，第一掺杂区4和第二掺杂区5在第一连接端1中形成了PN结，这就相当于在行选择线100和列选择线200的连接交点处设置了PN二极管，具体的，第一掺杂区4对应于PN二极管的阳极，第二掺杂区5对应于PN二极管的阴极。在反熔丝器10设置在行选择线100和列选择线200的交点处的设计方案中，行选择线100和列选择线200通过PN二极管连接，这能够避免由于第二连接端2的电位值高于第一连接端1的电位值，致使第二连接端2中的电流通过导电路径反向泄漏到第一连接端1中，出现第二连接端2的电流下降至低电位的问题，从而确保对选中的反熔丝器10进行读取操作时读取结果的精确性，避免误读取，进而保证检测第二连接端2执行读取操作时，能够根据第二连接端2的电位获得准确的检测结果。
在一些实施例中，参照图4和图5，第一掺杂区4包括P型半导体材料，第二掺杂区5包括N型半导体材料。
其中，第一掺杂区4可以为重掺杂区，第二掺杂区5可以为轻掺杂区，也即，第一掺杂区4中的具有P型导电类型的导电离子的浓度大于第二掺杂区5中的具有N型导电类型的导电离子的浓度。
在一些实施例中，参照图4和图5，沿第一连接端1的径向方向，介质层3环绕并连续覆盖第二掺杂区5，第二连接端2环绕并连续覆盖介质层3。
在一些实施例中，参照图4和图5，第一掺杂区4的径向尺寸小于第二掺杂区5的径向尺寸，第一掺杂区4在第二掺杂区5上形成的投影落在第二掺杂区5内。
根据一示例性实施例，本示例性实施例提供了一种存储装置，该存储装置包括上述实施例中的反熔丝阵列，其中，反熔丝阵列为一次性可编程存储器。
根据一示例性实施例，本示例性实施例提供了一种反熔丝阵列的操作方法，应用于上述实施例的反熔丝阵列，操作方法包括以下步骤：
S1：向选中的反熔丝器连接的行选择线施加编程电压，同时向选中的反熔丝器连接的列选择线施加低电压，在选中的反熔丝器的第一连接端和第二连接端之间形成电压差以击穿介质层，在第一连接端的第二掺杂区和第二连接端之间形成导电路径。
其中，第一连接端和第二连接端之间的电压差大于介质层的击穿电压。
本实施例的反熔丝阵列的电路参照图6所示，本实施例的反熔丝阵列的电路包括反熔丝阵列，反熔丝阵列包括平行设置的列选择线200-0、列选择线200-1和列选择线200-2，反熔丝阵列还包括平行设置的行选择线100-0和行选择线100-1，行选择线100-0和行选择线100-1分别和列选择线200-0、列选择线200-1和列选择线200-2相交，反熔丝阵列还包括反熔丝器10-0至反熔丝器10-5，反熔丝器10-0至反熔丝器10-2分别设置在行选择线100-0和列选择线200-0、列选择线200-1和列选择线200-2的交点处，反熔丝器10-3至反熔丝器10-5分别设置在行选择线100-1和列选择线200-0、列选择线200-1和列选择线200-2的交点处。
本实施例中，反熔丝阵列还可以包括编程控制模块(图中未示出)，通过编程控制模块为反熔丝阵列提供编程电流。
以选中的反熔丝器为反熔丝器10-0对本实施例进行说明。本实施例中，通过编程控制模块向行选择线100-0施加编程电压(高电压)，同时向列选择线200-0施加低电压，向列选择线200-1、列选择线200-2施加二分之一编程电压，将行选择线100-1浮置。其中，施加到行选择线100-0的编程电压大约可以为4V到6V，例如，施加到行选择线100-0的编程电压为5V，施加到列选择线200-1、列选择线200-2的电压为2.5V。可以将列选择线200-0接地，列选择线200-0的低电位为0V。
反熔丝器10-0的第一连接端1(参照图5)和第二连接端2(参照图5)之间形成电压差以击穿介质层3(参照图5)，在第一连接端1(参照图5)和第二连接端2(参照图5)之间形成导电路径，完成对反熔丝器10-0的编程操作，完成对反熔丝器10-0的编程操作后，反熔丝阵列的电路参照图7所示。
本实施例中，操作方法还包括以下步骤：
S2：将选中的反熔丝器连接的列选择线的电位下拉至低电位。
本实施例中，将列选择线200-0的电位下拉至低电位0。
S3：向选中的反熔丝器连接的行选择线施加检测电压，然后，将列选择线的电位下拉至低电位的状态解除。
向行选择线100-0施加检测电压，检测电压低于编程电压，以使行选择线100-0处于高电位1，施加到行选择线100-0的检测电压大约可以为2V到3V，例如，2.5V的电压。
然后，将列选择线200-0的电位下拉至低电位0的状态解除，从而列选择线200-0可以持续接受来自行选择线100-0的漏电流。
静置一段时间，在行选择线100-0和列选择线200-0的电位差的作用下，反熔丝器10-0的第一连接端1(参照图5)中的电流通过导电路径泄漏到第二连接端2(参照图5)中并存储在第二连接端2(参照图5)中，第二连接端2(参照图5)的电位上升。
S4：读取第二连接端的电位值，根据第二连接端的电位值判断选中的反熔丝器的编程状态。
本实施例中，读取获得的第二连接端的电位值为低电位，选中的反熔丝器处于未编程状态；读取获得的第二连接端的电位值为高电位，选中的反熔丝器处于已编程状态。
本公开示例性的实施例中提供一种反熔丝器的制作方法，如图8所示，图8示出了根据本公开一示例性的实施例提供的反熔丝器的制作方法的流程图，图10-图15为反熔丝器的制作方法的各个阶段的示意图，下面结合图10-图15、参照图1-图3对反熔丝器的制作方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图8所示，本公开一示例性的实施例提供的一种反熔丝器的制作方法，包括如下的步骤：
步骤S110：提供衬底。
参照图10，衬底6包括本征半导体材料，本征半导体材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)、绝缘体上锗(GOI)；或者还可以为其它的具有半导体性能的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中，衬底6的材料包括多晶硅。
步骤S120：刻蚀去除部分衬底，形成沿第一方向延伸的第一柱体，向第一柱体掺杂具有P型导电类型的导电离子，形成第一掺杂区。
参照图10，本实施例中，可以在衬底6的顶面形成掩膜(图中未示出)，掩膜上定义有同于形成第一柱体61的掩膜图案，根据掩膜图案刻蚀去除部分衬底6，形成第一柱体61，第一柱体61沿第一方向D1延伸。
参照图10和图11，然后，采用离子注入工艺向第一柱体61中掺杂具有P型导电类型的导电离子，示例性的，具有P型导电类型的导电离子可以包括硼离子B3+、镓离子Ga3+中的一种或多种。
接着，对第一柱体61进行退火处理，以激活第一柱体61中的具有P型导电类型的导电离子，在第一柱体61中形成第一掺杂区4。例如，可以在热退火装置中对第一柱体61进行退火处理。
本实施例中，形成第一柱体61之后，还执行了以下步骤：
参照图10、图11和图12，形成隔离层7，隔离层7覆盖第一柱体61的侧壁和顶面。可以采用合适的沉积工艺沉积隔离材料，隔离材料覆盖第一柱体61的侧壁、第一柱体61顶面以及衬底6的暴露的顶面。然后，采用各向异性刻蚀工艺刻蚀去除位于衬底6的顶面上的隔离材料，覆盖第一柱体61的侧壁和顶面的隔离材料被保留形成为隔离层7。
步骤S130：刻蚀位于第一柱体下方衬底，在第一柱体的下方形成第二柱体。
参照图13，基于隔离层7刻蚀第一柱体61(参照图10)下方的衬底6，去除被隔离层7暴露出的衬底6，形成第二柱体62。沿第二方向D2，第一柱体61的宽度小于第二柱体62的宽度，第一柱体61在第二柱体62上形成的投影落在第二柱体62内。
本实施例中，可以采用干法工艺或湿法工艺刻蚀第一柱体61(参照图10)下方的衬底6，在第一柱体61下方形成第二柱体62。
步骤S140：向第二柱体掺杂具有N型导电类型的导电离子，形成第二掺杂区，第一掺杂区和第二掺杂区共同形成第一连接端，第一掺杂区和第二掺杂区形成PN结。
参照图13和图14，可以采用离子注入工艺向第二柱体62中掺杂具有N型导电类型的导电离子，示例性的，具有N型导电类型的导电离子可以包括磷离子P5+、砷离子As5+、碲离子Te5+中的一种或多种。接着，对第二柱体62进行退火处理，以激活第二柱体62中具有N型导电类型的导电离子，在第二柱体62中形成第二掺杂区5。示例性的，可以在热退火装置中对第二柱体62进行退火处理。
步骤S150：形成介质层，覆盖第二掺杂区的侧壁。
采用热氧化工艺处理第二掺杂区5，在第二掺杂区5的侧壁形成介质层3，本实施例中，介质层3的材料包括氧化硅。
步骤S160：形成第二连接端，在与第一方向相交的第二方向延伸，第二连接端和第一连接端的第二掺杂区相交，第二连接端和第二掺杂区之间通过介质层隔开。
参照图1、图2、图3和图15，选用合适的沉积工艺沉积导电材料，导电材料覆盖介质层3以及隔离层7，刻蚀去除覆盖在隔离层7上的导电材料，被保留的导电材料形成第二连接端2，第二连接端2的材料可以包括金属钛(Titanium)或其合金、金属钽(Tantalum)或其合金、金属钨(Tungsten)或其合金中的至少一种。
本实施例的反熔丝器的制作方法，通过形成具有第一掺杂区和第二掺杂区的第一连接端，第一掺杂区和第二掺杂区形成PN结，再形成依次覆盖第二掺杂区的介质层和第二连接端构成反熔丝器，向第一连接端施加编程电压击穿介质层即可完成对反熔丝器的编程操作，无需为反熔丝器额外配置选择晶体管，本实施例中形成的反熔丝器仅包括一个半导体器件，减小了反熔丝器的尺寸，为半导体结构提供了更多可利用的空间。
本公开示例性的实施例中提供一种反熔丝阵列的制作方法，图9示出了根据本公开一示例性的实施例提供的反熔丝阵列的制作方法的流程图，如图9所示，本示例性的实施例提供的一种反熔丝阵列的制作方法，包括如下的步骤：
步骤S210：提供衬底。
参照图10，本实施例中提供的衬底6和上述实施例中步骤S110中提供的衬底相同，在此不再赘述。
步骤S220：刻蚀去除部分衬底，形成多个独立设置的第一柱体，第一柱体沿第一方向延伸，向第一柱体掺杂具有P型导电类型的导电离子，形成第一掺杂区。
参照图4和图10，第一柱体61沿第一方向D1延伸，且多个第一柱体61沿第二方向D2间隔、第三方向D3设置。本实施例中，第二方向D2和第三方向D3位于同一平面，第二方向D2和第三方向D3垂直，第一方向D1垂直于第二方向D2和第三方向D3所在的平面。
参照图4、图10和图11，采用离子注入工艺向第一柱体61中掺杂具有P型导电类型 的导电离子，对第一柱体61进行退火处理后，在第一柱体61中形成第一掺杂区4。
步骤S230：形成隔离层，隔离层覆盖每个第一柱体的侧壁和顶面。
参照图12，采用合适的沉积工艺形成隔离层7，隔离层7覆盖第一柱体61(参照图10)的侧壁和顶面，并暴露出相邻的两个第一柱体61之间的衬底6的部分顶面。
步骤S240：刻蚀位于第一柱体下方衬底，在每个第一柱体的下方形成第二柱体。
参照图13，刻蚀去除被隔离层7暴露出的衬底6，在每个第一柱体61(参照图10)的下方形成第二柱体62，沿第二方向D2，第一柱体61(参照图10)的宽度小于第二柱体62的宽度，第一柱体61(参照图10)在第二柱体62上形成的投影落在第二柱体62内。
步骤S250：向第二柱体掺杂具有N型导电类型的导电离子，形成第二掺杂区，第一掺杂区和第二掺杂区共同形成第一连接端，第一掺杂区和第二掺杂区形成PN结。
参照图14，可以采用离子注入工艺向第二柱体62中掺杂具有N型导电类型的导电离子，对第二柱体62进行退火处理，在每个第一掺杂区4的下方形成第二掺杂区5，第一掺杂区4和第二掺杂区5形成具有PN结的第一连接端1。
第一连接端1还构成行选择线100的部分结构，也即第一连接端1和行选择线100共用部分结构。
步骤S260：形成介质层，覆盖第二掺杂区的侧壁。
参照图15，本实施例中形成介质层3的步骤和上述实施例中步骤S150中形成介质层3的步骤相同，在此不再赘述。
步骤S270：形成第二连接端，在与第一方向相交的第二方向延伸，第二连接端和第一连接端的第二掺杂区相交，第二连接端和第二掺杂区之间通过介质层隔开。
参照图4和图5，选用合适的沉积工艺沉积导电材料，导电材料覆盖介质层3以及隔离层7，导电材料还填充到相邻的第二柱体62之间的间隙。然后，刻蚀去除部分导电材料，将被保留的导电材料划分成多条沿第二方向D2延伸的列选择线200，在本实施例中，列选择线200可以是位线。
参照图4和图5，多条列选择线200在第三方向D3上间隔设置，每条列选择线200和沿第二方向D2排列的若干个行选择线100相交，每条列选择线200覆盖位于其延伸方向排列的若干个行选择线100的第二掺杂区5，每条列选择线200和每条行选择线100的相交的交点处形成反熔丝器10，每条列选择线200和第二掺杂区5相交的部分结构形成为反熔丝器10的第二连接端2。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图 中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (14)

  1. 一种反熔丝器，包括：
    第一连接端(1)，包括第一掺杂区(4)以及设置在所述第一掺杂区(4)下方的第二掺杂区(5)，所述第一掺杂区(1)和所述第二掺杂区(5)的导电类型相反，所述第一掺杂区(1)和所述第二掺杂区(5)连接并形成PN结；
    第二连接端(2)，至少覆盖所述第二掺杂区(5)；
    介质层(3)，设置在所述第二连接端和所述第二掺杂区之间，所述第二连接端和所述第二掺杂区通过所述介质层隔开。
  2. 根据权利要求1所述的反熔丝器，其中，沿所述第一连接端(1)的径向方向，所述介质层(3)环绕并连续覆盖所述第二掺杂区(5)，所述第二连接端(2)环绕并连续覆盖所述介质层(3)。
  3. 根据权利要求1或2所述的反熔丝器，其中，所述第一掺杂区(4)的径向尺寸小于所述第二掺杂区(5)的径向尺寸，所述第一掺杂区(4)在所述第二掺杂区(5)上的投影落在所述第二掺杂区(5)内。
  4. 根据权利要求1所述的反熔丝器，其中，还包括隔离层(7)，所述隔离层(7)覆盖所述第一掺杂区(4)。
  5. 根据权利要求1-4中任一项所述的反熔丝器，其中，所述第一连接端(1)连接至行选择线(100)，所述第二连接端(2)连接至列选择线(200)，所述行选择线(100)和所述列选择线(200)交叉连接。
  6. 一种反熔丝器的制作方法，所述制作方法包括：
    提供衬底(6)；
    刻蚀去除部分所述衬底(6)，形成沿第一方向(D1)延伸的第一柱体(61)，向所述第一柱体(61)掺杂具有P型导电类型的导电离子，形成第一掺杂区(4)；
    刻蚀位于所述第一柱体(61)下方的所述衬底(6)，在所述第一柱体(61)的下方形成第二柱体(62)；
    向所述第二柱体(62)掺杂具有N型导电类型的导电离子，形成第二掺杂区(5)，所述第一掺杂区(4)和所述第二掺杂区(5)共同形成第一连接端(1)，所述第一掺杂区(4)和所述第二掺杂区(5)形成PN结；
    形成介质层(3)，覆盖所述第二掺杂区(5)的侧壁；
    形成第二连接端(2)，在与所述第一方向(D1)相交的第二方向(D2)延伸，所述第二连接端(2)和所述第一连接端(1)的所述第二掺杂区(5)相交，所述第二连接端(2)和所述第二掺杂区(5)之间通过所述介质层(3)隔开。
  7. 根据权利要求6所述的反熔丝器的制作方法，其中，所述制作方法还包括：
    形成隔离层(7)，所述隔离层(7)覆盖所述第一柱体(61)的侧壁和顶面；
    基于所述隔离层(7)刻蚀所述第一柱体(61)下方的所述衬底(6)，去除被所述隔离层(7)暴露出所述衬底(6)，形成所述第二柱体(62)，且沿所述第二方向(D2)，所述第一柱体(61)的宽度小于所述第二柱体(62)的宽度，所述第一柱体(61)在所述第二柱体(62)上形成的投影落在所述第二柱体(62)内。
  8. 一种反熔丝阵列，其中，包括交叉的多条行选择线(100)和多条列选择线(200)；以及设置在所述行选择线(100)与所述列选择线(200)的交点处的多个反熔丝器(10)；
    每个所述反熔丝器(10)包括：
    连接至所述行选择线(100)的第一连接端(1)，包括第一掺杂区(4)以及设置在所述第一掺杂区(4)下方的第二掺杂区(5)，所述第一掺杂区(4)和所述第二掺杂区(5)的导电类型相反，所述第一掺杂区(4)和所述第二掺杂区(5)连接并形成PN结；
    连接至所述列选择线(200)的第二连接端(2)，至少覆盖所述第二掺杂区(5)；
    介质层(3)，设置在所述第二连接端(2)和所述第二掺杂区(5)之间。
  9. 根据权利要求8所述的反熔丝阵列，其中，沿所述第一连接端(1)的径向方向，所述介质层(3)环绕并连续覆盖所述第二掺杂区(5)，所述第二连接端(2)环绕并连续覆盖所述介质层(3)。
  10. 根据权利要求8或9所述的反熔丝阵列，其中，所述第一掺杂区(4)的径向尺寸小于所述第二掺杂区(5)的径向尺寸，所述第一掺杂区(4)在所述第二掺杂区(5)上形成的投影落在所述第二掺杂区(5)内。
  11. 一种反熔丝阵列的操作方法，应用于权利要求8-10所述的反熔丝阵列，所述操作方法包括：
    向选中的反熔丝器(10)连接的行选择线(100)施加编程电压，同时向所述选中的反熔丝器(10)连接的列选择线(200)施加低电压，在所述选中的反熔丝器(10)的第一连接端(1)和第二连接端(2)之间形成电压差以击穿介质层(3)，在所述第一连接端(1)的第二掺杂区(5)和所述第二连接端(2)之间形成导电路径。
  12. 根据权利要求11所述的反熔丝阵列的操作方法，其中，所述第一连接端(1)和所述第二连接端(2)之间的电压差大于所述介质层(3)的击穿电压。
  13. 根据权利要求11或12所述的反熔丝阵列的操作方法，其中，所述操作方法还包括：
    将所述选中的反熔丝器(10)连接的所述列选择线(200)的电位下拉至低电位；
    向所述选中的反熔丝器(10)连接的行选择线(100)施加检测电压，然后，将所述列选择线(200)的电位下拉至低电位的状态解除；
    读取所述第二连接端(2)的电位值，根据所述第二连接端(2)的电位值判断所述选中的反熔丝器(10)的编程状态。
  14. 根据权利要求11-13中任一项所述的反熔丝阵列的操作方法，其中，读取获得的所述第二连接端(2)的电位值为低电位，所述选中的反熔丝器(10)处于未编程状态；
    读取获得的所述第二连接端(2)的电位值为高电位，所述选中的反熔丝器(10)处于已编程状态。
PCT/CN2023/094538 2023-02-24 2023-05-16 反熔丝器及制作方法、反熔丝阵列及操作方法 WO2024174395A1 (zh)

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CN109326581A (zh) * 2014-03-24 2019-02-12 英特尔公司 使用间隔体击穿的反熔丝元件

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CN1339159A (zh) * 1998-11-16 2002-03-06 矩阵半导体公司 垂直叠式现场可编程非易失存储器和制造方法
US20040041233A1 (en) * 2002-08-29 2004-03-04 Porter Stephen R. Shallow trench antifuse and methods of making and using same
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