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WO2024001426A1 - 一种相变薄膜、薄膜制备方法及相变存储器 - Google Patents

一种相变薄膜、薄膜制备方法及相变存储器 Download PDF

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WO2024001426A1
WO2024001426A1 PCT/CN2023/088326 CN2023088326W WO2024001426A1 WO 2024001426 A1 WO2024001426 A1 WO 2024001426A1 CN 2023088326 W CN2023088326 W CN 2023088326W WO 2024001426 A1 WO2024001426 A1 WO 2024001426A1
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tite
phase change
crystallized
change memory
phase
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PCT/CN2023/088326
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English (en)
French (fr)
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程晓敏
崔铭格
曾运韬
李凯
缪向水
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华中科技大学
湖北江城实验室
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Publication of WO2024001426A1 publication Critical patent/WO2024001426A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/46—Sulfur-, selenium- or tellurium-containing compounds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering

Definitions

  • the invention belongs to the field of microelectronic devices, and more specifically, relates to a phase change film, a film preparation method and a phase change memory.
  • the invention of memory has made the storage density of information higher and higher.
  • Traditional DRAM has the characteristics of fast erasing and writing speed, long service life, and volatility.
  • FLASH has the characteristics of low cost, non-volatile, and slow erasing and writing speed. Users hope that the memory will have the high speed and long life of DRAM and the low cost and non-volatile advantages of FLASH.
  • Phase change memory is considered to be one of the next generation non-volatile storage devices most likely to replace DRAM and FLASH. It has the characteristics of fast storage speed, high reliability and long service life.
  • Phase change memory is a non-volatile memory based on phase change materials (one or more chalcogenide compounds). It is mainly realized by using the Joule heat of electric current to transform the material between the crystalline and amorphous states. Storage of information.
  • phase change memory phase change material is a key part. This material has a higher resistance in the amorphous state and a lower resistance in the crystalline state. We use this difference in high and low resistance to achieve "0" and "1" information storage. Apply an electrical pulse with a large amplitude and short duration to a crystalline material. Due to the large amplitude and high energy, the material can quickly reach the melting temperature and lose the crystalline structure. However, due to the short duration and a rapid cooling process, the atoms are restored.
  • an electric pulse of medium amplitude and long duration is applied to the amorphous material.
  • the energy of this pulse can make the material reach the crystallization temperature without being lower than Melting temperature, during the duration of the pulse, atoms can rearrange and crystallize, achieving the transformation of the material from an amorphous to a crystalline state.
  • Sb 2 Te 3 is a phase change material with growth-dominated crystallization. Compared with Ge 2 Sb 2 Te 5 with nucleation-dominated crystallization, SET speed is faster, melting point is lower, and RESET power consumption is smaller. However, the crystallization temperature of Sb 2 Te 3 is very low, About 100°C, amorphous stability is poor.
  • researchers optimized Sb 2 Te 3 phase change memory through doping Current research on Sb 2 Te 3 phase change memory cells is mostly based on doping single element atoms. Research shows that doping single element atoms can effectively improve the amorphous stability of Sb 2 Te 3 , but generally at the expense of SET speed. cost.
  • the purpose of the present invention is to provide a phase change film, a film preparation method and a phase change memory, aiming to solve the problem of conventional single element doping that improves the amorphous stability of Sb 2 Te 3 phase change materials but SET The speed is reduced, and the problem of conventional single element doping destroying the Sb 2 Te 3 lattice structure.
  • the present invention provides a phase change film.
  • the general chemical formula of the phase change film is: (TiTe 2 ) x (Sb 2 Te 3 ) 1-x , 0 ⁇ x ⁇ 0.6 .
  • phase change film when the phase change film is crystallized for the first time, TiTe 2 and Sb 2 Te 3 are crystallized respectively;
  • TiTe 2 After the phase change film is crystallized for the first time, TiTe 2 always remains in the crystalline state, the TiTe 2 crystal nuclei are dispersedly distributed, the TiTe 2 crystal structure is stable, and does not chemically react with Sb 2 Te 3 ;
  • Sb 2 Te 3 can be repeatedly amorphized or crystallized.
  • the mismatch between the Sb 2 Te 3 crystal structure and the TiTe 2 crystal structure is low.
  • Sb 2 Te 3 is crystallized, Using the TiTe 2 crystal structure as a template for epitaxial growth, the time for Sb 2 Te 3 to complete crystallization is relatively shortened.
  • the greater the TiTe 2 doping ratio The higher the amorphous stability of the film in the amorphous state.
  • the invention provides a method for preparing a phase change film, which includes the following steps:
  • the above two targets are sputtered, and the doping ratio x of TiTe 2 is controlled by controlling the sputtering power of the two targets to deposit on the substrate to obtain a chemical formula of (TiTe 2 ) x (Sb 2 Te 3 ) 1-x phase change film , 0 ⁇
  • TiTe 2 and Sb 2 Te 3 crystallize respectively; after the phase change film is crystallized for the first time, TiTe 2 always maintains the crystalline state, the TiTe 2 crystal nuclei are dispersedly distributed, and the TiTe 2 crystal structure is stable and does not interact with Sb 2 Te 3 A chemical reaction occurs; after the phase change film is crystallized for the first time, Sb 2 Te 3 can be repeatedly amorphized or crystallized.
  • the mismatch between the Sb 2 Te 3 crystal structure and the TiTe 2 crystal structure is low.
  • Sb 2 Te 3 When crystallized, the TiTe 2 crystal structure is used as a template to grow epitaxially, and the time for Sb 2 Te 3 to complete crystallization is relatively shortened.
  • the doping ratio x of the doping material TiTe 2 is controlled.
  • the larger the x the smaller the time required for Sb 2 Te 3 to complete crystallization when the phase change film is crystallized. , the smaller the crystallized Sb 2 Te 3 grain size is, and the higher the amorphous stability of the phase change film in the amorphous state.
  • the present invention provides a phase change memory, including: an upper electrode, a phase change layer, an insulating and thermal insulation layer, and a lower electrode;
  • the upper electrode is placed on the upper surface of the phase change layer
  • the lower electrode is placed on the lower surface of the phase change layer
  • the insulating and thermal insulation layer is placed around the phase change layer to isolate the phase change memory cells;
  • the phase change layer includes a phase change material and a doping material, the phase change material is Sb 2 Te 3 , the doping material is TiTe 2 , and the doping ratio of the doping material is x, 0 ⁇ x ⁇ 0.6.
  • phase change memory when the phase change memory is first set, TiTe 2 and Sb 2 Te 3 crystallize respectively. After that, TiTe 2 always remains in the crystalline state, the TiTe 2 crystal nuclei are dispersed, and the TiTe 2 crystal structure is unstable. Chemical reaction with Sb 2 Te 3 ;
  • phase change memory when the phase change memory is RESET, Sb 2 Te 3 changes from the crystalline state to the amorphous state; when the When the phase change memory SET is described, Sb 2 Te 3 changes from an amorphous state to a crystalline state.
  • the mismatch between the Sb 2 Te 3 crystal structure and the TiTe 2 crystal structure is low.
  • Sb 2 Te 3 crystallizes the TiTe 2 crystal structure is The template grows epitaxially, and the time for Sb 2 Te 3 to complete crystallization is relatively shortened, which makes the SET speed of the phase change memory relatively increased.
  • the invention provides a phase change film, a film preparation method and a phase change memory, which improves the amorphous stability of the Sb 2 Te 3 phase change material by doping the stable binary compound TiTe 2.
  • the amorphous stability of the phase change film of the present invention is significantly improved, effectively solving the current situation of insufficient stability of Sb 2 Te 3 amorphous film.
  • the ten-year data retention temperature of the phase change film of the present invention is significantly improved, effectively improving the data retention capability of Sb 2 Te 3 .
  • the grain size of the phase change film of the present invention is significantly reduced, shortening the time required for grain growth.
  • the present invention provides a phase change film, a film preparation method and a phase change memory.
  • the SET speed of the phase change memory of the present invention can be further improved.
  • the RESET power consumption of the phase change memory of the present invention is significantly reduced.
  • the resistance drift coefficient of the phase change memory of the present invention is significantly reduced.
  • the present invention provides a phase change film, a film preparation method and a phase change memory.
  • the present invention improves the SET speed of the Sb 2 Te 3 phase change memory without sacrificing Amorphous stability can even further improve its SET speed.
  • the present invention selects the stable binary compound TiTe 2 for doping. After doping, TiTe 2 and Sb 2 Te 3 crystallize separately without destroying the original properties of Sb 2 Te 3. of crystal structure.
  • Figure 1 shows the Sb 2 Te 3 , (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 and (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 phase change films measured in Example 3 of the present invention when the annealing temperature is 250°C. XRD result diagram;
  • Figure 2 shows the HRTEM results measured in Example 4 of the present invention.
  • (a) (b) (c) in Figure 2 are Sb 2 Te 3 , (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 and (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 phase change films respectively.
  • Figure 3 shows the SAED results measured in Example 4 of the present invention.
  • (a) (b) (c) in Figure 3 are Sb 2 Te 3 , (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 and (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 phase change films respectively.
  • Figure 4 shows Sb 2 Te 3 , (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 , (TiTe 2 ) 0.15 (Sb 2 Te 3 ) 0.85 , (TiTe 2 ) 0.25 (Sb 2 ) measured in Example 5 of the present invention .
  • Figure 5 shows the Arrhenis extrapolation of the Sb 2 Te 3 , (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 and (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 phase change films measured in Example 6 of the present invention. curve;
  • Figure 6 is a cross-sectional view of an exemplary structure of a phase change memory cell used in Embodiment 7 of the present invention.
  • Figure 7 shows the IV characteristic curves of Sb 2 Te 3 , (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 and (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 phase change memories measured in Embodiment 9 of the present invention
  • Figure 8 shows the SET speed results measured in Embodiment 10 of the present invention.
  • (a) (b) (c) in Figure 8 are Sb 2 Te 3 , (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 and (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 phase change memory SET VR relationship diagram of the process;
  • Figure 9 is a VR relationship diagram of the RESET process of the Sb 2 Te 3 , (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 and (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 phase change memory measured in Embodiment 11 of the present invention;
  • Figure 10 shows the resistance drift results measured in Embodiment 12 of the present invention.
  • (a) (b) (c) in Figure 10 are Sb 2 Te 3 , (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 and (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 phase change memory resistance. Resistance change curve with time.
  • the present invention provides a phase change film, a film preparation method and a phase change memory, which improves the amorphous stability of Sb 2 Te 3 by doping the stable binary compound TiTe 2 .
  • TiTe 2 and Sb 2 Te 3 are crystallized separately without destroying the original lattice structure of Sb 2 Te 3 .
  • the size of the crystal grains of the present invention is significantly reduced, shortening the time required for grain growth, thereby increasing the SET speed of the phase change memory.
  • TiTe 2 becomes a dispersed crystal nucleus.
  • TiTe 2 and Sb 2 Te 3 in the phase change film provided by the invention are crystallized respectively, and their chemical composition conforms to the general chemical formula (TiTe 2 ) x (Sb 2 Te 3 ) 1-x , x is the component ratio of TiTe 2 , and 0 ⁇ x ⁇ 0.6.
  • TiTe 2 has cubic structures, and the lattice constant of TiTe 2
  • the lattice constant of Sb 2 Te 3 is The difference in lattice constants is small, and the lattice mismatch between the two is about 11%, which is a small mismatch.
  • the melting point of TiTe 2 is higher, about 1500K, and the melting point of Sb 2 Te 3 is about 900K.
  • TiTe 2 has strong stability and remains crystalline during the amorphization process of Sb 2 Te 3 , and provides structurally stable crystal nucleus seeds during the crystallization process.
  • TiTe 2 has low thermal conductivity, which can effectively prevent heat loss.
  • TiTe 2 has a small resistivity and good electrical conductivity, which will not affect the current transport of the device.
  • the amorphous stability is significantly improved, the ten-year data retention temperature is significantly improved, and the data retention capability is significantly improved. As the TiTe 2 doping ratio increases, the data retention capability is further improved.
  • the RESET power consumption of the phase change memory provided by the present invention is significantly reduced. As the TiTe 2 doping ratio increases, RESET power consumption is further reduced.
  • the phase change memory provided by the present invention has a significantly reduced resistance drift coefficient. As the TiTe 2 doping ratio increases, the resistance drift coefficient further decreases.
  • the phase change memory cell structure includes a substrate, a lower electrode, a phase change material layer, and an upper electrode arranged above the substrate in sequence from bottom to top, and the phase change material is filled with insulating and heat-insulating materials to achieve horizontal electrical and thermal isolation.
  • the insulating and thermal insulation materials have low thermal conductivity.
  • the insulating and thermal insulation materials are silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, zinc oxide, tungsten oxide, titanium oxide, boron nitride and silicon carbide. Any kind.
  • the thickness of the phase change material layer is 2 nm to 300 nm.
  • the materials of the upper electrode and the lower electrode include metal elements Au, Ta, Pt, Al, W, Ti, Cu, Ir and their metal alloys and metal compounds, such as TiW and TiN.
  • the thickness of the material of the upper electrode and the lower electrode is 2 nm to 500 nm.
  • the invention provides a TiTe 2 doped Sb 2 Te 3 phase change film and a phase change memory, which effectively improves the amorphous stability of Sb 2 Te 3 and can further increase the SET speed of the memory device.
  • the memory device provided by the present invention also has the advantages of low power consumption and small resistance drift coefficient.
  • the AC power sputtering power of the Sb 2 Te 3 target was set to 30W, and the DC power sputtering power of the TiTe 2 target was set to 0W.
  • the sputtering time for 500s.
  • the grain size is about 10nm . Compared with Sb2Te3 film, the grain size is reduced by about 75%. When TiTe2 is doped 40%, the grain size is reduced to less than 10nm, or even up to 5nm . Compared with Sb2Te3 film, the grain size is reduced by about 87.5%. It can be seen that the ratio of the TiTe 2 -doped Sb 2 Te 3 phase change film to the pure Sb 2 Te 3 phase change film significantly reduces the grain size after crystallization and achieves the effect of refining the grains. The higher the TiTe 2 doping ratio, the smaller the grain size. This result is consistent with the above XRD results.
  • FIG. 3 Selected area electron diffraction is shown in Figure 3.
  • (a) (b) (c) are the selected electrons of Sb 2 Te 3 , (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 and (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 phase change films respectively. Diffraction pattern versus selected area electron diffraction pattern.
  • the crystal plane indices of Sb 2 Te 3 and TiTe 2 can be obtained from the analysis and correspond to the XRD results in Figure 1, further proving that Sb 2 Te 3 and TiTe 2 are crystallized respectively.
  • the reduction in grain size causes the selective electron diffraction rings to become diffuse.
  • the crystallization temperature of Sb 2 Te 3 is 103.8°C
  • the crystallization temperature of (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 is 124.7°C
  • the crystallization temperature of (TiTe 2 ) 0.15 (Sb 2 Te 3 ) 0.85 is 135.1°C
  • the crystallization temperature of (TiTe 2 ) 0.15 (Sb 2 Te 3 ) 0.85 is 150.9°C
  • the crystallization temperature of (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 is 178.0°C.
  • the (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 film can maintain data for ten years at 113°C, and the crystallization activation energy is 2.8eV.
  • Doping TiTe 2 can significantly increase the ten-year data retention temperature of Sb 2 Te 3 , and the greater the TiTe 2 doping concentration, the higher the ten-year data retention temperature.
  • the increase in ten-year data retention temperature shows that doping TiTe 2 can effectively improve the amorphous stability of Sb 2 Te 3 films, which is consistent with the above RT test results.
  • the greater the TiTe 2 doping ratio the better the amorphous stability.
  • the data retention time test can be divided into long-term test and accelerated test according to the test duration. Due to the length of the test, the present invention chooses accelerated testing, and obtains corresponding ten years of data through accelerated testing. Accelerated testing is to accelerate the failure of components or materials by increasing stress without changing the failure mechanism, thereby obtaining data such as data retention time under accelerated conditions in a short time, and then calculating the reliability characteristic quantities under normal stress conditions. .
  • the present invention provides a TiTe 2 doped Sb 2 Te 3 phase change memory, including a substrate 1, a lower electrode 2 arranged above the substrate from bottom to top, an insulating and thermal insulation material 3, and a phase change memory.
  • Variable layer 4 upper electrode 5.
  • the substrate 1 may be a silicon single-wafer substrate or other semiconductor material substrate.
  • the lower electrode 2 is a conductive material that requires low resistivity and stable properties. Materials such as TiW, TiN, HfN, Ag, Al, Cu, W, Ta, and Pt can be used.
  • the upper electrode 5 can be made of the same material as the lower electrode 2 .
  • the insulating and thermal insulation material 3 is required to have high resistivity, low thermal conductivity, and stable properties, and materials such as SiO 2 , ZrO 2 , Y 2 O 3 , and TiO 2 can be used.
  • the phase change layer 4 is a phase change material, which is required to have reversible phase change properties.
  • the material used in the present invention is (TiTe 2 ) x (Sb 2 Te 3 ) 1-x , where x is the percentage of TiTe 2 , and 0 ⁇ x ⁇ 0.6.
  • the lower electrode is made of Pt material.
  • high-purity argon gas is passed in as the sputtering gas.
  • the sputtering gas pressure is 0.5Pa and the power supply is 35W.
  • the thickness of the lower electrode is usually 10 nm to 300 nm.
  • the insulating layer is SiO 2 with a thickness of 100 nm.
  • EBL electron beam exposure system
  • ICP plasma etching technology
  • phase change material layers (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 and (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 in the square hole.
  • the thickness of the phase change material layer is 100nm.
  • High-purity argon was used as the sputtering gas, the argon gas flow rate was set to 80 sccm, and the sputtering gas pressure was 5 ⁇ 10 -1 Pa.
  • the same method was used to deposit the Sb 2 Te 3 phase change material layer in the control group.
  • the AC power sputtering power of the Sb 2 Te 3 target was set to 30W, and the DC power sputtering power of the TiTe 2 target was set to 0W.
  • the time is 500s, and the thickness of the phase change material layer is 100nm.
  • Magnetron sputtering is used to deposit the upper electrode, which is also made of Pt metal electrode material.
  • the phase change memory prepared in Example 7 was subjected to a DC IV test, and the test results are shown in Figure 7.
  • the Sb 2 Te 3 threshold current is 8 ⁇ A.
  • the threshold current is 28 ⁇ A, which is 2.5 times higher than that of pure Sb 2 Te 3 .
  • the threshold current of the phase change memory cell is 39 ⁇ A. Compared with pure Sb 2 Te 3 , the threshold current is increased by 3.875 times.
  • DC scanning converts the phase change memory cell from an amorphous state to a crystalline state.
  • the threshold current required during the conversion process is related to the amorphous stability of the phase change memory cell.
  • phase change memory prepared in Example 7 was subjected to a SET speed test, and the test results are shown in Figure 8.
  • Figure 8 (a) (b) (c) are respectively the SET process of Sb 2 Te 3 , (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 and (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 phase change memory. VR relationship diagram. Among them, the pulse width value of the minimum SET pulse signal that enables the phase change memory to complete the SET process is its SET speed.
  • the SET speed of Sb 2 Te 3 is 50ns
  • the SET speed of (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 is 50ns
  • the SET speed of (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 is 30ns.
  • doping TiTe 2 will not only not reduce the SET speed of the Sb 2 Te 3 phase change memory cell, but will further increase its SET speed. This shows that the Sb 2 Te 3 phase change memory cell doped with TiTe 2 can simultaneously improve amorphous stability and SET speed.
  • the mechanism analysis of the improvement of SET speed of Sb 2 Te 3 phase change memory cells doped with TiTe 2 can be started from two aspects.
  • film characterization can lead to the conclusion that doping TiTe 2 results in grain refinement. Reducing the grain size can shorten the time required for grain growth, thereby increasing the SET speed. As the proportion of doped TiTe 2 increases, the grain size further decreases and the SET speed further increases.
  • the melting point of TiTe 2 is very high, about 1500K, while the melting point of Sb 2 Te 3 is about 900K. Therefore, when Sb 2 Te 3 doped with TiTe 2 is completely crystallized and then transformed into an amorphous state, TiTe 2 still remains in the crystalline state.
  • TiTe 2 becomes a dispersed crystal nucleus inside the phase change material.
  • Sb 2 Te 3 can be epitaxially grown, thereby increasing the crystallization speed. The more TiTe 2 crystal nuclei there are, the smaller the Sb 2 Te 3 growth space is compressed, and the shorter the time required to complete crystallization.
  • the RESET power consumption test was performed on the phase change memory prepared in Example 7, and the test results are shown in Figure 9.
  • the results show that the RESET voltage of Sb 2 Te 3 is 1.27V and the required power consumption is 45pJ.
  • the RESET voltage of (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 is 0.47V, and the required power consumption is 2pJ. Compared with pure Sb 2 Te 3 , the RESET power consumption is reduced by 95.5%.
  • the TiTe 2 material selected in the present invention itself has low thermal conductivity. Doping TiTe 2 into Sb 2 Te 3 can effectively reduce the heat loss of the phase change layer, thereby reducing RESET power consumption.
  • phase change memory prepared in Example 7 was subjected to a resistance drift test, and the test results are shown in Figure 10.
  • Figure 10 (a) (b) (c) are the phase change memory resistor values of Sb 2 Te 3 , (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 and (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 respectively. Change curve over time. First, a SET pulse of 200ns pulse width and 100ns rising and falling edges is applied to the phase change memory cell to transform it into a crystalline state. Then apply a RESET pulse with a pulse width of 50ns and a rising and falling edge of 8ns to transform it into an amorphous state.
  • the resistance drift coefficient of the Sb 2 Te 3 phase change memory cell is 0.001, (TiTe 2 ) 0.1 (Sb 2 Te 3 ) 0.9 is 0.0006, and (TiTe 2 ) 0.4 (Sb 2 Te 3 ) 0.6 is 0.00004.
  • the resistance drift coefficient of TiTe-doped Sb 2 Te 3 phase change memory is significantly lower than Sb 2 Te 3 phase change memory.
  • the greater the TiTe 2 doping ratio the smaller the resistance drift coefficient.
  • Structural relaxation is the main source of resistance drift.
  • the size of the grains in the Sb 2 Te 3 phase change layer doped with TiTe 2 decreases, so the volume ratio occupied by the grain boundaries increases, and the greater the doping ratio, the greater the volume ratio occupied by the grain boundaries.
  • the existence of grain boundaries restricts the movement of phase change material atoms, thereby inhibiting structural relaxation near the grain boundaries.
  • the local structure of TiTe 2 that still maintains the crystalline state can be regarded as a pinning point inside the material, inhibiting the relaxation of the nearby amorphous Sb 2 Te 3 structure.
  • the higher the doping ratio of TiTe 2 the more obvious this suppression effect is. Therefore, doping TiTe 2 can effectively suppress the resistance drift of Sb 2 Te 3 phase change memory, and the greater the TiTe 2 doping ratio, the smaller the resistance drift coefficient.
  • this application compares the performance of traditional Sb 2 Te 3 and TiTe 2 -doped Sb 2 Te 3 phase change films and phase change memories, and demonstrates that doping TiTe 2 can achieve SET speed without sacrificing Sb 2 Te 3 Under the premise of improving its amorphous stability, it can even further improve its SET speed.
  • This patent also demonstrates that doping TiTe 2 can also effectively reduce the RESET power consumption of Sb 2 Te 3 phase change memory cells and suppress resistance drift.

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Abstract

本发明提供一种相变薄膜、薄膜制备方法及相变存储器，相变薄膜的化学组成符合化学通式(TiTe2)x(Sb2Te3)1-x，其中，x为TiTe2的百分比，且0＜x＜0.6。该相变薄膜与纯Sb2Te3相变薄膜相比，非晶稳定性明显提升，晶粒尺寸明显减小。随着TiTe2掺杂比例的增加，非晶稳定性进一步提升，晶粒尺寸进一步减小。将该相变薄膜应用于相变存储器中，可以在不牺牲Sb2Te3相变存储器SET速度的前提下提升非晶稳定性，甚至能进一步提高其SET速度。该相变存储器与纯Sb2Te3相变存储器相比，RESET功耗明显降低且能有效抑制电阻漂移。随着TiTe2掺杂比例的增加，RESET功耗进一步降低，电阻漂移系数进一步减小。

Description

一种相变薄膜、薄膜制备方法及相变存储器 【技术领域】
本发明属于微电子器件领域，更具体地，涉及一种相变薄膜、薄膜制备方法及相变存储器。
【背景技术】
人类活动离不开信息的传递与存储，存储器的发明让信息的存储密度越来越高。传统的DRAM具有擦写速度快、使用寿命长、易失等特点，FLASH具有低成本、非易失、擦写速度慢等特点。用户希望存储器同时具有DRAM的高速度、高寿命和FLASH的低成本、非易失的优点。相变存储器被认为是最有可能取代DRAM和FLASH的下一代非易失性存储设备之一，其具有存储速度快、可靠性高、使用寿命长等特点。
相变存储器是一种基于相变材料(一种或多种硫系化合物)的非易失性存储器，其主要是利用电流的焦耳热使材料在晶态和非晶态之间的转变来实现信息的存储。在相变存储器中，相变材料是关键的部分，这种材料在非晶态时阻值较高，在晶态时阻值较低，我们利用这种高低阻值的差异来实现“0”和“1”的信息存储。对晶态材料施加一个幅度大且持续时间短的电脉冲，由于幅度大能量高，材料能够很快达到熔化温度，失去晶态结构，但因为持续时间短又经过一个快速冷却的过程，原子还来不及重新排列，所以实现了材料从晶态到非晶态的转变；对非晶态材料施加一个幅度中等且持续时间较长的电脉冲，这个脉冲的能量能够让材料达到结晶温度而又低于熔化温度，在脉冲的持续时间内，原子能够重新排列结晶，实现材料从非晶态到晶态的转变。
Sb2Te3是生长主导结晶的相变材料，与成核主导结晶的Ge2Sb2Te5相比，SET速度较快，熔点较低，RESET功耗较小。然而，Sb2Te3的结晶温度很低， 约为100℃，非晶稳定性较差。研究人员通过掺杂的手法对Sb2Te3相变存储器进行优化。目前对Sb2Te3相变存储单元的研究多以掺杂单元素原子为主，研究表明掺杂单元素原子可以有效提升Sb2Te3的非晶稳定性，但一般会以牺牲SET速度为代价。此外，晶化过程中掺杂的原子大多会取代Sb或Te原子位置，破坏Sb2Te3原有的晶格结构。因此，发展同时具有高非晶稳定性和SET速度的新型掺杂Sb2Te3材料及其存储器对于提高相变存储器性能具有重要意义。
【发明内容】
针对现有技术的缺陷，本发明的目的在于提供一种相变薄膜、薄膜制备方法及相变存储器，旨在解决常规单元素掺杂使得Sb2Te3相变材料非晶稳定性提高但SET速度降低，以及常规单元素掺杂破坏Sb2Te3晶格结构的问题。
为实现上述目的，第一方面，本发明提供了一种相变薄膜，所述相变薄膜的化学通式为：(TiTe2)x(Sb2Te3)1-x，0＜x＜0.6。
在一个可选的示例中，所述相变薄膜被首次晶化时，TiTe2和Sb2Te3分别结晶；
所述相变薄膜被首次晶化后，TiTe2始终保持晶态，TiTe2晶核呈弥散分布，TiTe2晶体结构稳定，不与Sb2Te3发生化学反应；
所述相变薄膜被首次晶化后，Sb2Te3可被反复非晶化或晶化，Sb2Te3晶体结构与TiTe2晶体结构的失配度低，Sb2Te3被晶化时以TiTe2晶体结构为模板向外延生长，Sb2Te3完成晶化的时间相对缩短。
在一个可选的示例中，TiTe2掺杂比例x越大，Sb2Te3完成晶化所需的时间越小，晶化后的Sb2Te3晶粒尺寸越小，且所述相变薄膜处于非晶态的非晶稳定性越高。
第二方面，本发明提供了一种相变薄膜的制备方法，包括如下步骤：
确定待溅射的基片；
确定Sb2Te3靶材和TiTe2靶材，并将前述两种靶材置于待溅射的基片上方；
对上述两种靶材进行溅射，并通过控制两种靶材的溅射功率控制TiTe2的掺杂比例x，以在基片上沉积得到化学通式为(TiTe2)x(Sb2Te3)1-x的相变薄膜，0＜x＜0.6；其中，TiTe2作为相变薄膜的掺杂材料，Sb2Te3作为相变薄膜的相变材料，所述相变薄膜被首次晶化时，TiTe2和Sb2Te3分别结晶；所述相变薄膜被首次晶化后，TiTe2始终保持晶态，TiTe2晶核呈弥散分布，TiTe2晶体结构稳定，不与Sb2Te3发生化学反应；所述相变薄膜被首次晶化后，Sb2Te3可被反复非晶化或晶化，Sb2Te3晶体结构与TiTe2晶体结构的失配度低，Sb2Te3被晶化时以TiTe2晶体结构为模板向外延生长，Sb2Te3完成晶化的时间相对缩短。
在一个可选的示例中，控制所述掺杂材料TiTe2的掺杂比例x，所述x越大，所述相变薄膜进行晶化时Sb2Te3完成晶化所需的时间越小，晶化后的Sb2Te3晶粒尺寸越小，且所述相变薄膜处于非晶态的非晶稳定性越高。
第三方面，本发明提供了一种相变存储器，包括：上电极、相变层、绝缘绝热层以及下电极；
所述上电极置于相变层的上表面；
所述下电极置于相变层的下表面；
所述绝缘绝热层置于相变层的四周，在相变存储单元间起隔离作用；
所述相变层包括相变材料和掺杂材料，所述相变材料为Sb2Te3，掺杂材料为TiTe2，所述掺杂材料的掺杂比例为x，0＜x＜0.6。
在一个可选的示例中，当所述相变存储器首次SET时，TiTe2和Sb2Te3分别结晶，之后TiTe2始终保持晶态，TiTe2晶核呈弥散分布，TiTe2晶体结构稳定不与Sb2Te3发生化学反应；
随后，当所述相变存储器RESET时，Sb2Te3由晶态转变为非晶态；当所 述相变存储器SET时，Sb2Te3由非晶态转变为晶态，Sb2Te3晶体结构与TiTe2晶体结构的失配度低，Sb2Te3晶化时以TiTe2晶体结构为模板向外延生长，Sb2Te3完成晶化的时间相对缩短，使得相变存储器的SET速度相对提升。
在一个可选的示例中，TiTe2掺杂比例x越大，所述相变存储器的SET速度越快，RESET功耗越低，电阻漂移系数越小。
总体而言，通过本发明所构思的以上技术方案与现有技术相比，具有以下有益效果：
本发明提供一种相变薄膜、薄膜制备方法及相变存储器，通过掺杂稳定二元化合物TiTe2的方式提高Sb2Te3相变材料的非晶稳定性，对比Sb2Te3相变薄膜，本发明的相变薄膜非晶稳定性明显提升，有效解决Sb2Te3非晶稳定性不足的现状。对比Sb2Te3相变薄膜，本发明的相变薄膜十年数据保持温度明显提升，有效提升Sb2Te3的数据保持能力。对比Sb2Te3相变薄膜，本发明的相变薄膜晶粒尺寸明显减小，缩短了晶粒生长所需要的时间。
本发明提供一种相变薄膜、薄膜制备方法及相变存储器，对比Sb2Te3相变存储器，本发明的相变存储器SET速度可以进一步提高。对比Sb2Te3相变存储器，本发明的相变存储器RESET功耗明显降低。对比Sb2Te3相变存储器，本发明的相变存储器电阻漂移系数明显降低。
本发明提供一种相变薄膜、薄膜制备方法及相变存储器，对比单元素掺杂Sb2Te3的现有技术，本发明在不牺牲Sb2Te3相变存储器SET速度的前提下提升了非晶稳定性，甚至能进一步提高其SET速度。对比单元素掺杂Sb2Te3的现有技术，本发明选择稳定二元化合物TiTe2进行掺杂，掺杂之后的TiTe2和Sb2Te3分别结晶，不会破坏Sb2Te3原有的晶体结构。
【附图说明】
图1为本发明实施例3中所测退火温度为250℃时Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6相变薄膜的XRD结果图；
图2为本发明实施例4中所测HRTEM结果。其中，图2中(a)(b)(c)分别是Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6相变薄膜的高分辨图像；
图3为本发明实施例4中所测SAED结果。其中，图3中(a)(b)(c)分别是Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6相变薄膜的选区电子衍射图；
图4为本发明实施例5中所测Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9、(TiTe2)0.15(Sb2Te3)0.85、(TiTe2)0.25(Sb2Te3)0.75以及(TiTe2)0.4(Sb2Te3)0.6相变薄膜的R-T曲线；
图5为本发明实施例6中所测Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6相变薄膜的阿伦尼斯外推曲线；
图6为本发明实施例7使用的相变存储单元示范性结构剖视图；
图7为本发明实施例9所测Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6相变存储器I-V特性曲线；
图8为本发明实施例10所测SET速度结果。其中，图8中(a)(b)(c)分别是Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6相变存储器SET过程的V-R关系图；
图9为本发明实施例11所测Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6相变存储器RESET过程的V-R关系图；
图10为本发明实施例12所测电阻漂移结果。其中，图10中(a)(b)(c)分别是Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6相变存储器电阻阻值随时间的变化曲线。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
为实现上述目的，本发明提供了一种相变薄膜、薄膜制备方法及相变存储器，通过掺杂稳定二元化合物TiTe2的方式提高Sb2Te3的非晶稳定性。本发明的相变薄膜中，TiTe2和Sb2Te3分别结晶，不会破坏Sb2Te3原有的晶格结构。且本发明的晶粒尺寸明显减小，缩短了晶粒生长所需要的时间，从而提高相变存储器的SET速度。在相变材料的内部，TiTe2成为了弥散的晶核。以TiTe2为模板，可以外延生长Sb2Te3，从而提高结晶速度。TiTe2晶核越多，Sb2Te3生长空间被压缩的越小，完成结晶需要的时间也就越短。实验结果证明，稳定二元化合物TiTe2掺杂Sb2Te3相变存储单元可以在不牺牲SET速度的前提下提升Sb2Te3的非晶稳定性；同时，该相变存储器与纯Sb2Te3相变存储器相比，RESET功耗明显降低且能有效抑制电阻漂移。随着TiTe2掺杂比例的增加，RESET功耗进一步降低，电阻漂移系数进一步减小。
本发明提供的相变薄膜中TiTe2和Sb2Te3分别结晶，其化学组成符合化学通式(TiTe2)x(Sb2Te3)1-x，x为TiTe2的成分比例，且0＜x＜0.6。
本发明选择TiTe2作为掺杂材料的理由如下：第一，TiTe2和Sb2Te3均为立方结构，且TiTe2晶格常数Sb2Te3晶格常数为晶格常数相差较小，二者晶格失配度约为11％，失配度较小。第二，TiTe2熔点较高，约为1500K，Sb2Te3熔点约为900K。TiTe2稳定性较强，在Sb2Te3非晶化过程中仍保持晶态，并在晶化过程中提供结构稳定的晶核种子。第三，TiTe2热导率较低，可以有效防止热量散失。第四，TiTe2电阻率较小，导电性能较好，不会影响器件的电流输运。
本发明提供的相变薄膜与纯Sb2Te3相变薄膜对比，非晶稳定性明显提升，十年数据保持温度明显提高，数据保持能力明显提升。随着TiTe2掺杂比例的提高，数据保持能力进一步提高。
本发明提供的相变存储器与纯Sb2Te3相变存储器对比，RESET功耗明显降低。随着TiTe2掺杂比例的提高，RESET功耗进一步降低。
本发明提供的相变存储器与纯Sb2Te3相变存储器对比，电阻漂移系数明显减小。随着TiTe2掺杂比例的提高，电阻漂移系数进一步减小。
更进一步地，相变存储单元结构包括衬底，从下到上依次设置于所述衬底上方的下电极、相变材料层、上电极，相变材料周围填充绝缘绝热材料以实现水平方向上的电热隔离。
更进一步地，绝缘绝热材料具有较低的热导率，绝缘绝热材料为氧化硅、氮化硅、氧化铝、氮化铝、氧化锌、氧化钨、氧化钛、氮化硼和碳化硅中的任意一种。
更进一步地，相变材料层的厚度为2nm～300nm。
更进一步地，上电极和下电极的材料包括金属单质Au、Ta、Pt、Al、W、Ti、Cu、Ir及其金属合金和金属化合物，如TiW，TiN。
更进一步地，上电极和下电极的材料的厚度为2nm～500nm。
本发明提供了一种TiTe2掺杂Sb2Te3相变薄膜及相变存储器，有效提升Sb2Te3的非晶稳定性，且能进一步提高存储器件的SET速度。此外，本发明提供的存储器件还具有低功耗优势，以及电阻漂移系数小的优势。
为了更进一步的说明本发明提供的TiTe2掺杂Sb2Te3相变薄膜及相变存储器，以下结合具体实施例详述如下：
实施例1：
制备不同掺杂比例的(TiTe2)x(Sb2Te3)1-x及Sb2Te3相变薄膜，具体工艺流程如下：
(1)选取SiO2/Si(100)基片，将SiO2/Si(100)基片在丙酮溶液中用40W的功率超声15分钟，用于清洗表面、灰尘颗粒和有机杂质，再用去离子水冲洗；
(2)将处理后的基片在乙醇溶液中用40w的功率超声15分钟，用去离子水冲洗，高纯氮气吹干表面和背面，得到待溅射基片；
(3)应用双靶材共溅射方法，将Sb2Te3靶材和TiTe2靶材放在溅射仪的靶位上，其中，Sb2Te3采用射频溅射方法，TiTe2采用直流溅射方法；
(4)将待溅射基片固定在样品托盘上，密封溅射仪器腔体，关闭对外通气阀门；
(5)开启真空计和机械泵抽真空，待腔体内真空达到5Pa或以下时，启动分子泵，打开插板阀，抽真空至1×10-4Pa以下；
(6)将Sb2Te3靶材的交流电源溅射功率设置为26W，TiTe2靶材直流电源溅射功率依次设置为10W、15W、20W、25W，溅射时间为500s；
(7)使用高纯氩气作为溅射气体，氩气流量设为80sccm，溅射气压为5×10- 1Pa。
同时，采用同样的方法制备对照组Sb2Te3相变薄膜，将Sb2Te3靶材的交流电源溅射功率设置为30W，TiTe2靶材直流电源溅射功率设置为0W，溅射时间为500s。
实施例2：
对实施例1制备的(TiTe2)x(Sb2Te3)1-x相变薄膜进行EDS测试，Sb2Te3靶材的交流电源溅射功率为26W，根据EDS测试结果中Ti的原子百分比计算TiTe2靶材直流电源溅射功率依次为10W、15W、20W、25W的相变薄膜中TiTe2所占百分比依次是10％、15％、25％、40％。对实施例2制备的(TiTe2)x(Sb2Te3)1-x相变薄膜进行AFM测试，结果表明所制备薄膜厚度均为100nm左右。
实施例3：
制备200nm的纯Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6相变薄膜并在250℃下退火10min，然后进行XRD测试。XRD测试结果如图1所示。由图可知，TiTe2和Sb2Te3薄膜在28°、39°、49°的衍射峰峰值基本重合，说明二者具有外延生长的可能性。研究表明，TiTe2和Sb2Te3的失配率 约为11％，可以外延生长。从掺杂TiTe2的Sb2Te3薄膜XRD结果可以看出TiTe2和Sb2Te3分别结晶，这说明掺杂TiTe2不会破坏Sb2Te3原有的结构。对比掺杂TiTe2的Sb2Te3相变薄膜和纯Sb2Te3相变薄膜的XRD结果可知，掺杂后薄膜的衍射峰半高宽明显增大，这表明掺杂后薄膜晶粒尺寸明显减小。
实施例4：
在铜网上制备15nm的纯Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6相变薄膜并在280℃下退火10min，然后进行TEM测试。HRTEM测试结果如图2所示。图2中(a)(b)(c)分别是Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6相变薄膜的高分辨图像。经测量得出，纯Sb2Te3晶粒直径约为41.23nm。TiTe2掺杂10％时，晶粒尺寸约为10nm左右，与Sb2Te3薄膜相比，晶粒尺寸降低约75％。TiTe2掺杂40％时，晶粒尺寸降低到10nm以下，甚至可达5nm，与Sb2Te3薄膜相比，晶粒尺寸降低约87.5％。由此可知，掺杂TiTe2的Sb2Te3相变薄膜与纯Sb2Te3相变薄膜比，显著降低了结晶后晶粒尺寸，达到细化晶粒的效果。TiTe2掺杂比例越高，晶粒尺寸越小。这一结果与上述XRD结果相吻合。选区电子衍射如图3所示。图3中(a)(b)(c)分别是Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6相变薄膜的选区电子衍射图对选区电子衍射图。分析可得Sb2Te3以及TiTe2的晶面指数且与图1的XRD结果相对应，进一步证明Sb2Te3和TiTe2分别结晶。晶粒尺寸减小使得选区电子衍射环变得弥散。
实施例5：
制备200nm的Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9、(TiTe2)0.15(Sb2Te3)0.85、(TiTe2)0.25(Sb2Te3)0.75以及(TiTe2)0.4(Sb2Te3)0.6相变薄膜进行结晶温度测试，以10℃/min的速度升温到250℃，描绘不同掺杂浓度的相变薄膜R-T曲线，如图4所示。由图可知，Sb2Te3晶化温度为103.8℃，(TiTe2)0.1(Sb2Te3)0.9晶化温度为124.7℃，(TiTe2)0.15(Sb2Te3)0.85晶化温度为135.1℃， (TiTe2)0.15(Sb2Te3)0.85晶化温度为150.9℃，(TiTe2)0.4(Sb2Te3)0.6晶化温度为178.0℃。结果表明，掺杂TiTe2可以有效提高Sb2Te3的晶化温度，提升其非晶稳定性，弥补其非晶态稳定性不足的缺陷。且随着TiTe2掺杂浓度的提升，晶化温度也进一步提升，非晶稳定性越来越好。
实施例6：
制备200nm的Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9以及(TiTe2)0.4(Sb2Te3)0.6相变薄膜进行数据保持能力测试，结果如图5所示。由图可知，纯Sb2Te3薄膜可以在28℃下保持十年数据，结晶活化能为1.5eV。(TiTe2)0.1(Sb2Te3)0.9薄膜可以在62℃下保持十年数据，结晶活化能为2.5eV。(TiTe2)0.4(Sb2Te3)0.6薄膜可以在113℃下保持十年数据，结晶活化能为2.8eV。掺杂TiTe2可以明显提高Sb2Te3的十年数据保持温度，且TiTe2掺杂浓度越大，十年数据保持温度越高。十年数据保持温度的提升表明掺杂TiTe2可以有效提升Sb2Te3薄膜的非晶稳定性，这与上述R-T测试结果相吻合。且TiTe2掺杂比例越大，非晶稳定性越好。同时，这也进一步说明掺杂TiTe2可以有效提升Sb2Te3相变存储单元的数据保持能力。
需要说明的是，根据测试时长的不同可将数据保持时间测试分为长期测试和加速测试。由于测试时长的原因，本发明选择的是加速测试，通过加速测试获得对应的十年数据。加速测试是在不改变失效机理的情况下，通过增加应力来加速部件或材料的失效，从而在短时间内获得加速条件下的数据保持时间等数据，然后计算正常应力条件下的可靠性特征量。
实施例7：
如图6所示，本发明提供了一种TiTe2掺杂Sb2Te3相变存储器，包括衬底1，从下到上依次设置于衬底上方的下电极2、绝缘绝热材料3、相变层4、上电极5。
具体地，衬底1可以采用硅单晶片衬底或者其他半导体材料衬底。
具体地，下电极2为导电材料，要求电阻率低，性质稳定，可以采用TiW、TiN、HfN、Ag、Al、Cu、W、Ta、Pt等材料。上电极5可采用与下电极2相同的材料。
具体地，绝缘绝热材料3，要求其电阻率高、热导率低、性质稳定，可以采用SiO2、ZrO2、Y2O3、TiO2等材料。
具体地，相变层4为相变材料，要求其具有可逆相变的性质，本发明采用的材料为(TiTe2)x(Sb2Te3)1-x，其中，x为TiTe2的百分比，且0＜x＜0.6。
实施例8：
根据实施例7的相变存储单元结构，制备不同掺杂比例的(TiTe2)0.1(Sb2Te3)0.9、(TiTe2)0.4(Sb2Te3)0.6及Sb2Te3相变存储器，具体工艺流程如下：
(1)选取SiO2/Si(100)基片，将SiO2/Si(100)基片在丙酮溶液中用40W的功率超声15分钟，用于清洗表面、灰尘颗粒和有机杂质，再去离子水冲洗。
(2)将处理后的基片在乙醇溶液中用40w的功率超声15分钟，用去离子水冲洗，高纯氮气吹干表面和背面，得到待溅射基片。
(3)使用磁控溅射法将下电极生长于衬底上，该下电极使用Pt材料，制备时通入高纯氩气作为溅射气体，溅射气压为0.5Pa，电源功率为35W，该下电极厚度通常为10nm～300nm。
(4)利用物理气相沉积(PECVD)方法在下电极上沉积绝缘层，绝缘层为SiO2，厚度为100nm。
(5)利用匀胶机在绝缘层上均匀平铺一层光刻胶。
(6)利用电子束曝光系统(EBL)在绝缘层上形成带250nm直径的圆形小孔的光刻胶掩膜。
(7)利用等离子体刻蚀技术(ICP)刻蚀绝缘层，由于被光刻胶覆盖的部分受到保护，不会被刻蚀，而没有光刻胶覆盖的部分暴露在外会被刻蚀掉，直 到露出下电极。
(8)利用去胶液去除光刻胶。
(9)利用紫外光刻系统在小孔上套刻出100μm×100μm的方形孔结构。该方形孔与ICP刻蚀出的圆形小孔中心对准。
(10)在方形孔内利用磁控溅射沉积出相变材料层(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6。抽真空至1×10-4Pa以下，将Sb2Te3靶材的交流电源溅射功率设置为26W，TiTe2靶材直流电源溅射功率依次设置为10W和25W，溅射时间为500s，相变材料层厚度为100nm。使用高纯氩气作为溅射气体，氩气流量设为80sccm，溅射气压为5×10-1Pa。同时，采用同样的方法沉积对照组Sb2Te3相变材料层，将Sb2Te3靶材的交流电源溅射功率设置为30W，TiTe2靶材直流电源溅射功率设置为0W，溅射时间为500s，相变材料层厚度为100nm。
(11)利用磁控溅射沉积上电极，上电极同样为Pt金属电极材料。
(12)利用剥离工艺去除紫外光刻的光刻胶。
实施例9：
对实施例7制备的相变存储器进行直流I-V测试，测试结果如图7所示。由图可见，Sb2Te3阈值电流为8μA。(TiTe2)0.1(Sb2Te3)0.9阈值电流为28μA，与纯Sb2Te3相比，阈值电流提高了2.5倍。(TiTe2)0.4(Sb2Te3)0.6相变存储单元阈值电流为39μA，与纯Sb2Te3相比，阈值电流提高了3.875倍。直流扫描将相变存储单元从非晶态转变为晶态，转变过程中所需的阈值电流与相变存储单元的非晶稳定性有关。阈值电流越大，相变存储单元的非晶稳定性越好。所以，掺杂TiTe2可以增大Sb2Te3相变存储单元的阈值电流，从而增强其非晶稳定性。并且，随着掺杂浓度的增加，阈值电流进一步增大，相变存储单元的非晶稳定性进一步提升。这与R-T测试结果以及十年数据保持时间测试结果相吻合。
实施例10：
对实施例7制备的相变存储器进行SET速度测试，测试结果如图8所示。图8中(a)(b)(c)分别是Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6相变存储器SET过程的V-R关系图。其中，能够使相变存储器完成SET过程的最小SET脉冲信号的脉宽值即为其SET速度。由图8可见，Sb2Te3的SET速度为50ns，(TiTe2)0.1(Sb2Te3)0.9的SET速度为50ns，(TiTe2)0.4(Sb2Te3)0.6的SET速度为30ns。由此得出结论：掺杂TiTe2不仅不会降低Sb2Te3相变存储单元的SET速度，反而还会进一步提升其SET速度。这说明掺杂TiTe2的Sb2Te3相变存储单元可以同时提升非晶稳定性和SET速度。
对掺杂TiTe2的Sb2Te3相变存储单元SET速度提高的机理分析可以从两方面入手。一方面，通过膜表征可以得出掺杂TiTe2使得晶粒细化这一结论。晶粒尺寸减小可以缩短晶粒生长所需要的时间，从而提高SET速度。掺杂TiTe2的比例增大，晶粒尺寸进一步减小，SET速度进一步提高。另一方面，由于TiTe2的熔点很高，约为1500K，而Sb2Te3的熔点约为900K。所以掺杂TiTe2的Sb2Te3完全结晶再转变为非晶态的时候，TiTe2仍保持晶态。此时，在相变材料的内部，TiTe2成为了弥散的晶核。以TiTe2为模板，可以外延生长Sb2Te3，从而提高结晶速度。TiTe2晶核越多，Sb2Te3生长空间被压缩的越小，完成结晶需要的时间也就越短。
实施例11：
对实施例7制备的相变存储器进行RESET功耗测试，测试结果如图9所示。设置RESET脉宽为50ns，上升沿和下降沿都为8ns，每隔1ms幅值增加100mV，并读取一次电阻阻值。结果显示，Sb2Te3的RESET电压为1.27V，所需的功耗为45pJ。(TiTe2)0.1(Sb2Te3)0.9的RESET电压为0.47V，所需的功耗为2pJ，与纯Sb2Te3相比，RESET功耗降低了95.5％。(TiTe2)0.4(Sb2Te3)0.6的RESET电压为0.37V，所需的功耗为0.55pJ，与纯Sb2Te3 相变存储单元相比，RESET功耗降低了98.7％。对比可以得出掺杂TiTe2有效降低Sb2Te3相变过程中所需的功耗，且掺杂浓度越高，功耗越低。
通过薄膜表征可以得出掺杂TiTe2使得晶粒细化这一结论，晶粒细化可以减小相变区域，提高热量的利用效率，达到降低功耗的效果。研究表明，常见的Ge2Sb2Te5、Sb2Te3及其掺杂体系的晶粒尺寸和热导率之间呈近似线性关系，Ge2Sb2Te5、Sb2Te3及其掺杂体系的晶粒尺寸越小，热导率越小。所以，掺杂TiTe2的Sb2Te3相变存储单元晶粒尺寸减小，热导率也减小。随着TiTe2掺杂比例的增加，热导率进一步降低。研究表明，导热性是降低功耗的关键。导热性控制着热传输以及热损失。使用相同的热源，热导率降低，热量散失减少，工作区域的温度升高，达到相同熔化温度所需的热量减小，RESET功耗也就随之降低。本发明选择的TiTe2材料本身就具有较低的热导率，在Sb2Te3中掺杂TiTe2可以有效减少相变层的热量散失，进而降低RESET功耗。
实施例12：
对实施例7制备的相变存储器进行电阻漂移测试，测试结果如图10所示。图10中(a)(b)(c)分别是Sb2Te3、(TiTe2)0.1(Sb2Te3)0.9和(TiTe2)0.4(Sb2Te3)0.6相变存储器电阻阻值随时间的变化曲线。先对相变存储单元施加200ns脉宽，100ns上升、下降沿的SET脉冲，使其转变为晶态。然后施加50ns脉宽，8ns上升、下降沿的RESET脉冲，使其转变为非晶态。循环操作后，分别对晶态和非晶态相变存储单元施加100mV的小电压，并持续读取电阻阻值。每隔6ms读取一次电阻阻值，一共读取50000次，累计时长为3000s。计算得到非晶态时，Sb2Te3相变存储单元电阻漂移系数为0.003，(TiTe2)0.1(Sb2Te3)0.9为0.001，(TiTe2)0.4(Sb2Te3)0.6为0.0007。晶态时，Sb2Te3相变存储单元电阻漂移系数为0.001，(TiTe2)0.1(Sb2Te3)0.9为0.0006，(TiTe2)0.4(Sb2Te3)0.6为0.00004。
对比可知，掺杂TiTe2的Sb2Te3相变存储器的电阻漂移系数明显低于 Sb2Te3相变存储器。且TiTe2掺杂比例越大，电阻漂移系数越小。对其机理分析如下：结构弛豫是电阻漂移的主要来源。掺杂TiTe2的Sb2Te3相变层中晶粒尺寸减小，因此晶界所占体积比增加，且掺杂比例越大，晶界所占体积比越大。晶界的存在限制了相变材料原子的移动，从而抑制了晶界附近的结构弛豫。相变材料呈非晶态时，仍保持晶态的TiTe2局部结构可以看作是材料内部的钉扎点，抑制附近的非晶态Sb2Te3结构弛豫。TiTe2的掺杂比例越高，这种抑制效果越明显。所以，掺杂TiTe2可以有效抑制Sb2Te3相变存储器的电阻漂移，且TiTe2掺杂比例越大，电阻漂移系数越小。
本申请从实际制备出发，对比传统Sb2Te3和掺杂TiTe2的Sb2Te3相变薄膜及相变存储器的性能，论证了掺杂TiTe2可以在不牺牲Sb2Te3的SET速度的前提下提升其非晶稳定性，甚至能进一步提高其SET速度。本专利还论证了掺杂TiTe2还可以有效降低Sb2Te3相变存储单元的RESET功耗并且能抑制电阻漂移。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (8)

  1. 一种相变薄膜，其特征在于，所述相变薄膜的化学通式为：(TiTe2)x(Sb2Te3)1-x，0＜x＜0.6。
  2. 根据权利要求1所述的相变薄膜，其特征在于，所述相变薄膜被首次晶化时，TiTe2和Sb2Te3分别结晶；
    所述相变薄膜被首次晶化后，TiTe2始终保持晶态，TiTe2晶核呈弥散分布，TiTe2晶体结构稳定，不与Sb2Te3发生化学反应；
    所述相变薄膜被首次晶化后，Sb2Te3可被反复非晶化或晶化，Sb2Te3晶体结构与TiTe2晶体结构的失配度低，Sb2Te3被晶化时以TiTe2晶体结构为模板向外延生长，Sb2Te3完成晶化的时间相对缩短。
  3. 根据权利要求1或2所述的相变薄膜，其特征在于，TiTe2掺杂比例x越大，Sb2Te3完成晶化所需的时间越小，晶化后的Sb2Te3晶粒尺寸越小，且所述相变薄膜处于非晶态的非晶稳定性越高。
  4. 一种相变薄膜的制备方法，其特征在于，包括如下步骤：
    确定待溅射的基片；
    确定Sb2Te3靶材和TiTe2靶材，并将前述两种靶材置于待溅射的基片上方；
    对上述两种靶材进行溅射，并通过控制两种靶材的溅射功率控制TiTe2的掺杂比例x，以在基片上沉积得到化学通式为(TiTe2)x(Sb2Te3)1-x的相变薄膜，0＜x＜0.6；其中，TiTe2作为相变薄膜的掺杂材料，Sb2Te3作为相变薄膜的相变材料，所述相变薄膜被首次晶化时，TiTe2和Sb2Te3分别结晶；所述相变薄膜被首次晶化后，TiTe2始终保持晶态，TiTe2晶核呈弥散分布，TiTe2晶体结构稳定，不与Sb2Te3发生化学反应；所述相变薄膜被首次晶化后，Sb2Te3可被反复非晶化或晶化，Sb2Te3晶体结构与TiTe2晶体结构的失配度低，Sb2Te3被晶化时以TiTe2晶体结构为模板向外延生长，Sb2Te3完成晶化的时 间相对缩短。
  5. 根据权利要求4所述的制备方法，其特征在于，控制所述掺杂材料TiTe2的掺杂比例x，所述x越大，所述相变薄膜进行晶化时Sb2Te3完成晶化所需的时间越小，晶化后的Sb2Te3晶粒尺寸越小，且所述相变薄膜处于非晶态的非晶稳定性越高。
  6. 一种相变存储器，其特征在于，包括：上电极、相变层、绝缘绝热层以及下电极；
    所述上电极置于相变层的上表面；
    所述下电极置于相变层的下表面；
    所述绝缘绝热层置于相变层的四周，在相变存储单元间起隔离作用；
    所述相变层包括相变材料和掺杂材料，所述相变材料为Sb2Te3，掺杂材料为TiTe2，所述掺杂材料的掺杂比例为x，0＜x＜0.6。
  7. 根据权利要求6所述的相变存储器，当所述相变存储器首次SET时，TiTe2和Sb2Te3分别结晶，之后TiTe2始终保持晶态，TiTe2晶核呈弥散分布，TiTe2晶体结构稳定不与Sb2Te3发生化学反应；
    随后，当所述相变存储器RESET时，Sb2Te3由晶态转变为非晶态；当所述相变存储器SET时，Sb2Te3由非晶态转变为晶态，Sb2Te3晶体结构与TiTe2晶体结构的失配度低，Sb2Te3晶化时以TiTe2晶体结构为模板向外延生长，Sb2Te3完成晶化的时间相对缩短，使得相变存储器的SET速度相对提升。
  8. 根据权利要求7所述的相变存储器，其特征在于，TiTe2掺杂比例x越大，所述相变存储器的SET速度越快，RESET功耗越低，电阻漂移系数越小。
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