[go: up one dir, main page]

WO2023098545A1 - Packaging structure for large-current power semiconductor device and packaging method therefor - Google Patents

Packaging structure for large-current power semiconductor device and packaging method therefor Download PDF

Info

Publication number
WO2023098545A1
WO2023098545A1 PCT/CN2022/133852 CN2022133852W WO2023098545A1 WO 2023098545 A1 WO2023098545 A1 WO 2023098545A1 CN 2022133852 W CN2022133852 W CN 2022133852W WO 2023098545 A1 WO2023098545 A1 WO 2023098545A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
conductive film
chip base
electrode
packaging
Prior art date
Application number
PCT/CN2022/133852
Other languages
French (fr)
Chinese (zh)
Inventor
杨洋
邱松
姚建军
Original Assignee
无锡华润华晶微电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润华晶微电子有限公司 filed Critical 无锡华润华晶微电子有限公司
Publication of WO2023098545A1 publication Critical patent/WO2023098545A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for individual devices of subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a packaging structure and a packaging method for high-current power semiconductor devices.
  • FIG. 1 is a schematic structural diagram of the existing miniaturized packaging structure of MOSFET devices.
  • the miniaturized packaging process of MOSFET devices in the prior art is as follows: a metal frame is used as a base, and then the chip is flipped on the metal frame through a material with a low curing temperature such as conductive glue. For the chip mounting, after that, the front side of the flipped chip is drawn through the wire in the wire bonding through the wire bonding process to electrically connect the pads of the chip to other circuits or internal pins on the PCB.
  • the miniaturized packaging process in the prior art needs to use materials such as conductive adhesives with low curing temperature and low bonding strength to seal the chip and the metal frame, a vacuum is required when the chip is sealed and solidified.
  • Environment which requires high equipment, and there is no protection around the chip (there is no plastic packaging process in the miniaturized packaging process in the prior art), all five sides of the chip are exposed to the environment, and the existing miniaturized package
  • the wire bonding process in the process can also lead to the problem of high package resistance and parasitic inductance. Therefore, the existing miniaturized package process of MOSFET devices cannot be suitable for high-reliability application environments.
  • the object of the present invention is to provide a packaging structure and packaging method for high-current power semiconductor devices, so as to reduce packaging resistance and parasitic inductance under the condition of being suitable for high-reliability application environments.
  • the present invention provides a packaging structure of a high-current power semiconductor device, including:
  • the lead structure has a plurality of chip base islands and a plurality of electrode bumps located on the periphery of the lead structure corresponding to each chip base island;
  • a plurality of chips each of which is provided with a source and a gate on the front, and a drain on the back, the plurality of chips are arranged in one-to-one correspondence with the plurality of chip base islands, and each The drains on the back of each chip are mounted on the corresponding chip base island;
  • a conductive film part of which is arranged between the drain of each chip and its corresponding chip base island, so that the drain of each chip is electrically connected to the periphery of the lead structure corresponding to the corresponding chip base island a plurality of electrode bumps, and another part of the conductive film is arranged between the source and gate of each chip and the external PCB board, so that the source and gate of each chip are directly electrically connected to the The PCB board;
  • a layer of plastic encapsulation material, each of the chip base islands and the gap between the chip and the conductive film pasted therein is provided with the plastic encapsulation material layer, so as to bury the chip in each chip base island that is not covered by the conductive film. covered surface.
  • the material of the conductive film may include solder paste.
  • the chip may include a power MOSFET chip.
  • the material of the molding material layer may include a cured material selected from polyimide, silica gel and epoxy resin.
  • each of the chip base islands may be plate-shaped and stacked with the chips, and each of the chip base islands extends outward on both sides in the length direction to form an airfoil connection part, and Each of the airfoil connection parts extends outward in the length direction of the chip substrate island to form at least two first electrode bumps spaced apart from each other, and the first electrode bumps are connected to the plate-shaped chip substrate.
  • the islands are not coplanar.
  • At least two second electrode bumps that are spaced apart from each other and coplanar with the plate-shaped chip base island can be formed on both sides of each chip base island in the width direction extending outward.
  • the material of the lead frame may be metal.
  • the present invention also provides a packaging method, comprising the following steps:
  • the lead structure in the packaging structure of the high-current power semiconductor device as described above, has a plurality of chip base islands and a plurality of electrode bumps located on the periphery of the lead structure corresponding to each chip base island;
  • a plurality of chips are provided, each chip is provided with a source and a gate on the front, and a drain on the back;
  • Each of the chips is respectively bonded on a chip base island in the lead structure, so that the drain disposed on the back side of the chip is electrically connected to a plurality of surrounding lead structures corresponding to the corresponding chip base island. electrode bumps exposing the front side of each of said chips;
  • a plastic encapsulation material layer is formed to bury the surface of the chip in each chip base island that is not covered by the conductive film.
  • the step of bonding each of the chips on a chip base island in the lead structure may include:
  • the process of forming a conductive film on the surface of the source electrode and the gate electrode on the front side of each chip as an electrode bump externally connected to the PCB includes a stencil brushing process and a reflow soldering process.
  • the material of the conductive film may include solder paste
  • the material of the molding material layer may include a cured material selected from polyimide, silica gel and epoxy resin.
  • the encapsulation method provided by the present invention may also include the following steps:
  • the mass production of the high-current power semiconductor device is realized by using the lead frame as the substrate of the packaging process; and because in the packaging structure provided by the present invention, each A plurality of electrode bumps are arranged on the periphery of the lead structure corresponding to the chip base island where the chip is installed to realize the electrical extraction of the drain on the back of the chip, and electrode bumps are formed on the surface of the source and gate of the chip. Solder paste, to achieve the electrical lead-out of the source and gate of each chip, and direct electrical connection with the external PCB board, so that there is no need to set up leads between the chip and the PCB board for electrical connection, thereby reducing the packaging structure package resistance and parasitic inductance.
  • each chip after mounting is plastic-encapsulated and solidified by using a conductive film made of epoxy resin, so that the six surfaces of the chips pasted on each chip base island are uniform. protected, thereby meeting the design requirements for high-reliability application environments.
  • Fig. 1 is a structural schematic diagram of a miniaturized package structure of a MOSFET device provided in the prior art
  • FIG. 2 is a top view of a lead frame provided in an embodiment of the present invention.
  • FIG. 3 is a side view of a chip base island and electrode bumps arranged around it in the lead structure provided in FIG. 2;
  • FIG. 4 is a schematic structural diagram of the package structure corresponding to each chip package provided in an embodiment of the present invention.
  • FIG. 5 is a schematic flowchart of a packaging method for a packaging structure of a high-current power semiconductor device provided in an embodiment of the present invention
  • 6a to 6e are structural schematic diagrams of a packaging structure of a high-current power semiconductor device provided in an embodiment of the present invention during the manufacturing process;
  • 1-lead structure 2-chip, 31/32/33-conductive film (solder paste), 4/4'-molding material layer, 10-chip base island, 11-electrode bump, 11a-first electrode bump , 11b—the second electrode bump, 5—the electroplating tin layer.
  • FIG. 1 is a schematic structural diagram of the existing miniaturized packaging structure of MOSFET devices.
  • the miniaturized packaging process of MOSFET devices in the prior art is as follows: a metal frame is used as a base, and then the chip is flipped on the metal frame through a material with a low curing temperature such as conductive glue. After the chip is mounted, the front side of the flipped chip is led out to other circuits or internal leads on the PCB through the wires (not shown) in the wire bonding through the wire bonding process. Foot connection.
  • the miniaturized packaging process in the prior art needs to use materials such as conductive adhesives with low curing temperature and low bonding strength to seal the chip and the metal frame, a vacuum is required when the chip is sealed and solidified.
  • Environment which requires high equipment, and there is no protection around the chip (there is no plastic packaging process in the miniaturized packaging process in the prior art), all five sides of the chip are exposed to the environment, and the existing miniaturized package
  • the wire bonding process in the process can also lead to the problem of high package resistance and parasitic inductance. Therefore, the existing miniaturized package process of MOSFET devices cannot be suitable for high-reliability application environments.
  • the present invention provides a packaging structure and packaging method for high-current power semiconductor devices, so as to reduce packaging resistance and parasitic inductance under the condition of being suitable for high-reliability application environments.
  • the packaging structure of the high-current power semiconductor device provided by the present invention will be introduced below.
  • FIG. 2 is a top view of a lead structure provided in an embodiment of the present invention
  • Fig. 3 is a chip base island and its peripheral arrangement in the lead structure provided in Fig. 2
  • FIG. 4 is a schematic structural diagram of the package structure corresponding to each chip package provided in an embodiment of the present invention.
  • the packaging structure provided by the present invention may include a lead frame 1 as a substrate for pasting multiple chips, and the material of the lead frame 1 may be metal, such as gold, copper and other metals.
  • the lead frame 1 can slice multiple chips at the same time, therefore, it can include multiple chip base islands 10 and multiple electrode bumps 11 located on the periphery of the lead frame corresponding to each chip base island 10 .
  • the packaging structure provided by the present invention, it can also have a plurality of chips, each of the chips is provided with a source and a gate on the front, and a drain on the back, and the plurality of chips and the A plurality of chip base islands 10 are provided in one-to-one correspondence, and the drain on the back of each chip is attached to the corresponding chip base island 10 .
  • each of the chip base islands 10 is plate-shaped and stacked with the chips, and each of the chip base islands 10 extends outward on both sides in the length direction to form an airfoil connection. 12, and each airfoil connecting portion 12 extends outward in the length direction of the chip base island 10 to form at least two first electrode bumps 11a spaced apart from each other, and the first electrode bumps 11a is not coplanar with the plate-shaped chip base island 10 .
  • at least two second electrode bumps 11b that are spaced apart from each other and coplanar with the plate-shaped chip base island 10 are respectively formed extending outward on both sides in the width direction of each chip base island 10 .
  • an embodiment of the present invention also provides a structural schematic diagram of the corresponding packaging structure of each chip after packaging.
  • the back of the chip 2 faces the chip base island 10, and a conductive film 31 with adhesiveness on both sides is arranged between the back of the chip 2 and the chip base island 10, for
  • the drain on the back of the chip 2 is electrically connected to a plurality of first electrode bumps 11a on the periphery of the lead structure corresponding to the corresponding chip base island 10; All have the conductive film 32 of stickiness, and the conductive film 33 that all has stickiness on both sides is formed on the surface of the source electrode of the front side of described chip 2, and will stick on the source electrode of the front side of described chip 2
  • the conductive films 32 and 33 on the surface of the drain electrode are used as electrode bumps, so that the source electrode and the gate electrode of the chip 2 are directly electrically connected to an external PCB board.
  • the packaging structure further includes a molding material layer 4, and the molding material layer 4 is located between the chip base island 10 and the chips 2 and conductive films 31, 32 and 33 pasted therein. to bury the surface of the chip 2 in the chip base island 10 that is not covered by the conductive films 31 , 32 and 33 .
  • the material of the conductive films 31, 32 and 33 can be solder paste; the chip 2 can be a power MOSFET chip; the material of the plastic packaging material layer 4 includes one of polyimide, silica gel and epoxy resin. a solidified material.
  • the material of the molding material layer in the embodiment of the present invention is epoxy resin. It can be seen that the packaging structure of the high-current power semiconductor device provided by the present invention is composed of various materials such as lead frame, solder paste (conductive film), chip, and epoxy resin molding material layer.
  • a passivation layer may also be formed on the surface of each of the chips 2 to prevent each of the chips from The front and back (surface) of 2 are contaminated.
  • the packaging structure provided by the present invention is to carry out flip-chip splitting of the chip, so that the external PCB board can brush the welding material according to the electrode window on the gate and source surface on the front of the chip, so as to realize the reverse buckle reflow of the product welding.
  • both sides in the length direction of the chip base island extend outward to form an airfoil connection part respectively, and each of the airfoil connection parts is within the length of the chip base island Extend outward in the direction to form at least two first electrode bumps that are spaced apart from each other, which can conduct the electrode (drain) on the back of each chip to the welding surface. Mass production.
  • the packaging form provided by the present invention exposes the electrode bumps, and the first electrode bumps and the front of the chip are on the same plane, therefore, when forming the electrode bumps provided by the present invention
  • the packaging structure needs to be plastic-sealed first, and then ground to ensure the flatness of the product and the exposure of the electrode bumps.
  • the material of the lead frame provided by the present invention is metal, it can meet heat dissipation requirements, and manufacturers can also install heat sinks if conditions permit. Due to the support of the first electrode bumps, the packaging structure provided by the present invention can also withstand relatively large mechanical forces.
  • the packaging structure provided by the present invention has a plastic packaging material layer, so that the six sides of the chip are protected by plastic packaging, which can meet the high reliability requirements.
  • the present invention is to make the electrode bump that connects its gate and source on the front of the chip with brush solder paste, so the chip will carry out Ni/Au/Cu chemical plating or electroplating pad and reasonable Passivate the layout, and then use the molding effect of the solder paste to make bumps.
  • the process is simpler and the chip can be bonded to the frame. It is completed together with bump production, and also avoids the problems caused by suction bumps during film loading.
  • the packaging structure provided by the present invention adopts solder paste (conductive film) as the material for pasting the chip and the chip base island, therefore, avoiding the low curing temperature and low bonding strength of using conductive glue in the prior art
  • solder paste conductive film
  • the packaging structure provided by the present invention is that the material formed on the front side of the chip is an electrode bump of solder paste, and the front side of the chip on the lead frame is directly flip-mounted on the PCB board without the lead wire connection. Low on-resistance compared to conventional wire bonded packages.
  • the present invention also provides a packaging method, which may specifically include the following steps:
  • Step S100 providing the lead structure in the packaging structure of the high-current power semiconductor device provided by the present invention
  • the lead structure has a plurality of chip base islands 10 and a plurality of electrode bumps located on the periphery of the lead structure corresponding to each chip base island piece.
  • step S200 a plurality of chips are provided, each chip is provided with a source and a gate on the front, and a drain on the back.
  • Step S300 bonding each of the chips to a chip base island in the lead structure, so that the drain disposed on the back of the chip is electrically connected to the lead structure 1 corresponding to the corresponding chip base island a plurality of electrode bumps on the periphery, and expose the front side of each chip.
  • Step S400 forming a conductive film on the surface of the source and gate on the front side of each chip, and using the conductive film as the source and gate of each chip to be directly electrically connected to the electrodes of the external PCB board bump.
  • Step S500 forming a plastic encapsulation material layer to bury the surface of the chip in each chip base island not covered by the conductive film.
  • step S100 specifically referring to FIG. 6a, the lead frame 1 in the packaging structure of the high-current power semiconductor device provided by the present invention is provided, wherein the lead frame 1 has a plurality of chip base islands 10 and is located in each The chip base island 10 corresponds to a plurality of electrode bumps 11 on the periphery of the lead frame 1 .
  • step S200 a plurality of chips 2 are provided, each chip 2 is provided with a source and a gate on the front, and a drain on the back.
  • step S300 continuing to refer to FIG. 6a and in conjunction with FIG. 6c, each of the chips 2 is respectively bonded on a chip base island 10 in the lead frame 1, so that the chips 2
  • the drain on the back is electrically connected to a plurality of electrode bumps 11 on the periphery of the lead structure 1 corresponding to the corresponding chip base island 10 , and exposes the front of each chip 2 .
  • the present invention provides a specific method of bonding each of the chips 2 to a chip base island 10 in the lead frame 1, which may include the following steps:
  • Step S301 forming a conductive film on the surface of each chip base, and bonding the back surface of the chip 2 to the upper surface of the conductive film, and the upper and lower surfaces of the conductive film are both adhesive.
  • Step S302 paste the chip 2 pasted with the conductive film on a chip base island 10 on the lead frame 1, so that the drain disposed on the back of the chip 2 is electrically connected to the corresponding chip through the conductive film
  • the base island 10 corresponds to a plurality of first electrode bumps 11a on the periphery of the lead frame 1 .
  • an open stencil brushing film layer process can be used at the position for pasting the chip on each chip base island of the lead frame Brush a layer of solder paste (conductive film) with a certain thickness, and then paste the back of the chip on the surface of the solder paste, thereby using the solder paste brushed on the surface of the chip base island as the material for fixing the chip .
  • solder paste conductive film
  • step S400 specifically referring to FIG. 6b, a conductive film is formed on the surface of the source and gate on the front side of each chip 2, and the conductive film is used as the source and gate of each chip 2.
  • the gate is directly electrically connected to the electrode bump on the external PCB.
  • an open stencil brushing film layer process can be used at the position for pasting the chip on each chip base island of the lead frame Brush a layer of solder paste (conductive film) with a certain thickness, then paste the back of the chip on the surface of the solder paste, and brush the exposed front of the chip with a stencil brushing process layer a certain thickness of solder paste, and then use a reflow soldering process to reflow the solder paste covered on the front side of the chip to form a paste on the surface of the gate and source electrodes on the front side of the chip as shown in Figure 4
  • the solder paste bumps 32 and 33 are used as electrode bumps electrically connecting the front side of the chip with the external PCB board.
  • step S500 specifically referring to FIG. 6 c , a plastic encapsulation material layer 4 is formed to bury the surface of the chip 2 in each chip base island 10 not covered by the conductive film.
  • the material of the molding material layer 4 is epoxy resin.
  • step S400 the structure formed in step S400 is encapsulated with epoxy resin in the mold, and post-cured according to the characteristics of the epoxy resin.
  • the packaging method may also include the following steps:
  • Step S600 specifically referring to FIG. 6d, grinding the molding material layer 4' covering the front surface of the chip until the solder paste formed on the source and gate surfaces of the chip on the front surface of the chip is exposed
  • Step S700 specifically referring to 6e, the whole frame is electroplated with the tin layer 5 to meet the welding requirements of the client. Afterwards, the plurality of packaging structures on the lead frame 1 are diced and divided to remove redundant ribs. Finally, each packaging structure is packaged after product FT testing.
  • the mass production of the high-current power semiconductor device is realized by using the lead frame as the substrate of the packaging process; and because in the packaging structure provided by the present invention
  • Each lead structure corresponding to the chip base island used to set up the chip is provided with a plurality of electrode bumps to realize the electrical extraction of the drain on the back of the chip, and formed on the surface of the source and gate of the chip Solder paste used as electrode bumps to electrically lead out the source and gate of each chip and directly connect to the external PCB board, so that there is no need to set up leads between the chip and the PCB board for electrical connection, so that Package resistance and parasitic inductance of the package structure are reduced.
  • each chip after mounting is plastic-encapsulated and solidified by using a conductive film made of epoxy resin, so that the six surfaces of the chips pasted on each chip base island are uniform. protected, thereby meeting the design requirements for high-reliability application environments.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present invention provides a packaging structure for a large-current power semiconductor device and a packaging method therefor, applied to the technical field of semiconductors. Specifically, in the packaging structure for a large-current power semiconductor device provided by the present invention, batch production of large-current power semiconductor devices is implemented by means of using a lead frame as a substrate of a packaging process. Moreover, in the packaging structure provided by the present invention, a plurality of electrode bumps are provided on the periphery of a lead frame corresponding to each chip base island used for providing a chip, so that a drain electrode on the back surface of the chip is electrically led out, and solder paste serving as electrode bumps is formed on the surfaces of a source electrode and a gate electrode of the chip, so that the source electrode and the gate electrode of each chip are electrically led out and are directly and electrically connected to an external PCB. Therefore, no lead needs to be provided between the chip and the PCB for electric connection, and the packaging resistance and the parasitic inductance of the packaging structure are reduced.

Description

大电流功率半导体器件的封装结构及其封装方法Encapsulation structure and encapsulation method of high-current power semiconductor device 技术领域technical field

本发明涉及半导体技术领域，特别涉及一种大电流功率半导体器件的封装结构及其封装方法。The invention relates to the technical field of semiconductors, in particular to a packaging structure and a packaging method for high-current power semiconductor devices.

背景技术Background technique

随着半导体行业的不断发展，人们对半导体的要求也越来越高，希望半导体的电性能越来越好，而制造成本可以越来越小。为了更好地满足市场的需求，芯片设计开发端不断对芯片的设计进行改进，同时，也对封装设计开发端提出了更高的要求，而MOSFET器件的小型化封装是目前封装的发展方向。尤其是对于一些大电流的应用环境，其要求器件产品的导通电阻低，散热要求高，电感小。With the continuous development of the semiconductor industry, people have higher and higher requirements for semiconductors, hoping that the electrical performance of semiconductors will be better and better, and the manufacturing cost will be lower and lower. In order to better meet the needs of the market, the chip design and development end continues to improve the chip design. At the same time, it also puts forward higher requirements for the packaging design and development end, and the miniaturized packaging of MOSFET devices is the current development direction of packaging. Especially for some high-current application environments, it is required that the on-resistance of the device product is low, the heat dissipation requirement is high, and the inductance is small.

目前，现有的MOSFET器件的小型化封装工艺是一种小型金属倒装封装，图1为现有的MOSFET器件的小型化封装结构的结构示意图。如图1所述，现有技术中的MOSFET器件的小型化封装工艺过程为：用金属框架作为基座，然后，将芯片通过导电胶等固化温度较低的材料倒装在该金属框架上实现对芯片的装片，之后，在通过引线键合工艺将倒装后的芯片的正面通过引线键合中的导线将芯片的焊盘引出与PCB板上的其他电路或内部引脚电连接。At present, the existing miniaturized packaging process of MOSFET devices is a small metal flip-chip packaging. FIG. 1 is a schematic structural diagram of the existing miniaturized packaging structure of MOSFET devices. As shown in Figure 1, the miniaturized packaging process of MOSFET devices in the prior art is as follows: a metal frame is used as a base, and then the chip is flipped on the metal frame through a material with a low curing temperature such as conductive glue. For the chip mounting, after that, the front side of the flipped chip is drawn through the wire in the wire bonding through the wire bonding process to electrically connect the pads of the chip to other circuits or internal pins on the PCB.

然而，由于现有技术中的小型化封装工艺中需要用导电胶等固化温度较低、粘接强度不高的材料对芯片和金属框架进行封片，因此，在芯片封片后固化时需要真空环境，这对设备要求较高，且其芯片周围没有任何保护(现有技术中的小型化封装工艺中没有塑封工艺)，芯片的五面全部裸露在环境中，并且，现有的小型化封装工艺中的引线键合工艺还会导致封装电阻和寄生电感高的问题，因此，现有的MOSFET器件的小型化封装工艺无法适用于高可靠性应用环境下。However, since the miniaturized packaging process in the prior art needs to use materials such as conductive adhesives with low curing temperature and low bonding strength to seal the chip and the metal frame, a vacuum is required when the chip is sealed and solidified. Environment, which requires high equipment, and there is no protection around the chip (there is no plastic packaging process in the miniaturized packaging process in the prior art), all five sides of the chip are exposed to the environment, and the existing miniaturized package The wire bonding process in the process can also lead to the problem of high package resistance and parasitic inductance. Therefore, the existing miniaturized package process of MOSFET devices cannot be suitable for high-reliability application environments.

发明内容Contents of the invention

本发明的目的在于提供一种大电流功率半导体器件的封装结构及其封装 方法，以在适用于高可靠性应用环境的情况下，降低封装电阻和寄生电感。The object of the present invention is to provide a packaging structure and packaging method for high-current power semiconductor devices, so as to reduce packaging resistance and parasitic inductance under the condition of being suitable for high-reliability application environments.

第一方面，为了实现上述目的以及其他相关目的，本发明提供一种大电流功率半导体器件的封装结构，包括：In the first aspect, in order to achieve the above object and other related objects, the present invention provides a packaging structure of a high-current power semiconductor device, including:

引线架构，所述引线架构具有多个芯片基岛和位于每个芯片基岛对应的引线架构外围的多个电极凸块；a lead structure, the lead structure has a plurality of chip base islands and a plurality of electrode bumps located on the periphery of the lead structure corresponding to each chip base island;

多个芯片，每个所述芯片的正面均设置有一源极和一栅极，背面设置有一漏极，所述多个芯片与所述多个芯片基岛一一对应设置，并使所述每个芯片背面的漏极均贴装于所对应的芯片基岛；A plurality of chips, each of which is provided with a source and a gate on the front, and a drain on the back, the plurality of chips are arranged in one-to-one correspondence with the plurality of chip base islands, and each The drains on the back of each chip are mounted on the corresponding chip base island;

导电薄膜，部分所述导电薄膜设置在每个芯片的漏极与其所对应的芯片基岛之间，以使所述每个芯片的漏极电连接于所对应的芯片基岛对应的引线架构外围的多个电极凸块，而另一部分所述导电薄膜设置在每个芯片的源极和栅极与外接的PCB板之间，以使所述每个芯片的源极和栅极直接电连接于所述PCB板；A conductive film, part of which is arranged between the drain of each chip and its corresponding chip base island, so that the drain of each chip is electrically connected to the periphery of the lead structure corresponding to the corresponding chip base island a plurality of electrode bumps, and another part of the conductive film is arranged between the source and gate of each chip and the external PCB board, so that the source and gate of each chip are directly electrically connected to the The PCB board;

塑封材料层，每个所述芯片基岛以及粘贴在其内的芯片和导电薄膜之间的空隙均设有所述塑封材料层，以掩埋每个芯片基岛中芯片未被所述导电薄膜所覆盖的表面。A layer of plastic encapsulation material, each of the chip base islands and the gap between the chip and the conductive film pasted therein is provided with the plastic encapsulation material layer, so as to bury the chip in each chip base island that is not covered by the conductive film. covered surface.

进一步的，所述导电薄膜的材料可以包括锡膏。Further, the material of the conductive film may include solder paste.

进一步的，所述芯片可以包括功率MOSFET芯片。Further, the chip may include a power MOSFET chip.

进一步的，所述塑封材料层的材料可以包括聚酰亚胺、硅胶以及环氧树脂中的一种固化材料。Further, the material of the molding material layer may include a cured material selected from polyimide, silica gel and epoxy resin.

进一步的，每个所述芯片基岛可以呈板状，并与所述芯片层叠布置，在每个所述芯片基岛的长度方向上的两侧向外延伸分别形成有一翼型连接部，且每个所述翼型连接部在所述芯片基岛的长度方向上向外延伸形成有至少两个相互间隔分布的第一电极凸块，所述第一电极凸块与呈板状的芯片基岛不共面。Further, each of the chip base islands may be plate-shaped and stacked with the chips, and each of the chip base islands extends outward on both sides in the length direction to form an airfoil connection part, and Each of the airfoil connection parts extends outward in the length direction of the chip substrate island to form at least two first electrode bumps spaced apart from each other, and the first electrode bumps are connected to the plate-shaped chip substrate. The islands are not coplanar.

进一步的，在每个所述芯片基岛的宽度方向上的两侧向外延伸可以分别形成有至少两个相互间隔分布的且与呈板状的芯片基岛共面的第二电极凸块。Further, at least two second electrode bumps that are spaced apart from each other and coplanar with the plate-shaped chip base island can be formed on both sides of each chip base island in the width direction extending outward.

进一步的，所述引线架构的材料可以为金属。Further, the material of the lead frame may be metal.

第二方面，基于相同的发明构思，本发明还提供了一种封装方法，包括以下步骤：In the second aspect, based on the same inventive concept, the present invention also provides a packaging method, comprising the following steps:

提供如上所述的大电流功率半导体器件的封装结构中的引线架构，所述引线架构具有多个芯片基岛和位于每个芯片基岛对应的引线架构外围的多个电极凸块；Provide the lead structure in the packaging structure of the high-current power semiconductor device as described above, the lead structure has a plurality of chip base islands and a plurality of electrode bumps located on the periphery of the lead structure corresponding to each chip base island;

提供多个芯片，每个所述芯片的正面均设置有一源极和一栅极，背面设置有一漏极；A plurality of chips are provided, each chip is provided with a source and a gate on the front, and a drain on the back;

将每个所述芯片分别键合在所述引线架构中的一芯片基岛上，以使设置在所述芯片背面的漏极电连接于所对应的芯片基岛对应的引线架构外围的多个电极凸块，并暴露出每一所述芯片的正面；Each of the chips is respectively bonded on a chip base island in the lead structure, so that the drain disposed on the back side of the chip is electrically connected to a plurality of surrounding lead structures corresponding to the corresponding chip base island. electrode bumps exposing the front side of each of said chips;

在每一所述芯片的正面上的源极和栅极的表面上形成导电薄膜，并将所述导电薄膜作为每个芯片的源极和栅极直接电连接于外接PCB板的电极凸块；Form a conductive film on the surface of the source electrode and the grid on the front side of each chip, and directly connect the conductive film to the electrode bump of the external PCB board as the source electrode and the grid of each chip;

形成塑封材料层，以掩埋每个芯片基岛中芯片未被导电薄膜所覆盖的表面。A plastic encapsulation material layer is formed to bury the surface of the chip in each chip base island that is not covered by the conductive film.

进一步的，将每个所述芯片分别键合在所述引线架构中的一芯片基岛上的步骤，可以包括：Further, the step of bonding each of the chips on a chip base island in the lead structure may include:

在每个所述芯片基岛的表面上形成导电薄膜，并将所述芯片的背面键合在所述导电薄膜的上表面，所述导电薄膜的上下表面均具有粘性；forming a conductive film on the surface of each of the chip base islands, and bonding the back of the chip to the upper surface of the conductive film, the upper and lower surfaces of the conductive film are sticky;

将粘贴有导电薄膜的所述芯片粘贴在引线架构上的一芯片基岛上，以使设置在所述芯片背面的漏极通过该导电薄膜电连接于所对应的芯片基岛对应的引线架构外围的多个第一电极凸块。Paste the chip with the conductive film on a chip base island on the lead structure, so that the drain electrode arranged on the back of the chip is electrically connected to the periphery of the lead structure corresponding to the corresponding chip base island through the conductive film a plurality of first electrode bumps.

进一步的，在每一所述芯片的正面上的源极和栅极的表面上形成导电薄膜，以作为外接PCB板的电极凸块的工艺包括开钢网刷膜层工艺和回流焊接工艺。Further, the process of forming a conductive film on the surface of the source electrode and the gate electrode on the front side of each chip as an electrode bump externally connected to the PCB includes a stencil brushing process and a reflow soldering process.

进一步的，所述导电薄膜的材料可以包括锡膏，所述塑封材料层的材料可以包括聚酰亚胺、硅胶以及环氧树脂中的一种固化材料。Further, the material of the conductive film may include solder paste, and the material of the molding material layer may include a cured material selected from polyimide, silica gel and epoxy resin.

进一步的，本发明提供的封装方法还可以包括如下步骤：Further, the encapsulation method provided by the present invention may also include the following steps:

研磨覆盖所述芯片正面上的所述塑封材料层，直至暴露出所述芯片正面 上形成在芯片的源极和栅极表面上的所述电极凸块，以及每个芯片基岛对应的引线架构外围的多个电极凸块。Grinding the molding material layer covering the front surface of the chip until the electrode bumps formed on the source and gate surfaces of the chip on the front surface of the chip are exposed, as well as the lead structure corresponding to each chip base island Multiple electrode bumps on the periphery.

与现有技术相比，本发明的技术方案具有以下有益效果：Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

在本发明提供的大电流功率半导体器件的封装结构中，通过使用引线架构作为封装工艺的基底，实现了大电流功率半导体器件的批量生产；并且由于在本发明提供的封装结构中，每个用于设置芯片的芯片基岛对应的引线架构外围设有多个电极凸块，以实现将芯片背面的漏极电性引出，而在芯片的源极和栅极的表面上形成有作为电极凸块的锡膏，以实现将每个芯片的源极和栅极电性引出，并与外接PCB板直接电连接，从而无需在芯片和PCB板之间再设置引线进行电连接，从而降低了封装结构的封装电阻和寄生电感。In the packaging structure of the high-current power semiconductor device provided by the present invention, the mass production of the high-current power semiconductor device is realized by using the lead frame as the substrate of the packaging process; and because in the packaging structure provided by the present invention, each A plurality of electrode bumps are arranged on the periphery of the lead structure corresponding to the chip base island where the chip is installed to realize the electrical extraction of the drain on the back of the chip, and electrode bumps are formed on the surface of the source and gate of the chip. Solder paste, to achieve the electrical lead-out of the source and gate of each chip, and direct electrical connection with the external PCB board, so that there is no need to set up leads between the chip and the PCB board for electrical connection, thereby reducing the packaging structure package resistance and parasitic inductance.

进一步的，由于在本发明提供的封装结构中，利用材料为环氧树脂的导电薄膜将装片后的每个芯片进行塑封固化，从而是每个芯片基岛上粘贴的芯片的六个表面均受到保护，进而满足了高可靠性应用环境的设计要求。Further, since in the packaging structure provided by the present invention, each chip after mounting is plastic-encapsulated and solidified by using a conductive film made of epoxy resin, so that the six surfaces of the chips pasted on each chip base island are uniform. protected, thereby meeting the design requirements for high-reliability application environments.

附图说明Description of drawings

图1是现有技术中提供的一种MOSFET器件的小型化封装结构的结构示意图；Fig. 1 is a structural schematic diagram of a miniaturized package structure of a MOSFET device provided in the prior art;

图2为本发明一实施例中提供的引线架构的俯视图；FIG. 2 is a top view of a lead frame provided in an embodiment of the present invention;

图3为图2中提供的引线架构中的一个芯片基岛及其外围设置的电极凸块的侧视图；FIG. 3 is a side view of a chip base island and electrode bumps arranged around it in the lead structure provided in FIG. 2;

图4为本发明一实施例中提供的每个芯片封装后对应的封装结构的结构示意图；FIG. 4 is a schematic structural diagram of the package structure corresponding to each chip package provided in an embodiment of the present invention;

图5是本发明一实施例中提供的一种大电流功率半导体器件的封装结构的封装方法的流程示意图；5 is a schematic flowchart of a packaging method for a packaging structure of a high-current power semiconductor device provided in an embodiment of the present invention;

图6a～图6e是本发明一实施例中提供的一种大电流功率半导体器件的封装结构在制造过程中的结构示意图；6a to 6e are structural schematic diagrams of a packaging structure of a high-current power semiconductor device provided in an embodiment of the present invention during the manufacturing process;

其中，附图标记如下：Wherein, the reference signs are as follows:

1-引线架构，2-芯片，31/32/33-导电薄膜(锡膏)，4/4’-塑封材料层，10-芯片基岛，11-电极凸块，11a-第一电极凸块，11b-第二电极凸块，5-电镀锡层。1-lead structure, 2-chip, 31/32/33-conductive film (solder paste), 4/4'-molding material layer, 10-chip base island, 11-electrode bump, 11a-first electrode bump , 11b—the second electrode bump, 5—the electroplating tin layer.

具体实施方式Detailed ways

承如背景技术所述，目前，现有的MOSFET器件的小型化封装工艺是一种小型金属倒装封装，图1为现有的MOSFET器件的小型化封装结构的结构示意图。如图1所述，现有技术中的MOSFET器件的小型化封装工艺过程为：用金属框架作为基座，然后，将芯片通过导电胶等固化温度较低的材料倒装在该金属框架上实现对芯片的装片，之后，在通过引线键合工艺将倒装后的芯片的正面通过引线键合中的导线(未图示)将芯片的焊盘引出与PCB板上的其他电路或内部引脚电连接。As mentioned in the background, at present, the existing miniaturized packaging process of MOSFET devices is a small metal flip-chip packaging. FIG. 1 is a schematic structural diagram of the existing miniaturized packaging structure of MOSFET devices. As shown in Figure 1, the miniaturized packaging process of MOSFET devices in the prior art is as follows: a metal frame is used as a base, and then the chip is flipped on the metal frame through a material with a low curing temperature such as conductive glue. After the chip is mounted, the front side of the flipped chip is led out to other circuits or internal leads on the PCB through the wires (not shown) in the wire bonding through the wire bonding process. Foot connection.

然而，由于现有技术中的小型化封装工艺中需要用导电胶等固化温度较低、粘接强度不高的材料对芯片和金属框架进行封片，因此，在芯片封片后固化时需要真空环境，这对设备要求较高，且其芯片周围没有任何保护(现有技术中的小型化封装工艺中没有塑封工艺)，芯片的五面全部裸露在环境中，并且，现有的小型化封装工艺中的引线键合工艺还会导致封装电阻和寄生电感高的问题，因此，现有的MOSFET器件的小型化封装工艺无法适用于高可靠性应用环境下。However, since the miniaturized packaging process in the prior art needs to use materials such as conductive adhesives with low curing temperature and low bonding strength to seal the chip and the metal frame, a vacuum is required when the chip is sealed and solidified. Environment, which requires high equipment, and there is no protection around the chip (there is no plastic packaging process in the miniaturized packaging process in the prior art), all five sides of the chip are exposed to the environment, and the existing miniaturized package The wire bonding process in the process can also lead to the problem of high package resistance and parasitic inductance. Therefore, the existing miniaturized package process of MOSFET devices cannot be suitable for high-reliability application environments.

为此，本发明提供了一种大电流功率半导体器件的封装结构及其封装方法，以在适用于高可靠性应用环境的情况下，降低封装电阻和寄生电感。Therefore, the present invention provides a packaging structure and packaging method for high-current power semiconductor devices, so as to reduce packaging resistance and parasitic inductance under the condition of being suitable for high-reliability application environments.

以下结合附图和具体实施例对本发明提出的大电流功率半导体器件的封装结构及其封装方法作进一步详细说明。根据下面说明书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。The packaging structure and packaging method of the high-current power semiconductor device proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will be more apparent from the following description. It should be noted that all the drawings are in very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

下面首先对本发明提供的大电流功率半导体器件的封装结构进行介绍。Firstly, the packaging structure of the high-current power semiconductor device provided by the present invention will be introduced below.

请参考图2、图3和图4，其中，图2为本发明一实施例中提供的引线架构的俯视图，图3为图2中提供的引线架构中的一个芯片基岛及其外围设置的电极凸块的侧视图，图4为本发明一实施例中提供的每个芯片封装后对应的封装结构的结构示意图。Please refer to Fig. 2, Fig. 3 and Fig. 4, wherein Fig. 2 is a top view of a lead structure provided in an embodiment of the present invention, and Fig. 3 is a chip base island and its peripheral arrangement in the lead structure provided in Fig. 2 As for the side view of the electrode bumps, FIG. 4 is a schematic structural diagram of the package structure corresponding to each chip package provided in an embodiment of the present invention.

如图2所示，在本发明提供的封装结构中其可以包含一引线架构1作为粘贴多个芯片的基底，所述引线架构1的材料可以为金属，例如，金，铜等 金属。而所述引线架构1可以同时对多个芯片进行分片，因此，其可以包括多个芯片基岛10和位于每个芯片基岛10对应的引线架构外围的多个电极凸块11。为此，在本发明提供的封装结构中，其还可以多个芯片，每个所述芯片的正面均设置有一源极和一栅极，背面设置有一漏极，所述多个芯片与所述多个芯片基岛10一一对应设置，并使所述每个芯片背面的漏极均贴装于所对应的芯片基岛10。As shown in FIG. 2, the packaging structure provided by the present invention may include a lead frame 1 as a substrate for pasting multiple chips, and the material of the lead frame 1 may be metal, such as gold, copper and other metals. The lead frame 1 can slice multiple chips at the same time, therefore, it can include multiple chip base islands 10 and multiple electrode bumps 11 located on the periphery of the lead frame corresponding to each chip base island 10 . For this reason, in the packaging structure provided by the present invention, it can also have a plurality of chips, each of the chips is provided with a source and a gate on the front, and a drain on the back, and the plurality of chips and the A plurality of chip base islands 10 are provided in one-to-one correspondence, and the drain on the back of each chip is attached to the corresponding chip base island 10 .

为了更清晰的了解本发明提供的引线架构中每个芯片基岛10和位于每个芯片基岛10对应的引线架构外围的多个电极凸块的位置关系，本发明提供了其侧视图，如图3所示，每个所述芯片基岛10呈板状，并与所述芯片层叠布置，在每个所述芯片基岛10的长度方向上的两侧向外延伸分别形成有一翼型连接部12，且每个所述翼型连接部12在所述芯片基岛10的长度方向上向外延伸形成有至少两个相互间隔分布的第一电极凸块11a，所述第一电极凸块11a与呈板状的芯片基岛10不共面。并且，在每个所述芯片基岛10的宽度方向上的两侧向外延伸分别形成有至少两个相互间隔分布的且与呈板状的芯片基岛10共面的第二电极凸块11b。In order to understand more clearly the positional relationship between each chip base island 10 in the lead structure provided by the present invention and a plurality of electrode bumps located on the periphery of the lead structure corresponding to each chip base island 10, the present invention provides its side view, as As shown in FIG. 3 , each of the chip base islands 10 is plate-shaped and stacked with the chips, and each of the chip base islands 10 extends outward on both sides in the length direction to form an airfoil connection. 12, and each airfoil connecting portion 12 extends outward in the length direction of the chip base island 10 to form at least two first electrode bumps 11a spaced apart from each other, and the first electrode bumps 11a is not coplanar with the plate-shaped chip base island 10 . Moreover, at least two second electrode bumps 11b that are spaced apart from each other and coplanar with the plate-shaped chip base island 10 are respectively formed extending outward on both sides in the width direction of each chip base island 10 .

进一步的，为了清晰的展示每个芯片封装后对应的封装结构，本发明一实施例中还提供了每个芯片封装后对应的封装结构的结构示意图。如图4所示，芯片2的背面朝向所述芯片基岛10，且所述芯片2的背面与所述芯片基岛10之间设置有两面均具有粘黏性的导电薄膜31，以用于将位于芯片2背面的漏极电连接于所对应的芯片基岛10对应的引线架构外围的多个第一电极凸块11a；而在所述芯片2的正面的栅极的表面上形成有两面均具有粘黏性的导电薄膜32，以及在所述芯片2的正面的源极的表面上形成有两面均具有粘黏性的导电薄膜33，并将粘贴在所述芯片2的正面的源极和漏极表面上的导电薄膜32和33作为电极凸块，以使所述芯片2的源极和栅极直接电连接于外接的PCB板。Further, in order to clearly show the corresponding packaging structure of each chip after packaging, an embodiment of the present invention also provides a structural schematic diagram of the corresponding packaging structure of each chip after packaging. As shown in Figure 4, the back of the chip 2 faces the chip base island 10, and a conductive film 31 with adhesiveness on both sides is arranged between the back of the chip 2 and the chip base island 10, for The drain on the back of the chip 2 is electrically connected to a plurality of first electrode bumps 11a on the periphery of the lead structure corresponding to the corresponding chip base island 10; All have the conductive film 32 of stickiness, and the conductive film 33 that all has stickiness on both sides is formed on the surface of the source electrode of the front side of described chip 2, and will stick on the source electrode of the front side of described chip 2 The conductive films 32 and 33 on the surface of the drain electrode are used as electrode bumps, so that the source electrode and the gate electrode of the chip 2 are directly electrically connected to an external PCB board.

此外，如图4所示，所述封装结构还包括塑封材料层4，且所述塑封材料层4位于所述芯片基岛10以及粘贴在其内的芯片2和导电薄膜31、32和33之间的空隙内，以掩埋所述芯片基岛10中所述芯片2未被导电薄膜31、32和33所覆盖的表面。In addition, as shown in FIG. 4 , the packaging structure further includes a molding material layer 4, and the molding material layer 4 is located between the chip base island 10 and the chips 2 and conductive films 31, 32 and 33 pasted therein. to bury the surface of the chip 2 in the chip base island 10 that is not covered by the conductive films 31 , 32 and 33 .

其中，所述导电薄膜31、32和33的材料可以为锡膏；所述芯片2可以为功率MOSFET芯片；所述塑封材料层4的材料包括聚酰亚胺、硅胶以及环氧树脂中的一种固化材料。示例性的，本发明实施例中的塑封材料层的材料为环氧树脂。由此可见，本发明提供的大电流功率半导体器件的封装结构是由引线架构、锡膏(导电薄膜)、芯片、环氧树脂塑封材料层等多种材质组成。Wherein, the material of the conductive films 31, 32 and 33 can be solder paste; the chip 2 can be a power MOSFET chip; the material of the plastic packaging material layer 4 includes one of polyimide, silica gel and epoxy resin. a solidified material. Exemplarily, the material of the molding material layer in the embodiment of the present invention is epoxy resin. It can be seen that the packaging structure of the high-current power semiconductor device provided by the present invention is composed of various materials such as lead frame, solder paste (conductive film), chip, and epoxy resin molding material layer.

可以理解的是，在本发明提供的大电流功率半导体器件的封装结构中，在每个所述芯片2的表面上还可以形成有钝化层(未图示)，以防止每个所述芯片2的正面和背面(表面)受到污染。It can be understood that, in the packaging structure of the high-current power semiconductor device provided by the present invention, a passivation layer (not shown) may also be formed on the surface of each of the chips 2 to prevent each of the chips from The front and back (surface) of 2 are contaminated.

综上，根据附图2～4所示的本发明提供的封装结构可知，本发明提供的封装结构具体可以具有以下优点：To sum up, according to the packaging structure provided by the present invention shown in accompanying drawings 2 to 4, it can be seen that the packaging structure provided by the present invention can specifically have the following advantages:

(1)、本发明提供的封装结构是对芯片进行倒装分片，以使外接PCB板根据位于芯片正面上的栅极和源极表面上的电极开窗刷焊接材料，实现产品倒扣回流焊接。(1), the packaging structure provided by the present invention is to carry out flip-chip splitting of the chip, so that the external PCB board can brush the welding material according to the electrode window on the gate and source surface on the front of the chip, so as to realize the reverse buckle reflow of the product welding.

(2)、本发明提供的引线架构中的芯片基岛的长度方向上的两侧向外延伸分别形成有一翼型连接部，且每个所述翼型连接部在所述芯片基岛的长度方向上向外延伸形成有至少两个相互间隔分布的第一电极凸块，其可将每个芯片背面上的电极(漏极)导通至焊接面，由于是引线架构装片，可以进行大批量生产。(2) In the lead structure provided by the present invention, both sides in the length direction of the chip base island extend outward to form an airfoil connection part respectively, and each of the airfoil connection parts is within the length of the chip base island Extend outward in the direction to form at least two first electrode bumps that are spaced apart from each other, which can conduct the electrode (drain) on the back of each chip to the welding surface. Mass production.

(3)、不同于传统封装，本发明提供的封装形式由于要露出了所述电极凸块，并且所述第一电极凸块和芯片的正面要在一个平面上，因此，在形成本发明提供的封装结构时需要先塑封，然后进行研磨，以保证了产品平整度和电极凸块露出。(3), different from the traditional packaging, the packaging form provided by the present invention exposes the electrode bumps, and the first electrode bumps and the front of the chip are on the same plane, therefore, when forming the electrode bumps provided by the present invention The packaging structure needs to be plastic-sealed first, and then ground to ensure the flatness of the product and the exposure of the electrode bumps.

(4)、由于本发明提供的引线架构的材料为金属，因此，其可以满足散热需求，有条件厂商也可加装散热片。由于有所述第一电极凸块支撑，本发明提供的封装结构也可以承受较大机械力。(4) Since the material of the lead frame provided by the present invention is metal, it can meet heat dissipation requirements, and manufacturers can also install heat sinks if conditions permit. Due to the support of the first electrode bumps, the packaging structure provided by the present invention can also withstand relatively large mechanical forces.

(5)、本发明提供的封装结构中有塑封材料层，使得芯片的六面有塑封保护，可以满足高可靠性要求。(5) The packaging structure provided by the present invention has a plastic packaging material layer, so that the six sides of the chip are protected by plastic packaging, which can meet the high reliability requirements.

(6)、由于本发明是用刷锡膏制作芯片正面上连接其栅极和源极的电极凸块，所以芯片要在其开窗部分进行Ni/Au/Cu化镀或电镀pad以及合理的钝 化layout，然后，利用锡膏融化后的成型作用，进行凸块制作，这种方法相比于现在芯片上制作凸块，然后进行装片，工艺上更简单，可以将芯片与框架粘接和凸块制作一起完成，也避免了装片时吸取凸块带来的问题。(6), because the present invention is to make the electrode bump that connects its gate and source on the front of the chip with brush solder paste, so the chip will carry out Ni/Au/Cu chemical plating or electroplating pad and reasonable Passivate the layout, and then use the molding effect of the solder paste to make bumps. Compared with the current method of making bumps on the chip and then mounting the chip, the process is simpler and the chip can be bonded to the frame. It is completed together with bump production, and also avoids the problems caused by suction bumps during film loading.

(7)、由于本发明提供的封装结构采用锡膏(导电薄膜)作为粘贴芯片与芯片基岛的材料，因此，避免了现有技术中利用导电胶等固化温度较低、粘接强度不高的材料造成的导电胶残留污染，以及固化时需要真空环境，对设备要求较高的问题。(7), because the packaging structure provided by the present invention adopts solder paste (conductive film) as the material for pasting the chip and the chip base island, therefore, avoiding the low curing temperature and low bonding strength of using conductive glue in the prior art The residual pollution of the conductive adhesive caused by the material, and the need for a vacuum environment during curing, which requires high equipment requirements.

(8)、本发明提供的封装结构是通过芯片正面上形成的材料为锡膏的电极凸块，直接将封片在引线架构上的芯片的正面倒装在PCB板上，其没有引线连接，与传统打线封装相比，导通电阻低。(8), the packaging structure provided by the present invention is that the material formed on the front side of the chip is an electrode bump of solder paste, and the front side of the chip on the lead frame is directly flip-mounted on the PCB board without the lead wire connection. Low on-resistance compared to conventional wire bonded packages.

基于如上所述的大电流功率半导体器件的封装结构，如图5所示，本发明还提供了一种封装方法，具体可以包括以下步骤：Based on the packaging structure of the high-current power semiconductor device described above, as shown in Figure 5, the present invention also provides a packaging method, which may specifically include the following steps:

步骤S100，提供如上本发明提供的大电流功率半导体器件的封装结构中的引线架构，所述引线架构具有多个芯片基岛10和位于每个芯片基岛对应的引线架构外围的多个电极凸块。Step S100, providing the lead structure in the packaging structure of the high-current power semiconductor device provided by the present invention, the lead structure has a plurality of chip base islands 10 and a plurality of electrode bumps located on the periphery of the lead structure corresponding to each chip base island piece.

步骤S200，提供多个芯片，每个所述芯片的正面均设置有一源极和一栅极，背面设置有一漏极。In step S200, a plurality of chips are provided, each chip is provided with a source and a gate on the front, and a drain on the back.

步骤S300，将每个所述芯片分别键合在所述引线架构中的一芯片基岛上，以使设置在所述芯片背面的漏极电连接于所对应的芯片基岛对应的引线架构1外围的多个电极凸块，并暴露出每一所述芯片的正面。Step S300, bonding each of the chips to a chip base island in the lead structure, so that the drain disposed on the back of the chip is electrically connected to the lead structure 1 corresponding to the corresponding chip base island a plurality of electrode bumps on the periphery, and expose the front side of each chip.

步骤S400，在每一所述芯片的正面上的源极和栅极的表面上形成导电薄膜，并将所述导电薄膜作为每个芯片的源极和栅极直接电连接于外接PCB板的电极凸块。Step S400, forming a conductive film on the surface of the source and gate on the front side of each chip, and using the conductive film as the source and gate of each chip to be directly electrically connected to the electrodes of the external PCB board bump.

步骤S500，形成塑封材料层，以掩埋每个芯片基岛中芯片未被导电薄膜所覆盖的表面。Step S500, forming a plastic encapsulation material layer to bury the surface of the chip in each chip base island not covered by the conductive film.

以下结合附图6a～6e和具体实施例对本发明提出的封装方法作进一步详细说明。根据下面说明，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。The encapsulation method proposed by the present invention will be further described in detail below with reference to the accompanying drawings 6a-6e and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that all the drawings are in very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

在步骤S100中，具体参考图6a所示，提供如上本发明提供的大电流功率半导体器件的封装结构中的引线架构1，其中，所述引线架构1具有多个芯片基岛10和位于每个芯片基岛10对应的引线架构1外围的多个电极凸块11。In step S100, specifically referring to FIG. 6a, the lead frame 1 in the packaging structure of the high-current power semiconductor device provided by the present invention is provided, wherein the lead frame 1 has a plurality of chip base islands 10 and is located in each The chip base island 10 corresponds to a plurality of electrode bumps 11 on the periphery of the lead frame 1 .

在步骤S200中，提供多个芯片2，每个所述芯片2的正面均设置有一源极和一栅极，背面设置有一漏极。In step S200, a plurality of chips 2 are provided, each chip 2 is provided with a source and a gate on the front, and a drain on the back.

在步骤S300中，继续参考图6a所示，并结合图6c，将每个所述芯片2分别键合在所述引线架构1中的一芯片基岛10上，以使设置在所述芯片2背面的漏极电连接于所对应的芯片基岛10对应的引线架构1外围的多个电极凸块11，并暴露出每一所述芯片2的正面。具体的，本发明提供了一种将每个所述芯片2分别键合在所述引线架构1中的一芯片基岛10上的具体方式，可以包括如下步骤：In step S300, continuing to refer to FIG. 6a and in conjunction with FIG. 6c, each of the chips 2 is respectively bonded on a chip base island 10 in the lead frame 1, so that the chips 2 The drain on the back is electrically connected to a plurality of electrode bumps 11 on the periphery of the lead structure 1 corresponding to the corresponding chip base island 10 , and exposes the front of each chip 2 . Specifically, the present invention provides a specific method of bonding each of the chips 2 to a chip base island 10 in the lead frame 1, which may include the following steps:

步骤S301，在每个所述芯片基的表面上形成导电薄膜，并将所述芯片2的背面键合在所述导电薄膜的上表面，所述导电薄膜的上下表面均具有粘性。Step S301 , forming a conductive film on the surface of each chip base, and bonding the back surface of the chip 2 to the upper surface of the conductive film, and the upper and lower surfaces of the conductive film are both adhesive.

步骤S302，将粘贴有导电薄膜的所述芯片2粘贴在引线架构1上的一芯片基岛10上，以使设置在所述芯片2背面的漏极通过该导电薄膜电连接于所对应的芯片基岛10对应的引线架构1外围的多个第一电极凸块11a。Step S302, paste the chip 2 pasted with the conductive film on a chip base island 10 on the lead frame 1, so that the drain disposed on the back of the chip 2 is electrically connected to the corresponding chip through the conductive film The base island 10 corresponds to a plurality of first electrode bumps 11a on the periphery of the lead frame 1 .

在本实施例中，在步骤S100和步骤S200提供了所述引线架构和芯片之后，可以在所述引线架构的每个芯片基岛的用于粘贴芯片的位置处利用开钢网刷膜层工艺刷一层一定厚度的锡膏(导电薄膜)，然后，将芯片的背面粘贴在所述锡膏的表面上，从而利用所述芯片基岛的表面上刷的锡膏作为固定所述芯片的材料。In this embodiment, after the lead frame and the chip are provided in step S100 and step S200, an open stencil brushing film layer process can be used at the position for pasting the chip on each chip base island of the lead frame Brush a layer of solder paste (conductive film) with a certain thickness, and then paste the back of the chip on the surface of the solder paste, thereby using the solder paste brushed on the surface of the chip base island as the material for fixing the chip .

在步骤S400中，具体参考图6b所示，在每一所述芯片2的正面上的源极和栅极的表面上形成导电薄膜，并将所述导电薄膜作为每个芯片2的源极和栅极直接电连接于外接PCB板的电极凸块。In step S400, specifically referring to FIG. 6b, a conductive film is formed on the surface of the source and gate on the front side of each chip 2, and the conductive film is used as the source and gate of each chip 2. The gate is directly electrically connected to the electrode bump on the external PCB.

在本实施例中，在步骤S100和步骤S200提供了所述引线架构和芯片之后，可以在所述引线架构的每个芯片基岛的用于粘贴芯片的位置处利用开钢网刷膜层工艺刷一层一定厚度的锡膏(导电薄膜)，然后，将芯片的背面粘贴在所述锡膏的表面上，并在暴露出的所述芯片的正面再利用开钢网刷膜层工艺刷一层一定厚度的锡膏，之后，再利用回流焊接工艺将覆盖在所述芯片正 面上的所述锡膏回流后形成如图4所述的粘贴在所述芯片正面上栅极和源极表面上的锡膏凸块32和33，并将该锡膏凸块32和33作为电连接该芯片正面与外接PCB板的电极凸块。In this embodiment, after the lead frame and the chip are provided in step S100 and step S200, an open stencil brushing film layer process can be used at the position for pasting the chip on each chip base island of the lead frame Brush a layer of solder paste (conductive film) with a certain thickness, then paste the back of the chip on the surface of the solder paste, and brush the exposed front of the chip with a stencil brushing process layer a certain thickness of solder paste, and then use a reflow soldering process to reflow the solder paste covered on the front side of the chip to form a paste on the surface of the gate and source electrodes on the front side of the chip as shown in Figure 4 The solder paste bumps 32 and 33 are used as electrode bumps electrically connecting the front side of the chip with the external PCB board.

在步骤S500中，具体参考图6c所示，形成塑封材料层4，以掩埋每个芯片基岛10中芯片2未被导电薄膜所覆盖的表面。其中，所述塑封材料层4的材料为环氧树脂。In step S500 , specifically referring to FIG. 6 c , a plastic encapsulation material layer 4 is formed to bury the surface of the chip 2 in each chip base island 10 not covered by the conductive film. Wherein, the material of the molding material layer 4 is epoxy resin.

在本实施例中，将步骤S400形成的结构在模具内用环氧树脂封装，按照环氧树脂特性进行后固化。In this embodiment, the structure formed in step S400 is encapsulated with epoxy resin in the mold, and post-cured according to the characteristics of the epoxy resin.

进一步的，在本发明提供的所述封装方法中其还可以包括如下步骤：Further, in the packaging method provided by the present invention, it may also include the following steps:

步骤S600，具体参考图6d所示，研磨覆盖所述芯片正面上的所述塑封材料层4’，直至暴露出所述芯片正面上形成在芯片的源极和栅极表面上的所述锡膏凸块32和33，以及每个芯片基岛对应的引线架构外围的多个电极凸块11。Step S600, specifically referring to FIG. 6d, grinding the molding material layer 4' covering the front surface of the chip until the solder paste formed on the source and gate surfaces of the chip on the front surface of the chip is exposed The bumps 32 and 33, and a plurality of electrode bumps 11 on the periphery of the lead structure corresponding to each chip substrate island.

步骤S700，具体参考6e所示，将整条框架进行电镀锡层5，以适用客户端焊接要求。之后，将所述引线架构1上的多个封装结构划片分割，以去除多余连筋。最后，对每个封装结构进行产品FT测试后包装。Step S700, specifically referring to 6e, the whole frame is electroplated with the tin layer 5 to meet the welding requirements of the client. Afterwards, the plurality of packaging structures on the lead frame 1 are diced and divided to remove redundant ribs. Finally, each packaging structure is packaged after product FT testing.

综上可见，在本发明提供的大电流功率半导体器件的封装结构中，通过使用引线架构作为封装工艺的基底，实现了大电流功率半导体器件的批量生产；并且由于在本发明提供的封装结构中，每个用于设置芯片的芯片基岛对应的引线架构外围设有多个电极凸块，以实现将芯片背面的漏极电性引出，而在芯片的源极和栅极的表面上形成有作为电极凸块的锡膏，以实现将每个芯片的源极和栅极电性引出，并与外接PCB板直接电连接，从而无需在芯片和PCB板之间再设置引线进行电连接，从而降低了封装结构的封装电阻和寄生电感。In summary, in the packaging structure of the high-current power semiconductor device provided by the present invention, the mass production of the high-current power semiconductor device is realized by using the lead frame as the substrate of the packaging process; and because in the packaging structure provided by the present invention Each lead structure corresponding to the chip base island used to set up the chip is provided with a plurality of electrode bumps to realize the electrical extraction of the drain on the back of the chip, and formed on the surface of the source and gate of the chip Solder paste used as electrode bumps to electrically lead out the source and gate of each chip and directly connect to the external PCB board, so that there is no need to set up leads between the chip and the PCB board for electrical connection, so that Package resistance and parasitic inductance of the package structure are reduced.

进一步的，由于在本发明提供的封装结构中，利用材料为环氧树脂的导电薄膜将装片后的每个芯片进行塑封固化，从而是每个芯片基岛上粘贴的芯片的六个表面均受到保护，进而满足了高可靠性应用环境的设计要求。Further, since in the packaging structure provided by the present invention, each chip after mounting is plastic-encapsulated and solidified by using a conductive film made of epoxy resin, so that the six surfaces of the chips pasted on each chip base island are uniform. protected, thereby meeting the design requirements for high-reliability application environments.

此外，可以理解的是，虽然本发明已以较佳实施例披露如上，然而上述实施例并非用以限定本发明。对于任何熟悉本领域的技术人员而言，在不脱 离本发明技术方案范围情况下，都可利用上述揭示的技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。In addition, it can be understood that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or be modified to be equivalent to equivalent changes. Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

而且还应该理解的是，本发明并不限于此处描述的特定的方法、化合物、材料、制造技术、用法和应用，它们可以变化。还应该理解的是，此处描述的术语仅仅用来描述特定实施例，而不是用来限制本发明的范围。必须注意的是，此处的以及所附权利要求中使用的单数形式“一个”、“一种”以及“该”包括复数基准，除非上下文明确表示相反意思。因此，例如，对“一个步骤”引述意味着对一个或多个步骤的引述，并且可能包括次级步骤。应该以最广义的含义来理解使用的所有连词。因此，词语“或”应该被理解为具有逻辑“或”的定义，而不是逻辑“异或”的定义，除非上下文明确表示相反意思。此处描述的结构将被理解为还引述该结构的功能等效物。可被解释为近似的语言应该被那样理解，除非上下文明确表示相反意思。Furthermore, it is to be understood that this invention is not limited to the particular methods, compounds, materials, fabrication techniques, usages and applications described herein, which may vary. It should also be understood that the terminology described herein is used to describe particular embodiments only and is not intended to limit the scope of the present invention. It must be noted that as used herein and in the appended claims, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" means reference to one or more steps, and may include sub-steps. All conjunctions used should be understood in their broadest sense. Therefore, the word "or" should be understood as having a logical "or" definition rather than a logical "exclusive or", unless the context clearly indicates the contrary meaning. Structures described herein are to be understood as also referring to functional equivalents of the structures. Language that may be construed as approximation should be construed as such, unless the context clearly dictates otherwise.

Claims (12)

一种大电流功率半导体器件的封装结构，其特征在于，包括：A packaging structure for a high-current power semiconductor device, characterized in that it includes: 引线架构，所述引线架构具有多个芯片基岛和位于每个所述芯片基岛对应的引线架构外围的多个电极凸块；a lead structure, the lead structure has a plurality of chip base islands and a plurality of electrode bumps located on the periphery of the lead structure corresponding to each of the chip base islands; 多个芯片，每个所述芯片的正面均设置有一源极和一栅极，背面设置有一漏极，所述多个芯片与所述多个芯片基岛一一对应设置，并使每个所述芯片背面的漏极均贴装于所对应的芯片基岛；A plurality of chips, each of which is provided with a source and a gate on the front, and a drain on the back, the plurality of chips are arranged in one-to-one correspondence with the plurality of chip base islands, and each of the chips The drains on the back of the chip are mounted on the corresponding chip base island; 导电薄膜，部分所述导电薄膜设置在每个所述芯片的漏极与其所对应的芯片基岛之间，以使所述每个芯片的漏极电连接于所对应的芯片基岛对应的引线架构外围的多个电极凸块，而另一部分所述导电薄膜设置在每个芯片的源极和栅极与外接的PCB板之间，以使所述每个芯片的源极和栅极直接电连接于所述PCB板；Conductive film, part of the conductive film is arranged between the drain of each chip and its corresponding chip base island, so that the drain of each chip is electrically connected to the lead corresponding to the corresponding chip base island A plurality of electrode bumps on the periphery of the structure, and another part of the conductive film is arranged between the source and gate of each chip and the external PCB board, so that the source and gate of each chip are directly electrically connected. connected to the PCB board; 塑封材料层，每个所述芯片基岛以及粘贴在其内的芯片和导电薄膜之间的空隙均设有所述塑封材料层，以掩埋每个所述芯片基岛中芯片未被所述导电薄膜所覆盖的表面。A layer of plastic encapsulation material, each of the chip base islands and the gap between the chip and the conductive film pasted therein is provided with the plastic encapsulation material layer, so as to bury the chip in each of the chip base islands that is not covered by the conductive film. The surface covered by the film. 权利要求1所述的大电流功率半导体器件的封装结构，其特征在于，所述导电薄膜的材料包括锡膏。The packaging structure of a high-current power semiconductor device according to claim 1, wherein the material of the conductive thin film includes solder paste. 如权利要求1所述的大电流功率半导体器件的封装结构，其特征在于，所述芯片包括功率MOSFET芯片。The packaging structure of a high-current power semiconductor device according to claim 1, wherein the chip comprises a power MOSFET chip. 如权利要求1所述的大电流功率半导体器件的封装结构，其特征在于，所述塑封材料层的材料包括聚酰亚胺、硅胶以及环氧树脂中的一种固化材料。The packaging structure of a high-current power semiconductor device according to claim 1, wherein the material of the plastic sealing material layer comprises a cured material selected from polyimide, silica gel and epoxy resin. 如权利要求1所述的大电流功率半导体器件的封装结构，其特征在于，每个所述芯片基岛呈板状，并与所述芯片层叠布置，在每个所述芯片基岛的长度方向上的两侧向外延伸分别形成有一翼型连接部，且每个所述翼型连接部在所述芯片基岛的长度方向上向外延伸形成有至少两个相互间隔分布的第一电极凸块，所述第一电极凸块与呈板状的芯片基岛不共面。The packaging structure of high-current power semiconductor devices according to claim 1, wherein each of the chip base islands is plate-shaped and arranged in layers with the chips, in the length direction of each of the chip base islands The two sides of the top extend outward to form an airfoil connection part, and each of the airfoil connection parts extends outward in the length direction of the chip base island to form at least two first electrode protrusions spaced apart from each other. blocks, the first electrode bumps are not coplanar with the plate-shaped chip substrate island. 如权利要求5所述的大电流功率半导体器件的封装结构，其特征在于，在每个所述芯片基岛的宽度方向上的两侧向外延伸分别形成有至少两个 相互间隔分布的且与呈板状的芯片基岛共面的第二电极凸块。The packaging structure of high-current power semiconductor devices according to claim 5, characterized in that, on both sides in the width direction of each said chip base island, there are respectively formed at least two mutually spaced and distributed The plate-shaped chip base island is coplanar with the second electrode bumps. 如权利要求1所述的大电流功率半导体器件的封装结构，其特征在于，所述引线架构的材料为金属。The packaging structure of a high-current power semiconductor device according to claim 1, wherein the material of the lead frame is metal. 一种用于权利要求1～7中任一项所述的封装结构的封装方法，其特征在于，包括以下步骤：A packaging method for the packaging structure described in any one of claims 1 to 7, characterized in that it comprises the following steps: 提供权利要求1～7中任一项所述的大电流功率半导体器件的封装结构中的引线架构，所述引线架构具有多个芯片基岛和位于每个芯片基岛对应的引线架构外围的多个电极凸块；The lead frame in the packaging structure of the high-current power semiconductor device according to any one of claims 1 to 7 is provided, the lead frame has a plurality of chip base islands and multiple lead frame peripherals corresponding to each chip base island. electrode bumps; 提供多个芯片，每个所述芯片的正面均设置有一源极和一栅极，背面设置有一漏极；A plurality of chips are provided, each chip is provided with a source and a gate on the front, and a drain on the back; 将每个所述芯片分别键合在所述引线架构中的一芯片基岛上，以使设置在所述芯片背面的漏极电连接于所对应的芯片基岛对应的引线架构外围的多个电极凸块，并暴露出每一所述芯片的正面；Each of the chips is respectively bonded on a chip base island in the lead structure, so that the drain disposed on the back side of the chip is electrically connected to a plurality of surrounding lead structures corresponding to the corresponding chip base island. electrode bumps exposing the front side of each of said chips; 在每一所述芯片的正面上的源极和栅极的表面上形成导电薄膜，并将所述导电薄膜作为每个芯片的源极和栅极直接电连接于外接PCB板的电极凸块；Form a conductive film on the surface of the source electrode and the grid on the front side of each chip, and directly connect the conductive film to the electrode bump of the external PCB board as the source electrode and the grid of each chip; 形成塑封材料层，位于每个所述芯片基岛以及粘贴在其内的芯片和导电薄膜之间的空隙，以掩埋每个所述芯片基岛中芯片未被导电薄膜所覆盖的表面。A plastic encapsulation material layer is formed, located in the space between each of the chip base islands and the chip pasted therein and the conductive film, so as to bury the surface of the chip in each of the chip base islands that is not covered by the conductive film. 如权利要求8所述的封装方法，其特征在于，将每个所述芯片分别键合在所述引线架构中的一芯片基岛上的步骤，包括：The packaging method according to claim 8, wherein the step of bonding each of the chips to a chip base island in the lead structure includes: 在每个所述芯片基岛的表面上形成导电薄膜，并将所述芯片的背面键合在所述导电薄膜的上表面，所述导电薄膜的上下表面均具有粘性；forming a conductive film on the surface of each of the chip base islands, and bonding the back of the chip to the upper surface of the conductive film, the upper and lower surfaces of the conductive film are sticky; 将粘贴有导电薄膜的所述芯片粘贴在引线架构上的一芯片基岛上，以使设置在所述芯片背面的漏极通过该导电薄膜电连接于所对应的芯片基岛对应的引线架构外围的多个第一电极凸块。Paste the chip with the conductive film on a chip base island on the lead structure, so that the drain electrode arranged on the back of the chip is electrically connected to the periphery of the lead structure corresponding to the corresponding chip base island through the conductive film a plurality of first electrode bumps. 如权利要求7所述的封装方法，其特征在于，在每一所述芯片的正面上的源极和栅极的表面上形成导电薄膜，以作为外接PCB板的电极凸块的工艺包括开钢网刷膜层工艺和回流焊接工艺。The packaging method according to claim 7, wherein the process of forming a conductive film on the surface of the source electrode and the grid on the front side of each chip as an electrode bump on an external PCB board includes opening a steel plate. Screen brush film layer process and reflow soldering process. 如权利要求10所述的封装方法，其特征在于，所述导电薄膜的材料包括锡膏，所述塑封材料层的材料包括聚酰亚胺、硅胶以及环氧树脂中的一种固化材料。The packaging method according to claim 10, wherein the material of the conductive film comprises solder paste, and the material of the plastic sealing material layer comprises a cured material selected from polyimide, silica gel and epoxy resin. 如权利要求8所述的封装方法，其特征在于，所述封装方法还包括：The packaging method according to claim 8, further comprising: 研磨覆盖所述芯片正面上的所述塑封材料层，直至暴露出所述芯片正面上形成在芯片的源极和栅极表面上的所述电极凸块，以及每个芯片基岛对应的引线架构外围的多个电极凸块。Grinding the molding material layer covering the front surface of the chip until the electrode bumps formed on the source and gate surfaces of the chip on the front surface of the chip are exposed, as well as the lead structure corresponding to each chip base island Multiple electrode bumps on the periphery.
PCT/CN2022/133852 2021-11-30 2022-11-24 Packaging structure for large-current power semiconductor device and packaging method therefor WO2023098545A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111443889.7 2021-11-30
CN202111443889.7A CN116207067A (en) 2021-11-30 2021-11-30 Packaging structure and packaging method of high-current power semiconductor device

Publications (1)

Publication Number Publication Date
WO2023098545A1 true WO2023098545A1 (en) 2023-06-08

Family

ID=86506422

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/133852 WO2023098545A1 (en) 2021-11-30 2022-11-24 Packaging structure for large-current power semiconductor device and packaging method therefor

Country Status (2)

Country Link
CN (1) CN116207067A (en)
WO (1) WO2023098545A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117438394A (en) * 2023-12-21 2024-01-23 润新微电子(大连)有限公司 GaN HEMT cascade device multi-layer stack structure and preparation method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116544197A (en) * 2023-07-05 2023-08-04 华羿微电子股份有限公司 Power device packaging structure and packaging method
CN117119807A (en) * 2023-08-10 2023-11-24 惠州佰维存储科技有限公司 Memory device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101080816A (en) * 2004-12-31 2007-11-28 万国半导体股份有限公司 Flip chip contact(PCC) power package
US20070296077A1 (en) * 2006-06-27 2007-12-27 Hvvi Semiconductors, Inc. Semiconductor component and method of manufacture
CN101995707A (en) * 2010-08-30 2011-03-30 昆山龙腾光电有限公司 Fringe field switching (FFS) liquid crystal display (LCD) panel, manufacturing method thereof and LCD
CN102201449A (en) * 2011-05-27 2011-09-28 电子科技大学 Low-heat-resistance packaging structure of power MOS (Metal Oxide Semiconductor) device
US9437528B1 (en) * 2015-09-22 2016-09-06 Alpha And Omega Semiconductor (Cayman) Ltd. Dual-side exposed semiconductor package with ultra-thin die and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101080816A (en) * 2004-12-31 2007-11-28 万国半导体股份有限公司 Flip chip contact(PCC) power package
US20070296077A1 (en) * 2006-06-27 2007-12-27 Hvvi Semiconductors, Inc. Semiconductor component and method of manufacture
CN101995707A (en) * 2010-08-30 2011-03-30 昆山龙腾光电有限公司 Fringe field switching (FFS) liquid crystal display (LCD) panel, manufacturing method thereof and LCD
CN102201449A (en) * 2011-05-27 2011-09-28 电子科技大学 Low-heat-resistance packaging structure of power MOS (Metal Oxide Semiconductor) device
US9437528B1 (en) * 2015-09-22 2016-09-06 Alpha And Omega Semiconductor (Cayman) Ltd. Dual-side exposed semiconductor package with ultra-thin die and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117438394A (en) * 2023-12-21 2024-01-23 润新微电子(大连)有限公司 GaN HEMT cascade device multi-layer stack structure and preparation method thereof
CN117438394B (en) * 2023-12-21 2024-04-16 润新微电子(大连)有限公司 GaN HEMT cascade device multi-layer sealing structure and preparation method thereof

Also Published As

Publication number Publication date
CN116207067A (en) 2023-06-02

Similar Documents

Publication Publication Date Title
TW502406B (en) Ultra-thin package having stacked die
TWI453838B (en) No lead package with heat spreader
JP5227501B2 (en) Stack die package and method of manufacturing the same
WO2023098545A1 (en) Packaging structure for large-current power semiconductor device and packaging method therefor
US20030178719A1 (en) Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package
TW200427029A (en) Thermally enhanced semiconductor package and fabrication method thereof
JPH0955455A (en) Resin-encapsulated semiconductor device, lead frame and manufacture of resin-encapsulated semiconductor device
CN102341899A (en) Leadless array plastic package with multiple IC package structures
TW432558B (en) Dual-chip packaging process and method for forming the package
CN100378972C (en) Heat sink and package using the same
TW201415589A (en) Semiconductor package and fabrication method thereof
TW200531188A (en) Land grid array packaged device and method of forming same
CN101043009A (en) Method of packaging semiconductor die
TW559959B (en) TAB package and method for fabricating the same
TWI332694B (en) Chip package structure and process for fabricating the same
US20080036054A1 (en) Packaging System For Semiconductor Devices
CN101656246A (en) Chip stacking packaging structure of substrate with opening and packaging method thereof
JP3628991B2 (en) Semiconductor device and manufacturing method thereof
CN100411121C (en) Heat dissipation type package structure and manufacturing method thereof
JP3529507B2 (en) Semiconductor device
CN102254880B (en) Chip packaging device and manufacturing method thereof
TW201413904A (en) Wiring member for semiconductor device, composite wiring member for semiconductor device, and resin-sealed semiconductor device
JP3827978B2 (en) Manufacturing method of semiconductor device
TWI860036B (en) Semiconductor package manufacturing method
JPH11274360A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22900350

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22900350

Country of ref document: EP

Kind code of ref document: A1