CN102254880B - Chip packaging device and manufacturing method thereof - Google Patents

Abstract

A chip packaging device comprises a carrier with a chip joint area and at least one electric contact, a chip with an active surface and a passive surface, at least one lead, an adhesive layer, a heat dissipation member and an adhesive body. The chip is arranged on the chip bonding area of the carrier in a manner that the passive surface faces the carrier. The active surface of the chip comprises at least one welding pad, and the wire is correspondingly connected with the at least one welding pad and the at least one electric contact. The adhesion layer covers the active surface of the chip and covers the part of the lead extending on the welding pad. The heat sink is fixed on the adhesion layer and covers the chip. The sealing colloid partially seals the chip, the adhesive layer and the periphery of the heat sink, and a concave opening is formed on the sealing colloid to expose the surface of the heat sink.

Description

Chip packaging device and manufacturing method thereof

technical field

The invention relates to a chip packaging device and a manufacturing method thereof.

Background technique

Generally speaking, semiconductor packaging refers to covering a semiconductor chip with a package body, and providing electrical contacts outside the package body to connect external devices or circuits, and the Ball Grid Array (BGA) package technology (BGA) package technology) is often used to construct semiconductor dies with high density and high pin count. In a conventional BGA package, the semiconductor die is placed on the circuit substrate, the semiconductor die is bonded to the circuit substrate by wire bonds, and the package wraps the semiconductor die and the wires. Solder balls are formed on the backside of the circuit substrate to electrically connect external devices and semiconductor chips.

When the circuits on the semiconductor die operate, the semiconductor die generates heat. In the traditional BGA package, the semiconductor die is covered by a package body that is not easy to conduct heat, so the heat generated by the semiconductor die is not easy to dissipate.

In addition, some BGA packages are equipped with heat sinks inside the package body, hoping to promote the heat dissipation of the semiconductor die. However, due to the poor thermal conductivity of the package, and the heat sink is covered by the package, the improvement of the overall heat dissipation effect is limited.

In addition, US Pat. No. 6,458,626 discloses a package structure, which exposes the surface of the heat sink to improve heat dissipation efficiency. In the packaging structure, after the interface layer/heat sink and the semiconductor chip are completely coated with the packaging colloid, cutting is performed. After cutting, use the interface layer to remove the encapsulation compound above the heat sink to expose the heat sink. However, the method disclosed in this patent is complicated, and the cutting tool is easy to wear out because the cutting tool needs to cut the metal heat sink during the cutting step. Furthermore, metal heat sinks are not easy to cut flat, resulting in poor product quality.

In view of the lack of heat dissipation on the conventional semiconductor package, a new semiconductor heat dissipation design is required.

Contents of the invention

An object of the present invention is to provide a chip packaging device and a manufacturing method thereof. The chip packaging device includes a heat dissipation element, which can be fully exposed outside the package of the chip packaging device, so that the chip packaging device has good heat dissipation efficiency. However, the manufacturing method of a chip packaging device disclosed by the present invention can easily manufacture a packaging structure with exposed heat sinks, without cutting the heat sink after packaging, so the process is simple and the yield is high.

According to the above purpose, an embodiment of the present invention discloses a chip packaging device, which includes a carrier, a chip, at least one wire, an adhesive layer, a heat sink, and an encapsulant. The carrier includes at least one chip bonding area and at least one electrical contact, wherein the at least one electrical contact is arranged along the periphery of the at least one chip bonding area. The chip has an active surface and a passive surface. The chip includes at least one welding pad disposed on the active surface. The chip faces the carrier with the passive surface, and is arranged on the at least one chip bonding area of the carrier. At least one wire connects the at least one welding pad and the at least one electrical contact. The adhesive layer covers the active surface of the chip and covers the part extending on the corresponding at least one welding pad in the at least one wire. The heat sink is fixed on the adhesive layer and covers the chip. The encapsulant partially seals the chip, the adhesive layer and the peripheral side of the heat dissipation element, and forms a recessed opening on the encapsulant to expose the surface of the heat dissipation element.

An embodiment of the present invention discloses a method for manufacturing a chip packaging device, which includes the following steps: providing a carrier, wherein the carrier includes at least one chip bonding area and at least one electrical contact; providing at least one chip, the chip includes an active surface and a passive surface, at least one pad is formed on the active surface of the chip, and the passive surface of the chip is fixed on the at least one chip bonding area of the carrier; the at least one pad and the at least one pad are connected by a wire An electrical contact; an adhesive layer is used to cover the active surface of the chip, wherein the adhesive layer covers the at least one wire extending on the at least one pad; a heat dissipation component is fixed on the adhesive layer, wherein the heat dissipation The component includes a heat dissipation element and a cover element, the heat dissipation element is located between the chip and the cover element; an encapsulant is formed, which is sealed along the periphery of the chip, the adhesive layer and the heat dissipation component, and is placed on the sealing surface exposing the cover on the top surface of the colloid; and removing the cover.

The technical features and advantages of the present disclosure have been briefly described above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claimed scope of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be used as a basis to easily modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure as set forth in the claims.

Description of drawings

FIG. 1 shows a schematic cross-sectional view of a chip packaging device according to an embodiment of the present invention;

2 to 6 are schematic process flow diagrams illustrating a method for manufacturing a chip packaging device according to an embodiment of the present invention;

7 to 9 are schematic process flow diagrams illustrating a method for manufacturing a heat dissipation component according to an embodiment of the present invention; and

FIG. 10 shows a schematic cross-sectional view of a chip packaging device according to another embodiment of the present invention.

Detailed ways

FIG. 1 shows a schematic cross-sectional view of a chip packaging device 1 according to an embodiment of the present invention. 1, the chip packaging device 1 can include a carrier 11, a chip 14, at least one wire 16, an adhesive layer 17, a heat sink 18 and a sealant 19, wherein the chip 14 is arranged on the carrier 11; The layer 17 is arranged on the chip 14; the heat sink 18 is arranged on the adhesive layer 17; the wire 16 is electrically connected to the chip 14 and the carrier 11 and partly covered by the adhesive layer 17; and the sealing body 19 partially seals the chip 14, the adhesive layer 17 and the surrounding area of the heat sink 18 stack structure, and expose the surface 24 of the heat sink 18 .

Specifically, the carrier 11 may include at least one chip bonding area 25 and at least one electrical contact 12 , wherein the at least one electrical contact 12 is disposed on a peripheral side of the at least one chip bonding area 25 . In one embodiment, the carrier 11 includes a plurality of electrical contacts 12 , wherein the electrical contacts 12 are disposed along the periphery of the at least one chip bonding region 25 . The carrier 11 can be a printed circuit board or an FR-4 substrate, an FR-5 substrate, a BT substrate or other similar substrates.

The chip 14 includes at least one bonding pad 15 , an active surface 26 and a passive surface 27 , wherein at least one bonding pad 15 is disposed on the active surface 26 . The chip 14 is bonded to at least one corresponding chip bonding area 25 of the carrier 11 with the passive surface 27 facing the carrier 11, wherein the adhesive 13 may include epoxy resin (epoxy), silver glue or B-stage (B-Stage) Resin.

At least one pad 15 of the chip 14 is connected to at least one corresponding electrical contact 12 on the carrier 11 by a wire 16 .

The adhesive layer 17 covers the active surface 26 of the chip 14 and covers the portion of at least one wire 16 extending on the corresponding at least one pad 15 . In one embodiment, the adhesive layer 17 includes a film over wire (FOW; Film Over Wire) adhesive.

The heat sink 18 is fixed on the adhesive layer 17 and covers the chip 14 . In this embodiment, the surface area of the heat sink 18 is equivalent to the surface area of the chip 14 . In addition, the heat sink 18 can be made of metal (such as copper) or silicon. Moreover, the heat sink 18 has a surface 23 fixed on the adhesive layer 17 and another surface 24 opposite to the surface 23 , wherein the surface 23 can be rougher than the surface 24 to increase the bonding strength between the heat sink 18 and the adhesive layer 17 .

The encapsulant 19 partially seals the peripheral sides of the chip 14 , the adhesive layer 17 and the heat sink 18 . A recessed opening 20 is formed on the encapsulant 19 , wherein the opening 20 exposes the entire surface 24 of the heat sink 18 .

Several solder balls 21 can be formed on the carrier 11 , wherein the solder balls 21 are arranged opposite to the chips 14 . Through the solder balls 21 , the chip 14 is electrically connected to devices or circuits outside the chip packaging device 1 .

2 to 6 are schematic process flow diagrams illustrating a manufacturing method of the chip packaging device 1 according to an embodiment of the present invention. Referring to FIG. 2 , the manufacturing method of the chip packaging device 1 firstly provides a carrier 11 . The carrier 11 includes at least one chip bonding area 25 and at least one electrical contact 12 , wherein the at least one electrical contact 12 is disposed on a peripheral area of the at least one chip bonding area 25 . Next, at least one chip 14 is provided. The chip 14 includes at least one bonding pad 15 , an active surface 26 and a passive surface 27 , wherein at least one bonding pad 15 is disposed on the active surface 26 . Then, with the passive surface 27 of the chip 14 facing the carrier 11 , the chip 14 is fixed to at least one corresponding chip bonding area 25 on the carrier 11 by using the adhesive 13 . Afterwards, at least one wire 16 is used to correspondingly connect the pads 15 on the chip 14 to the electrical contacts 12 on the carrier 11 .

Referring to FIG. 3 , an adhesive layer 17 covers the active surface 26 of the chip 14 , wherein the adhesive layer 17 covers at least part of the wires 16 extending on the corresponding at least one solder pad 15 .

Referring to FIG. 4 , a heat dissipation component 28 is fixed on the adhesive layer 17 , wherein the heat dissipation component 28 includes a heat dissipation element 18 and a cover element 30 . In one embodiment, the size of the heat sink 18 , the adhesive layer 17 , the cover 30 and the chip 14 may be comparable.

Referring to FIG. 5 , an encapsulant 19 is formed on the peripheral side of the chip 14 , the adhesive layer 17 and the heat dissipation component 28 to seal the peripheral side of the chip 14 , the adhesive layer 17 and the heat dissipation component 28 , and on the top surface of the encapsulant 19 The cover 30 is exposed.

Referring to FIG. 6 , after dicing, a plurality of independent chip packaging devices 1 covered by the cover 30 are obtained, and finally the cover 30 is removed. The covering member 30 is an adhesive film that can withstand the high temperature when the sealant 19 is formed. The cover 30 can be a thermal release film, and the cover 30 can be removed by heating. In addition, the cover 30 can also be an adhesive film that can be removed by tearing.

7 to 9 are schematic process flow diagrams illustrating a manufacturing method of the heat dissipation component 28 according to an embodiment of the present invention. Referring to FIG. 7 , the manufacturing method of the heat sink assembly 28 firstly provides a wafer 31 . Then stick a cover sheet 32 on the surface 33 of the wafer 31 .

Referring to FIG. 8, the wafer 31 is thinned to obtain a thinned wafer 31'. Then, the surface 34 of the wafer 31 ′ is roughened or a number of dimples are formed on the surface 34 by chemical etching or ion etching.

Referring to FIG. 9 , the combination of the thinned wafer 31 ′ and the cover sheet 32 is finally cut to obtain several heat dissipation components 28 .

FIG. 10 shows a schematic cross-sectional view of a chip packaging device 3 according to another embodiment of the present invention. Referring to FIG. 10 , the chip packaging device 3 may include a carrier 11 , a chip 14 , at least one wire 16 , an adhesive layer 17 , a heat sink 38 and an encapsulant 39 . The chip 14 is fixed in such a way that its passive surface 27 is adhered to the chip bonding area 25 on the carrier 11 , and the bonding pad 15 is correspondingly connected to the electrical contact 12 located around the chip bonding area 25 by the wire 16 . The adhesive layer 17 covers the active surface 26 of the chip 14 and wraps part of the wires 16 extending on the corresponding bonding pads 15 . The heat sink 38 is fixed and covered on the adhesive layer 17 . The encapsulant 39 partially seals the surrounding area of the stacked structure of the chip 14 , the adhesive layer 17 and the heat sink 38 , and exposes the surface 40 of the heat sink 18 . In this embodiment, the surface area of the heat sink 38 is larger than the surface area of the chip 14 . The heat sink 38 can be made of metal (such as copper) or silicon. Moreover, the heat sink 38 has a surface 41 fixed on the adhesive layer 17 and another surface 40 opposite to the surface 41 , wherein the surface 41 can be rougher than the surface 40 to increase the bonding strength between the heat sink 38 and the adhesive layer 17 .

The encapsulant 39 partially seals the peripheral sides of the chip 14 , the adhesive layer 17 and the heat sink 38 . A recessed opening 20 is formed on the encapsulant 39 , wherein the opening 20 exposes the entire surface 40 of the heat sink 38 .

Several solder balls 21 can be formed on the carrier 11 , wherein the solder balls 21 are arranged opposite to the chips 14 . Through the solder balls 21 , the chip 14 is electrically connected to devices or circuits outside the chip packaging device 3 .

To sum up, the present invention discloses a chip packaging device, which includes a heat sink. The heat dissipation element can be fully exposed outside the package of the chip packaging device, so the chip packaging device has good heat dissipation efficiency. In addition, the chip packaging device further includes an adhesive layer, and the adhesive layer covers part of the wires connecting the chip and the carrier. The present invention also discloses a method for manufacturing a chip packaging device. In this method, a cover is used to cover the heat sink, and then a sealant is formed on the periphery of the chip, the adhesive layer, the heat sink, and the cover, so that the heat sink can be easily manufactured. Exposed package structure without cutting heat sink.

The technical content and technical features of this disclosure have been disclosed above, but those who are familiar with this technology may still make various substitutions and modifications based on the teachings and disclosures of this disclosure without departing from the spirit of this disclosure. Therefore, the protection scope of the present disclosure should not be limited to those disclosed in the embodiments, but should include various replacements and modifications that do not deviate from the present disclosure, and are covered by the claims.

Claims (6)

1. A method for manufacturing a chip packaging device, comprising the following steps: providing a carrier, wherein the carrier includes at least one die bonding area and at least one electrical contact; Provide at least one chip, wherein the chip includes an active surface and a passive surface, at least one pad is formed on the active surface of the chip, the chip faces the carrier with the passive surface, and the at least one chip fixed on the carrier on the junction zone; connecting the at least one pad and the at least one electrical contact with a wire; Covering the active surface of the chip with an adhesive layer, wherein the adhesive layer covers a portion of the wire extending on the at least one pad; fixing a heat dissipation component on the adhesive layer, wherein the heat dissipation component includes a heat dissipation element and a cover, and the heat dissipation element is located between the adhesive layer and the cover; forming an encapsulant, which is sealed along the peripheral sides of the chip, the adhesive layer and the heat dissipation component, and the cover is exposed on the top surface of the encapsulant; and remove the overlay; Wherein, the manufacturing method of the cooling assembly includes the following steps: sticking a cover on a wafer, wherein the cover covers a surface of the wafer; thinning the wafer from another surface of the wafer not covered by the cover; roughening or forming dimples on the other surface of the wafer; and The combination of the cover and the wafer is cut to obtain several heat dissipation components. 2. The manufacturing method according to claim 1, wherein the heat sink is made of silicon. 3 . The manufacturing method according to claim 1 , wherein the step of removing the cover comprises removing the cover by heating or tearing off. 4 . 4 . The manufacturing method according to claim 1 , wherein after the cover is removed, an opening is formed on the top surface of the encapsulant to expose the surface of the heat sink. 5 . The manufacturing method according to claim 1 , wherein the adhesive layer is an adhesive material with a film covering the welding wire. 5 . 6. The manufacturing method according to claim 1, wherein the material of the heat sink is metal.

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