WO2023071077A1 - Display data updating method and apparatus, and display screen - Google Patents

Abstract

Disclosed are a display data updating method and apparatus, and a display screen. The method comprises dividing X rows of pixels of a display into 2Y virtual rows, each virtual row comprising X/2Y rows of pixels, and Y being a data bit width of sub-pixels; and dividing a frame of image data into 2Y rows, storing the 2Y rows of data to a cache part and a storage part in corresponding rows, and driving, by driving units, according to the data stored in the cache part, light-emitting units to emit light, wherein when data of row a is stored, data of the lowest bit in the data of row a is stored to the cache part in the a-th virtual row, data of the remaining (Y-1) bits is stored to the storage part, and data of the next bit stored in the storage part in the (a-(2i-1))-th virtual row is read and written into the cache part in the corresponding row. According to the present invention, the power consumption and the cost can be effectively reduced, and the display effect is improved.

Description

Display data updating method, device and display screen technical field

The invention relates to the field of display technology, in particular to a method and device for updating display data and a display screen with the device.

Background technique

With the continuous development of display technology, displays have become ubiquitous in our daily life, and they are widely used in smartphones, tablets, desktop monitors, TVs, data projectors and augmented reality/virtual reality devices. Depending on the resolution, the display may include different numbers of rows of pixels, each row of pixels may include several sub-pixels, each sub-pixel includes a light-emitting unit and a driving unit, and the driving unit is used to drive the light-emitting unit to emit light. When designing a display, power consumption and cost are usually inevitable considerations. However, some displays in the prior art require a separate storage medium (off-chip storage medium) for storing display data. When displaying an image, the drive unit obtains corresponding data from the storage medium to drive the light-emitting unit to emit light according to the data. Setting up the storage medium separately is likely to cause an increase in cost and high power consumption.

Contents of the invention

The object of the present invention is to provide a display data update method, which can effectively reduce power consumption, and at the same time, provide a display data update device for realizing the display data update method and a display screen with the display data update device.

In order to achieve the above object, the present invention proposes a method for updating display data. The display includes X rows of pixels, each row of pixels includes several sub-pixels, and each sub-pixel includes a data storage unit, a data cache unit, a driving unit and a light emitting unit, X All data storage units of a row of pixels form a storage part, and all data buffer units form a buffer part, and the method for updating display data includes:

S100, dividing the X row of pixels of the display into 2 ^Y virtual rows, each virtual row includes X/2 ^Y rows of pixels, and Y is the data bit width of the sub-pixel;

S200, divide one frame of image data into 2 ^Y lines, and store the data of 2 ^Y lines into the buffer part and the storage part of the corresponding row, and the driving unit drives the light emitting unit to emit light according to the data stored in the buffer part. For row data, store the lowest bit data of row a in the cache part of the virtual row a, store the remaining Y-1 bit data in the storage part, and read the a-(2 ⁱ -1) virtual row The next bit of data stored in the part is stored and written into the cache part of the corresponding row, wherein, i is 1 to Y-1, and a is greater than or equal to 0 and less than or equal to 2 ^Y-1 .

Preferably, in step S200, when a-(2 ⁱ -1) is less than 0, the a-(2 ⁱ -1)+2 ^Yth row reads the next bit of data from the storage part and writes it into the cache part

Preferably, during data storage, the following steps are used to determine the virtual line that is reading the next bit of data from the storage part and storing it in the cache part:

Determine whether the difference between the counter and the virtual row number is one of 2 ^j -1, and when it is one of them, the virtual row corresponding to the virtual row number is reading the next bit of data from the storage part and storing it in the cache part, j It is 0 to Y-1.

Preferably, the storage part is divided into Y-1 storage areas, wherein the kth storage area includes ^2k virtual rows;

The kth storage area stores the k+1th bit data of each row of data, where k is 1 to Y-1.

Preferably, the light emitting time of the driving unit to drive the light emitting unit according to the Y-bit data is divided into 2 ^m ×t, where m is 0˜Y−1, wherein t is T/2 ^Y .

Preferably, the light-emitting time of the driving unit driving the light-emitting unit according to the Y-bit data is distributed according to the weight, and the distribution according to the weight includes the following steps:

According to the number of pixel rows X of the display and the data bit width Y of the sub-pixel, calculate the value of a when (X/2 ^Y )×2 ^a takes the smallest integer P, and a is an integer;

Divide the Y-bit data into two groups, one group includes a-bit data, and one group includes Y-a-bit data;

Divide the time corresponding to the Ya bit data into 2 ^Ya -1 parts;

Judging whether the difference between X and the product of 2 ^Ya and P is 0, and when the difference is 0, in the Ya bit data, the nth bit data is the driving time of 2 ^n-1 P rows; in the difference When it is not 0, in the Ya-bit data, the n-th bit data is the driving time of 2 ^n-1 P rows, and the driving time of the remaining pixel rows is allocated to the driving time required for any one-bit data or multi-bit data , n is 1～Ya.

Preferably, both the data storage unit and the data cache unit include first to sixth switch tubes, and the third switch tube and the fifth switch tube are connected in series between the first power supply and the second power supply to form a first inverter. Phase device, the fourth switching tube and the sixth switching tube are connected in series between the first power supply and the second power supply to form a second inverter, the input terminal of the first inverter is connected to the output of the second inverter The output end is connected to the input end of the second inverter, and the output end is connected to the first data line through the first switch tube, and the output end of the second inverter is connected to the second data line through the second switch tube , the gate of the sixth switching transistor is connected to the driving unit.

Preferably, the withstand voltage values of the first switch tube to the sixth switch tube are all 0.9-1.8V.

The present invention also discloses a device for updating display data. The display includes X rows of pixels, each row of pixels includes several sub-pixels, and each sub-pixel includes a data storage unit, a data buffer unit, a driving unit, and a light emitting unit. All data storage units form a storage part, and all data buffer units form a cache part, and the display data update device includes:

The segmentation module is used to divide the X line pixels of the display into 2 ^Y virtual lines, each virtual line includes X/2 ^Y line pixels, and Y is the data bit width of the sub-pixel;

The processing module is used to divide one frame of image data into 2 ^Y lines, and store the data of 2 ^Y lines into the buffer part and the storage part of the corresponding row, so that the driving unit drives the light emitting unit to emit light according to the data stored in the buffer part, wherein, When storing the a-th row of data, store the lowest bit data of the a-th row of data in the cache part of the a-th virtual row, store the remaining Y-1 bit data in the storage part, and read the a-(2 ⁱ -1 ) stores the next bit of data partially stored in the virtual row and writes it into the cache part of the corresponding row, wherein, i is 1 to Y-1, a is greater than or equal to 0, and is less than or equal to 2 ^Y-1 .

Preferably, both the data storage unit and the data cache unit include first to sixth switch tubes, and the third switch tube and the fifth switch tube are connected in series between the first power supply and the second power supply to form a first inverter. Phase device, the fourth switching tube and the sixth switching tube are connected in series between the first power supply and the second power supply to form a second inverter, the input terminal of the first inverter is connected to the output of the second inverter The output end is connected to the input end of the second inverter, and the output end is connected to the first data line through the first switch tube, and the output end of the second inverter is connected to the second data line through the second switch tube , the gate of the sixth switching transistor is connected to the driving unit.

The beneficial effects of the present invention are:

In the present invention, a data storage unit and a data cache unit for storing data are arranged in each sub-pixel, and the data storage unit and the data cache unit adopt an SRAM structure, which can effectively reduce power consumption, and do not need to set an off-chip storage medium, only need to display It only needs to store the data in the corresponding data storage unit and the data cache unit, which can effectively reduce the cost, and at the same time, the present invention can also improve the display effect.

Description of drawings

FIG. 1 is a schematic flow chart of a method for updating display data;

Fig. 2 is a schematic structural view of a display in an embodiment of the present invention;

Fig. 3 is a schematic structural diagram of a data storage unit and a data cache unit;

Fig. 4 is a schematic diagram of storage part partition;

FIG. 5 is a schematic diagram of data storage in the second area as an example;

Fig. 6 is a schematic structural diagram of a device for updating display data.

Detailed ways

The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention.

As shown in Figure 1, the display data update method disclosed by the present invention includes the following steps:

S100, dividing the X row of pixels of the display into 2 ^Y virtual rows, each virtual row includes X/2 ^Y rows of pixels, and Y is the data bit width of the sub-pixel;

Specifically, as shown in FIG. 2 and FIG. 3 , the display is used for image display, which has X rows of pixels, each row of pixels includes several sub-pixels, and each sub-pixel includes a light emitting unit, a data storage unit, a data buffer unit and a driving unit The data storage unit is used for storing display data, the data buffer unit is used for temporarily storing display data, and the driving unit is used for driving the light emitting unit to emit light according to the data stored in the data buffer unit. In X rows of pixels, the data storage units of all rows form the storage part, and the data buffer units of all rows form the cache part. The location of the storage part can be set according to actual needs. For example, when the area of the sub-pixel is reduced, the storage part can be placed outside the sub-pixel.

Further, the data bit width of each sub-pixel is Y, that is, each sub-pixel corresponds to Y-bit display data, and the Y-bit display data can drive the light-emitting time of the light-emitting unit in the sub-pixel as T, where T is the time for displaying one frame of image, The light-emitting time of each bit of data driving the light-emitting unit is divided into 2 ^m × t, m is 0 ~ Y-1, where t is T/2 ^Y , that is, the driving time of the first bit of data (ie, the lowest bit of data) is 2 ⁰ ×t, the driving time of the second bit of data is 2 ¹ ×t, ..., the driving time of the Yth bit of data is 2 ^Y-1 ×t.

In this embodiment, the light-emitting unit includes a light-emitting element, such as an OLED light-emitting element, etc.;

Both the data storage unit and the data cache unit are SRAM structures composed of 6 switching tubes, the 6 switching tubes are respectively recorded as the first switching tube M1 to the sixth switching tube M6, and the third switching tube M3 and the fifth switching tube M5 are connected in series and connected in series between the first power supply VDD and the second power supply VSS to form a first inverter; the fourth switching tube M4 and the sixth switching tube M6 are connected in series, and the two are also connected in series It is connected between the first power supply VDD and the second power supply VSS to form a second inverter, and at the same time, the gate terminal of the sixth switching transistor M6 is connected to the driving unit; the input terminal of the first inverter is connected to the second inverter connected to the output terminal of the second inverter, and the output terminal of the first inverter is connected to the first data line B0 through the first switch tube M1, and the output terminal of the second inverter is connected to the first data line B0 through the first inverter The second switching tube M2 is connected to the second data line B1, and the input terminal of the second inverter is also connected to the gate terminal of the second driving tube; the gate terminals of the first switching tube M1 and the second switching tube M2 are both connected to the scanning signal line, The data signal lines here are used for inputting data signals, and the scanning signal lines are used for inputting switching signals.

In this embodiment, the first switching tube M1 to the sixth switching tube M6 are all MOS tubes with a withstand voltage of 0.9-1.8V, wherein the first switching tube M1, the second switching tube M2, the fifth switching tube M5 and Both the sixth switch tube M6 are NMOS tubes, and the third switch tube M3 and the fourth switch tube M4 are both PMOS tubes. Since the lower the power supply voltage is when data is written, the lower the power consumption of the data cache unit is, so the data cache unit composed of MOS transistors with low withstand voltage can significantly reduce power consumption. At the same time, since the size of the MOS tube with a low withstand voltage value is significantly smaller than that of a MOS tube with a high withstand voltage value, usually, the size of a MOS tube with a high withstand voltage value is 2 to 3 times larger than that of a MOS tube with a low withstand voltage value. Therefore, the size of the data buffer unit formed by the MOS transistor with a low withstand voltage value is smaller, which can significantly reduce the area of the pixel driving circuit. In addition, the present invention drives a MOS tube with a high withstand voltage by using a MOS tube with a low withstand voltage value. For example, a MOS tube with a withstand voltage value of 1.8V is used to drive a MOS tube with a withstand voltage value of 5V. It needs to be connected to an NMOS transistor with a withstand voltage of 5V that needs to be connected to 0V, that is, in the layout design, a deep N well is made under the entire pixel circuit, and the substrate voltage here is the second power supply VSS voltage when the data logic is 0. (non-zero value), the MOS tubes in the N well only have low withstand voltage MOS tubes and high withstand voltage PMOS tubes, but there is no NMOS tube with a high withstand voltage value that needs to be connected to 0V.

The drive unit includes a first drive tube and a second drive tube, the first drive tube and the second drive tube are connected in series, the first drive tube and the second drive tube are connected in series and then connected between the first power supply and the second power supply, and the second drive tube is connected in series. Both the first drive tube and the second drive tube are PMOS tubes with a withstand voltage of 3.2V-5V. When the NMOS tube is used as the driving tube, on the one hand, when it is turned on at a low voltage, such as 1.8V, the on-resistance generated by it is relatively large, and it cannot drive the light-emitting element to emit light. For example, the resistance of the light-emitting element is 100M ohms. For example, when the NMOS transistor is turned on, the current increases, and the voltage obtained by the light-emitting element becomes larger. At this time, the source voltage of the NMOS transistor increases accordingly, and the on-resistance of the NMOS transistor increases. When the source voltage is greater than Vgs-Vth, the NMOS tube is turned off. At this time, the voltage of the light-emitting element cannot meet the actual demand and cannot produce enough light; on the other hand, if the NMOS tube is driven by high voltage, such as 3.2V ~ 5V When driving the NMOS tube, the NMOS tube cannot be turned off. In addition, when NMOS tubes are used as drive tubes, two types of MOS tubes are required in the branch where the drive tubes are located, that is, NMOS tubes and PMOS tubes are required. The DRC distance between these two types of MOS tubes is relatively large, and finally As a result, the area of the pixel driving circuit is larger. In the present invention, by adopting PMOS transistors instead of NMO transistors for the first driving transistor and the second driving transistor, the light-emitting element can be driven to emit light without increasing the area of the pixel driving circuit.

As shown in FIG. 1 , each sub-pixel also includes a latch buffer for reading data from the data storage unit and storing it in the data buffer unit. In this embodiment, each column of pixels corresponds to a latch buffer, that is to say, all rows of pixels in each column share one latch buffer. By sharing a latch buffer, the chip area under the pixel can be fully utilized, maximizing the utilization of the wafer, and at the same time reducing the pressure on external storage, and the storage function can be realized under the pixel circuit.

Further, the data stored in the data storage unit and the data read from the first buffer circuit through the latch buffer and stored in the data buffer unit are all operated on a whole row at the same time, that is, each row of data is simultaneously operated. storing the data in the data storage unit, or the latch buffer simultaneously reads data from the first buffer circuit and simultaneously writes data into the data buffer unit. If there are 1024 pixels in each row, then there are 2048 data buffer units in each row, and there are 1024 latch buffers. When storing data, the data required by each row of pixels is stored in the data storage unit 40 at the same time, and the 1024 latch buffers simultaneously read the data stored in the corresponding data storage unit 40, and write the data into the corresponding in the data cache unit.

It can be known from the above that the display includes X rows of pixels in total, and X can be 768, 1024, etc., and X can be set according to actual needs. When updating data, first, according to the number of pixel rows X of the display and the data bit width Y of the sub-pixels in each row of pixels, the X row of pixels of the display is divided into 2 ^Y virtual rows, which are respectively recorded as the 0th to Y virtual rows. 2nd ^Y-1 -1 dummy row. By establishing a virtual row, it is convenient for the storage of subsequent display data.

S200, divide one frame of image data into 2 ^Y lines, and store the data of 2 ^Y lines into the buffer part and the storage part of the corresponding row, and the driving unit drives the light emitting unit to emit light according to the data stored in the buffer part. For row data, store the lowest bit data of row a in the cache part of the virtual row a, store the remaining Y-1 bit data in the storage part, and read the a-(2 ⁱ -1) virtual row The next bit of data stored in the part is stored and written into the cache part of the corresponding row, wherein, i is 1 to Y-1, and a is greater than or equal to 0 and less than or equal to 2 ^Y-1 .

Specifically, when performing data update, one frame of image data is firstly divided into 2 ^Y lines of data, which are denoted as 0th to 2nd ^Y-1 -1 lines of data. When the data of the 0th row is input, the data of the lowest bit is first written into the cache part of the 0th virtual row, and the rest of the data is written into the storage part, and the driving unit drives the light emitting unit to emit light according to the data stored in the cache part.

When the data of the first row is input, the lowest bit data is first written into the cache part of the first virtual row, and the rest of the data is written into the storage part. At this time, in the 0th virtual row, the drive unit drives and emits light according to the data stored in the cache part. When the time for the unit to emit light is up, the second bit of data in the storage part needs to be read out and written into the buffer part, and the driving unit drives the light emitting unit to emit light again according to the data stored in the buffer part.

When the data of the second row is input, the data of the lowest bit is first written into the cache part of the second virtual row, and the rest of the data is written into the storage part. It is time for the stored data to drive the light-emitting unit to emit light. It is necessary to read the next bit of data in the storage part and write it into the cache part. The drive unit drives the light-emitting unit to emit light according to the data stored in the cache part. For example, the 0th imaginary row needs to read the third bit of data from the storage part to drive and emit light, and the first dummy row needs to read the second bit of data from the storage part to drive and emit light.

And so on;

When inputting the data of the ath row, the data of the lowest bit is first written into the cache part of the ath virtual row, and the rest of the data is written into the storage part. At this time, in the a-(2 ⁱ -1)th virtual row, i is 1～Y-1, the driving time of this line Y-1 is up, that is, a-(2 ¹ -1), a-(2 ² -1), a-(2 ³ -1),..., a- (2 ^Y-1 -1) The driving time of the row is up, that is to say, the time for the driving unit to drive the light-emitting unit to emit light according to the data stored in the buffer part is up, and the next bit of data stored in the storage part needs to be read out and written into the buffer part, the driving unit drives the light emitting unit to emit light according to the data stored in the cache part.

When in the 2nd ^Y-1-1 data, after the remaining Y-1 bit data are all stored in the storage part, at this moment, there are 2 virtual rows storing the second bit data (2nd ^Y-1-1 virtual row , 2nd ^Y-1-2 virtual row), there are 4 rows (2nd ^Y-1-3 virtual row, 2nd ^Y- 1-6 virtual row) for storing the third data, storing the Y-1 bit There are 2 ^Y-1 rows, therefore, the number of virtual rows that need to be stored is 2 ^Y -2 rows. Since the number of data storage units in the virtual row is ^2Y , the storage requirement can be met.

Further, in the process of storing 2 ^Y lines of data of a frame of image data, the following steps can be used to determine which virtual lines are reading data from the storage part and writing to the buffer part.

If the a-th row of data is input at this time, the a-(2 ⁱ -1)th row is reading data from the storage part and writing it into the cache part, and i is 1 to Y-1. Due to the number of virtual lines calculated by a-(2 ¹ -1), a-(2 ² -1), a-(2 ³ -1), ..., a-(2 ^Y-1 -1) may There are negative numbers, so the situation of negative numbers can be avoided by introducing 2 ^Y virtual number of rows into the calculated number of virtual rows, that is, when a-(2 ⁱ -1) is less than 0, the first a-(2 ⁱ -1)+ Line 2 ^Y reads the next bit of data from the storage section and writes it into the cache section.

Of course, in other embodiments, which virtual lines are reading data from the storage part and writing into the cache part can also be determined by the virtual line number (Line-Id) and the counter (line-cnt). Specifically, when the difference between the virtual row number and the counter is one of ^2j -1, the virtual row corresponding to the virtual row number is the virtual row that is reading data from the storage part and writing the cache part, and j is 0 ~Y-1.

As shown in Figure 4 and Figure 5, the Y-1 bit data in each row of data is stored through the following steps:

First, the storage part is divided into Y-1 storage areas, wherein the first storage area includes 2 virtual rows, the second storage area includes 4 virtual rows, ..., the Y-1th storage area contains 2 ^{Y- 1} virtual row, that is, the kth storage area includes ^2k virtual rows, where k is 1 to Y-1;

Finally, store the second bit data of each row of data in the first storage area, store the third bit data of each row of data in the second storage area, ..., store the Y-th bit of each row of data in the Y-1 storage area Bit data, that is, the k+1th bit data of each row of data is stored in the kth storage area.

Specifically, when storing 2 ^Y rows of data, the number of required virtual rows is 2 ^Y -2 rows, and there are 2 virtual rows for storing the second bit of data (the above-mentioned 2 ^Y-1 rows of data are stored as For example, the 2nd ^Y-1 -1 virtual row to the 2nd ^Y-1 -2 virtual row), there are 4 virtual rows for storing the third data (take the above-mentioned 2nd ^Y-1 row data storage as an example , wherein the 2nd ^Y-1-3 virtual row to the 2nd ^Y- 1-6 virtual row), ..., there are 2 ^Y-1 rows storing the Y-1th bit data. Therefore, the storage part can be divided into Y-1 storage areas. After being divided into storage areas, store the second bit data of each row of data in the first storage area, store the third bit data of each row of data in the second storage area, ..., store each row of data in the Y-1 storage area The Yth bit data of the row data. As shown in Figure 5, taking the second storage area as an example, when the data from row 0 to the second row is input, the third bit data stores the first three virtual rows of the second storage area, and when the data on the third row is input, the first three virtual rows of the second storage area are stored. The third data is stored in the fourth virtual row of the second storage area, and at the same time, the third bit data stored in the first virtual row in the second storage area is read out to store the cache part, and the driving unit can drive light according to the third bit data The unit glows. When the fourth line is input, the third bit of data is stored in the first virtual line of the second storage area, and at the same time, the data in the second virtual line of the second storage area is read and written into the cache part. In other words, when the last row of data is stored in each storage area, the first virtual row of data is taken out, and then the cycle starts to store a row of data and take out the previous row of data at the same time.

Further, when the driving unit drives the light-emitting unit to emit light, the light-emitting time of the light-emitting unit is respectively 2 ⁰ ×t, 2 ¹ ×t, 2 ² ×t, ..., 2 ^Y-1 ×t, that is, the first The driving time of one bit of data is 2 ⁰ ×t, the driving time of the second bit of data is 2 ¹ ×t, and so on, the driving time of the Yth bit of data is 2 ^Y-1 ×t, where t=T/2 ^Y and T are the display time of one frame of image. However, when the driving unit drives the light-emitting unit to emit light, the light-emitting time of the light-emitting unit may not follow the above rules, and weight redistribution is required at this time. specifically,

First, according to the number of pixel rows X of the display and the data bit width Y of the sub-pixel, calculate the value of a when (X/2 ^Y )×2 ^a takes the smallest integer P, and a is an integer;

Secondly, the Y-bit data is divided into two groups, one group includes a-bit data, and one group includes Y-a-bit data;

Secondly, the time corresponding to the Ya bit data is divided into 2 ^Ya -1 parts;

Second, judge whether the difference between X and the product of 2 ^Ya and P is 0. When the difference is 0, then in the Ya-bit data, the first bit of data is the time of P row, the second bit of data is the time of 2P row,..., the Ya-th bit of data is the time of 2 ^Ya-1 P, That is, the nth bit of data is the driving time of 2 ^n-1 P rows, and n is 1˜Ya. When the difference is non-zero, the first bit of data is the time of P lines, the second bit of data is the time of 2P lines, ..., and the remaining pixel lines are arranged in any one bit of data. During implementation, the weights of all data can also be configured. For example, for the first a data, it can be configured as P rows, or P±Q _f rows, and the weights of the rest of the data can be configured as 2 ^Ya-1 P±Q _f travel time, the configuration basis is approximately 2 ^Ya-1 P travel time, Q _f corresponding to each bit of data can be configured according to actual needs.

Specifically, taking a display with 400 rows of pixels as an example, and the data bit width of the sub-pixel is 12, the total driving time for 12-bit data is T, and the driving time for the first bit of data (the lowest bit) is t=T/2 ¹² . T here is the display time of one frame of image. Since the display contains 400 rows of pixels, the display time of each row of pixels is 256t/25.

Further, according to the number of pixel rows X of the display and the data bit width Y of the sub-pixel, calculate the value of a when (X/2 ^Y )×2 ^a takes the smallest integer P, and substitute X=400 and Y=12 into the above formula , and make a gradually increase from 1. When a is 5, P can obtain the smallest positive integer. It can be seen through calculation that P is 3, that is to say, the driving time of the first 5 bits of data is about the driving time of 3 rows. The driving time of the first (lowest bit) data in the last 7 bits of data is the same as the sum of the driving times of the first 5 bits of data.

Further, the driving time of the last 7-bit data is divided into 127 parts, and 127×3=381, plus the 3 lines corresponding to the previous 5-bit data, a total of 384 lines, it can be seen that there is a difference of 16 lines from the number of pixel lines of the display , the timing of these 16 rows needs to be redistributed. During implementation, the time of these 16 lines can be allocated to any one bit of data, for example, in the last 7 bits of data, the first bit of data is a time of 3 lines, and the second bit of data is two times of 3 lines, The third bit of data is 4 times of 3 lines, the fourth bit of data is 8 times of 3 lines, the fifth bit of data is 16 times of 3 lines, the sixth bit of data is 34 times of 3 lines, the seventh The bit data is 67 times of 3 lines. Another example is that the time of the 16 lines can be directly configured in the last bit of data, which can be set according to actual needs.

Take the display including 768 rows of pixels as an example, and the data bit width of the sub-pixel is 12. According to the number of pixel rows X of the display and the data bit width Y of the sub-pixel, calculate (X/2 ^Y )×2 ^a when taking the smallest integer P Substitute X=400, Y=12 into the above formula, and make a gradually increase from 1. When a is 4, P can obtain the smallest positive integer, and it can be known that P is 3 through calculation. That is to say, the driving time of the first 4 bits of data is about the driving time of 3 rows. Then, the driving time of the first (lowest bit) data in the last 8 bits of data is the same as the sum of the driving times of the first 4 bits of data.

Further, the last 8-bit data is divided into 255 parts, and the total number of rows is (255+1)×3=768, which is the same as the number of pixel rows of the display, so there is no need to perform weight distribution, and only need to distribute according to the multiple of 2, That is: the first (lowest) data is the time of one 3-line, the second data is two 3-line time, the third data is four 3-line time, ..., the eighth data For 128 times of 3 rows.

Further, when the time is allocated according to the weight, the P rows of data are updated at one time. When updating, the time of the first 3 rows updates the first 5 digits of data, and is updated 32 times, that is, the time of the 3 rows is divided into 32 points, and each The time updates the data once, and the last 7 bits of data are updated according to the time when the lowest bit is 3 rows. And when updating, it can also determine which 3 virtual lines are reading data from the storage part and writing to the cache part according to the virtual line number (Line-Id) and counter (line-cnt), such as 400 lines plus two empty lines The line is divided into 134 three lines. At this time, the counter is from 0 to 133, and the virtual line number is also 0 to 133. When the counter subtracts the virtual line number, the value is 0, 1, 2, 6, 14, 30, 64 , 131, these 3 lines all need to update data.

Furthermore, when storing Y-1 bit data of each row of data, the partition needs to be adjusted appropriately according to the weight of each bit of data. For example, if the above-mentioned display contains 400 rows of pixels, the storage part can be divided into 7 storage areas, each The number of rows in the zone is consistent with the weight of the last 7 digits.

As shown in Figure 6, the present invention also discloses a device for updating display data, including a segmentation module and a data processing module, wherein the segmentation module is used to divide the X row of pixels of the display into 2 ^Y virtual rows, each virtual row Including X/2 ^Y rows of pixels, Y is the data bit width of the sub-pixel; the data processing module is used to divide a frame of image data into 2 ^Y rows, and store the 2 ^Y rows of data into the cache part and storage part of the corresponding row , so that the driving unit drives the light-emitting unit to emit light according to the data stored in the buffer part, wherein, when storing the a-th row of data, the lowest bit data of the a-th row of data is stored in the buffer part of the a-th virtual row, and the remaining Y-1 The bit data is stored in the storage part, and the next bit data stored in the storage part of the a-(2 ⁱ -1)th virtual row is read and written into the cache part of the corresponding row, wherein, i is 1 to Y-1, and a is greater than Or equal to 0, and less than or equal to 2 ^Y-1 , see the above for details, and will not repeat them here.

In the present invention, a data storage unit and a data cache unit for storing data are arranged in each sub-pixel, and the data storage unit and the data cache unit adopt an SRAM structure, which can effectively reduce power consumption, and do not need to set an off-chip storage medium, only need to display The data can be stored in the corresponding data storage unit and the data cache unit, which can effectively reduce the cost.

The technical contents and technical characteristics of the present invention have been disclosed above, but those skilled in the art may still make various replacements and modifications based on the teachings and disclosures of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to The content disclosed in the embodiment should include various replacements and modifications that do not depart from the present invention, and are covered by the claims of this patent application.

Claims (11)

A display data update method, the display includes X rows of pixels, each row of pixels includes several sub-pixels, each sub-pixel includes a data storage unit, a data buffer unit, a driving unit and a light emitting unit, and all the data storage units of the X row of pixels are composed In the storage part, all data cache units form a cache part, and the display data update method includes: S100, dividing the X row of pixels of the display into 2 ^Y virtual rows, each virtual row includes X/2 ^Y rows of pixels, and Y is the data bit width of the sub-pixel; S200, divide one frame of image data into 2 ^Y lines, and store the data of 2 ^Y lines into the buffer part and the storage part of the corresponding row, and the driving unit drives the light emitting unit to emit light according to the data stored in the buffer part. For row data, store the lowest bit data of row a in the cache part of the virtual row a, store the remaining Y-1 bit data in the storage part, and read the a-(2 ⁱ -1) virtual row The next bit of data stored in the part is stored and written into the cache part of the corresponding row, wherein, i is 1 to Y-1, and a is greater than or equal to 0 and less than or equal to 2 ^Y-1 . The display data update method according to claim 1, in step S200, when a-(2 ⁱ -1) is less than 0, the a-(2 ⁱ -1)+2 ^Y line reads the next bit from the storage part data and write to the cache section. According to the display data update method described in claim 1, when data is stored, it is determined by the following steps that the next bit of data is being read from the storage part and stored in the virtual line of the cache part: Determine whether the difference between the counter and the virtual row number is one of 2 ^j -1, and when it is one of them, the virtual row corresponding to the virtual row number is reading the next bit of data from the storage part and storing it in the cache part, j It is 0 to Y-1. According to the display data update method described in claim 1, in step S200, the remaining Y-1 bit data is stored in the storage part through the following steps: Divide the storage part into Y-1 storage areas, wherein the kth storage area includes 2 ^k virtual rows; The kth storage area stores the k+1th bit data of each row of data, where k is 1 to Y-1. According to the method for updating display data according to claim 1, the light emitting time of the driving unit driving the light emitting unit according to the Y-bit data is divided into 2 ^m × t, where m is 0 to Y-1, wherein t is T/2 ^Y . According to the method for updating display data according to claim 1, the driving unit drives the light-emitting time of the light-emitting unit according to the Y-bit data to distribute according to the weight, and the distribution according to the weight comprises the following steps: According to the number of pixel rows X of the display and the data bit width Y of the sub-pixel, calculate the value of a when (X/2 ^Y )×2 ^a takes the smallest integer P, and a is an integer; Divide the Y-bit data into two groups, one group includes a-bit data, and one group includes Y-a-bit data; Divide the time corresponding to the Ya bit data into 2 ^Ya -1 parts; Judging whether the difference between X and the product of 2 ^Ya and P is 0, and when the difference is 0, in the Ya bit data, the nth bit data is the driving time of 2 ^n-1 P rows; in the difference When it is not 0, in the Ya-bit data, the n-th bit data is the driving time of 2 ^n-1 P rows, and the driving time of the remaining pixel rows is allocated to the driving time required for any one-bit data or multi-bit data , n is 1～Ya. According to the method for updating display data according to claim 1, the data storage unit and the data cache unit both include first to sixth switch tubes, and the third switch tube and the fifth switch tube are connected in series to the first power supply and the sixth switch tube. Between the two power supplies, a first inverter is formed, the fourth switching tube and the sixth switching tube are connected in series between the first power supply and the second power supply, forming a second inverter, and the input of the first inverter The terminal is connected to the output terminal of the second inverter, the output terminal is connected to the input terminal of the second inverter, and the output terminal is connected to the first data line through the first switch tube, and the output terminal of the second inverter is connected through the The second switch transistor is connected to the second data line, and the gate of the sixth switch transistor is connected to the driving unit. According to the display data updating method according to claim 7, the withstand voltage values of the first switch tube to the sixth switch tube are all 0.9-1.8V. A display data updating device, the display includes X rows of pixels, each row of pixels includes several sub-pixels, each sub-pixel includes a data storage unit, a data buffer unit, a driving unit and a light emitting unit, and all data storage units of the X row of pixels are composed of In the storage part, all data cache units form a cache part, and the display data update device includes: The segmentation module is used to divide the X line pixels of the display into 2 ^Y virtual lines, each virtual line includes X/2 ^Y line pixels, and Y is the data bit width of the sub-pixel; The data processing module is used to divide a frame of image data into 2 ^Y lines, and store the 2 ^Y lines of data into the buffer part and the storage part of the corresponding row, so that the driving unit drives the light emitting unit to emit light according to the data stored in the buffer part, wherein , when storing the a-th row of data, store the lowest bit data of the a-th row of data in the cache part of the a-th virtual row, store the remaining Y-1 bit data in the storage part, and read the a-(2 ⁱ - 1) The next bit of data partially stored is stored in the virtual row and written into the cache part of the corresponding row, wherein, i is 1 to Y-1, a is greater than or equal to 0 and less than or equal to 2 ^Y-1 . According to the display data update device according to claim 9, the data storage unit and the data cache unit both include first to sixth switch tubes, and the third switch tube and the fifth switch tube are connected in series to the first power supply and the sixth switch tube. Between the two power supplies, a first inverter is formed, the fourth switching tube and the sixth switching tube are connected in series between the first power supply and the second power supply, forming a second inverter, and the input of the first inverter The terminal is connected to the output terminal of the second inverter, the output terminal is connected to the input terminal of the second inverter, and the output terminal is connected to the first data line through the first switch tube, and the output terminal of the second inverter is connected through the The second switch transistor is connected to the second data line, and the gate of the sixth switch transistor is connected to the driving unit. A display screen, characterized by comprising the display data updating device described in any one of claims 9-10.

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