CN103544926A - Liquid crystal display panel and display device - Google Patents
Liquid crystal display panel and display device Download PDFInfo
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- CN103544926A CN103544926A CN201310490559.2A CN201310490559A CN103544926A CN 103544926 A CN103544926 A CN 103544926A CN 201310490559 A CN201310490559 A CN 201310490559A CN 103544926 A CN103544926 A CN 103544926A
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 15
- 230000005540 biological transmission Effects 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 5
- 230000011664 signaling Effects 0.000 claims description 4
- 230000007704 transition Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- 239000010409 thin film Substances 0.000 description 1
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Abstract
The invention discloses a liquid crystal display panel and a display device which are low in cost. The display panel comprises a plurality of gate scanning lines, a plurality of data lines, a plurality of pixels, a gate driver, and a time schedule controller. The gate scanning lines are arranged along a longitudinal direction. The data lines are arranged along a horizontal direction and are intersected with the gate scanning lines in an insulating manner. Each pixel comprises a plurality of sub-pixels arranged in parallel along a longitudinal direction, and each sub-pixel is composed of unit areas limited by the gate scanning lines and the data lines. The gate drivers are connected with the gate scanning lines. The time schedule controller is respectively connected with the gate drivers and source drivers, is used for sending time schedule control signals to the gate drivers and the source drivers, and inputs received video data signals to the source drivers. Due to the fact that positions of the source drivers and the gate drivers are exchanged, a plurality of data lines can be omitted, number of the source drivers can be reduced, and cost of a product is greatly lowered on the premise of not changing image quality.
Description
Technical field
The present invention relates to electronic technology field, particularly relate to a kind of display panels and display device.
Background technology
Liquid crystal panel because volume is little, thin thickness, lightweight, power consumption less, electromagnetic-radiation-free, picture flicker free, avoid geometric distortion, the plurality of advantages such as anti-interference to be widely used in the every field such as televisor, display, supervisory system.But the price of liquid crystal panel is always high, become its universal key factor of restriction.Therefore, reduce the key that cost of products becomes industry technological breakthrough.
In liquid crystal panel, the direction that three sub-pixels in each pixel follow according to red/green/blue order is arranged in order.The schematic diagram of liquid crystal panel as depicted in figs. 1 and 2, the working method of liquid crystal panel is: time schedule controller (T-con) receives the low voltage difference vision signal (LVDS) that mainboard transmits, export after treatment control signal TP1, the control signals such as POL are to data driver (Source Driver IC), output CPV, OE, STVA, the control signals such as T1 are to gate drivers (Gate Driver IC), and outputting data signals (data layout is mini-LVDS) is given data driver (Source Driver IC), by data driver (Source Driver IC) and gate drivers (Gate Driver IC), drive thin film transistor (TFT) (TFT), realizing video shows.
At present, the displaying principle of liquid crystal panel is, each sub-pixel needs independent data to control its demonstration, take resolution as 1920*1080 be example, data driver (Source Driver IC) demand motive H=1920*3 column data (in data line 1 corresponding diagram 1, be S1, S2, S3 ...), the capable switching signal of gate drivers (Gate Driver IC) driving V=1080 (in controlling grid scan line 2 corresponding diagram 1, be n, n+1, n+2 ...).In when normal operation, the same time of gate drivers is only opened the capable pixel of n, and the data that then data driver is exported this line show; Then n is capable closes, the capable unlatching of n+1 simultaneously, and the capable data of data driver input n+1, show.Therefore, the Source Driver IC quantity needing is more than Gate Driver IC, and the data-driven line that display panel needs is H=1920*3 bar, and controlling grid scan line is V=1080 bar.Under current market condition, the price of the cost ratio Gate Driver IC of Source Driver IC is high a lot, because required data driver quantity is more, causes the cost of liquid crystal panel higher.
Summary of the invention
The object of the invention is for the technological deficiency existing in prior art, and the display panels that a kind of cost is low be provided, for realizing the technical scheme that object of the present invention adopts, be:
, comprising:
Many the controlling grid scan lines of arranging along column direction;
Many the data lines of arranging, intersecting with described controlling grid scan line insulation along line direction;
A plurality of pixels, are rectangular distribution; Wherein, each pixel comprises a plurality of sub-pixels that are arranged in parallel along column direction, and the unit area that each sub-pixel is limited by described controlling grid scan line and described data line forms;
The gate drivers being connected with described controlling grid scan line, for sequentially providing grid impulse to described controlling grid scan line;
The data driver being connected with described data line, for providing data voltage to described data line;
The time schedule controller being connected with described data driver with described gate drivers respectively, for to described gate drivers and described data driver transmission timing control signal, and the video data signal receiving to described data driver input.
Preferably, the length of the line direction of each sub-pixel is longer than the length of the column direction of each sub-pixel.
Preferably, each pixel comprises red sub-pixel R, green sub-pixels G and blue subpixels B, and wherein, red sub-pixel R, green sub-pixels G and blue subpixels B are arranged in parallel along column direction successively; The sub-pixel of same color is arranged in parallel along line direction.
Preferably, described timing control signal comprises for the grid timing control signal in time sequential routine of control gate driver with for controlling the data time sequence control signal in the polarity of data voltage and the time sequential routine of data driver.
Preferably, when the video data format receiving when described time schedule controller does not meet column scan condition, described time schedule controller also comprises storer, the video data signal that described storer receives for buffer memory, and described video data signal is exported to described data driver according to each row pixel data.
Further preferred, described storer is frame buffer.
Another object of the present invention is to provide the liquid crystal indicator that a kind of cost is low, for realizing the technical scheme that this object adopts, is:
, comprising:
Display panels as above;
Display control chip, is connected with described time schedule controller, for the video data signal of external video equipment input being converted to the data layout that is suitable for the resolution that shows at described display panels.
Preferably, described display control chip by Low Voltage Differential Signal interface or transition minimized differential signaling interface to described time schedule controller inputting video data signal.
Compared with prior art, the invention has the beneficial effects as follows:
Display panels of the present invention and liquid crystal indicator, by the position of swap data driver and gate drivers, can omit many data lines; Red sub-pixel R in each pixel, green sub-pixels G and blue subpixels B adopt and along column direction, are arranged in parallel successively, and the sub-pixel of same color is arranged in parallel along line direction; Memory stores one frame image data by increase with caching function, then exports view data and shows with the unit of classifying as, can save the quantity of data driver under the prerequisite that does not change image quality, greatly reduces the cost of product.
Accompanying drawing explanation
Figure 1 shows that the structural representation of display panels of the prior art;
Figure 2 shows that the circuit theory diagrams of display panels of the prior art;
Figure 3 shows that the structural representation of display panels of the present invention;
Figure 4 shows that the circuit theory diagrams of display panels of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.
Display panels of the present invention is by the position of swap data driver and gate drivers, to reduce the quantity of data line and data driver, to reach the object reducing costs.Its schematic diagram as shown in Figure 3 and Figure 4, comprises many controlling grid scan lines 2, many data lines 1, a plurality of pixel, gate drivers, data driver and time schedule controllers, and many described controlling grid scan lines are arranged along column direction; Many described data line is arranged along line direction, and intersects with described controlling grid scan line insulation; Described a plurality of pixel is rectangular distribution, and wherein, each pixel comprises a plurality of sub-pixels that are arranged in parallel along column direction, and the unit area that each sub-pixel is limited by described controlling grid scan line and described data line forms.In the present embodiment, the length of the line direction of each sub-pixel is longer than the length of the column direction of each sub-pixel.Each pixel comprises red sub-pixel R, green sub-pixels G and blue subpixels B, and wherein, red sub-pixel R, green sub-pixels G and blue subpixels B are arranged in parallel along column direction successively; The sub-pixel of same color is arranged in parallel along line direction.
Described gate drivers is connected with described controlling grid scan line, for sequentially providing grid impulse to described controlling grid scan line.Described data driver is connected with described data line, for providing data voltage to described data line.Described time schedule controller is connected with described data driver with described gate drivers respectively, for to described gate drivers and described data driver transmission timing control signal, and the video data signal receiving to described data driver input.In the present embodiment, described timing control signal comprises grid timing control signal for the time sequential routine of control gate driver, for controlling the polarity of data voltage and for controlling the data time sequence control signal in the time sequential routine of data driver.
The vision signal that described time schedule controller in the present embodiment receives can be the vision signal converting to from the display control chip in display, or receives the vision signal from PC or other equipment video cards.
Described time schedule controller sends grid timing control signal to gate drivers, and the video data signal that sends data time sequence control signal and receive to data driver, control corresponding controlling grid scan line and data line, the vision signal that described time schedule controller receives meets the condition of column scan.The same time of gate drivers is only opened n row pixel, and the video data that then data driver is exported these row shows; Then n row are closed, and n+1 row are opened simultaneously, and the video data of data driver input n+1 row, shows.By that analogy, complete the output of video data and show.
By the display panels of embodiment 1 and conventional miscellaneous part, form liquid crystal indicator.This liquid crystal indicator comprises many controlling grid scan lines, many data lines, a plurality of pixel, gate drivers, data driver, time schedule controller and display control chips.Many described controlling grid scan line is arranged along column direction; Many described data line is arranged along line direction, and intersects with described controlling grid scan line insulation; Described a plurality of pixel is rectangular distribution, and wherein, each pixel comprises a plurality of sub-pixels that are arranged in parallel along column direction, and the unit area that each sub-pixel is limited by described controlling grid scan line and described data line forms.In the present embodiment, the length of the line direction of each sub-pixel is longer than the length of the column direction of each sub-pixel.Each pixel comprises red sub-pixel R, green sub-pixels G and blue subpixels B, and wherein, red sub-pixel R, green sub-pixels G and blue subpixels B are arranged in parallel along column direction successively; The sub-pixel of same color is arranged in parallel along line direction.
Described gate drivers is connected with described controlling grid scan line, for sequentially providing grid impulse to described controlling grid scan line.Described data driver is connected with described data line, for providing data voltage to described data line.Described time schedule controller is connected with described data driver with described gate drivers respectively, for to described gate drivers and described data driver transmission timing control signal, and the video data signal receiving to described data driver input.In the present embodiment, described timing control signal comprises for the grid timing control signal in the time sequential routine of control gate driver with for controlling the data time sequence control signal in the polarity of data voltage and the time sequential routine of data driver.Described display control chip is connected with described time schedule controller, for the video data signal of external video equipment input being converted to the data layout that is suitable for the resolution that shows at described display panels.In the present embodiment, described display control chip by Low Voltage Differential Signal (LVDS) interface or transition minimized differential signaling (TMDS) interface to described time schedule controller inputting video data signal.
Described display control chip is converted to the video data signal of external video equipment input the data layout that is suitable for the resolution that shows in described display panels, by Low Voltage Differential Signal (LVDS) interface or transition minimized differential signaling (TMDS) interface to described time schedule controller inputting video data signal.Described time schedule controller sends grid timing control signal to gate drivers, and the video data signal that sends data time sequence control signal and receive to data driver, controls corresponding controlling grid scan line and data line.The same time of gate drivers is only opened n row pixel, and the video data that then data driver is exported these row shows; Then n row are closed, and n+1 row are opened simultaneously, and data driver is inputted the video data of n+1 row, shows.By that analogy, complete the output of vision signal and show.
Display panels of the present invention is by the position of swap data driver and gate drivers, to reduce the quantity of data line and data driver, to reach the object reducing costs.Its schematic diagram as shown in Figure 3 and Figure 4, comprises many controlling grid scan lines 2, many data lines 1, a plurality of pixel, gate drivers, data driver and time schedule controllers, and many described controlling grid scan lines are arranged along column direction; Many described data line is arranged along line direction, and intersects with described controlling grid scan line insulation; Described a plurality of pixel is rectangular distribution, and wherein, each pixel comprises a plurality of sub-pixels that are arranged in parallel along column direction, and the unit area that each sub-pixel is limited by described controlling grid scan line and described data line forms.In the present embodiment, the length of the line direction of each sub-pixel is longer than the length of the column direction of each sub-pixel.Each pixel comprises red sub-pixel R, green sub-pixels G and blue subpixels B, and wherein, red sub-pixel R, green sub-pixels G and blue subpixels B are arranged in parallel along column direction successively; The sub-pixel of same color is arranged in parallel along line direction.
Described gate drivers is connected with described controlling grid scan line, for sequentially providing grid impulse to described controlling grid scan line.Described data driver is connected with described data line, for providing data voltage to described data line.Described time schedule controller is connected with described data driver with described gate drivers respectively, described time schedule controller is used for to described gate drivers and described data driver transmission timing control signal, and to described data driver output video data-signal.In the present embodiment, described timing control signal comprises for the grid timing control signal in the time sequential routine of control gate driver with for controlling the data time sequence control signal in the polarity of data voltage and the time sequential routine of data driver.
When the video data format receiving when described time schedule controller does not meet column scan condition, in described time schedule controller, increase and be provided with storer, the video data signal that described storer is changed for time schedule controller described in buffer memory, and video data signal is exported to data driver according to each row pixel data.Storer in the present embodiment is frame buffer (Frame Buffer).
Described time schedule controller receiving video data signal, is cached in a frame image data in storer.Time schedule controller sends grid timing control signal to gate drivers, and sends data time sequence control signal and video data signal to data driver, controls corresponding controlling grid scan line and data line.The same time of gate drivers is only opened n row pixel, and then storer is exported to data driver by n row video data signal according to a row pixel data and shown; Then n row are closed, and n+1 row are opened simultaneously, and storer is exported to data driver by the vision signal of n+1 row according to a row pixel data and shown.By that analogy, complete the output of video data and show.
Display panels of the present invention reaches by the position of swap data driver and gate drivers the object reducing costs.The display panels that the resolution of take is 1920*1080 is example, and the general data driver using is 6, and gate drivers is 3.By the position of swap data driver and gate drivers, by 1920*3(data line) * 1080(controlling grid scan line) panel driving mode, change into 1080*3(data line) * 1920(controlling grid scan line) panel driving mode.
As shown in table 1 with method contrast of the present invention before improving.
Table 1
| Type of drive | Data line | Controlling grid scan line |
| Before improvement | 1920*3=5760 | 1080 |
| The present invention | 1080*3=3240 | 1920 |
As can be seen from Table 1, the present invention is owing to being row * row=1080*1920 by video format conversion, thereby make the data of each row be reduced to 1080*3, and then make the burden of data driver reduce (5760-3240)/5760=43.75%, omit (1920-1080) * 3 data lines, can save 2 data drivers, thereby realized, not change under the prerequisite of image quality the object reducing costs.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (8)
1. a display panels, is characterized in that, comprising:
Many the controlling grid scan lines of arranging along column direction;
Many the data lines of arranging, intersecting with described controlling grid scan line insulation along line direction;
A plurality of pixels, are rectangular distribution; Wherein, each pixel comprises a plurality of sub-pixels that are arranged in parallel along column direction, and the unit area that each sub-pixel is limited by described controlling grid scan line and described data line forms;
The gate drivers being connected with described controlling grid scan line, for sequentially providing grid impulse to described controlling grid scan line;
The data driver being connected with described data line, for providing data voltage to described data line;
The time schedule controller being connected with described data driver with described gate drivers respectively, for to described gate drivers and described data driver transmission timing control signal, and the video data signal receiving to described data driver input.
2. display panels as claimed in claim 1, is characterized in that, the length of the line direction of each sub-pixel is longer than the length of the column direction of each sub-pixel.
3. display panels as claimed in claim 1, is characterized in that, each pixel comprises red sub-pixel R, green sub-pixels G and blue subpixels B, and wherein, red sub-pixel R, green sub-pixels G and blue subpixels B are arranged in parallel along column direction successively; The sub-pixel of same color is arranged in parallel along line direction.
4. display panels as claimed in claim 1, it is characterized in that, described timing control signal comprises for the grid timing control signal in the time sequential routine of control gate driver with for controlling the data time sequence control signal in the polarity of data voltage and the time sequential routine of data driver.
5. the display panels as described in claim 1-4 any one, it is characterized in that, described time schedule controller also comprises storer, the video data signal that described storer receives for buffer memory, and described video data signal is exported to described data driver according to each row pixel data.
6. display panels as claimed in claim 5, is characterized in that, described storer is frame buffer.
7. a liquid crystal indicator, is characterized in that, comprising:
Display panels as described in claim 1-4 any one;
Display control chip, is connected with described time schedule controller, for the video data signal of external video equipment input being converted to the data layout that is suitable for the resolution that shows at described display panels.
8. liquid crystal indicator as claimed in claim 7, is characterized in that, described display control chip by Low Voltage Differential Signal interface or transition minimized differential signaling interface to described time schedule controller inputting video data signal.
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| CN201310490559.2A CN103544926A (en) | 2013-10-18 | 2013-10-18 | Liquid crystal display panel and display device |
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| CN201310490559.2A CN103544926A (en) | 2013-10-18 | 2013-10-18 | Liquid crystal display panel and display device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104038718A (en) * | 2014-06-18 | 2014-09-10 | 刘兴宾 | Mini-LVDS (Low Voltage Differential Signaling) channel multiplexing interface and channel signal time-sharing multiplexing method thereof |
| CN109599070A (en) * | 2017-09-30 | 2019-04-09 | 咸阳彩虹光电科技有限公司 | Liquid crystal display device and its control method |
| CN112133259A (en) * | 2020-10-09 | 2020-12-25 | 上海中航光电子有限公司 | Display module, matching method of display module and main control chip signal format and display device |
| CN113012614A (en) * | 2019-12-20 | 2021-06-22 | 高创(苏州)电子有限公司 | Display assembly, display device, data signal display method and data signal transmission method |
| WO2023015583A1 (en) * | 2021-08-09 | 2023-02-16 | Tcl华星光电技术有限公司 | Display apparatus and mobile terminal |
| WO2023071077A1 (en) * | 2021-10-27 | 2023-05-04 | 问显科技(苏州)有限公司 | Display data updating method and apparatus, and display screen |
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| US20050156168A1 (en) * | 2002-07-31 | 2005-07-21 | Seiko Epson Corporation | System and methods for driving an electro-optical device |
| CN102737596A (en) * | 2011-04-01 | 2012-10-17 | 乐金显示有限公司 | Liquid crystal display |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20050156168A1 (en) * | 2002-07-31 | 2005-07-21 | Seiko Epson Corporation | System and methods for driving an electro-optical device |
| CN102737596A (en) * | 2011-04-01 | 2012-10-17 | 乐金显示有限公司 | Liquid crystal display |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104038718A (en) * | 2014-06-18 | 2014-09-10 | 刘兴宾 | Mini-LVDS (Low Voltage Differential Signaling) channel multiplexing interface and channel signal time-sharing multiplexing method thereof |
| CN104038718B (en) * | 2014-06-18 | 2017-09-01 | 广州晶序达电子科技有限公司 | A kind of Mini LVDS channel multiplexings interface and its channel signal time-sharing multiplexing method |
| CN109599070A (en) * | 2017-09-30 | 2019-04-09 | 咸阳彩虹光电科技有限公司 | Liquid crystal display device and its control method |
| CN113012614A (en) * | 2019-12-20 | 2021-06-22 | 高创(苏州)电子有限公司 | Display assembly, display device, data signal display method and data signal transmission method |
| CN112133259A (en) * | 2020-10-09 | 2020-12-25 | 上海中航光电子有限公司 | Display module, matching method of display module and main control chip signal format and display device |
| CN112133259B (en) * | 2020-10-09 | 2022-01-11 | 上海中航光电子有限公司 | Display module, matching method of display module and main control chip signal format and display device |
| WO2023015583A1 (en) * | 2021-08-09 | 2023-02-16 | Tcl华星光电技术有限公司 | Display apparatus and mobile terminal |
| US12067927B2 (en) | 2021-08-09 | 2024-08-20 | Tcl China Star Optoelectronics Technology Co., Ltd. | Display apparatus and mobile terminal |
| WO2023071077A1 (en) * | 2021-10-27 | 2023-05-04 | 问显科技(苏州)有限公司 | Display data updating method and apparatus, and display screen |
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Application publication date: 20140129 |