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WO2022166296A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2022166296A1
WO2022166296A1 PCT/CN2021/130597 CN2021130597W WO2022166296A1 WO 2022166296 A1 WO2022166296 A1 WO 2022166296A1 CN 2021130597 W CN2021130597 W CN 2021130597W WO 2022166296 A1 WO2022166296 A1 WO 2022166296A1
Authority
WO
WIPO (PCT)
Prior art keywords
film layer
protective film
insulating protective
display panel
circuit board
Prior art date
Application number
PCT/CN2021/130597
Other languages
English (en)
French (fr)
Inventor
孙浩
黄小霞
杨恩建
高亮
张爽
李非凡
王彬
杨虎飞
都阿娟
王永乐
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/914,235 priority Critical patent/US20240213181A1/en
Publication of WO2022166296A1 publication Critical patent/WO2022166296A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10128—Display
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil

Definitions

  • the present disclosure relates to the technical field of display product manufacturing, and in particular, to a display panel and a display device.
  • the flexible OLED module needs to be Aging (aging treatment) in the cell state, and needs to be lit for a long time to help stabilize the performance of the light-emitting device.
  • ET Pad Electro Test Pad
  • the ET Pad is the connection Pin that lights up in the cell state.
  • the ET Pad is set at the lower end of the bonding pin (bonding pin) of the panel (panel) and COF (chip-on-film), and is removed by laser cutting before the panel is bonded to the COF, and will not remain in the product in the end. superior.
  • a gate layer trace that is not easy to corrode is used in the cut area, but the resistance of the gate layer is about 10 times that of the SD trace.
  • the current generated when Aging is lit is more than twice that of small-size products.
  • the large current will cause burns to the gate layer wiring and cause aging failure. Therefore, the ET Pad for large-size products needs to be placed on both sides of the panel and the bonding pin of the FPC or COF, but the ET Pad remains on the product and will corrode in a high temperature and high humidity environment.
  • the present disclosure provides a display panel and a display device, which can effectively prevent the ET Pad from being corroded.
  • a display panel including a substrate, the substrate includes a display area and a non-display area, and the non-display area includes a binding located on one side of the display area
  • the bonding area includes a plurality of bonding pads, and also includes a first insulating protective film layer, a detection pad is provided between at least two of the bonding pads, and the first insulating protective film layer is located in the The detection pad is away from the side of the substrate.
  • the display panel further includes a chip on film connected to the bonding pad, and the display panel further includes a second insulating protective film layer on a side of the chip on film away from the substrate.
  • the first insulating protective film layer and the second insulating protective film layer are integrally provided.
  • the first insulating protective film layer and the second insulating protective film layer are separately disposed along a first direction, and the first direction is the direction from the bonding pad to the detection pad .
  • the display panel further includes a third insulating protective film layer located on a side of the circuit board away from the substrate.
  • the third insulating protective film layer includes at least two sub-insulating protective film layers, and a space between adjacent two sub-insulating protective film layers is provided.
  • the connectors are spaced apart.
  • the third insulating protective film layer includes at least two sub-insulating protective film layers along the second direction, and the sub-insulating protective film layer and the second insulating protective film layer close to the second insulating protective film layer
  • the layer is an integral structure, and the second direction is the direction from the chip on film to the circuit board.
  • the first insulating protective film layer, the second insulating protective film layer and the third insulating protective film layer are all made of insulating tape.
  • it further includes a first conductive film layer for deriving static electricity, the first conductive film layer is located on the side of the second insulating protective film layer away from the substrate.
  • it also includes a second conductive film layer for deriving static electricity, the second conductive film layer is located on the side of the third insulating protective film layer away from the substrate, and the third insulating protective film layer An opening is provided thereon, so that the second conductive film layer is connected to the ground.
  • the first conductive film layer and the second conductive film layer are integrally provided.
  • the first conductive film layer and the second conductive film layer are integrally formed with conductive cloth.
  • it also includes a wave-absorbing film layer for absorbing electromagnetic waves, electronic components are provided on the circuit board, and the third insulating protective film layer includes a first region, the wave absorbing film layer is located between the first region and the second conductive film layer.
  • the orthographic projection of the wave-absorbing film layer in the direction perpendicular to the circuit board is completely located on the circuit board, and the orthographic projection of the wave-absorbing film layer on the circuit board is greater than that of the electronic component on the circuit board. Orthographic projection on the circuit board.
  • Embodiments of the present disclosure further provide a display device, including the above-mentioned display panel.
  • the beneficial effects of the present disclosure are: by the arrangement of the first insulating protective film layer, the detection pad is protected to prevent the detection pad from being corroded.
  • FIG. 1 shows a schematic diagram of a display panel without a protective film attached in an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram 1 of a display panel structure according to an embodiment of the present disclosure
  • FIG. 3 shows a second schematic structural diagram of a display panel according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram 3 of the structure of the display panel according to the embodiment of the present disclosure.
  • this embodiment provides a display panel, including a substrate, the substrate including a display area and a non-display area 10 surrounding the display area, the non-display area 10 including a display area located in the display area
  • the binding area on one side of the area, the binding area includes a plurality of binding pads, and also includes a first insulating protective film layer 411, and a detection pad 1 is arranged between at least two of the binding pads, so The first insulating protective film layer 411 is located on the side of the detection pad 1 away from the substrate.
  • the arrangement of the first insulating protective film layer 411 can effectively prevent the detection pad 1 from being corroded.
  • the display panel further includes a chip on film 2 connected to the bonding pads, and the display panel further includes a second insulating film on the side of the chip on film 2 away from the substrate.
  • the protective film layer 412 is a part of the display panel.
  • the disposition of the second insulating protective film layer 412 can protect the chip on film 2 .
  • the first insulating protective film layer 411 and the second insulating protective film layer 412 are integrally provided. This simplifies the process steps.
  • the first insulating protective film layer 411 and the second insulating protective film layer 412 are disposed separately along a first direction (refer to the X direction in FIG. 1 ), and the first direction is From the bonding pad to the detection pad 1 , referring to FIG. 3 , the first insulating protective film layer 411 and the second insulating protective film layer 412 are separated at the position of the dotted line.
  • the first insulating protective film layer 411 and the second insulating protective film layer 412 are arranged separately along the first direction, and the first insulating protective film layer 411 and the second insulating protective film layer can be flexibly arranged as required 412.
  • the display panel further includes a circuit board 3, the chip on film 2 is bound and connected to the circuit board 3, and the display panel further includes a circuit board 3 that is far from the substrate.
  • FIG. 2 shows the display panel in an unbent state
  • FIG. 4 shows the display panel in a bent state
  • the side of the substrate on which the bonding pads are arranged is the front side
  • the side opposite to the front side is the back side
  • the display panel is in a folded state.
  • the third insulating protective film layer 413 is located on the side away from the front side of the substrate, and when the display panel is in the bent state, the circuit board 3 is located on the back side of the substrate, and the third The insulating protective film layer 413 is located on the side away from the back surface of the substrate.
  • the third insulating protective film layer 413 and the second insulating protective film layer 412 are integrally provided. That is, the first insulating protective film layer 411 , the second insulating protective film layer 412 and the third insulating protective film layer 413 are integrally arranged, and the detection pad 1 and the chip-on-chip film can be completed by a single sticking process. 2 and circuit board 3 protection, simple and easy to operate.
  • the first insulating protective film layer 411 , the second insulating protective film layer 412 and the third insulating protective film layer 413 are integrally arranged to improve production efficiency.
  • the circuit board 3 is provided with at least one connector connected to an external device (for example, a host), and the connector cannot be covered by the third insulating protective film layer 413 . Therefore, in order to avoid interference, the third insulating protective film layer 413 includes at least two sub-insulating protective film layers, and two adjacent sub-insulating protective film layers are separated by the connector.
  • the number of the sub-insulating protective film layers is determined according to the number of the connectors. For example, if two of the connectors are provided on the circuit board 3, the third insulating protective film layer 413 includes three of the connectors. Sub-insulating protective film layers, two adjacent sub-insulating protective film layers are separated by the corresponding connectors.
  • the third insulating protective film layer 413 includes at least two sub-insulating protective film layers along the second direction, and the sub-insulating protective film layer adjacent to the second insulating protective film layer 412 is connected to all the sub-insulating protective film layers.
  • the second insulating protective film layer 412 has an integrated structure, and the second direction is the direction from the chip on film 2 to the circuit board 3 , with reference to the Y direction in FIG. 2 .
  • the circuit board 3 also includes connection devices connected to devices such as the touch control structure (ie, connectors that need to be connected to devices other than the circuit board 3 ).
  • connection devices connected to devices such as the touch control structure (ie, connectors that need to be connected to devices other than the circuit board 3 ).
  • the sub-insulation protective film layer is also provided with openings for avoidance.
  • the first insulating protective film layer 411 , the second insulating protective film layer 412 and the third insulating protective film layer 413 are all made of insulating tape, but not limited thereto.
  • the display panel further includes a first conductive film layer 421 for discharging static electricity, and the first conductive film layer 421 is located on the side of the second insulating protective film layer 412 away from the substrate.
  • the arrangement of the first conductive film layer 421 increases the electrostatic protection for the chip-on-film 2 , and plays the role of electromagnetic protection on the bending region of the chip-on film 2 .
  • the display panel further includes a second conductive film layer 422 for discharging static electricity, the second conductive film layer 422 is located on the side of the third insulating protective film layer 413 away from the substrate, And the third insulating protective film layer 413 is provided with an opening, so that the second conductive film layer is connected to the ground.
  • the second conductive film layer 422 is connected to the grounding circuit on the circuit board 3 through the opening on the third insulating protective film layer 413 , so as to discharge static electricity and prevent the occurrence of static electricity on the circuit board 3 .
  • the first conductive film layer 421 and the second conductive film layer 422 are integrally provided.
  • the first conductive film layer 421 and the second conductive film layer 422 are integrally formed with conductive cloth, but not limited thereto.
  • the first conductive film layer 421 and the second conductive film layer 422 are integrally provided, which can simplify the process steps.
  • the integrally provided first conductive film layer 421 and the second conductive film layer 422 After the first insulating protective film layer 411 , the second insulating protective film layer 412 and the third insulating protective film layer 413 are bonded together, they are integrally bonded to the corresponding area of the display panel, which is simple and easy to operate.
  • the display panel further includes a wave-absorbing film layer 43 for absorbing electromagnetic waves
  • the circuit board 3 is provided with an electronic element 31
  • the third insulating protective film layer 413 includes a layer located on the electronic element.
  • 31 is a first region on the side away from the substrate
  • the wave absorbing film layer 43 is located between the first region and the second conductive film layer 422 .
  • the orthographic projection of the wave absorbing film layer 43 in the direction perpendicular to the circuit board 3 is completely located on the circuit board 3, and the wave absorbing film layer 43 is on the circuit board.
  • the orthographic projection on 3 is larger than the orthographic projection of the electronic component 31 on the circuit board 3 .
  • the clutter generated by the operation of the electronic components 31 on the circuit board 3 can be efficiently absorbed.
  • the first insulating protective film layer 411 , the second insulating protective film layer 412 and the third insulating protective film layer 413 are collectively named as insulating layers, the first conductive film layer 421 and all the
  • the second conductive film layer 422 is described as an overall structure (named as the conductive layer 42 as a whole).
  • the insulating layer, the wave absorbing film layer 43 and the conductive layer are now bonded into an overall structure, and then the bonded together
  • the insulating layer, the wave-absorbing film layer 43 and the conductive layer are integrally attached to the corresponding areas of the display panel.
  • Figure 2 shows a schematic diagram of the state before the chip on film is bent
  • Figure 4 shows a schematic diagram of the state after the chip on film 2 is bent.
  • the circuit board 3 is located on the backlight side of the display panel.
  • the insulating layer, the wave absorbing film layer 43 and the conductive layer that are attached together are attached to the display panel before the chip on film 2 is bent.
  • the display panel includes a protective film
  • the protective film includes an insulating layer 41 , a wave absorbing film layer 43 and a conductive layer 42 that are stacked in sequence;
  • the conductive layer 42 is made of conductive cloth, and includes a first conductive film layer 421 and a second conductive film layer 422.
  • the first conductive film layer 421 is used to stick to the second insulating protective film layer 412 away from all parts.
  • the second conductive film layer 422 is used to stick to the side of the third insulating protective film layer 413 away from the circuit board 3;
  • the circuit board 3 includes the electronic element 31 , the third insulating protective film layer 413 includes a first region located on the electronic element 31 , and the wave absorbing film layer 43 is located between the first region and the first region. between the two conductive film layers 422 .
  • Embodiments of the present disclosure further provide a display device, including the above-mentioned display panel.
  • the display device can be any product or component with a display function, such as a liquid crystal TV, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board 3, a printed circuit board 3 and a backplane .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本公开涉及一种显示面板，包括基板，所述基板包括显示区和非显示区，所述非显示区包括位于所述显示区一侧的绑定区，所述绑定区包括多个绑定焊盘，还包括第一绝缘保护膜层，至少两个所述绑定焊盘之间设置有检测焊盘，所述第一绝缘保护膜层位于所述检测焊盘远离所述基板的一侧。本公开还涉及一种显示装置。

Description

显示面板和显示装置
相关申请的交叉引用
本申请主张在2021年02月03日在中国提交的中国专利申请号No.202110151117.X的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示产品制作技术领域，尤其涉及一种显示面板和显示装置。
背景技术
柔性OLED模组需要在cell状态下进行Aging(老化处理)，需要长时间点亮以助于发光器件的性能稳定。ET Pad(Electric Test Pad)就是cell状态下点亮的连接Pin。在小尺寸产品上，ET Pad设置在panel(面板)与COF(覆晶薄膜)的bonding pin(绑定引脚)的下端，在面板绑定COF前被激光切割去掉，最终不会留在产品上。为防止切割的SD层金属走线截面发生腐蚀，在切割区域使用不易腐蚀的gate层走线，但gate层的电阻约为SD走线的10倍。而在大尺寸产品上，Aging点亮时产生的电流约为小尺寸产品的两倍以上，在Aging时大电流会对gate层走线造成灼伤，引起aging失效。故大尺寸产品ET Pad需要放置在panel与FPC或COF的bonding pin的两侧，但ET Pad保留在产品上，在高温高湿环境下会发生腐蚀。
发明内容
为了解决上述技术问题，本公开提供一种显示面板和显示装置，有效防止ET Pad被腐蚀。
为了达到上述目的，本公开实施例采用的技术方案是：一种显示面板，包括基板，所述基板包括显示区和非显示区，所述非显示区包括位于所述显示区一侧的绑定区，所述绑定区包括多个绑定焊盘，还包括第一绝缘保护膜层，至少两个所述绑定焊盘之间设置有检测焊盘，所述第一绝缘保护膜层位于所述检测焊盘远离所述基板的一侧。
可选的，还包括于所述绑定焊盘连接的覆晶薄膜，所述显示面板还包括位于所述覆晶薄膜远离所述基板的一侧的第二绝缘保护膜层。
可选的，所述第一绝缘保护膜层和所述第二绝缘保护膜层一体设置。
可选的，沿第一方向所述第一绝缘保护膜层和所述第二绝缘保护膜层分体设置，所述第一方向为从所述绑定焊盘到所述检测焊盘的方向。
可选的，还包括电路板，所述覆晶薄膜与所述电路板绑定连接，所述显示面板还包括位于所述电路板远离所述基板的一侧的第三绝缘保护膜层。
可选的，所述电路板上设置有用于与外部设备连接的至少一个连接器，所述第三绝缘保护膜层包括至少两个子绝缘保护膜层，相邻两个子绝缘保护膜层之间被所述连接器隔开。
可选的，沿第二方向所述第三绝缘保护膜层包括至少两个子绝缘保护膜层，靠近所述第二绝缘保护膜层的所述子绝缘保护膜层与所述第二绝缘保护膜层为一体结构，所述第二方向为从所述覆晶薄膜到所述电路板的方向。
可选的，所述第一绝缘保护膜层、所述第二绝缘保护膜层和所述第三绝缘保护膜层均采用绝缘胶布制成。
可选的，还包括用于导出静电的第一导电膜层，所述第一导电膜层位于所述第二绝缘保护膜层远离所述基板的一侧。
可选的，还包括用于导出静电的第二导电膜层，所述第二导电膜层位于所述第三绝缘保护膜层远离所述基板的一侧，且所述第三绝缘保护膜层上设置有开口，以使得所述第二导电膜层接地连接。
可选的，所述第一导电膜层和所述第二导电膜层一体设置。
可选的，所述第一导电膜层和所述第二导电膜层采用导电布一体成型。
可选的，还包括用于吸收电磁波的吸波膜层，所述电路板上设置有电子元件，所述第三绝缘保护膜层包括位于所述电子元件远离所述基板的一侧的第一区域，所述吸波膜层位于所述第一区域与所述第二导电膜层之间。
所述吸波膜层在垂直于所述电路板方向上的正投影完全位于所述电路板上，且所述吸波膜层在所述电路板上的正投影大于所述电子元件在所述电路板上的正投影。
本公开实施例还提供一种显示装置，包括上述的显示面板。
本公开的有益效果是：通过所述第一绝缘保护膜层的设置，对检测焊盘进行保护，防止检测焊盘被腐蚀。
附图说明
图1表示本公开实施例中未贴付保护膜的显示面板示意图；
图2表示本公开实施例中显示面板结构示意图一；
图3表示本公开实施例中显示面板结构示意图二；
图4表示本公开实施例中显示面板结构示意图三。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
如图1-图4所示，本实施例提供一种显示面板，包括基板，所述基板包括显示区和环绕所述显示区的非显示区10，所述非显示区10包括位于所述显示区一侧的绑定区，所述绑定区包括多个绑定焊盘，还包括第一绝缘保护膜层411，至少两个所述绑定焊盘之间设置有检测焊盘1，所述第一绝缘保护膜层411位于所述检测焊盘1远离所述基板的一侧。
所述第一绝缘保护膜层411的设置，可以有效的防止检测焊盘1被腐蚀。
本实施例中示例性的，显示面板还包括于所述绑定焊盘连接的覆晶薄膜2，所述显示面板还包括位于所述覆晶薄膜2远离所述基板的一侧的第二绝缘保 护膜层412。
所述第二绝缘保护膜层412的设置可以对覆晶薄膜2起到保护作用。
本实施例中示例性的，所述第一绝缘保护膜层411和所述第二绝缘保护膜层412一体设置。这样可以简化工艺步骤。
本实施例中示例性的，沿第一方向(参考图1中的X方向)所述第一绝缘保护膜层411和所述第二绝缘保护膜层412分体设置，所述第一方向为从所述绑定焊盘到所述检测焊盘1的方向，参考图3，所述第一绝缘保护膜层411和所述第二绝缘保护膜层412在虚线位置是分开的。
沿第一方向所述第一绝缘保护膜层411和所述第二绝缘保护膜层412分体设置，可以根据需要灵活设置所述第一绝缘保护膜层411和所述第二绝缘保护膜层412。
本实施例中示例性的，显示面板还包括电路板3，所述覆晶薄膜2与所述电路板3绑定连接，所述显示面板还包括位于所述电路板3远离所述基板的一侧的第三绝缘保护膜层413。
图2表示的是显示面板处于未弯折状态，图4表示显示面板处于弯折状态，所述基板设置所述绑定焊盘的一面为正面，与正面相背的一面为背面，显示面板处于未弯折状态时，所述第三绝缘保护膜层413位于远离所述基板的正面的一侧，显示面板处于弯折状态时，所述电路板3位于所述基板的背面，所述第三绝缘保护膜层413位于远离所述基板的背面的一侧。
本实施例中示例性的，所述第三绝缘保护膜层413与所述第二绝缘保护膜层412一体设置。即所述第一绝缘保护膜层411、所述第二绝缘保护膜层412和所述第三绝缘保护膜层413一体设置，通过一次贴付工艺即可完成对检测焊盘1、覆晶薄膜2和电路板3的保护，简单易操作。且在制作绝缘保护膜层时，所述第一绝缘保护膜层411、所述第二绝缘保护膜层412和所述第三绝缘保护膜层413一体设置，提高生产效率。但在实际使用中，所述电路板3上设置有与外部设备(例如，主机)连接的至少一个连接器，而该连接器不能被所述第三绝缘保护膜层413覆盖，因此，为了避免干涉，所述第三绝缘保护膜层413包括至少两个子绝缘保护膜层，相邻两个子绝缘保护膜层之间被所述连接器隔开。
所述子绝缘保护膜层的数量根据所述连接器的数量决定，例如，所述电路板3上设置有两个所述连接器，则所述第三绝缘保护膜层413包括三个所述子绝缘保护膜层，相邻两个所述子绝缘保护膜层被相应的所述连接器隔开。
本实施例中示例性的，沿第二方向所述第三绝缘保护膜层413包括至少两个子绝缘保护膜层，靠近所述第二绝缘保护膜层412的所述子绝缘保护膜层与所述第二绝缘保护膜层412为一体结构，所述第二方向为从所述覆晶薄膜2到所述电路板3的方向，参考图2中的Y方向。
在实际使用中，所述电路板3上还包括与触控结构等器件连接的连接器件(即需要与所述电路板3之外的器件连接的连接器)，本实施例中示例性的，所述子绝缘保护膜层还设置有开口以进行避让。
本实施例中，所述第一绝缘保护膜层411、所述第二绝缘保护膜层412和所述第三绝缘保护膜层413均采用绝缘胶布制成，但并不以此为限。
对于COF(覆晶薄膜2)产品，在COF与panel的bonding(绑定)区会存在ESD(静电)风险；且COF的弯折区线路存在对整机的电磁干扰。
本实施例中示例性的，显示面板还包括用于导出静电的第一导电膜层421，所述第一导电膜层421位于所述第二绝缘保护膜层412远离所述基板的一侧。
所述第一导电膜层421的设置，增加了对覆晶薄膜2的静电防护，且对覆晶薄膜2的弯折区域起到电磁防护的作用。
本实施例中示例性的，显示面板还包括用于导出静电的第二导电膜层422，所述第二导电膜层422位于所述第三绝缘保护膜层413远离所述基板的一侧，且所述第三绝缘保护膜层413上设置有开口，以使得所述第二导电膜层接地连接。
所述第二导电膜层422通过所述第三绝缘保护膜层413上的开口与所述电路板3上的接地线路连接，以将静电导出，可以防止电路板3上静电的发生。
本实施例中示例性的，所述第一导电膜层421和所述第二导电膜层422一体设置。
本实施例中，所述第一导电膜层421和所述第二导电膜层422采用导电布一体制作成型，但并不以此为限。
所述第一导电膜层421和所述第二导电膜层422一体设置，可以简化工艺 步骤，将一体设置的所述第一导电膜层421和所述第二导电膜层422与一体设置的所述第一绝缘保护膜层411、所述第二绝缘保护膜层412和所述第三绝缘保护膜层413贴合后，再与显示面板相应区域进行整体贴付，简单易操作。
本实施例中示例性的，显示面板还包括用于吸收电磁波的吸波膜层43，所述电路板3上设置有电子元件31，所述第三绝缘保护膜层413包括位于所述电子元件31远离所述基板的一侧的第一区域，所述吸波膜层43位于所述第一区域与所述第二导电膜层422之间。
大尺寸产品在PCB上有大量的包括IC的电子元件31，在工作使会产生大量的电磁杂波，会对整机产生射频干扰，所述吸波膜层43的设置可以高效吸收电路板3上电子元件31工作产生的杂波，进而可以减少元件工作对整机产生的射频干扰，且所述吸波膜层43设置于所述第三绝缘保护膜层413和所述第二导电膜层422之间，可以有效防止吸波材掉粉。
本实施例中示例性的，所述吸波膜层43在垂直于所述电路板3方向上的正投影完全位于所述电路板3上，且所述吸波膜层43在所述电路板3上的正投影大于所述电子元件31在所述电路板3上的正投影。可以高效吸收电路板3上电子元件31工作产生的杂波。
本实施例中，所述第一绝缘保护膜层411、所述第二绝缘保护膜层412和所述第三绝缘保护膜层413整体命名为绝缘层，所述第一导电膜层421和所述第二导电膜层422为整体结构(整体命名为导电层42)，实际操作中，现将绝缘层、吸波膜层43和导电层贴合为一整体结构，然后将贴合在一起的绝缘层、吸波膜层43和导电层，整体贴付于显示面板的相应区域。
图2表示的是覆晶薄膜弯折前的状态示意图，图4表示的是覆晶薄膜弯折后的状态示意图，覆晶薄膜2弯折后，使得电路板3位于显示面板的背光侧，为了便于操作，本实施例中，在覆晶薄膜2弯折前将贴合在一起的绝缘层、吸波膜层43和导电层与显示面板进行贴付。
具体的，本实施例中，所述显示面板包括一保护膜，所述保护膜包括依次层叠设置的绝缘层41、吸波膜层43和导电层42；
所述绝缘层41采用绝缘胶布制成，包括第一绝缘保护膜层411、第二绝缘保护膜层412和第三绝缘保护膜层413，所述第一绝缘保护膜层411用于贴 付于显示面板上的检测区，所述第二绝缘保护膜层412用于贴付于显示面板上的覆晶薄膜2上，所述第三绝缘保护膜层413用于贴付于显示面板的电路板3上；
所述导电层42采用导电布制成，包括第一导电膜层421和第二导电膜层422，所述第一导电膜层421用于贴付于所述第二绝缘保护膜层412远离所述覆晶薄膜2的一侧，所述第二导电膜层422用于贴付于所述第三绝缘保护膜层413远离所述电路板3的一侧；
所述电路板3包括电子元件31，所述第三绝缘保护膜层413包括位于所述电子元件31之上的第一区域，所述吸波膜层43位于所述第一区域与所述第二导电膜层422之间。
本公开实施例还提供一种显示装置，包括上述的显示面板。
所述显示装置可以为：液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板3、印刷电路板3和背板。
以上所述为本公开较佳实施例，需要说明的是，对于本领域普通技术人员来说，在不脱离本公开所述原理的前提下，还可以做出若干改进和润饰，这些改进和润饰，也应视为本公开保护范围。

Claims (15)

  1. 一种显示面板，包括基板，所述基板包括显示区和非显示区，所述非显示区包括位于所述显示区一侧的绑定区，所述绑定区包括多个绑定焊盘，其中，还包括第一绝缘保护膜层，至少两个所述绑定焊盘之间设置有检测焊盘，所述第一绝缘保护膜层位于所述检测焊盘远离所述基板的一侧。
  2. 根据权利要求1所述的显示面板，其中，还包括与所述绑定焊盘连接的覆晶薄膜，所述显示面板还包括位于所述覆晶薄膜远离所述基板的一侧的第二绝缘保护膜层。
  3. 根据权利要求2所述的显示面板，其中，所述第一绝缘保护膜层和所述第二绝缘保护膜层一体设置。
  4. 根据权利要求2所述的显示面板，其中，沿第一方向所述第一绝缘保护膜层和所述第二绝缘保护膜层分体设置，所述第一方向为从所述绑定焊盘到所述检测焊盘的方向。
  5. 根据权利要求3或4所述的显示面板，其中，还包括电路板，所述覆晶薄膜与所述电路板绑定连接，所述显示面板还包括位于所述电路板远离所述基板的一侧的第三绝缘保护膜层。
  6. 根据权利要求5所述的显示面板，其中，所述电路板上设置有用于与外部设备连接的至少一个连接器，所述第三绝缘保护膜层包括至少两个子绝缘保护膜层，相邻两个子绝缘保护膜层之间被所述连接器隔开。
  7. 根据权利要求6所述的显示面板，其中，沿第二方向所述第三绝缘保护膜层包括至少两个子绝缘保护膜层，靠近所述第二绝缘保护膜层的所述子绝缘保护膜层与所述第二绝缘保护膜层为一体结构，所述第二方向为从所述覆晶薄膜到所述电路板的方向。
  8. 根据权利要求5所述的显示面板，其中，所述第一绝缘保护膜层、所述第二绝缘保护膜层和所述第三绝缘保护膜层均采用绝缘胶布制成。
  9. 根据权利要求5所述的显示面板，其中，还包括用于导出静电的第一导电膜层，所述第一导电膜层位于所述第二绝缘保护膜层远离所述基板的一侧。
  10. 根据权利要求9所述的显示面板，其中，还包括用于导出静电的第二 导电膜层，所述第二导电膜层位于所述第三绝缘保护膜层远离所述基板的一侧，且所述第三绝缘保护膜层上设置有开口，以使得所述第二导电膜层接地连接。
  11. 根据权利要求10所述的显示面板，其中，所述第一导电膜层和所述第二导电膜层一体设置。
  12. 根据权利要求11所述的显示面板，其中，所述第一导电膜层和所述第二导电膜层采用导电布一体成型。
  13. 根据权利要求11所述的显示面板，其中，还包括用于吸收电磁波的吸波膜层，所述电路板上设置有电子元件，所述第三绝缘保护膜层包括位于所述电子元件远离所述基板的一侧的第一区域，所述吸波膜层位于所述第一区域与所述第二导电膜层之间。
  14. 根据权利要求13所述的显示面板，其中，所述吸波膜层在垂直于所述电路板方向上的正投影完全位于所述电路板上，且所述吸波膜层在所述电路板上的正投影大于所述电子元件在所述电路板上的正投影。
  15. 一种显示装置，其中，包括权利要求1-14任一项所述的显示面板。
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